Systems and methods for communication using serial peripheral interface (SPI) protocol

Abstract

A system and method are provided. In an aspect, the system includes a plurality of serial peripheral interface (SPI) devices including a main SPI device and a plurality of SPI subnodes. The main SPI device is coupled with each one of the plurality of SPI subnodes via a 4-wire bus.

Description

SYSTEMS AND METHODS FOR COMMUNICATION USING SERIAL PERIPHERAL INTERFACE (SPI) PROTOCOLCROSS-REFERENCE TO RELATED APPLICATION

[0001] This patent application claims the benefit of U.S. Provisional Application No.63 / 748,824, filed on January 23, 2025, titled “SYSTEMS AND METHODS FOR COMMUNICATION USING SERIAL PERIPHERAL INTERFACE (SPI) PROTOCOL.” The disclosure of the prior application is hereby incorporated by reference in its entirety.BACKGROUND

[0001] The Serial Peripheral Interface (SPI) is a synchronous serial communication protocol widely used for short-distance communication, primarily in embedded systems. SPI facilitates full -duplex communication between a main SPI device, such as a microcontroller, and one or more peripheral devices, known as SPI subnodes. Conventionally, SPI systems operate in one of two primary modes: a parallel mode, where the main device communicates with each subnode via a dedicated chip select line, or a series (daisy-chain) mode, where data flows sequentially through a chain of connected subnodes.

[0002] While widely adopted, these conventional SPI communication modes present significant limitations, particularly in systems with a large number of subnodes. The parallel mode suffers from poor scalability, as the parallel mode requires a dedicated chip select pin on the main device for each SPI subnode, which can use up the available general-purpose input / output (GPIO) pins. The series or daisy-chain mode, on the other hand, is prone to performance degradation due to cumulative signal propagation delays. As data passes through each SPI subnode in the chain, the delay accumulates, potentially causing setup time violations at high clock frequencies for SPI subnodes positioned further from the main SPI device. These limitations create a need for a more scalable and efficient SPI communication method.SUMMARY

[0003] This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the DETAILED DESCRIPTION. This summary is not intended to identify key features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0004] According to an aspect of the present disclosure, a system is provided. The system includes a plurality of serial peripheral interface (SPI) devices including a main SPI device anda plurality of SPI subnodes. The main SPI device is coupled with each one of the plurality of SPI subnodes via a 4-wire bus.

[0005] According to another aspect of the present disclosure, a method is provided. The method includes providing a plurality of serial peripheral interface (SPI) devices including a main SPI device and a plurality of SPI subnodes. The method further includes coupling the main SPI device with each one of the plurality of SPI subnodes via a 4-wire bus.

[0006] Additional aspects of the present disclosure will be described in more detail below.BRIEF DESCRIPTION OF THE FIGURES

[0007] In the description that follows, like parts are marked throughout the specification and drawings with the same numerals. The drawing figures are not necessarily drawn to scale and certain figures may be shown in exaggerated or generalized form in the interest of clarity and conciseness. The disclosure itself, as well as a preferred mode of use and further advantages thereof, will be best understood by reference to the following detailed description of illustrative aspects of the disclosure when read in conjunction with the accompanying drawings, wherein:

[0008] FIG. 1A is a block diagram of an example connectivity configuration of multiple serial peripheral interface (SPI) devices in an example of series mode of communication.

[0009] FIG. IB is a block diagram of an example connectivity configuration of multiple SPI devices in an example of parallel mode of communication.

[0010] FIG. 2 is a schematic packet diagram that illustrates an example battery management system (BMS), in accordance with one or more aspects of this disclosure.

[0011] FIG. 3 is a schematic block diagram of multiple devices functionally coupled via a serial peripheral interface (SPI) bus, in accordance with one or more aspects of this disclosure.

[0012] FIGS. 4A-4C are schematic block diagrams representing respective examples of SPI frame, in accordance with one or more aspects of this disclosure.

[0013] FIGS. 5A-5B are schematic block diagrams representing respective examples of SPI frames, in accordance with one or more aspects of this disclosure.

[0014] FIG. 6 is a schematic block diagram of an example of a command field in accordance with one or more aspects of this disclosure.

[0015] FIG. 7 is a block diagram of an example of a SPI device in accordance with one or more aspects of this disclosure.

[0016] FIG. 8 is a block diagram of a broadcast write frame, in accordance with one or more aspects of this disclosure.

[0017] FIG. 9 is a block diagram of a compressed broadcast write frame, in accordance with one or more aspects of this disclosure.

[0018] FIG. 10 is a block diagram of an addressing write frame, in accordance with one or more aspects of this disclosure.

[0019] FIG. 11 is a block diagram of data writing sequence using compressed broadcast writes, in accordance with one or more aspects of this disclosure.

[0020] FIG. 12 is a block diagram of a data writing sequence combining a broadcast write with an offset, in accordance with one or more aspects of this disclosure.

[0021] FIG. 13 is a block diagram of a broadcast read frame, in accordance with one or more aspects of this disclosure.

[0022] FIG. 14 is a block diagram of an addressing read frame; in accordance with one or more aspects of this disclosure.

[0023] FIG. 15 is a block diagram of a sequence for read operations, in accordance with one or more aspects of this disclosure.

[0024] FIG. 16 is a block diagram of a mixed write and read operation, in accordance with one or more aspects of this disclosure.

[0025] FIG. 17 is a block diagram of a flexible write operation, in accordance with one or more aspects of this disclosure.

[0026] FIG. 18 is a block diagram of a flexible read operation, in accordance with one or more aspects of this disclosure.

[0027] FIG. 19 is a flowchart of a method, in accordance with one or more aspects of this disclosure.

[0028] FIG. 20 is a flowchart of a method, in accordance with one or more aspects of this disclosure.

[0029] FIG. 21 is a flowchart of a method, in accordance with one or more aspects of this disclosure.

[0030] FIG. 22 is a flowchart of an example method for an SPI communication frame, in accordance with one or more aspects of this disclosure.

[0031] FIG. 23 is a flowchart of a method for SPI write operations, in accordance with one or more aspects of this disclosure.

[0032] FIG. 24 is a flowchart of a method for SPI read operations , in accordance with one or more aspects of this disclosure.

[0033] FIG.25 is a flowchart of a method for operations involving a base address and an offset, in accordance with one or more aspects of this disclosure.

[0034] FIG. 26 is a flowchart of a method for operations involving writing and reading using a base address, in accordance with one or more aspects of this disclosure.DETAILED DESCRIPTION

[0035] The Serial Peripheral Interface (SPI) is a synchronous serial communication protocol that enables full-duplex communication between a main SPI device (e.g., a microcontroller unit or MCU) and one or more peripheral devices. Such peripheral devices may include, for example, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), digital potentiometers, nonvolatile memories (NVMs), and various types of sensors. SPI is used to exchange data and signaling among devices across a range of applications, including automotive, industrial, digital healthcare, power management, server platforms (e.g., cloud computing, cloud storage, database platforms), communication systems (wireless and wireline), and consumer electronics.

[0036] An arrangement of devices that exchanges data or signaling, or both, by means of SPI protocol includes multiple (two or more) devices coupled by a SPI bus. Each of the multiple devices can be referred to as an SPI device. One SPI device of the multiple devices provides a clock and other signaling and can be referred to as a main SPI device or main control device (e.g., an MCU). The other device or devices of the multiple devices can be referred to as “SPI subnodes.” The SPI subnodes can be labeled as “SPI DEV0,” “SPI DEVI,” and so forth, up to “SPI DEVN” for nomenclature, with N being a number that is equal to or greater than unity and denoting the number of SPI subnodes. The SPI bus utilizes a 4-wire bus. Thus, each one of the multiple devices includes at least four pins: Serial Chip Select (SCS or CS), Serial Clock (SCK or SCLK), Serial Data Input (SDI), and Serial Data Output (SDO). In one aspect, an MCU can have eight SCS wires and three other wires: one for SCK, one for SDI, and one for SDO. For example, when the MCU communicates with SPI subnode SPI DEV0, the active wires are SCSO, SCK, SDI, and SDO.

[0037] Existing SPI communication modes include a series mode and a parallel mode. Such a series mode and parallel mode are herein referred to as conventional series mode and conventional parallel series mode, respectively, simply for the sake of consistency. FIG. 1A and FIG. IB illustrate, respectively, connectivity among SPI devices in conventional series mode and conventional parallel mode for respective device arrangements each having N = 7 SPI subnodes.

[0038] As illustrated in FIG. 1A, a conventional series mode, also known as a daisy-chain configuration, connects multiple SPI devices. In this mode, the Serial Data Out (SDO) of a firstSPI device (e.g., the device proximate to MCU 110) is connected to the Serial Data In (SDI) of an adjacent second SPI device. The first and second SPI devices also share connections for Serial Chip Select (SCS) and Serial Clock (SCK). The first SPI device can be referred to as the “front device” and the second SPI device can be referred to as the “rear device.” A signal delay from SDI to SDO exists in each SPI device, and this signal delay accumulates across the entire chain of SPI subnodes (e.g., in device arrangement 100). Consequently, in high-frequency clock applications, the signal at the SDI devices further down the chain (“rear devices”) may lack sufficient setup time, preventing the rear devices from correctly receiving series data sent by the MCU.

[0039] As illustrated in FIG. IB, in a conventional parallel mode, an MCU (e.g., MCU 160) connects to multiple SPI subnodes. The SDI, SDO, and SCK lines of the MCU are bussed to corresponding pins of each SPI subnode. Each SPI subnode is connected to the MCU via a dedicated, individual SCS pin. Such a configuration exhibits poor scalability because each additional SPI subnode requires a dedicated general -purpose input / output (GPIO) pin on the MCU to serve as the respective SCS pin. This reliance on a growing number of GPIO pins leads to inefficiencies, such as the MCU repetitively sending a command and a corresponding command CRC to each SPI subnode.

[0040] Embodiments of this disclosure address compatibility issues between the existing SPI communication protocol and other protocols (such as BMS-compatible protocols), as well as other challenges associated with standard SPI communications. These challenges include pin count limitations, high clock frequency signal degradation, and poor expandability of certain SPI device arrangements (e.g., daisy-chain configurations).

[0041] Embodiments of this disclosure, individually or in combination, provide a serial peripheral interface (SPI) communication protocol having a SPI communication mode and SPI identifier (SPI ID) distribution techniques. In the communication mode, which may be referred to as an enhanced parallel mode, Serial Chip Select (SCS) pins are common across SPI devices (including a main SPI device and SPI subnodes), surpassing the performance of a conventional parallel mode in a standard SPI communication protocol.

[0042] The SPI communication protocol and SPI ID distribution techniques of this disclosure can, individually or in combination, achieve various efficiencies, such as complexity reduction and an increase in usable clock signal frequencies. This improved SPI communication protocol is compatible with the standard SPI communication protocol. Aspects may reduce the number of SPI modules needed to communicate with SPI devices and, in some cases, may maintain high communication clock frequencies (e.g., up to 10 MHz) without limitation on the numberof CS pins or devices. Accordingly, aspects may provide high communication efficiency, communication flexibility, and / or system expandability.

[0043] Aspects of this disclosure, individually or in combination, provide various improvements over existing SPI communication protocols. For example, aspects of this disclosure may: (a) permit SPI broadcast write / read and addressing write / read, supporting both high communication efficiency and fast response; (b) be compatible with existing BMS ISO protocol and non-ISO protocol; (c) be compatible with standard SPI communication protocol; (d) permit using same SCS pin / individual SCS pin architecture; and / or (e) permit high communication clock frequency.

[0044] Aspects of this disclosure may also: (f) reduce the number of GPIO pins used in a main SPI device for communication, such as by allowing main SPI device and SPI subnodes in a chain to share a set of four-wire SPI pins; (g) reduce the factors that can limit the number of SPI devices, such as SPI host performance, bus stray capacitance, and the number of bits for an SPI ID; and (h) map a location of a SPI device on a printed circuit board (PCB) to the SPI ID of the SPI device.

[0045] FIG.2 is a schematic packet diagram that illustrates an existing BMS protocol. Aspects of this disclosure permit using SPI protocol with the existing BMS protocol. The existing BMS protocol contains four parts: a 16-bit field defining a Command (CMD), a 16-bit field defining a CMD Packet Error Check (CMD PEC), a field defining DATA, and a 16-bit field defining a DATA PEC. In some cases, DATA and DATA PEC may not be present in one or more CMDs. In addition, CMD and CMD PEC are sent only once in one packet. Such a single packet without DATA and DATA PEC is illustrated in panel (A) of FIG. 2. In this disclosure, a “packet” refers to an information structure that includes data or signaling, or both, where the information structure is defined by a communication protocol.

[0046] As illustrated in panel (B), a packet for a write operation includes DATA and DATA PEC for DEVN after a CMD PEC. The packet includes subsequent blocks having DATA and DATA PEC for each of SPI subnode N-l, SPI subnode N-2, ... , down to SPI subnode 1. Here, DEVN represents the SPI subnode that is farthest from a main SPI device (or SPU host or MCU), and DEVI represents the SPI subnode that is nearest to the SPI host.

[0047] As is illustrated in panel (C), a packet for a read operation, response DATA and DATA PEC for DEVI follows the CMD PEC. In the existing BMS protocol illustrated in FIG. 2, the MCU (or host) uses CMD0, CMD1, CMD PECO, and CMD PEC1 to queiy all SPI subnodes. Each SPI subnode may then respond with DATA in response to the query.

[0048] FIG. 3 is a schematic block diagram of a system 300 with multiple Serial Peripheral Interface (SPI) devices functionally coupled via an SPI bus, in accordance with one or more aspects of this disclosure. The example of FIG. 3 shows a main SPI device 310 and eight SPI subnodes. Specifically, the device arrangement includes the main SPI device 310, a first SPI device 320(1), a group of second SPI devices 320(2), and a third SPI device 320(3) (labeled “SPI DEV7”). As illustrated, the first SPI device 320(1), each SPI device in the group of second SPI devices 320(2), and the third SPI device 320(3) share the same chip select (SCS), serial clock (SCK), serial data in (SDI), and serial data out (SDO) lines with the main SPI device 310. Such SPI devices connected to a main SPI device 310 may be referred to as “SPI subnodes” 320 or “SPI peripheral devices.”

[0049] All (or in some cases, at least some) SPI devices may share the same SCS, SCK, SDI, and SDO with a main SPI device (referred to as main control unit (MCU)). Each one of the multiple devices may be addressed with the first 6 bits of a 16-bit command. In one aspect, ID of each SPI Device is configurable.

[0050] The first 6 bits of a 16-bit command address the main SPI device 310 and each of the SPI subnodes 320. The ID of each SPI device is configurable. Different ID values correspond to different frame types, including:Addressed Frame: An ID in the range of 0x01 to 0x3E.- Broadcast Frame: An ID of 0x00. A Broadcast Frame may be a Broadcast Read Frame or a Broadcast Write Frame, where each SPI device can return or parse DATA and DATA PEC.Compressed Broadcast Write Frame: An ID of 0x3F, where all or some SPI devices configure the targeted register with the same DATA.

[0051] FIGS. 4A-4C are schematic block diagrams representing example SPI frames for various write operations, in accordance with one or more aspects of the disclosure. For illustrative purposes, the examples in FIGS. 4A-4C adopt a configuration for N=8 devices with a 16-bit command (CMD), a 16-bit CMD packet error check (PEC, 32-bit data (DATA), and a 16-bit DATA PEC. However, other configurations including other numbers of devices and other bit lengths can be used. A host device (e.g., main SPI device 310 of FIG. 3) sends information in each of the example SPI frames.

[0052] Block diagram 400 in FIG. 4A represents a SPI frame that may be used in a broadcast write operation in accordance with aspects of this disclosure. The SPI frame may be referred to as broadcast write SPI frame.

[0053] Block diagram 430 in FIG.4B represents a SPI frame that may be used in a compressed broadcast write operation in accordance with aspects of this disclosure. The SPI frame may be referred to as compressed broadcast write SPI frame.

[0054] Block diagram 460 in FIG.4C represents a SPI frame that may be used in an addressing write operation in accordance with aspects of this disclosure. The SPI frame may be referred to as addressing write SPI frame.

[0055] FIGS. 5A-5B are schematic block diagrams representing example SPI frames for various read operations, in accordance with one or more aspects of the disclosure. For illustrative purposes, the examples in FIGS. 5A-5B adopt a configuration for N=8 devices with a 16-bit command (CMD), a 16-bit CMD packet error check (PEC, 32-bit data (DATA), and a 16-bit DATA PEC. However, other configurations including other numbers of devices and other bit lengths can be used. A host device (e.g., main SPI device 310 of FIG. 3) sends a portion of the information in each of the example SPI frames, represented by unfilled rectangular blocks. A SPI subnode sends another portion of the information in each of the example SPI frames, represented by filled rectangular blocks.

[0056] Block diagram 500 in FIG 5A represents an example SPI frame that may be used in a broadcast read operation in accordance with aspects of this disclosure. The example SPI frame may be referred to as broadcast read SPI frame.

[0057] Block diagram 530 in FIG 5B represents an example SPI frame that may be used in an addressing read operation in accordance with aspects of this disclosure. The example SPI frame may be referred to as addressing read SPI frame.

[0058] FIG. 6 is a schematic block diagram of an example command field 600 in accordance with one or more aspects of the disclosure. The command field 600 has a length of 16 bits and can be partitioned into three subfields. A first subfield, bits [15:10], defines a frame identifier (SPI ID) 601. A second subfield, bits [9:8], defines a command type (CMD Type) 602. A third subfield, bits [7:0], defines a command code (CMD Code) 603. With proper design for CMD type and CMD Code, and information in data field, this example structure can support to access up to a 32-bit address length.

[0059] In one configuration, the SPI ID subfield can have one of the following values:0x00, indicating a Broadcast Frame;0x01 - 0x3E, indicating an Addressed Frame with a respective address or device number; and0x3F, indicating a Compressed Broadcast Write Frame.

[0060] In the same configuration, the CMD Type subfield can have one of the following values:2’b00: Reserved.2’b01 : Indicates a base address operation, where:o CMD Code == 0x00 indicates to update the base address using the DATA field; o CMD Code == OxFF indicates to read the current base address from an SPI subnode;ando CMD Codes 0x01 - OxFE are reserved.2’blO and 2’bl 1 : Indicate, respectively, a Write to and a Read from a targeted address, where the CMD Code indicates an offset from the base address.

[0061] In some applications, a Chip Select (CS) pin may function as one bit of the address length. In another aspect, a status of the CS pin can serve as an additional bit for the command field 600, resulting in a 17-bit command field. For example, a high or low state of the CS pin can represent an additional 1’bl or 1’bO, respectively, for the command field.

[0062] FIG. 7 is a block diagram of an example Serial Peripheral Interface (SPI device 710 in accordance with one or more aspects of the present disclosure. The example SPI device 710 can embody or can constitute a main SPI device or an SPI peripheral device (e.g., an SPI subnode). In one example, SPI device 710 embodies or forms part of a microcontroller unit (MCU), such as main SPI device 310 of FIG.3). In another example, SPI device 710 embodies or forms part of an SPI subnode in the group of SPI devices including SPI device 320(1), SPI devices 320(2), and SPI device 320(3) of FIG. 3.

[0063] An example SPI device 710 includes a plurality of registers 720, a clock generator 730, a processor 740, and one or more memory devices (memory) 750. The SPI device 710 includes a plurality of functional pins, including but not limited to, a Serial Data In (SDI pin 752, a Serial Data Out (SDO) pin 754, a Serial Clock (SCK) pin 756, and a Chip Select (CS) pin 758). In some embodiments, the plurality of functional pins comprises at least one of a Ready (RDY) pin, an Interrupt (INT) pin, or an Alert (ALERT) pin. For example, an analog-to-digital converter (ADC) can constitute an SPI subnode, wherein the ADC includes an interrupt pin (INT pin) to inform the MCU that there are one or more events to be checked, and an ALERT pin to indicate an emergency event that is occurring or that has occurred. The RDY, INT, and ALERT pins may be regarded as General-Purpose Input / Output (GPIO) pins with dedicated functions.

[0064] The registers 720 include one or more registers to transmit data to another SPI device and receive data from another SPI device. The one or more registers include a shift registerconfigured to contain an Af-bit word, where AY can be, for example, 8 bits, 16 bits, 32 bits, or 48 bits. During a data transmission or a data reception, which can be part of a write operation or a read operation, the SPI device 710 can serially send or receive data using a clock signal. In embodiments where the SPI device 710 is a main SPI device, the clock signal is generated by the clock generator 730 and can be output via the SCK pin 756 to another SPI device, as represented by dashed arrows in FIG. 7. In embodiments where the SPI device 710 is an SPI subnode, the clock signal for the shift register is received from another SPI device via the SCK pin 756, as represented by a dotted-line arrow in FIG. 7.

[0065] The processor 740 is configured to provide data from the memory 750 to the example SPI device 710 for transmission to another SPI device as part of a write operation. The write operation can use a write frame in accordance with aspects of this disclosure. For example, the example SPI device 710 can be embodied as a main SPI device and can write data to a SPI subnode.

[0066] The processor 740 is further configured to store, in the memory 750, data received from another SPI device during a read operation that uses a read frame in accordance with aspects of this disclosure. For example, the SPI device 710 is embodied as a main SPI device and reads data from an SPI subnode.

[0067] The SPI device 710 can further include a register for use in SPI ID distribution in accordance with aspects of this disclosure. The register can include a O-bit word, for example, a 6-bit word.

[0068] The memory 750 may include logic executable by the processor 740 to control SPI ID distribution. The logic may include a first command, referred to as an IDDONE command that causes a General-Purpose Input / Output (GPIO) pin of the SPI device to transition from a first mode of operation to a second mode of operation. Execution of the first command by the processor 740 releases the GPIO pin from the first mode of operation.

[0069] In addition, or in some cases, the logic used to control SPI ID distribution in accordance with aspects of this disclosure also can include a second command that causes the example SPI device 710 or a communication block within the example SPI device 710 to return to a defined initial state. The second command also can reset or otherwise configure a SPI ID to 0x00 or another defined value. The functionality of the second command is achieved in response to execution by the processor 740. The second command may be referred to herein as an IDRESET command, simply for the sake of nomenclature.

[0070] The logic may further include a second command, referred to as an IDRESET command, that, in response to execution by the processor 740, causes the SPI device 710 or acommunication block within the SPI device 710 to return to a defined initial state. Execution of the second command may also reset or configure a SPI ID to 0x00 or another defined value.

[0071] In a Serial Peripheral Interface (SPI) system configured for SPI ID distribution, multiple SPI devices may share a single SPI port. Each SPI frame transmitted by a SPI host device is received by all connected SPI subnodes.

[0072] A Serial Peripheral Interface (SPI) device includes a register (IDREG) for a 6-bit SPI identification (ID) configuration. The IDREG may be configured with a portion of Chip ID (with the Chip ID information is read-only (RO). The IDREG may also be configured with a whole 6-bit SPI ID, a number of SPI subnodes in an SPI chain, or other information indicative of a location on a printed circuit board (PCB). For example, writing to the IDREG for SPI ID reconfiguration is valid only when a portion of the Chip ID matches a predetermined value. Such a condition prevents all SPI subnodes from being configured with a same IDREG value, which would cause SPI ID distribution to fail. A validation mechanism is added, whereby the value in an IDREG register can be changed only when a portion of the Chip ID matches..

[0073] An SPI ID of an SPI subnode is mapped to a specific device in a PCB. In some configurations, arbitration in SDO pins may be insufficient because the SPI host device may only determine that a chipset with a given Chip ID is present on the SPI bus (4-wire bus), without determining the specific location of that chipset.

[0074] To resolve such an issue, a priori knowledge of a printed circuit board (PCB) may be added to an SPI frame. For example, each SPI subnode of a group of SPI subnodes in an SPI chain may be distinguished by assigning a distinctive datum to a respective SPI subnode in the group of SPI subnodes. Such distinctive data may then be mapped to respective locations of the SPI subnodes in the group of subnodes.

[0075] The a priori knowledge of the PCB can be used in numerous ways based on configuration of SPI subnodes, in accordance with this disclosure.

[0076] Aspects of this disclosure provide several techniques for serial peripheral interface (SPI) ID distribution to uniquely identify SPI subnodes on a shared bus. These techniques may rely on a priori knowledge of a PCB layout and utilize various hardware configurations to assign unique IDs. For the purposes of the following description, a SPI Device refers to a SPI subnode. The techniques include: Technique A, which utilizes a general-purpose input / output (GPIO) pin configured as a MUTE pin to selectively disable subnodes during ID assignment; Technique B, which leverages an intrinsic, factory-programmed Chip ID to differentiate between subnodes; Technique C, which uses a resistor-capacitor (RC) circuit on a RESETZEN pin to create a time-based differentiation for ID assignment; Technique D, which employsexternal resistors to create unique voltage levels for each subnode, readable via an analog-to-digital converter (ADC); Technique E, which uses a distinct pulse-width modulation (PWM) pattern sent to each subnode to assign an ID; and Technique F, which relies on a daisy-chain connection topology where the serial data out (SDO) of one subnode connects to the serial data in (SDI) of the next, enabling sequential ID assignment.

[0077] Technique A: SPI ID Distribution with MUTE pin

[0078] In cases where a SPI subnode has an individual GPIO connected with the SPI host (or main SPI device, e.g., main SPI device 310 of FIG. 3), one technique for SPI ID distribution uses a MUTE pin. This technique is referred to as “Technique A”. This technique can involve the following steps:A register for a 6-bit ID (IDREG) is configured with part of the Chip ID (RO), the 6- bit SPI ID, the number of SPI Devices in a SPI chain of SPI Devices, and may have other information of PCB location: addressing readIn an INIT state, a functional pin (e.g., RDY, INT, ALERT, GPIO) is switched to a MUTE pin (input for the SPI Device). When the MUTE pin is driven high, the corresponding SPI Device will not respond to either a broadcast or an addressing read frame.A read from the IDREG will get the Chip ID when the SPI ID is equal to 0x00.

[0079] Writing to the IDREG (SPI ID reconfiguration) is performed with the target SPI ID and the number of SPI Devices. The writing operation is valid only when other parts of the IDREG match.

[0080] An ID distribution done operation (IDDONE) releases the MUTE pin and changes the functional pin to the original function after all (or, in some cases, a defined number of) SPI Devices have finished the SPI ID distribution. In some cases, an addressable read frame may then be optionally used for testing the addressable read of each SPI Device in the SPI chain.

[0081] A SPI ID reset command (IDRESET) clears the SPI ID to 0x00 for all SPI Devices in the SPI chain and causes the SPI communication block to return to the INIT state.

[0082] Technique B: SPI ID Distribution with Intrinsic Chip ID

[0083] In another configuration, SPI IDs in a SPI chain of SPI subnodes are initialized differently. A technique for SPI ID distribution can utilize an Intrinsic Chip ID. An illustration of this technique is referred to as “Technique B.” This technique can involve the following steps:(Traverse all SPI ID) A register for a 6-bit ID (IDREG) is configured with part of a Chip ID (read-only), a whole 6-bit SPI ID, a number of SPI Devices in a SPI chain ofSPI Devices, and may have other information such as printed circuit board (PCB) location:In an INIT state, a default SPI ID of each SPI Device is set to the 6 least significant bits (LSB) of the chip ID of the SPI device. An SPI ID order is mapped to the location of the SPI device on a PCB. Such a mapping is implemented as part of a configuration stage that is separate from SPI ID distribution. The LSB is used for purpose of illustration. Other numbers of LSBs can be used.A read from the IDREG provides the Chip ID associated with the SPI ID.

[0084] (Locate SPI Device) A SPI host scans SPI IDs from 0x01 to 0x3F to find available devices on the SPI bus. Writing to the IDREG (SPI ID reconfiguration) is performed with a target SPI ID and a number of SPI Devices. The writing operation is valid only when other parts of the IDREG match.

[0085] Optionally, an addressable read frame is used for testing the addressable read of each SPI Device. This technique can involve the following steps:A SPI ID reset command (IDRESET) clears the SPI ID to the 6 LSB of the chip ID for all SPI Devices and causes the SPI communication block to return to the INIT state. o (SDO arbitration) A register for a 6-bit ID (IDREG) is configured with part of a Chip ID (read-only), a whole 6-bit SPI ID, a number of SPI Devices in the SPI chain, and may have other information such as PCB location (with SDO in OD mode):o In an INIT state, a default SPI ID of each SPI Device is set to the 6 LSB (LSB used for purpose of illustration) of the chip ID for that device. An SPI ID order is mapped to the location of the SPI device on a PCB. Such a mapping is implemented as part of a configuration stage separate from SPI ID distribution. o (Locate SPI Device) A broadcast read is used, and reading from the IDREG provides the Chip ID when the SPI ID is 0x00. During SDO output, a SPI Device reads from SDO; if the output and input mismatch, that SPI Device is muted. In some cases, only one SPI Device can respond at one time.Optionally, use addressable read frame to test the addressable read of each SPI Device. A SPI ID reset command (IDRESET) clears SPI ID = 0x00 and causes the SPI communication block to return to INIT state.

[0086] Technique C: SPI ID Distribution with RC control in RESETZEN pin

[0087] Other techniques use different power-up configurations for SPI ID distribution. One example technique includes using resistive-capacitive (RC) control in a RESETZEN pin. Thefollowing description describes such an example technique. In some implementations, an “EN startup” time may not be accurate. After EN reaches a POR threshold, a SPI Device may generate a pulse on the SDO pin (Initialization with OD mode, a pull-up resistor may be used on the SDO pin) and may then count a number of pulses on the SDO pin within a defined time interval (e.g., 10ms). After the number of pulses has been counted, each SPI Device can configure the initialization SPI ID to correspond to the number of pulses.

[0088] Under Technique C (“SPI ID Distribution with RC control in RESETZEN pin”), the enable / reset (RESETZEN) pin of the SPI device is connected to an RC network. After power rises above a power-on-reset (POR) threshold, the device measures the “EN startup” time, i.e., the rise-time behavior determined by the RC time constant (T = R * C), where R denotes a resistive component and C denotes a capacitive component. Different RC values produce different startup timings, which the SPI devices use to automatically set distinct SPI IDs. This technique can involve the following steps:A register for a 6-bit ID (IDREG) is configured with a part of a Chip ID (RO), a whole 6-bit SPI ID, a number of SPI Devices in the SPI chain, and may have other information of PCB location.In an INIT state, after a voltage battery (VBAT) level rises above a power-on-reset (POR) threshold, SPI Devices start to count an “EN startup” time that a RESETZEN pin reaches the POR threshold.After the “EN startup” times have been counted, SPI Devices automatically set a SPI ID corresponding to the respective “EN startup” times. For example, a first SPI Device in a SPI chain automatically sets a first SPI ID that corresponds to a first “EN startup” time for the first SPI Device, and a second SPI device in the SPI chain automatically sets a second SPI ID that corresponds to a second “EN startup” time for the second SPI device.A SPI host can use the targeted SPI ID to find available devices on a SPI bus.

[0089] Writing to the IDREG (SPI ID reconfiguration) with a target SPI ID and a number of SPI Devices. The writing operation is only valid when remaining portions of the IDREG match.

[0090] A SPI ID reset command (IDRESET) clears the SPI ID associated with the “EN startup” time of all SPI Devices in the SPI chain and causes the SPI communication block to return to an INIT state.

[0091] Technique D: SPI ID Distribution with external resistors

[0092] Another example of techniques based on power-up configuration for SPI ID distribution includes using an analog-to-digital converter (ADC) device, current source device,and external resistor to determine the SPI Device location. The example technique is referred to as “Technique D” .

[0093] An exemplary technique for SPI ID distribution based on a power-up configuration uses an analog-to-digital converter (ADC) device, a current source device, and an external resistor to determine a location of SPI Device. This technique can involve the following steps:A register for a 6-bit ID (IDREG) is configured with a portion of a Chip ID (RO), a 6- bit SPI ID, a number of SPI Devices in the SPI chain of SPI devices, and optionally other information such as a PCB location.In an INIT state, after VBAT rises above a POR threshold, each SPI Device in the SPI chain first activates a respective analog-to-digital converter (ADC) device to measure a target GPIO (ID pin). Each SPI Device then supplies a current from a respective current source device to a respective external resistor and reads back a respective voltage across the respective resistor. For example, a first SPI device in the SPI chain activates a first ADC device integrated into the first SPI device, supplies a first current to a first external resistor coupled with the first SPI device, and reads back a first voltage across the first external resistor. A second SPI device in the SPI chain activates a second ADC device integrated into the second SPI device, supplies a second current to a second external resistor coupled with the second SPI device, and reads back a second voltage across the second external resistor. This sequence of activation and voltage measurement may be repeated for all SPI devices in the SPI chain.After measurement of the respective voltages across the external resistors is completed, each of the SPI Devices automatically sets a respective SPI ID that corresponds to a respective measured voltage.An SPI host can use a targeted SPI ID to find available devices on the SPI bus.

[0094] A write operation to the IDREG (SPI ID reconfiguration) includes a target SPI ID and a number of SPI Devices. The write operation is valid when other portions of the IDREG match.

[0095] An ID distribution done (IDDONE) operation releases the ID pin to a GPIO mode.

[0096] Optionally, an addressable read frame is used to test the addressable read of each SPI Device in the SPI chain.

[0097] An SPI ID reset command (IDRESET) clears an SPI ID associated with the ADC sampled results of a target GPIO, and causes the SPI communication block to return to an INIT state.

[0098] Technique E: SPI ID Distribution with PWM pattern

[0099] Another exemplary technique for SPI ID distribution based on a power-up configuration uses a GPIO to receive a PWM pattern and uses a pulse-width modulation (PWM) frequency, or in some cases a duty cycle, to determine a default SPI ID of the SPI device. This example technique is referred to herein as "Technique E." In Technique E, a PWM generator device may be implemented in a test kit after PCB assembly, and a PWM monitor device may be integrated into an SPI node or multiple SPI subnodes. This technique can involve the following steps:A register for a 6-bit ID (IDREG) configuration may include part of a Chip ID (RO), a 6-bit SPI ID, the number of SPI Devices in the SPI chain of SPI devices, and other information related to PCB location.After the PWM monitor device has been activated, each SPI Device of the SPI Devices automatically sets a respective SPI ID that corresponds to the respective PWM frequency (or duty cycle) of the SPI Device.After the PWM monitor device is activated, each SPI Device of the SPI Devices automatically sets a respective SPI ID that corresponds to a PWM frequency, or duty cycle, associated with the SPI Device.An SPI host can use the targeted SPI ID to find available devices on the SPI bus.

[0100] Writing to the IDREG (SPI ID reconfiguration) includes the target SPI ID and the number of SPI Devices, wherein the write operation is valid when other portions of the IDREG match.

[0101] An ID distribution done (IDDONE) operation releases the PWMIN pin to a GPIO mode. Optionally, use the addressable read frame to test the addressable read of each SPI Device.

[0102] An SPI ID reset command (IDRESET) clears the SPI ID based on the PWM monitor device result from PWMIN and causes the SPI communication block to return to the INIT state.

[0103] Technique F: SPI ID Distribution with Different Load

[0104] Another example of a technique based on a power-up configuration for SPI ID distribution includes supplying, using a test accessorial tool, a different current and / or voltage to each of a plurality of SPI Devices (e.g., SPI subnodes) in a SPI chain of SPI Devices. The technique may further include using an addressed frame to distinguish each SPI Device in the SPI chain. The test accessorial tool may be used for testing functions of a PCB after assembly. For example, if a PCB is or includes an ADC IC or an ADC function, the test accessorial tool can supply a specific voltage to a test point on the PCB and can check whether results are satisfactory. This technique can involve the following steps:A register (IDREG) for a 6-bit ID configuration may include part of a Chip ID (RO), a 6-bit SPI ID, the number of SPI Devices in the SPI chain of SPI Devices, and may include other information related to a PCB location (e.g., with SDO in OD mode). In an INIT state, the default SPI ID of each SPI Device in the SPI chain is 6 LSB of the Chip ID of the SPI Device. The use of LSB is for purposes of illustration.(Map Chip ID with primary SPI ID) A broadcast read from IDREG is used to obtain the Chip ID with SPI ID = 0x00. During SDO output, a SPI Device reads from SDO. If the output and input mismatch, then the SPI Device is muted. In some cases, only one SPI Device can respond at one time.- Writing to the IDREG (SPI ID reconfiguration) uses the primary SPI ID and the number of SPI Devices. The write operation is valid only when other parts of the IDREG match.

[0105] (Locate each SPI Device) Using a test accessorial tool, each SPI Device can be injected with a different current or voltage corresponding to the PCB location of the SPI device. The SPI ID is refreshed to a desired SPI ID for each SPI Device.

[0106] Optionally, an addressable read frame is used to test the addressable read of each SPI Device.

[0107] An SPI ID reset command (IDRESET) clears the SPI ID to 0x00 and causes the SPI communication block to return to the INIT state.

[0108] In summary, these techniques offer a range of solutions for assigning unique SPI IDs in a shared bus environment. By leveraging different hardware features — such as GPIOs, Chip IDs, RC circuits, ADCs, PWM signals, or daisy-chain connections — this disclosure provides flexible and robust methods for SPI ID distribution, ensuring reliable communication and preventing conflicts between subnodes on the same PCB.

[0109] SPI Main Node Writes to SPI Subnodes

[0110] The following disclosure describes various embodiments for Serial Peripheral Interface (SPI) communication between a main node and one or more subnodes. An exemplary broadcast write frame is illustrated in FIG. 8. An exemplary compressed broadcast write frame is illustrated in FIG. 9. An exemplary addressing write frame is illustrated in FIG. 10. An exemplary data writing sequence using compressed broadcast writes is illustrated in FIG. 11.An exemplary data writing sequence combining a broadcast write with an offset is illustrated in FIG. 12. An exemplary broadcast read frame is illustrated in FIG. 13. An exemplary addressing read frame is illustrated in FIG. 14. An exemplary sequence for read operations is illustrated in FIG. 15. An exemplary mixed write and read operation is illustrated in FIG. 16.An exemplary flexible write operation is illustrated in FIG. 17. An exemplary flexible read operation is illustrated in FIG. 18.[OHl] The following description outlines a process for an SPI main node to write data to multiple SPI subnodes (e.g., e-Fuses). An e-Fuse (or electronic fuse) product has an nonvolatile memory that can be programmed once, often used to store permanent data such as configuration settings or security keys. The description details a command and data frame structure for various write operations, including broadcast, compressed broadcast, and addressing writes. Examples demonstrate writing the same data to all subnodes simultaneously and writing different data to unique addresses on individual subnodes by manipulating base addresses and using offsets.

[0112] In an example implementation, an SPI main node writes to eight e-Fuse subnodes on an SPI bus. In this scenario, the SPI frame includes a 5 -bit SPI ID, an 11 -bit command (CMD), and a 16-bit command Packet Error Code (CMD PEC). Eight e-Fuse subnodes are addressed on the SPI bus with SPI IDs ranging from 5’h01 (e-FuseO) to 5’h08 (e-Fuse7).

[0113] General SPI ID mapping (6-bit SPI ID: bits [15:10] of the 16-bit command):0x00 — Broadcast Frame: Used for broadcast operations. May be a Broadcast Read or a Broadcast Write; each SPI device parses / retums DATA and DATA PEC in its slot per the frame definition.0x01-0x3E — Addressed Frame: Unicast to a single, specific SPI subnode. The value selects the target device / address.0x3F — Compressed Broadcast Write Frame: Special broadcast that writes the same DATA value to all (or a defined subset of) devices using a single DATA field.

[0114] Field placement: The SPI ID occupies the six most significant bits of the 16 bit command field.

[0115] Optional extra address bit: In some applications, the CS pin state can serve as an additional bit, effectively making the command “17 bits” for addressing purposes.

[0116] e Fuse illustrative mapping (5-bit SPI ID example used in FIGS. 8-18):0x00 — Broadcast Frame: Broadcast Read / Write targeting all e Fuse subnodes on the bus.0x01-0x08 — Addressed Frame (example set): Unicast to specific e Fuse subnodes e FuseO through e Fuse7.OxlF — Compressed Broadcast Write Frame: Special broadcast that writes the same DATA value to all e Fuses using a single DATA field.Other values (e.g., 0x09-0xlE): Not explicitly defined in the example; behavior is implementation specific within the disclosed framework.

[0117] Context reminders for both schemes:- Broadcast Write (full): Carries distinct DATA+PEC segments for each device, consumed sequentially (last device in a daisy chain first, then upstream).Compressed Broadcast Write: Carries one DATA+PEC that all devices apply to the targeted register.Addressed Read / Write: Only the device whose local ID (in IDREG) matches the SPI ID in the frame processes the DATA phase (others remain high Z on SDO).

[0118] FIG. 8 illustrates an example broadcast write frame 800 for writing different data to multiple subnodes 320. In an embodiment, the broadcast write frame 800 includes a 5-bit Serial Peripheral Interface (SPI) ID field 801, an 11 -bit command (CMD) field 802, and a 16-bit CMD Packet Error Code (PEC) field 803.

[0119] The SPI ID field 801 is set to a broadcast value (e.g., 0x00) to indicate a broadcast write operation targeting all e-Fuses 0-7 on the bus. A broadcast value signals all subnodes 320 to process the incoming command. Upon receiving the broadcast write frame 800, each of the e-Fuses 0-7 validates the SPI ID field 801, CMD field 802, and CMD PEC field 803 to confirm the frame is a valid broadcast write operation before processing the data fields.

[0120] The broadcast write frame 800 further includes eight 48-bit data fields 804-811, each including data and a corresponding data PEC for a specific subnode. Each of the eight data fields 804-811 corresponds to one of the e-Fuses 0-7. Data is written sequentially in a daisychain fashion, starting from the last subnode in the chain (e-Fuse 7) and proceeding to the first subnode (e-Fuse 0).

[0121] For example, data field 804 includes 48 bits for DATA7 and a PEC for DATA7. Upon receipt, e-Fuse 7, the last subnode in the chain, validates DATA7 and the corresponding PEC and writes DATA7 to a target register within e-Fuse 7. Subsequently, the frame shifts, and data field 805, including DATA6 and a PEC for DATA6, is presented to and processed by e-Fuse 6. This sequential process of data validation and writing continues for the remaining e-Fuses down to e-Fuse 0, which processes the last data field.

[0122] FIG. 9 illustrates an example compressed broadcast write frame 900, used for writing the same data to all subnodes 320. In an embodiment, the compressed broadcast write frame 900 includes a 5-bit Serial Peripheral Interface (SPI) ID field 901, an 11 -bit command (CMD) field 902, a 16-bit CMD Packet Error Code (PEC) field 903, a 32-bit DATA0 field 904, and a 16-bit DATA PECO field 905.

[0123] The SPI ID field 901 is set to a specific broadcast value (e.g., OxlF) to indicate a compressed broadcast write operation targeting all e-Fuses 0-7. This value is distinct from the standard broadcast value to signal a compressed operation. Upon receiving the compressed broadcast write frame 900, each of the e-Fuses 0-7 validates the SPI ID, CMD, and CMD PEC fields.

[0124] In contrast to the broadcast write frame 800, the compressed broadcast write frame 900 includes only a single data field (DATA0 904) and a corresponding single data PEC field (DATA PECO 905). This efficient structure allows the same data to be written to all subnodes 320. Each of the e-Fuses 0-7 validates the data in the DATA0 field 904 and the associated DATA PECO field 905 and writes the same data to a target register within each respective e-Fuse.

[0125] FIG. 10 illustrates an example addressing write frame 1000, which is used to write data to a single, specific subnode. In an embodiment, the addressing write frame 1000 includes a 5-bit Serial Peripheral Interface (SPI) identification (ID) field 1001, an 11-bit command (CMD) field 1002, a 16-bit CMD Packet Error Code (PEC) field 1003, a 32-bit data field (DAT A0) 1004, and a 16-bit data PEC field (DATA PECO) 1005.

[0126] The addressing write frame 1000 is directed to a specific e-Fuse by placing the unique address of the subnode in the SPI ID field 1001. To target e-Fuse 0, for example, the SPI ID field 1001 is set to its specific address value, such as 0x01. Upon receipt of the addressing write frame 1000, all e-Fuses 0-7 validate the SPI ID field 1001, the CMD field 1002, and the CMD PEC field 1003. Based on the address included in SPI ID field 1001, only the targeted e-Fuse, in this example e-Fuse 0, proceeds to validate the DAT A0 field 1004 and the DATA PECO field 1005. Following successful validation, e-Fuse 0 writes the contents of the DATA0 field 1004 to a target register within e-Fuse 0, while non-targeted e-Fuses take no further action on the data fields.

[0127] FIG. 11 illustrates an example data writing sequence 1100 for writing data to addresses 0x1234 and 0x1237 for all e-Fuses using compressed broadcast writes. This demonstrates how a base address can be set and then used with an offset for subsequent writes.

[0128] The example sequence 1100 includes: a first compressed broadcast write frame 1110 configured to update a base address to 0x1234 for all e-Fuses; a second compressed broadcast write frame 1120 configured to write data to a register at that base address (0x1234); and a third compressed broadcast write frame 1130 configured to write data to a register at an offset from the base address, resulting in a write to address 0x1237.

[0129] In an e-Fuse subnode, an entire SRAM and Flash may be accessed via SPI. To write data values 0x5555_AAAA and 0xAAAA_5555 to addresses 0x1234 and 0x1237, respectively, for all e-Fuses, an SPI host may perform the following steps:

[0130] Step 1: To update the base address to 0x1234 for all e-Fuses, the SPI host sends a compressed broadcast write frame 1110. The frame 1110 is configured with SPI ID 1111 set to 5’hlF (compressed broadcast), CMD Type 1112 set to 2’b01 (base address operation), CMD Code 1113 set to 0x00 (update base address using DATA field), and DATA 1115 set to the new base address, 0x0000 1234. The CMD PEC (CPEC) 1114 and DATA PEC (DPEC) 1116 are validated by all subnodes 320. The base address for subsequent operations on all e-Fuses is now 0x1234.

[0131] Step 2: To write the first data value to the register at address 0x1234, the SPI host sends a second compressed broadcast write frame 1120. The frame 1120 is configured with SPI ID 1121 set to 5’hlF (compressed broadcast), CMD Type 1122 set to 2’blO (write to targeted address), CMD Code 1123 set to 0x00 (indicating no offset from the base address), and DATA 1125 set to 0x5555_AAAA. The CMD PEC 1124 and DATA PEC 1126 are validated. All e-Fuses write 0x5555_AAAA to address 0x1234.

[0132] Step 3: To write the second data value to the register at address 0x1237, the SPI host sends a third compressed broadcast write frame 1130. The third compressed broadcast write frame 1130 is configured with SPI ID 1131 set to 5’hlF (compressed broadcast), CMD Type 1132 set to 2’blO (write to targeted address), CMD Code 1133 set to 0x03 (representing an offset of 3 from the base address of 0x1234), and DATA 1135 set to 0xAAAA_5555. The CMD PEC 1134 and DATA PEC 1136 are validated. All e-Fuses write 0xAAAA_5555 to the target address 0x1237 (0x1234 + 0x03).

[0133] FIG. 12 illustrates an example data writing sequence 1200 for writing different 32-bit data values to different addresses across the eight e-Fuses in the SPI bus, combining a broadcast write with an offset.

[0134] Step 1: Update the base address for each e-Fuse individually. A first broadcast frame 1210 is sent with SPI ID 1211 set to 0x00 (for all e-Fuses), CMD Type 1212 set to 2’b01 (base address operation), and CMD Code 1213 set to 0x00 (update the base address using the DATA field). The data portion (fields 1215-1221) of the frame includes unique addresses for each e-Fuse: DATA for e-Fuse7 is set to 0x0000_4000, DATA for e-Fuse6 is set to 0x0000_4001, and so on, up to DATA for e-FuseO being 0x0000 4008. After validation of CMD PEC 1204 and DATA PECs, the base address of e-Fuse7 is set to 0x0000_4000, e-Fuse6 to 0x0000_4001, ..., and e-FuseO is now 0x0000_4008.

[0135] Step 2: Write data using a common offset. A second broadcast frame 1250 is sent with SPI ID 1251 set to 0x00, CMD Type 1252 set to 2’blO (write to target address), and CMD Code 1253 set to 0x50 (offset is 0x50). The data portion (fields 1255-1262) includes different data values for each e-Fuse: DATA 1256 for e-Fuse7 is 0xAAAA_AAAA, ..., and DATA 1262 for e-FuseO is OxBBBB BBBB. After PEC 1254 validation, each e-Fuse adds the offset to the unique base address of that e-Fuse. Consequently, the data 0xAAAA_AAAA is written to address 0x4050 (0x4000 + 0x50) of e-Fuse7, and the data OxBBBB BBBB is written to address 0x4058 (0x4008 + 0x50) of e-FuseO.

[0136] Main SPI Device Reads from SPI Subnodes

[0137] FIG. 13 illustrates an example broadcast read frame 1300.

[0138] For this example, consider a scenario with a 5-bit SPI ID 1301 set to 0x00, a 11 -bit command (CMD) 1302 , a 16-bit CMD packet error check (PEC) 1303 , and 8 48-bit DATA and PEC fields (fields 1304-1311). The SPI bus includes eight e-Fuse subnodes, designated e-FuseO through e-Fuse7, with corresponding SPI IDs from 0x01 to 0x08.0x01 (e-FuseO) -0x08 (e-Fuse7) as an example.

[0139] Each of the e-Fuse subnodes (e-FuseO through e-Fuse7) validates the SPI ID, CMD, and CMD PEC, identifying the frame as a broadcast read command. Following validation, the subnodes 320 respond sequentially based on their SPI ID. First, e-FuseO (SPI ID 0x01) responds by driving the DATA and DATA PEC lines (OE=l'bl) while all other subnodes keep their outputs in a high-impedance state. This sequence continues with each subnode responding in order of the SPI ID of the subnode, concluding with e-Fuse7 (SPI ID 0x08) transmitting its DATA and DATA PEC, and so on until e-Fuze7 will respond DATA and DATA PEC with output enable (OE) set to 1’bl. Other e-Fuses keep OE set to 1’bO.

[0140] FIG. 14 illustrates an example of an addressing read frame 1400. In this example, the addressing read frame 1400 facilitates a data access to a specific subnode on the bus, such as the e-FuseO subnode.

[0141] All e-Fuse subnodes on the bus, from e-FuseO through e-Fuse7, receive and check the Serial Peripheral Interface (SPI) ID 1401, the command (CMD) 1402, and the CMD Packet Error Check (CMD PEC) 1403 included within the addressing read frame 1400. The subnodes determine that the frame is an addressing read command specifically for the subnode with the matching SPI ID. In this example, the matching subnode is e-FuseO. Consequently, the addressed subnode, e-FuseO, responds by driving the DATA and DATA PEC lines with the corresponding output enable (OE) signal set to a high state (for example, 1’bl). A 32-bit data payload is included in a DATA0 field 1404, and a 16-bit DATA PECO is included in a DATAPECO field 1405. The other e-Fuse subnodes that are not addressed maintain the respective OE signals for the subnodes in a low state (for example, 1'bO), keeping the outputs of the unaddressed subnodes in a high-impedance state.

[0142] How each subnode determines the frame is for e FuseO(1) Parse the command field.Each subnode latches the incoming command (CMD) 1402 and the CMD PEC 1403, then extracts the SPI ID 1401 (the most significant ID bits; 6 bits in the general description or 5 bits in the e-Fuse examples).2. Validate integrity and type.Verify CMD PEC 1403 .Check CMD Type indicates a read operation (e.g., CMD Type = 2’bll for addressing read in the general scheme).If PEC fails or CMD Type is not a read, the subnode ignores the frame.3. Compare addressed ID to local ID.Each subnode holds its own ID in IDREG (configured by one of the ID distribution techniques).The subnode compares SPI ID in frame to IDREG.For e FuseO, the addressed ID in the frame is the unique value assigned to e FuseO (e.g., 0x01 in the e Fuse example set 0x01-0x08).4. Drive or ignore the data phase based on the match.If SPI ID in frame is set to IDREG, then the subnode is the addressee: the subnode asserts OE = l’b 1 and drives DATA and DATA PEC on serial data out (SDO) for the read response.Otherwise, the subnode remains silent: OE = 1 ’b0 and its SDO output stays high impedance.

[0143] Serial Data Out (SDO): The unidirectional data output pin of an SPI device. On a main SPI device, SDO transmits data to the bus; on a subnode, SDO transmits data from the subnode back toward the main or downstream device, depending on the topology. SPI commonly uses CS (chip select), SCK (serial clock), SDI (serial data in), and SDO (serial data out). Data is shifted on SDO in-sync with SCK and sampled on the SDI of the receiving device.

[0144] FIG. 15 illustrates examples of read operations. In the examples, the read operations are for read address 0x5678 and read address 0x567F for a first e-Fuse subnode (e-FuseO).

[0145] In the e-Fuse of a subnode, a Static Random-Access Memory (SRAM and Flash memory can be accessed via the Serial Peripheral Interface (SPI). To read from address 0x5678and address 0x567F for the first e-Fuse subnode (e-FuseO), an SPI host may perform the following steps:

[0146] Step 1: To update a base address to 0x5678 for the first e-Fuse subnode (e-FuseO), an addressing write frame 1510 is sent with the SPI ID 1511 set to 0x01 (for the first e-Fuse subnode (e-FuseO), CMD Type 1512 set to 2’b01 (for a base address operation), and a CMD Code 1513 set to 0x00 (to update the base address using the DATA field 1515), with the DATA field 1515 set to 0x0000 5678. The CMD PEC 1514 and DATA PEC 1516 should be correct. The base address is now set to 0x5678.

[0147] Step 2: To read from a register with an address equal to 0x5678, an addressing write frame 1520 is sent with the SPI ID 1521 set to 0x01 (for the first e-Fuse subnode (e-FuseO), CMD Type 1522 set to 2’bll (to read from a targeted address), and the CMD Code 1523 set to 0x00 (indicating no offset). The first e-Fuse subnode (e-FuseO) will respond with DATA from the 0x5678 register in the DATA field 1525. The CMD PEC 1524 and DATA PEC 1526 are checked by the first e-Fuse subnode (e-FuseO slave and the SPI host, respectively.

[0148] Step 3 : To read from a register with an address equal to 0x567F, an addressing write frame 1530 is sent with the SPI ID 1531 set to 0x01 (for the first e-Fuse subnode (e-FuseO)), the CMD Type 1532 set to 2’bllto (read from a targeted address), and the CMD Code 1533 set to 0x07 indicating an offset of 0x0. The first e-Fuse subnode (e-FuseO) will respond with DATA from the 0x567F register in the DATA field 1535. The CMD PEC 1534 and DATA PEC 1536 are checked by the first e-Fuse subnode (e-FuseO) and the SPI host, respectively.

[0149] FIG. 16 illustrates an example of a mixed write and read operation for a seventh e-Fuse subnode (e-Fuse7 with register address set to OxABCD).

[0150] The example is directed to reading from a previously written register. For example, for register OxABCD for the seventh e-Fuse subnode (e-Fuse7), the SPI host first writes 0xl234_5678 into the register and then reads 0xl234_5678 from register OxABCD.

[0151] Step 1 : To update a base address to OxABCD for the seventh e-Fuse subnode (e-Fuse7), an addressing write frame 1610 is sent with the SPI ID 1611 set to 0x08 (for the seventh e-Fuse subnode (e-Fuse7)), the CMD Type 1612 set to 2’b01(for a base address operation), and the CMD Code 1613 set to 0x00 (to update the base address using the DATA field 1615), with the DATA field 1615 set to OxOOOO ABCD. The CMD PEC 1614 and DATA PEC 1616 should be correct. The base address is now set to OxABCD.

[0152] Step 2: To write to a register with an address equal to OxABCD, an addressing write frame 1620 is sent with the SPUD 1621 set to 0x08 (for the seventh e-Fuse subnode (e-Fuse7)), the CMD Type 1622 set to 2’blO (to write to a targeted address), and the CMD Code 1623 setto 0x00 (indicating no offset), with the DATA field 1625 set to 0xl234_5678. The CMD PEC 1624 and DATA PEC 1626 should be correct.

[0153] Step 3: To read from a register with an address equal to OxABCD, an addressing read frame 1630 is sent with the SPUD 1631 set to 0x08 (for the seventh e-Fuse subnode (e-Fuse7)), the CMD Type 1632 set to 2’bl Ito (read from a targeted address), and the CMD Code 1633 set to OxOOindicating (no offset). The seventh e-Fuse subnode (e-Fuse7) will respond with DATA from the OxABCD register in the DATA field 1635. The CMD PEC 1634 and DATA PEC 1636 are checked by the seventh e-Fuse subnode (e-Fuse7 subnode and the SPI host, respectively. The SPI host can now check whether the readback data is 0x1234 5678 as expected.

[0154] SPI Master Flexible Write and Read Operations

[0155] A reserved Command Type is utilized to identify a flexible write or a flexible read operation. In such operations, the first 32 bits of the data field are designated as a base address. Subsequent data is then written to or read from a sequence of addresses starting from the base address (e.g., base address, base address + 1, and so on).

[0156] A CMD Code ohOO designates a flexible write frame.

[0157] A CMD Code ohOl designates a flexible read frame.

[0158] FIG. 17 is a diagram illustrating an example of a flexible write operation for an e-Fuse subnode, in this case e-Fuse7 with a base address of 0x11223344.

[0159] In the example of FIG. 17, a flexible write frame 1700 includes an SPI ID 1701 set to 5’h08, a CMD Type 1702 set to 2’b00, and a CMD Code 1703 set to 9’h00. A 16-bit Command Packet Error Check (CPEC) 1704 follows the command fields. The data portion of the frame starts with a base address field 1705 that specifies the 32-bit base address, 32'hll22_3344. A data field 1706 provides a 16-bit Data Packet Error Check (DPEC) for the base address field 1705. The flexible write frame 1700 continues with a data field 1707 including the first 32-bit data value, 32’h5566_7788, to be written to the location specified by the base address. This data value is followed by a field 1708 including a 16-bit DPEC for the data field 1707. Subsequently, a data field 1709 includes the next 32-bit data value, 32’hAABB_CCDD, to be written to the next sequential address (base address + 1), followed by a field 1710 that provides a 16-bit DPEC for the data field 1709.

[0160] FIG. 18 is a diagram illustrating an example of a flexible read operation for an e-Fuse subnode, in this case e-Fuse7 with a base address of 0x11223344.

[0161] In the example of FIG. 18, a flexible read frame 1800 includes an SPI ID 1801 set to 5'h08, a CMD Type 1802 set to 2'b00, and a CMD Code 1803 set to 9'h01. A 16-bit CommandPacket Error Check (CPEC) 1804 follows the command fields. The flexible read frame continues with a base address field 1805 that specifies the 32-bit base address for the read operation, 32'hl 122 3344. A field 1806 provides a 16-bit Data Packet Error Check (DPEC) for the base address field 1805. The frame is followed by a response from the subnode, which includes a field 1807 including the first 32-bit data value (DAT A0) read from the base address and a corresponding 16-bit PEC. Subsequently, a field 1808 includes the next 32-bit data value (DATA1) read from the next sequential address (base address + 1) and a corresponding 16-bit PEC (PEC1).

[0162] The main SPI device 310 or the SPI subnodes 320 may be configured to perform the methods. It is noted that the blocks of the flowchart of FIG. 19 are mandatory, while the blocks of the remaining flowcharts are optional. The flowcharts illustrate mandatory blocks using solid lines and optional blocks using dashed lines. The main SPI device 310 can be configured to perform the method steps of providing the SPI devices and coupling the main SPI device 310 with the subnodes. The subnodes 320 may be configured to determine the SPI ID through various mechanisms.

[0163] FIG. 19 illustrates a flowchart of an example method 1900 for a system in accordance with aspects of the disclosure.

[0164] At block 1905, method 1900 includes providing a plurality of serial peripheral interface (SPI) devices including a main SPI device 310 and a plurality of SPI subnodes 320. The main SPI device 310 communicates with multiple SPI subnodes 320. A unique SPI identifier (ID) is assigned to each SPI subnode 320. This assignment may occur through various mechanisms such as measuring a PWM signal, a GPIO voltage, or an RC time constant. The system architecture supports daisy-chain configurations or parallel connections via a 4-wire bus.

[0165] At block 1910, method 1900 includes coupling the main SPI device 310 with each one of the plurality of SPI subnodes 320 via a 4-wire bus. The 4-wire bus comprises a chip select (CS) line, a serial clock (SCK) line, a serial data out (SDO) line, and a serial data in (SDI) line. The CS pin of the main SPI device 310 connects to the CS pins of the SPI subnodes 320. The SCK pin connects to the subnode SCK pins , and the main SDO pin connects to the subnode SDI pins. The main SDI pin connects to the subnode SDO pins, which are configured in an open-drain arrangement.

[0166] FIG. 20 illustrates a flowchart of an example method 2000 for a system in accordance with aspects of the disclosure.

[0167] At block 2005, method 2000 includes determining the SPI ID 601 based on a frequency or a duty cycle of a pulse-width modulation (PWM) signal. A PWM signal is provided to theSPI subnode 320. The SPI subnode 320 measures the characteristics of the PWM signal. The frequency or duty cycle measurement is then mapped to a specific SPI ID. This allows for dynamic assignment of identifiers without requiring pre-programming of each device. A PWM generator device may be implemented in a test kit after PCB assembly, and a PWM monitor device may be integrated into an SPI node or multiple SPI subnodes.

[0168] At block 2010, method 2000 includes measuring a voltage on a general -purpose input / output (GPIO) pin. A voltage divider circuit generates a specific voltage level. This voltage is applied to a GPIO pin of the SPI subnode. The internal analog-to-digital converter (ADC) of a subnode measures the voltage. The measured voltage level corresponds to a predefined SPI ID 205.

[0169] At block 2015, method 2000 includes measuring a startup time corresponding to a time constant of a resistor-capacitor (RC) network. An RC network is connected to a pin of the SPI subnode. Upon power-up, the capacitor in the RC network begins to charge. The subnode measures the time taken for the voltage to cross a certain threshold. This measured time, determined by the RC time constant, is used to assign the SPI ID.

[0170] At block 2020, method 2000 includes receiving the SPI ID 601 after an arbitration process. Multiple SPI subnodes may attempt to claim an SPI ID simultaneously. The arbitration process, managed by the main SPI device 310, resolves these conflicts. Each subnode listens for activity on the bus before transmitting an ID request. The main SPI device 310 then grants SPI IDs sequentially to the SPI subnodes 320.

[0171] At block 2025, method 2000 includes reading a pre-programmed non-volatile memory. The SPI ID is stored in a non-volatile memory location within the subnode. This preprogramming is typically done during the manufacturing or system assembly process. During initialization, the subnode reads this stored value from the memory of the subnode. This ensures a permanent and unique identifier for each subnode.

[0172] At block 2030, method 2000 includes determining the SPI ID 601 based on a daisychain position. For pre-programmed memory, the SPI ID is stored in a non-volatile memory location within the subnode, which is read during initialization. In a daisy-chain configuration, the main SPI device 310 sends a signal through the chain of subnodes 320. The position of a subnode within this chain determines the assigned SPI ID. The first subnode receives the signal first and takes the first ID, and so on.

[0173] FIG. 21 illustrates a flowchart of an example method 2100 for a system in accordance with aspects of the disclosure.pe 14092PC00APD10172PCT01

[0174] At block 2105, method 2100 includes coupling a chip select (CS) pin of the main SPI device 310 to CS pins of the plurality of SPI subnodes 320. This connection enables the main SPI device 310 to individually address and select a specific subnode for communication. Each subnode is connected to a dedicated CS line from the main SPI device 310. To initiate communication with a particular subnode, the main SPI device 310 asserts the corresponding CS line, typically by pulling the CS line to a low logic level. This active-low signal informs the selected subnode to listen for incoming clock and data signals. All other subnodes with their CS lines inactive will ignore the bus activity, preventing data conflicts. This individual chip select method ensures that only the intended subnode responds to the commands and data transfers of the main SPI device 310.

[0175] At block 2110, method 2100 includes coupling a serial clock (SCK) pin of the main SPI device 310 to SCK pins of the plurality of SPI subnodes 320. This shared clock line synchronizes the data transfer between the main SPI device 310 and all connected subnodes 320. The main SPI device 310 generates the clock signal, which dictates the timing for when data bits are transmitted and received. The SCK signal ensures that both the main SPI device 310 and the selected subnode sample the data lines at the same moments. The frequency of the SCK signal determines the data transfer rate of the SPI bus. The polarity and phase of the clock, configured in both the main SPI device 310 and subnodes 320, define the specific edge (rising or falling) on which data is latched.

[0176] At block 2115, method 2100 includes coupling a serial data out (SDO) pin of the main SPI device 310 to serial data in (SDI) pins of the plurality of SPI subnodes 320. This connection forms the data path for transmitting information from the main SPI device 310 to the subnodes 320. When the main SPI device 310 sends data, it places bits sequentially onto the SDO line, synchronized with the SCK clock pulses. All subnodes 320 are connected to this common data line, allowing them to receive the same data stream simultaneously in a broadcast fashion. However, only the subnode whose CS pin is currently asserted will process the incoming data on its SDI pin. This configuration allows for write operations and sending commands to specific or multiple subnodes 320. The data is transmitted one bit per clock cycle.

[0177] At block 2120, method 2100 includes coupling a serial data in (SDI) pin of the main SPI device 310 to SDO pins of the plurality of SPI subnodes 320. This establishes the return data path, allowing subnodes 320 to transmit data back to the main SPI device 310. When the main SPI device 310 initiates a read operation, the selected subnode places its data bits onto its SDO pin, which is connected to the SDI pin of the main SPI device 310. Since the SDO pins of all subnodes 320 are typically connected together, they must be in a high-impedance (tristate) mode when not selected. Only the subnode with its CS pin asserted will actively drive the SDO line of that subnode. This prevents bus contention and ensures that the main SPI device 310 receives data from only one subnode at a time. The main SPI device 310 reads the incoming bits on its SDI pin in synchronization with the SCK clock it generates.

[0178] FIG. 22 illustrates a flowchart of an example method 2200 for an SPI communication frame in accordance with aspects of the disclosure.

[0179] At block 2205, method 2200 includes providing an SPI communication frame with a command field comprising subfields for a frame identifier, command type, and command code. The command field includes a 5-bit SPI ID field 801 and an 11 -bit command (CMD) field 802. The 11 -bit command field 802 includes a 2 -bit command type (CMD Type) and a 9-bit command code (CMD Code) . The SPI ID field 801 identifies the target subnode or a broadcast type. The CMD Type specifies the operation category, such as write, read, or mixed operations. The CMD Code details the specific command within that category.

[0180] At block 2220, method 2200 includes using the most significant bits of the command field 802 to define the address of an SPI subnode. In this addressing scheme, the command field is repurposed to embed the address of a subnode, which can be particularly useful in systems where a dedicated SPI ID field is not present or when a more flexible addressing mechanism is needed. For example, a portion of the 11 -bit command field, typically the higher-order bits, can be allocated to represent the subnode address. The remaining lower-order bits of the command field would then specify the actual command or operation to be performed. This allows for a compact frame structure where both address and command information are encoded within a single field. The subnodes in the system would be configured to parse this command field, extracting the address bits to determine if the subnodes are the intended target before executing the specified command.

[0181] FIG. 23 illustrates a flowchart of an example method 2300 for SPI write operations in accordance with aspects of the disclosure.

[0182] At block 2305, method 2300 includes writing different data values to different subnodes 320 using a single broadcast write frame 800. The broadcast write frame 800 includes a sequence of data fields, each intended for a different subnode. Each of the subnodes 320 is preconfigured to know which data packet in the sequence belongs to it. For example, subnode 0 takes the first data packet, subnode 1 takes the second data packet, and so on. This enables parallel configuration of multiple SPI devices with unique values.

[0183] At block 2310, method 2300 includes writing a same data value to multiple subnodes 320 using a single compressed broadcast write frame 900. The main SPI device 310 transmitsa compressed broadcast write frame 900. This frame 900 includes only one data value field 904. All receiving SPI subnodes 320 read this single data value and write the value to a specified memory address. This method is efficient for initializing multiple SPI devices with the same configuration parameter.

[0184] At block 2315, method 2300 includes writing a data value to a single specific subnode identified by an address in an addressing write frame 1000. An addressing write frame 1000 is used for this operation. The command field includes the SPI ID field 1001 of the target subnode. Only the subnode whose ID matches the SPI ID field 1001 in the frame will process the command and write the accompanying data. Other subnodes on the bus ignore the frame.

[0185] FIG. 24 illustrates a flowchart of an example method 2400 for SPI read operations in accordance with aspects of the disclosure. The SPI read operations vary in transmitting either a broadcast read frame or an addressing read frame to cause either a plurality of SPI subnodes 320 or a specific SPI subnode to respond with data.

[0186] At block 2405, method 2400 includes transmitting a broadcast read frame 1300, causing a plurality of SPI subnodes 320 to respond sequentially with data. The main SPI device 310 sends a broadcast read frame 1300. In response, each SPI subnode 320 transmits its data onto the shared SDO line in a designated time slot. Subnode 0 responds first with data, followed by subnode 1 with data, and so on. This allows the main SPI device 310 to collect status information from all SPI subnodes 320 in a single transaction.

[0187] At block 2410, method 2400 includes transmitting an addressing read frame 1400, causing only a specific SPI subnode to respond with data. The main SPI device 310 transmits an addressing read frame 1400. This frame includes the SPI ID 1401 of the target subnode. Only the subnode with the matching ID will respond by sending data from the matching subnode back to the main SPI device 310. All other SPI subnodes remain silent on the SDO line.

[0188] FIG. 25 illustrates a flowchart of an example method 2500 for operations involving a base address and an offset, in accordance with aspects of the disclosure.

[0189] At block 2505, method 2500 includes writing a data value to a memory location determined by the base address and an offset from a subsequent write frame.

[0190] At block 2505, method 2500 includes writing a data value to a memory location determined by the base address and an offset from a subsequent write frame. First, a write frame 1110 is transmitted from the main SPI node to a SPI subnode to set a base address in a specific register of the SPI subnode. This establishes a reference point in the memory of the subnode. Following this, a second write frame 1120 is sent from the main SPP node to the SPIsubnode, which includes an offset value and the data to be written. The internal logic of the subnode then calculates the final memory address by adding the offset from the second write frame 1120 to the stored base address. The data from the second write frame 1120 is then written to this computed address. This two-step process allows for flexible memory access by decoupling the base location from the specific register being targeted.

[0191] At block 2510, method 2500 includes setting unique base addresses for multiple SPI subnodes 320 and then writing data based on a common offset. This operation begins by individually addressing each subnode to load a unique base address into a respective register of the subnode by a frame 1210. For instance, subnode A might be assigned a base address pointing to its configuration block, while subnode B is assigned a base address for its status block. Once all SPI subnodes 320 have their unique base addresses configured, a single broadcast write frame 1250 is sent. The single broadcast write frame 1250 includes a common offset and a data value. Each subnode receives this broadcast and independently calculates a target address by adding the common offset to its unique base address, writing the data to that location. This method enables synchronized updates to corresponding registers across a group of SPI subnodes 320 in a single transaction.

[0192] At block 2515, method 2500 includes reading data from a memory location determined by the base address and an offset from a subsequent read frame. Similar to the write operation, this process starts by sending a frame to set the base address in the memory of the target subnode. This pre-configures the starting point for the read operation. Subsequently, a second frame, an addressing read frame, is transmitted to the same subnode. This frame specifies an offset value, indicating which memory location to read relative to the established base address. The subnode computes the final address by summing the base address and the offset. The subnode then retrieves the data from this calculated address and transmits the data back to the main SPI device 310. This provides a flexible mechanism to query different data points within a larger memory region without repeatedly sending the full address.

[0193] FIG. 26 illustrates a flowchart of an example method 2500 for operations involving writing and reading using a base address, in accordance with aspects of the disclosure.

[0194] At block 2605, method 2600 includes using a flexible write frame 1700 including a base address and data to write from sequential memory locations starting at the base address. A flexible write frame 1700 is transmitted from the SPI main node to a SPI subnode. The flexible write frame 1700 includes a base address field 1705 and a sequence of data values specified in data field 1707 and data field 1709. The subnode writes the first data value specified in data field 1707 to the location specified by the base address field 1705. Subsequentdata values as specified in data field 1709 are written to sequentially increasing memory addresses (base address + 1, base address + 2, etc.). This allows for efficient block data transfers.

[0195] At block 2610, method 2600 includes using a flexible read frame 1800 including a base address to read data from sequential memory locations starting at the base address. A flexible read frame 1800 is sent from the SPI main node to a targeted SPI subnode, which includes a command field and a base address field 1805. The targeted SPI subnode responds with a sequence of data values. The first data value, specified in field 1807, is read from the base address, the second data value, specified in field 1808, is read from the next sequential address (base address + 1), and so on. This enables efficient reading of a contiguous block of memory.

[0196] At block 2615, method 2600 includes using mixed write-read frames 1600 to perform a write operation followed by a read operation within a single chip select assertion. Mixed write-read frames 1600 are transmitted from the main SPI device 310. Mixed write-read frames 1600 include data to be written. After processing the write portion, the targeted subnode immediately responds with read data on the SDO line without the CS line being de-asserted and re-asserted. This reduces communication overhead for atomic read-modify-write sequences.

[0197] Various aspects of the present disclosure are set forth regarding the following clauses.

[0198] Clause 1. A system, comprising: a plurality of serial peripheral interface (SPI) devices including a main SPI device and a plurality of SPI subnodes, wherein the main SPI device is coupled with each one of the plurality of SPI subnodes via a 4-wire bus.

[0199] Clause 2. The system of clause 1, wherein each SPI subnode of the plurality of SPI subnodes is coupled with another SPI subnode of the plurality of SPI subnodes via the 4-wire bus.

[0200] Clause 3. The system of any preceding clauses, wherein a chip select (CS pin of the main SPI device is coupled with a CS pin of a first SPI subnode of the plurality of SPI subnodes and a CS pin of a second SPI subnode of the plurality of SPI subnodes.

[0201] Clause 4. The system of any preceding clauses, wherein a serial clock (SCK pin of the main SPI device is coupled with a SCK pin of the first SPI subnode and a SCK pin of the second SPI subnode.

[0202] Clause 5. The system of any preceding clauses, wherein a serial data out (SDO pin of the main SPI device is coupled with a serial data in (SDI) pin of the first SPI subnode and an SDI pin of the second SPI subnode.

[0203] Clause 6. The system of any preceding clauses, wherein an SDI pin of the main SPI device is coupled with an SDO pin of the first SPI subnode and an SDO pin of the second SPI subnode.

[0204] Clause 7. The system of any preceding clauses, wherein an SPI communication frame comprises a command field including a first subfield defining a configurable frame identifier, a second subfield defining a command type, and a third subfield defining a command code.

[0205] Clause 8. The system of any preceding clauses, wherein the configurable frame identifier spans six bits that define one of an addressed frame or a type of broadcast frame corresponding to the SPI communication frame.

[0206] Clause 9. The system of any preceding clauses, wherein a first value of the configurable frame identifier defines a standard broadcast frame, a second value of the configurable frame identifier defines a compressed broadcast write frame, and third values of the configurable frame identifier define an addressed frame corresponding to respective SPI subnodes of the plurality of SPI subnodes.

[0207] Clause 10. The system of any preceding clauses, wherein the command field spans 16 bits, with six most significant bits of the 16 bits defining an address of an SPI subnode of the plurality of SPI subnodes.

[0208] Clause 11. The system of any preceding clauses, wherein the SPI communication frame comprises a broadcast write frame configured to write a first data value to a first subnode of the plurality of SPI subnodes and a second data value, different from the first data value, to a second subnode of the plurality of SPI subnodes in a single frame.

[0209] Clause 12. The system of any preceding clauses, wherein the SPI communication frame comprises a compressed broadcast write frame configured to write a same data value to at least two subnodes of the plurality of SPI subnodes in a single frame.

[0210] Clause 13. The system of any preceding clauses, wherein the SPI communication frame comprises an addressing write frame configured to write a data value to a single specific subnode of the plurality of SPI subnodes, the single specific subnode being identified by an address in the addressing write frame.

[0211] Clause 14. The system of any preceding clauses, wherein the main SPI device is configured to transmit a write frame to set a base address in at least one SPI subnode of the plurality of SPI subnodes for one or more subsequent data access operations.

[0212] Clause 15. The system of any preceding clauses, wherein the main SPI device is further configured to transmit a subsequent write frame including an offset and a data value, whereinthe at least one SPI subnode writes the data value to a memory location determined by the base address and the offset.

[0213] Clause 16. The system of any preceding clauses, wherein the main SPI device is configured to transmit a sequence of broadcast write frames to set a unique base address for each of a plurality of the SPI subnodes, and subsequently transmit a write frame with a common offset, causing each of the plurality of SPI subnodes to write data to an address based on its unique base address and the common offset.

[0214] Clause 17. The system of any preceding clauses, wherein the main SPI device is configured to transmit a broadcast read frame, and wherein each of the plurality of SPI subnodes responds sequentially with data during a single chip select assertion.

[0215] Clause 18. The system of any preceding clauses, wherein the main SPI device is configured to transmit an addressing read frame that includes an address of a specific SPI subnode, and wherein only the specific SPI subnode responds with data.

[0216] Clause 19. The system of any preceding clauses, wherein the main SPI device is further configured to transmit a subsequent read frame including an offset, wherein the at least one SPI subnode reads data from a memory location determined by the base address and the offset and transmits read data to the main SPI device.

[0217] Clause 20. The system of any preceding clauses, wherein the main SPI device is configured to transmit a mixed write-read frame to a specific SPI subnode, the mixed writeread frame causing the specific SPI subnode to first write provided data to a specified address and then read data from a second specified address within a single chip select assertion.

[0218] Clause 21. The system of any preceding clauses, wherein the SPI communication frame is a flexible write frame that includes a base address and one or more data values, wherein a receiving SPI subnode writes the one or more data values to memory locations starting at the base address.

[0219] Clause 22. The system of any preceding clauses, wherein the SPI communication frame is a flexible read frame that includes a base address, wherein a receiving SPI subnode reads one or more data values from memory locations starting at the base address and transmits the one or more data values to the main SPI device.

[0220] Clause 23. The system of any preceding clauses, wherein at least one SPI device of the plurality of SPI devices is configured to perform operations for assigning an SPI identifier (ID) to the at least one SPI device based on a power-up configuration.

[0221] Clause 24. The system of any preceding clauses, wherein the operations for assigning the SPI ID comprise determining the SPI ID based on a frequency or a duty cycle of a pulsewidth modulation (PWM) signal received on an input pin of the at least one SPI device.

[0222] Clause 25. The system of any preceding clauses, wherein the operations for assigning the SPI ID comprise: upon power-up, measuring, via an anal og-to-digi tai converter (ADC) of the at least one SPI device, a voltage on a general-purpose input / output (GPIO) pin coupled to an external resistor to determine the SPI ID.

[0223] Clause 26. The system of any preceding clauses, wherein the operations for assigning the SPI ID comprise: upon power-up, measuring a startup time corresponding to a time constant of a resistor-capacitor (RC) network coupled to an enable pin of the at least one SPI device to determine the SPI ID.

[0224] Clause 27. The system of any preceding clauses, wherein the operations for assigning the SPI ID comprise: upon power-up, receiving the SPI ID from the main SPI device on a serial data input (SDI) pin of the at least one SPI device, wherein prior to receiving the SPI ID, the at least one SPI device participates in an arbitration process on a serial data out (SDO) bus.

[0225] Clause 28. The system of any preceding clauses, wherein the operations for assigning the SPI ID comprise: upon power-up, reading a pre-programmed SPI non-volatile memory serial data in (SDI) pin of the at least one SPI device.

[0226] Clause 29. The system of any preceding clauses, wherein the operations for assigning the SPI ID comprise: upon power-up, determining the SPI ID based on a daisy-chain position of the at least one SPI device relative to other SPI devices in a daisy-chain configuration.

[0227] Clause 30. A method, comprising: providing a plurality of serial peripheral interface (SPI) devices including a main SPI device and a plurality of SPI subnodes; and coupling the main SPI device with each one of the plurality of SPI subnodes via a 4-wire bus.

[0228] Various aspects of the disclosure may take the form of an entirely or partially hardware aspect, an entirely or partially software aspect, or a combination of software and hardware. Furthermore, as described herein, various aspects of the disclosure (e.g., systems and methods) may take the form of a computer program product comprising a computer-readable non-transitory storage medium having computer-accessible instructions (e.g., computer-readable and / or computer-executable instructions) such as computer software, encoded or otherwise embodied in such storage medium. Those instructions can be read or otherwise accessed and executed by one or more processors to perform or permit the performance of the operations described herein. The instructions can be provided in any suitable form, such as source code,compiled code, interpreted code, executable code, static code, dynamic code, assembler code, combinations of the foregoing, and the like. Any suitable computer-readable non-transitory storage medium may be utilized to form the computer program product. For instance, the computer-readable medium may include any tangible non-transitory medium for storing information in a form readable or otherwise accessible by one or more computers or processor(s) functionally coupled thereto. Non-transitory storage media can include read-only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory, and so forth.

[0229] Aspects of this disclosure are described herein with reference to block diagrams and flowchart illustrations of methods, systems, devices, and apparatuses. It can be understood that each block of the block diagrams and flowchart illustrations, and combinations of blocks in the block diagrams and flowchart illustrations, respectively, can be implemented by processor-accessible instructions (e.g., processor-readable instructions and / or processor-executable instructions. In certain implementations, the processor-accessible instructions may be loaded or otherwise incorporated into a general purpose computer, a special purpose computer, or another programmable information processing apparatus to produce a particular machine, such that the operations or functions specified in the flowchart block or blocks can be implemented in response to execution at the computer or processing apparatus.

[0230] Unless otherwise expressly stated, it is in no way intended that any protocol, procedure, process, or method set forth herein be construed as requiring that its acts or steps be performed in a specific order. Accordingly, where a process or method claim does not actually recite an order to be followed by its acts or steps or it is not otherwise specifically recited in the claims or descriptions of the subject disclosure that the steps are to be limited to a specific order, it is in no way intended that an order be inferred, in any respect. This holds for any possible nonexpress basis for interpretation, including: matters of logic with respect to the arrangement of steps or operational flow; plain meaning derived from grammatical organization or punctuation; the number or type of aspects described in the specification or annexed drawings; or the like.

[0231] As used in this disclosure, including the annexed drawings, the term “component” “module,” “system,” and the like are intended to refer to a computer-related entity or an entity related to an apparatus with one or more specific functionalities. The entity can be either hardware, a combination of hardware and software, software, or software in execution. One or more of such entities are also referred to as “functional elements.” As an example, a component can be a process running on a processor, a processor, an object, an executable, a thread ofexecution, a program, and / or a computer. For example, both an application running on a server or network controller, and the server or network controller can be a component. One or more components can reside within a process and / or thread of execution, and a component can be localized on one computer and / or distributed between two or more computers. Also, these components can be executed from various computer readable media having various data structures stored thereon. The components can communicate via local and / or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and / or across a network such as the Internet with other systems via the signal). As another example, a component can be an apparatus with specific functionality provided by mechanical parts operated by electric or electronic circuitry, which parts can be controlled or otherwise operated by program code executed by a processor. As yet another example, a component can be an apparatus that provides specific functionality through electronic components without mechanical parts, the electronic components can include a processor to execute program code that provides, at least partially, the functionality of the electronic components. As still another example, interface(s) can include I / O components or Application Programming Interface (API) components. While the foregoing examples are directed to aspects of a component, the exemplified aspects or features also apply to a system, module, and similar.

[0232] In addition, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless specified otherwise, or clear from context, “X employs A or B” is intended to mean any of the natural inclusive permutations. That is, if X employs A; X employs B; or X employs both A and B, then “X employs A or B” is satisfied under any of the foregoing instances. Moreover, articles “a” and “an” as used in this specification and should be construed to mean “one or more” unless specified otherwise or clear from context to be directed to a singular form.

[0233] In addition, the terms “example” and “such as” are utilized herein to mean serving as an instance or illustration. Any aspect or design described herein as an “example” or referred to in connection with a “such as” clause is not necessarily to be construed as preferred or advantageous over other aspects or designs described herein. Rather, use of the terms “example” or “such as” is intended to present concepts in a concrete fashion. The terms “first,” “second,” “third,” and so forth, as used in the claims and description, unless otherwise clear by context, is for clarity only and does not necessarily indicate or imply any order in time or space.

[0234] The term “processor,” as utilized in this disclosure, can refer to any computing processing unit or device comprising processing circuitry that can operate on data and / orsignaling. A computing processing unit or device can include, for example, single-core processors; single-processors with software multithread execution capability; multi-core processors; multi-core processors with software multithread execution capability; multi-core processors with hardware multithread technology; parallel platforms; and parallel platforms with distributed shared memory. Additionally, a processor can include an integrated circuit, an application specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), a discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. In some cases, processors can exploit nano-scale architectures, such as molecular and quantumdot based transistors, switches and gates, in order to optimize space usage or enhance performance of user equipment. A processor may also be implemented as a combination of computing processing units.

[0235] In addition, terms such as “store,” “data store,” data storage,” “database,” and substantially any other information storage component relevant to operation and functionality of a component, refer to “memory components,” or entities embodied in a “memory” or components comprising the memory. The memory components described herein can be either volatile memory or nonvolatile memory or can include both volatile and nonvolatile memory. Moreover, a memory component can be removable or affixed to a functional element (e.g., device, server).

[0236] Simply as an illustration, nonvolatile memory can include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM), which acts as external cache memory. By way of illustration and not limitation, RAM is available in many forms such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), and direct Rambus RAM (DRRAM). Additionally, the disclosed memory components of systems or methods herein are intended to comprise, without being limited to comprising, these and any other suitable types of memory.

[0237] Various aspects described herein can be implemented as a method, device, system, apparatus, or article of manufacture using standard programming and / or engineering techniques. In addition, various of the aspects disclosed herein also can be implemented by means of program modules or other types of computer program instructions stored in a memorydevice and executed by a processor, or other combination of hardware and software, or hardware and firmware. Such program modules or computer program instructions can be loaded onto a general-purpose computer, a special purpose computer, or another type of programmable data processing apparatus to produce a machine, such that the instructions which execute on the computer or other programmable data processing apparatus create a means for implementing the functionality of disclosed herein.

[0238] The term “article of manufacture” as used herein is intended to encompass a computer program accessible from any computer-readable device, carrier, or media. For example, computer readable media can include but are not limited to magnetic storage devices (e.g., hard drive disk, floppy disk, magnetic strips, or similar), optical discs (e.g., compact disc (CD), digital versatile disc (DVD), Blu-ray disc (BD), or similar), smart cards, and flash memory devices (e.g., card, stick, key drive, or similar).

[0239] What has been described above includes examples of one or more aspects of the disclosure. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing these examples, and it can be recognized that many further combinations and permutations of the present aspects are possible. Accordingly, the aspects disclosed and / or claimed herein are intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the detailed description and the appended claims. Furthermore, to the extent that one or more of the terms “includes,” “including,” “has,” “have,” or “having” is used in either the detailed description or the claims, such term is intended to be inclusive in a manner similar to the term “comprising” as “comprising” is interpreted when employed as a transitional word in a claim.

Claims

CLAIMS1. A system, comprising:a plurality of serial peripheral interface (SPI) devices including a main SPI device and a plurality of SPI subnodes,wherein the main SPI device is coupled with each one of the plurality of SPI subnodes via a 4-wire bus.

2. The system of claim 1, wherein each SPI subnode of the plurality of SPI subnodes is coupled with another SPI subnode of the plurality of SPI subnodes via the 4-wire bus.

3. The system of claim 1 or 2, wherein a chip select (CS) pin of the main SPI device is coupled with a CS pin of a first SPI subnode of the plurality of SPI subnodes and a CS pin of a second SPI subnode of the plurality of SPI subnodes.

4. The system of claim 3, wherein a serial clock (SCK) pin of the main SPI device is coupled with a SCK pin of the first SPI subnode and a SCK pin of the second SPI subnode.

5. The system of claim 4, wherein a serial data out (SDO) pin of the main SPI device is coupled with a serial data in (SDI) pin of the first SPI subnode and an SDI pin of the second SPI subnode.

6. The system of claim 5, wherein an SDI pin of the main SPI device is coupled with an SDO pin of the first SPI subnode and an SDO pin of the second SPI subnode.

7. The system of any of claims 1 to 6, wherein an SPI communication frame comprises a command field including a first subfield defining a configurable frame identifier, a second subfield defining a command type, and a third subfield defining a command code sent from the main SPI device to one of more of the plurality of SPI subnodes.

8. The system of claim 7, wherein the configurable frame identifier spans six bits that define one of an addressed frame or a type of broadcast frame corresponding to the SPI communication frame.

9. The system of claim 8, wherein a first value of the configurable frame identifier defines a standard broadcast frame, a second value of the configurable frame identifier defines a compressed broadcast write frame, and third values of the configurable frame identifier define an addressed frame corresponding to respective SPI subnodes of the plurality of SPI subnodes.

10. The system of any of claims 7 to 9, wherein the command field spans 16 bits, with six most significant bits of the 16 bits defining an address of an SPI subnode of the plurality of SPI subnodes.

11. The system of any of claims 7 to 10, wherein the SPI communication frame comprises a broadcast write frame configured to write a first data value to a first subnode of the plurality of SPI subnodes and a second data value, different from the first data value, to a second subnode of the plurality of SPI subnodes in a single frame.

12. The system of any of claims 7 to 11, wherein the SPI communication frame comprises a compressed broadcast write frame configured to write a same data value to at least two subnodes of the plurality of SPI subnodes in a single frame.

13. The system of any of claims 7 to 12, wherein the SPI communication frame comprises an addressing write frame configured to write a data value to a single specific subnode of the plurality of SPI subnodes, the single specific subnode being identified by an address in the addressing write frame.

14. The system of any of claims 7 to 13, wherein the main SPI device is configured to transmit a write frame to set a base address in at least one SPI subnode of the plurality of SPI subnodes for one or more subsequent data access operations.

15. The system of claim 14, wherein the main SPI device is further configured to transmit a subsequent write frame including an offset and a data value, wherein the at least one SPI subnode writes the data value to a memory location determined by the base address and the offset.

16. The system of any of claims 7 to 15, wherein the main SPI device is configured to transmit a sequence of broadcast write frames to set a unique base address for each of a plurality of the SPI subnodes, and subsequently transmit a write frame with a common offset, causing each of the plurality of SPI subnodes to write data to an address based on its unique base address and the common offset.

17. The system of any of claims 7 to 16, wherein the main SPI device is configured to transmit a broadcast read frame, and wherein each of the plurality of SPI subnodes responds sequentially with data during a single chip select assertion.

18. The system of any of claims 7 to 17, wherein the main SPI device is configured to transmit an addressing read frame that includes an address of a specific SPI subnode, and wherein only the specific SPI subnode responds with data.

19. The system of any of claims 14 or 15, wherein the main SPI device is further configured to transmit a subsequent read frame including an offset, wherein the at least one SPI subnode reads data from a memory location determined by the base address and the offset and transmits read data to the main SPI device.

20. The system of any of claims 7 to 19, wherein the main SPI device is configured to transmit a mixed write-read frame to a specific SPI subnode, the mixed writeread frame causing the specific SPI subnode to first write provided data to a specified address and then read data from a second specified address within a single chip select assertion.

21. The system of any of claims 7 to 20, wherein the SPI communication frame is a flexible write frame that includes a base address and one or more data values, wherein a receiving SPI subnode writes the one or more data values to memory locations starting at the base address.

22. The system of any of claims 7 to 21, wherein the SPI communication frame is a flexible read frame that includes a base address, wherein a receiving SPI subnode reads one or more data values from memory locations starting at the base address and transmits the one or more data values to the main SPI device.

23. The system of any of claims 1 to 22, wherein at least one SPI device of the plurality of SPI devices is configured to perform operations for assigning an SPI identifier (ID) to the at least one SPI device based on a power-up configuration.

24. The system of claim 23, wherein the operations for assigning the SPI ID comprise determining the SPI ID based on a frequency or a duty cycle of a pulse-width modulation (PWM) signal received on an input pin of the at least one SPI device.

25. The system of claims 23 or 24, wherein the operations for assigning the SPI ID comprise: upon power-up, measuring, via an analog-to-digital converter (ADC) of the at least one SPI device, a voltage on a general-purpose input / output (GPIO) pin coupled to an external resistor to determine the SPI ID.

26. The system of any of claims 23 to 25, wherein the operations for assigning the SPI ID comprise: upon power-up, measuring a startup time corresponding to a time constant of a resistor-capacitor (RC) network coupled to an enable pin of the at least one SPI device to determine the SPI ID.

27. The system of any of claims 23 to 26, wherein the operations for assigning the SPI ID comprise: upon power-up, receiving the SPI ID from the main SPI device on a serial data input (SDI) pin of the at least one SPI device, wherein prior to receiving the SPI ID, the at least one SPI device participates in an arbitration process on a serial data out (SDO) bus.

28. The system of any of claims 23 to 27, wherein the operations for assigning the SPI ID comprise: upon power-up, reading a pre-programmed SPI non-volatile memory serial data in (SDI) pin of the at least one SPI device.

29. The system of any of claims 23 to 28, wherein the operations for assigning the SPI ID comprise: upon power-up, determining the SPI ID based on a daisy-chain position of the at least one SPI device relative to other SPI devices in a daisy-chain configuration.

30. A method, comprising:providing a plurality of serial peripheral interface (SPI) devices including a main SPI device and a plurality of SPI subnodes; andcoupling the main SPI device with each one of the plurality of SPI subnodes via a 4-wire bus.

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