Integrated semiconductor device module, method of operating an apparatus for testing of an integrated semiconductor device module, and apparatus for testing integrated semiconductor device module

Abstract

A 3D integrated semiconductor device module, particularly a high-bandwidth memory module, is described. The 3D integrated semiconductor device module includes a semiconductor body having a first surface opposite a second surface; a plurality of device connections; one or more data buses coupled to the plurality of device connections; a plurality of logic elements coupled to the one or more data buses; a plurality of ground connections; a ground network coupled directly or indirectly to the plurality of ground connections; a plurality of test connections, the plurality of test connections disconnected from the one or more data buses, and disconnected from the ground network, the plurality of test connections configured for voltage signal testing of the 3D integrated semiconductor device module; and a plurality of test interconnect paths, each coupled to one or more of the plurality of test connections.

Description

INTEGRATED SEMICONDUCTOR DEVICE MODULE, METHOD OF OPERATING AN APPARATUS FOR TESTING OF AN INTEGRATED SEMICONDUCTOR DEVICE MODULE, AND APPARATUS FOR TESTING INTEGRATED SEMICONDUCTOR DEVICE MODULEFIELD

[0001] The present disclosure relates to methods and apparatuses for testing integrated semiconductor device modules and integrated semiconductor devices. Further, it relates to integrated semiconductor device modules designed for testing and integrated semiconductor devices designed for testing. More particularly, embodiments described herein relate to the contactless testing of integrated semiconductor devices or modules included in integrated semiconductor devices by using charged particle beams, particularly for identifying, characterizing, detecting and / or classifying defects such as shorts, opens, and / or leakages.BACKGROUND

[0002] In many applications, it is necessary to inspect a device to monitor the quality of the device. Since defects may occur e.g. during the processing of the devices, an inspection of the devices for reviewing the defects and for monitoring the quality may be beneficial.

[0003] The ever-increasing demand for miniaturized semiconductor devices has led to continuously increasing circuit densities and decreasing device sizes. As a result of the continued scaling of these devices, integrated circuits have evolved into complex3D devices that can include millions of transistors, capacitors, and resistors on a single chip.3D integration allows a significant reduction in device footprint and enables ever shorter and faster connections between that device's subcomponents, thus improving processing capabilities and speed thereof. Thesecapabilities make 3D integration a desirable technique for the semiconductor device industry to keep pace with Moore's law.

[0004] High bandwidth memories (HBM) are an example of a 3D integrated semiconductor device, for which EDEC Solid State Technology Association has adapted several industry standards, such as HBM, HBM2 or HBM3. Another example is a hybrid memory cube (HBC), which is similar in technology. High bandwidth memories (HBM) as a general term and as referred to in the present disclosure relates to all 3D integrated memory devices such as HBM, HBM2, HBM3, HBC or the like.

[0005] The 3D device technology landscape includes several general classes of 3D integration processes. Such 3D integration processes include stacked integrated circuit ("SIC") technology, system-in-package ("SiP") technology, and system-on-chip ("SOC") technology. SIC devices are formed by stacking individual semiconductor dies on top of one another. Currently, such SIC devices are achieved by die-to-interposer stacking or die-to-wafer stacking approaches. SiP devices are formed by stacking packages on top of one another, or by integrating multiple semiconductor dies or devices in a single package. SOCs realize higher density by heterogeneously stacking several different functional partitions of a circuit. Conventionally, these functional circuit partitions are stacked through wafer-to-wafer bonding techniques.

[0006] Semiconductor packaging substrates, e.g. for wafer level packaging, and 3D integrated semiconductor devices for the manufacture of complex microelectronic components are typically tested during and / or after manufacturing for determining defects, such as shorts or opens, in metal paths and interconnects provided at the substrate.

[0007] Various methods for testing such components are known. For example, contact pads of a component to be tested may be contacted with a contact probe, in order to determine whether the component is defective or not. However, particularly for 3D integrated semiconductor devices connections can be too small and too sensitive for mechanical testing. A needle prober causes surface damagedue to the mechanical contact. Therefore, it cannot be used to test active networks, but only some dummy networks at remote locations on deices and / or with dummy daisy chained networks.

[0008] A contactless electrical test with an electron beam can be conducted with a voltage signal reading, i.e. voltage contrast by signal electrons detection, such as secondary electrons (SE) and with charging of the test points or networks with an electron beam. The SE energy depends on the starting potential and therefore the SE signal can be used to measure or evaluate the potential by voltage contrast on different positions on the packing substrate.

[0009] Also limits for an electron beam test can be given for 3D integrated circuits. For 3D integrated circuits or circuit modules, logic elements interrupt a direct ohmic top to bottom connection. This means that it might not be possible to measure the integrity of the top-bottom connections including logic elements using some e-beam based method of testing, since the impedance of the connection cannot be considered without an operation of logic element.

[0010] Accordingly, it would be beneficial to provide improved 3D integrated semiconductor device modules and 3D integrated semiconductor devices and improved testing methods for reliably and quickly testing complex microelectronic devices, particularly 3D integrated semiconductor devices such as HBMs.SUMMARY

[0011] In light of the above, a 3D integrated semiconductor device module, a 3D integrated semiconductor device, and a method of testing a 3D integrated semiconductor device module are provided according to the independent claims. Further aspects, advantages, and beneficial features are apparent from the dependent claims, the description, and the accompanying drawings.

[0012] According to an embodiment, a 3D integrated semiconductor device module, particularly a high-bandwidth memory module, is provided. The 3D integratedsemiconductor device module includes a semiconductor body having a first surface opposite a second surface; a plurality of device connections; one or more data buses coupled to the plurality of device connections; a plurality of logic elements coupled to the one or more data buses; a plurality of ground connections; a ground network coupled directly or indirectly to the plurality of ground connections; a plurality of test connections, the plurality of test connections disconnected from the one or more data buses, and disconnected from the ground network, the plurality of test connections configured for voltage signal testing of the 3D integrated semiconductor device module; and a plurality of test interconnect paths, each coupled to one or more of the plurality of test connections.

[0013] According to an embodiment, a 3D integrated semiconductor device is provided. The 3D integrated semiconductor device includes a first 3D integrated semiconductor device module according to embodiments of the present disclosure; and a second 3D integrated semiconductor device module according to embodiments of the present disclosure.

[0014] According to an embodiment, a method of testing one or more 3D integrated semiconductor device modules with at least one charged particle beam column is provided. The method includes: placing one or more 3D integrated semiconductor device modules according to embodiments of the present disclosure or a 3D integrated semiconductor device according to embodiments of the present disclosure on a stage in a vacuum chamber; directing a charged particle beam of the one at least charged particle beam column on at least one test connection of the one or more 3D integrated semiconductor device modules to provide a charge on the at least one test connection; detecting signal electrons provided upon impingement of the charged particle beam on the one or more 3D integrated semiconductor device modules; and testing the one or more 3D integrated semiconductor device modules in the vacuum chamber based upon the detected signal electrons.

[0015] According to an embodiment, a method of testing a 3D integrated semiconductor device module or a 3D integrated semiconductor device with at least one charged particle beam column is provided. The method includes: placing the3D integrated semiconductor device module or the 3D integrated semiconductor device on a stage in a vacuum chamber; directing a charged particle beam of the at least one charged particle beam column on at least one test connection of the one or more 3D integrated semiconductor device modules to provide a charge on the at least one test connection; detecting signal electron signal of signal electrons provided upon impingement of the charged particle beam on the one or more 3D integrated semiconductor device modules; and determining a state information about the at least one test connection depending on a drop or decline in the signal electron signal.

[0016] According to an embodiment, an apparatus for testing of an integrated semiconductor device module is provided. The apparatus for testing of an integrated semiconductor device module includes: a vacuum chamber; a stage within the vacuum chamber, the stage being configured to support the integrated semiconductor device module; a charged particle beam column configured to generate a charged particle beam, the charged particle beam column including: a lens assembly with an objective lens configured to focus the charged particle beam on the integrated semiconductor device module; a scanner stage configured to scan the charged particle beam to different positions on the integrated semiconductor device module; and an electron detector for detecting signal electrons emitted upon impingement of the charged particle beam on the integrated semiconductor device module; and a controller having a processor and a memory, storing instructions that, when executed by the processor, cause the apparatus to perform a method according to embodiments of the present disclosure.BRIEF DESCRIPTION OF THE DRAWINGS

[0017] So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only exemplary embodiments and aretherefore not to be considered limiting of its scope, and may admit to other equally effective embodiments.

[0018] FIG. 1 shows a schematic sectional view of an apparatus for testing a 3D integrated semiconductor device module or a 3D integrated semiconductor device in accordance with any of the testing methods described herein;

[0019] FIG. 2A shows a schematic view of a portion of a 3D integrated semiconductor device module according to embodiments of the present disclosure;

[0020] FIG. 2B shows a schematic perspective view of a 3D integrated semiconductor device module and a vector scan according to embodiments of the present disclosure;

[0021] FIG. 3A shows a schematic view of a portion of a 3D integrated semiconductor device according to embodiments of the present disclosure;

[0022] FIG. 3B shows a schematic view of a 3D integrated semiconductor device according to embodiments of the present disclosure;

[0023] FIG. 4 shows an enlarged top view a 3D integrated semiconductor device module according to embodiments of the present disclosure;

[0024] FIG. 5 shows a schematic view of a portion of a testing apparatus testing a 3D integrated semiconductor device module accordance with testing methods described herein;

[0025] FIG. 6 shows a flowchart of a method of testing a 3D integrated semiconductor device module according to embodiments of the present disclosure; and

[0026] FIG. 7 shows a flowchart of a method of testing one or more 3D integrated semiconductor device modules according to embodiments described herein.DETAILED DESCRIPTION

[0027] Reference will now be made in detail to the various exemplary embodiments, one or more examples of which are illustrated in each figure. Each example is provided by way of explanation and is not meant as a limitation. For example, features illustrated or described as part of one embodiment can be used on or in conjunction with other embodiments to yield yet further embodiments. The intention is that the present disclosure includes such modifications and variations.

[0028] Within the following description of the drawings, the same reference numbers refer to the same components. Only the differences with respect to the individual embodiments are described. The structures shown in the drawings are not necessarily depicted true to scale but rather serve to provide better understanding of the embodiments.

[0029] Embodiments of the present disclosure relate to testing and / or defect review for 3D integrated semiconductor device modules and / or 3D integrated semiconductor devices. Particularly embodiments relate to charged particle beam testing, for example, electron beam testing, of high bandwidth memory modules or devices.

[0030] On the one hand, an electrical test by electron beam can test everywhere on a 3D integrated semiconductor device module and particularly on designed test networks and on active networks, as well. No surface damages occur with an electron beam.

[0031] According to some implementations, the 3D integrated semiconductor device can be designed for testing, i.e. a design for testability can be provided. The design of special test networks helps to identify and control electrical contacts, e.g., through several stacked HBM modules, such modules stacked with hybrid bonding or die stacking with micro bumps.

[0032] For contactless testing with a charged particle beam, for example, an electron beam, at least one charged particle beam is used for writing and reading charges on the one or more 3D integrated semiconductor devices, particularly for identifyingand characterizing defects such as shorts, opens, and / or leakages. A contactless electrical test with a charged particle beam can be provided, wherein a voltage signal reading (e.g. voltage contrast by signal electron sensing) is provided. According to some embodiments, which can be combined with other embodiments described herein, the voltage contrasts on the 3D integrated semiconductor device module(s) may be determined by detection of signal electrons. According to some embodiments, which can be combined other embodiments described herein, the signal electrons may particularly be secondary electrons.

[0033] Further, test point or contact points can be charged contactless on a 3D integrated semiconductor device module. Contactless testing avoids damage to the 3D integrated semiconductor device module, which might be particularly beneficial for boding methods like hybrid bonding, but also other micro connections. Detection and classification of electrical defects is enabled. An example of an apparatus for testing of one or more 3D integrated semiconductor device modules according to embodiments of the present disclosure and for conducting methods according to embodiments of the present disclosure is shown in FIG. 1 and explained below.

[0034] FIG. 1 shows a schematic view of an apparatus according to embodiments of the present disclosure and illustrates the concept of contactless electron beam testing. A 3D integrated semiconductor device module 10 or a stack of 3D integrated semiconductor device modules is supported on a stage 105. The 3D integrated semiconductor device module is supported in the vacuum chamber 110. According to some embodiments, which can be combined with other embodiments described herein, the 3D integrated semiconductor device module 10 can be placed on the stage 105 being on ground potential.

[0035] In the following, reference is made to an electron beam of an electron beam column. A person skilled in the art can understand that the embodiments can be modified by using a charged particle beam of a charged particle beam column, wherein, for example, ions are utilized as primary charged particles and electrons are utilized as signal charged particles.

[0036] As is schematically depicted in FIG. 1, the electron beam column 120 may be provided on a first side of the stage 105. The electron beam column 120 has an electron source 121 for generating an electron beam. The beam is accelerated and guided towards the 3D integrated semiconductor device module 10. As it is schematically depicted in FIG. 1, the electron source 121 is connected to a power supply 130. The power supply can provide a high-voltage to the electron source for emitting the electron beam, i.e. the primary electron beam, from the electron source. According to some embodiments, which can be combined with other embodiments described herein, the voltage provided by the power supply 130 can be varied to change the energy of the electron beam and, thus, the landing energy of the electron beam on the 3D integrated semiconductor device module.

[0037] According to some embodiments, which can be combined with other embodiments described herein, a stigmator 126 is provided. The stigmator 126 is configured to reduce astigmatism. Astigmatism can be generated in one or more of the beam optical components of the electron beam column 12O.The stigmator is controlled, e.g. by controller 180, to adjust the shape of the electron beam on the 3D integrated semiconductor device module, particularly at various positions on the 3D integrated semiconductor device module, i.e. at large and small deflection angles of the electron beam. The shape of the beam is adjusted at positions extending over the field of view (FOV) on the packaging substrate.

[0038] According to some embodiments, which can be combined with other embodiments described herein, the size of the FOV can be from 10 cm or below. The size if the FOV can be at least 2 cm.

[0039] A scan deflector 122 is provided. The scan deflector 122 can provide a first scanning stage for deflecting the beam over a first area on the packaging substrate. A second scanning stage for deflecting the beam over a second area on the packaging substrate can be provided according to some embodiments. The second stage can be provided by a second scan deflector 125. According to some embodiments, the deflection fields of scan deflector 122 and the second scan deflector 125 may partially overlap or may be adjacent to each other. The secondstage can be operated to scan over the second area, which is smaller than the first area.

[0040] Accordingly, a large scanning area and a smaller scanning area, which is added to the larger scanning area, can be provided. By providing a two-stage scanning, a large FOV can be provided while having a precise electron beam positioning. In some embodiments, the apparatus 100 may include a scan controller 123 connected to a scan deflector 122 of the electron beam column 120 and the second scan deflector 125. The scan deflector 122 and the second scan deflector may be configured to vector scan the electron beam onto a substrate surface.

[0041] A first plurality of electrodes 146 can generate a multi-pole field, for example, an octupole field, to guide the signal electrons 113 towards the electron detector 140. For example, the first plurality of electrodes can include eight or more electrodes for generating an octupole field. The second plurality of electrodes 148 can generate a multi-pole field, for example, an octupole field, to guide the signal electrons 113 towards the electron detector 140. For example, the second plurality of electrodes can include eight or more electrodes for generating an octupole field. Particularly, the multi-pole field generated by the second plurality of electrodes 148 can be static. According to some embodiments, which can be combined with other embodiments described herein, one or more electrodes in the electron beam column 120 can be at least one assembly of four or eight electrodes (or more electrodes), configured to generate a multipole field for guiding signal electrons. As shown in FIG. 1, the one or more electrodes 154 having the first plurality of electrodes 146 and the second plurality of electrodes 148 can be integrated in the electron beam column 120.

[0042] The first plurality of electrodes and / or the second plurality of electrodes can be utilized for guiding of signal electrons during detection of the signal electrons and can be utilized for generating the electric field for charge control. According to additional or alternative modifications, the electric field may be generated by a further electrode, for example, electrode 154, or by a combination of a further electrode and the first plurality of electrodes and / or the second plurality of electrodes.

[0043] In some embodiments, which can be combined with other embodiments described herein, the electron detector 140 includes an Everhard-Thornley detector. An energy filter 142 for the signal electrons 113 may be arranged, e.g. in front of the electron detector 140, particularly in front of the Everhard-Thornley detector, as schematically depicted in FIG. 1. The energy filter may include a grid electrode configured to be set on a predetermined potential. The energy filter 142 may allow the suppression of low-energy signal electrons. The energy filter 142 may suppress signal electrons that are irrelevant for the voltage contrast measurements to be conducted. In some implementations, the energy filter 142 may suppress signal electrons emitted from uncharged surface areas and may only let through signal electrons emitted from a charged surface contact point. Accordingly, the signal current detected by the electron detector may depend on the energy of the signal electrons, which indicates if a probed surface contact point is defective or not. Accordingly, avoiding or reducing charging of undesired substrate areas by vector scanning and beam blanking improves the S / N-ratio for the defect detection.

[0044] FIG. 1 exemplarily illustrates the stage 105 being connected to ground. The stage may be connected directly to ground, may be connected to ground via a DC power supply as exemplarily shown in FIG. 1, or may be connected to ground via an AC power supply. According to some embodiments, which can be combined with other embodiments described herein, the stage can include a conductive stage surface connected directly or indirectly to ground for providing a reference potential. For example, a power supply 106 can be provided to indirectly connect the stage to ground.

[0045] According to some embodiments, which can be combined with other embodiments described herein, the stage includes a conductive stage surface connected directly or indirectly to ground for providing a reference potential. According to yet further additional or alternative modifications, the integrated semiconductor device module can be partially connected to ground, for example, by the stage. For example, some circuitries can be connected to GND while some circuits are not connected to ground. According to yet further modifications, which can be combined with other embodiments described herein, the integratedsemiconductor device module can be capacitively connected to ground, e.g. by the stage. For some embodiments, there is no ohmic connection.

[0046] The defined potential of the stage, particularly a conductive stage, provides electric field lines, particularly at non-conductive portions of the stage surface and the integrated semiconductor device module. The defined potential can be utilized to influence the electron beam of the electron beam column.

[0047] FIG. 1 shows a controller 180. According to some embodiments, which can be combined with other embodiments described herein, the controller can be connected to one or more of the components of the apparatus 100 for contactless testing of a integrated semiconductor device module and for charge control. As exemplarily shown in FIG. 1, the controller can be connected to the power supply 130, the scan controller 123, the analysis unit 141 , and the stage 105. The controller may also be connected to the electron detector 140.

[0048] The controller 180 includes a central processing unit (CPU), a memory and, for example, support circuits. To facilitate control of the apparatus for testing integrated semiconductor device modules, the CPU may be one of any form of general purpose computer processor that can be used in an industrial setting for controlling various chambers and sub-processors. The memory is coupled to the CPU. The memory, or a computer readable medium, may be one or more readily available memory devices such as random access memory, read only memory, hard disk, or any other form of digital storage either local or remote. The support circuits may be coupled to the CPU for supporting the processor in a conventional manner. These circuits include cache, power supplies, clock circuits, input / output circuitry and related subsystems, and the like. Inspecting process instructions are generally stored in the memory as a software routine typically known as a recipe. The software routine may also be stored and / or executed by a second CPU (not shown) that is remotely located from the hardware being controlled by the CPU. The software routine, when executed by CPU, transforms the general purpose computer into a specific purpose computer (controller) that controls the apparatus operation, such as that testing of high-bandwidth memories or other 3D integrated semiconductor modules. Although the method and / or process of the present disclosure is discussedas being implemented as a software routine, some of the method steps that are disclosed therein may be performed in hardware as well as by the software controller. As such, embodiments of the invention may be implemented in software as executed upon a computer system, and hardware as an application specific integrated circuit or other type of hardware implementation, or a combination of software and hardware.

[0049] The controller may execute or perform a method of testing an integrated semiconductor device module with a charged particle beam column, e.g. an electron beam column, according to embodiments of the present disclosure. According to an embodiment, an apparatus for testing of integrated semiconductor device modules with any of the methods described herein is provided. The apparatus may include the controller 180. The controller includes a processor and a memory, storing instructions that, when executed by the processor, cause the apparatus to perform a method according to embodiments of the present disclosure.

[0050] Electron beam testing offers a suitable solution as it allows testing of test points smaller than 60 pm or 10 pm, or even below. It is capable of voltage contrast imaging. The test structures can be charged positive or negative by the electron beam impact, and the test point potential can be determined by the voltage contrast principle for defect detection and sample parameter monitoring (such as capacitance, resistance, etc.)

[0051] Embodiments of the present disclosure relate to 3D integrated semiconductor device with micro-pump connections or hybrid bonding connections, with small size and / or pitch and which are highly sensitive to be scratched or otherwise mechanically influenced. Such device connections can have a size of 5 pm or below. Further, according to some embodiments, which can be combined with other embodiments described herein, the 3D integrated semiconductor device modules have ground networks, which may have ground connections with a size of 10 pm or below. According to some embodiments, which can be combined with other embodiments described herein, the 3D integrated semiconductor device modules have test interconnect paths with test connections of, for example, 30 pm or below or even 10 pm or below. The test connections can be sufficiently small tobe in the active area of the 3D integrated semiconductor device, i.e. in areas with logic elements below the surface and in areas with a large plurality of small device connections having a small pitch. The electron beam allows for being operated in the active area, without contact and on the small connections, e.g. contact pads.

[0052] Further, the electron beam column, further includes a lens assembly 124 with a first objective lens configured to focus the electron beam on the 3D integrated semiconductor device module. The objective lens or objective lenses may be electrostatic, magnetic, or a magnetic-electrostatic. The apparatus 100 further includes an electron detector 140 for detecting signal electrons 113, e.g. secondary electrons, emitted upon impingement of the electron beam on the 3D integrated semiconductor device module, and an analysis unit 141 configured to determine, based on the signal electrons 113, if e.g. a test interconnect path 20 of the 3D integrated semiconductor device module is defective.

[0053] In some embodiments, the analysis unit 141 may be configured to determine, based on the detected signal electrons, whether an electrical interconnect path of a integrated semiconductor device module has a defect, such as a short, an open and / or a leakage. Optionally, the analysis unit 141 may be configured to classify a detected defect. In some embodiments, the analysis unit 141 may be configured to determine, based on the detected signal electrons from subsequent measurements, whether a short or a leakage exists between two or more electrical interconnect paths. In some implementations, the signal electrons 113 detected by the electron detector 140 may provide information about an electric potential of the location from which the signal electrons 113 are emitted or reflected, and the analysis unit 141 may be configured to determine from said information if the electrical interconnect path, e.g. a test interconnect path 20, is defective or not. The analysis unit 141 may be further configured to classify a determined defect. Specifically, testing may include determining, by the analysis unit 141, if the electrical interconnect path, e.g. a test interconnect path 20, has any of a short, an open, and / or a leakage. An “open” is understood as an open electrical interconnect path that does not actually electrically connect the first surface contact point 21 and the second surface contactpoint 22. A “short” is understood as an electrical connection between two electrical interconnect paths that are actually to be electrically separated.

[0054] According to an embodiment, an apparatus for testing, e.g. for contactless testing, of a packaging substrate is provided. The apparatus includes a vacuum chamber and a stage within the vacuum chamber. The stage is configured to support the packaging substrate. The apparatus includes an electron beam column configured to generate an electron beam. The electron beam column includes a lens assembly with an objective lens configured to focus the electron beam on the integrated semiconductor device module. The electron beam column includes a scanner stage configured to scan the electron beam to different positions on the integrated semiconductor device module. The electron beam column includes an electron detector for detecting signal electrons emitted upon impingement of the electron beam on the integrated semiconductor device module. The electron beam column includes a controller having a processor and a memory, storing instructions that, when executed by the processor, cause the apparatus to perform a method according to any of the embodiments of the present disclosure. An analysis unit 141 can be provided. The analysis unit determines, based on the signal electrons, if, for example, a device-to-device electrical interconnect path or test interconnect path is defective.

[0055] Both the “electrical driving” and the “probing” is done with an electron beam, such that defects can be reliably and quickly found. Testing by electron beam charging and electron beam probing (e.g. with an electron beam test (EBT) column or an electron beam review (EBR) column) is independent of topography, fast, and flexible with regard to contact point positions, size and geometry, whereas the topography of the integrated semiconductor device module may be a problem for other test methods like capacitive or electric field detectors.

[0056] According to an embodiments of the present disclosure, a 3D integrated semiconductor device module, particularly a high-bandwidth memory module, is provided. The 3D integrated semiconductor device module includes semiconductor body having a first surface opposite a second surface, a plurality of device connections, one or more data buses coupled to the plurality of device connections,and a plurality of logic elements coupled to the one or more data buses. For example, the plurality of device connections ca be provided at the first surface and the second surface. The 3D integrated semiconductor device module further includes a plurality of ground connections and a ground network coupled directly or indirectly to the plurality of ground connections. For example, the plurality of ground connections can be provided at least at the first surface or the second surface. The 3D integrated semiconductor device module further includes a plurality of test connections, for example, provided at least at the first surface or the second surface, the plurality of test connections disconnected from the one or more data buses, and disconnected from the ground network, the plurality of test connections configured for voltage signal testing of the 3D integrated semiconductor device module, and a plurality of test interconnect path, each coupled to one or more of the plurality of test connections. According to some embodiments, the plurality of logic elements can be provided in one or more memory cells. Further, according to some implementations, the plurality of device connections can be configured for hybrid bonding.

[0057] According to some embodiments of the present disclosure, the test connection are design for electron beam test. The test connections have no functionality for operating of the 3D integrated semiconductor device, e.g. the memory. The functionality of the test connections and the test interconnect paths is only for electron beam testing. According to some embodiments, the test connections can be floating or grounded. The test connections are not connected to the ground network. For example, a ground network has several contact points to be redundant. The test networks are typically not redundant and are not connected, i.e. disconnected from the ground network. According to some embodiments, which can be combined with other embodiments described herein, the test interconnect paths can be TSVs, can be daisy chain structures. There may also be more complex interconnect structures as exemplarily explained with respect to FIG: 5.

[0058] Embodiments of 3D integrated semiconductor devices can have a design for testability, e.g. tailored for electron beam based electrical test (EBT). For example, top-down connections can be features that improve the testability. Particularly, thetop down connections for testing can be disconnected to the ground network(s) of a 3D integrated semiconductor device and can be disconnected to the active networks, buses, and logical elements of the 3D integrated semiconductor device. The test connections and test interconnect path allows, particularly only allows, to control the yield of the stacking and interconnect process, particularly at every stage from a single module to a complete device with a plurality of modules, e.g. all the way up to the full device stack. For example, the device stack can be a high bandwidth module stack. Much greater control over the production process can be provided.

[0059] FIG. 2A shows a 3D integrated semiconductor device module 10. The 3D integrated semiconductor device module exemplarily shown in FIG. 2A is a high-bandwidth memory with one or more memory cells 210. Each memory cell can include a plurality of bytes. The 3D integrated semiconductor device module can include a plurality of memory cells. The memory cell 210 shown in FIG. 2A is an example of a logic element of a 3D integrated semiconductor device module.

[0060] The 3D integrated semiconductor device module includes a semiconductor body 12 having a first surface 13 and a second surface 15 opposite the first surface. The one or more memory cells are connected to a bus 220. For operation of the 3D integrated semiconductor device module, a plurality of device connections 232 are provided. The device connections 232 are coupled e.g. to at least one bus 220. The device connections are coupled to lines 234, e.g. data lines, gate lines, or other active lines for operation of the 3D integrated semiconductor device module. For examples, a line can be an active top-down-connection.

[0061] The 3D integrated semiconductor device module 10 further includes ground connections 242 coupled one or more ground networks 244. The one or more ground networks 244 can be distributed within the semiconductor body 12. For example, the one or more ground networks can shield different logic elements from each other, different buses from each other, and / or different lines from each other. A plurality of ground connections can be redundant connections for one ground network. One or more ground networks may also be connected.

[0062] According to embodiments of the present disclosure, a 3D integrated semiconductor device module 10 can be designed for testability. A plurality of test connections 202 are provided. The plurality of test connections 202 are connected to test interconnect paths 204. For example, a test interconnect path can extend from the first surface 13 to the second surface 15. Additionally or alternatively, a test interconnect path 204 can start at the first surface 13, extend in a direction towards the second surface 14, and can end at the first surface 13.

[0063] The test interconnect path can be designed to test a manufacturing step within the 3D integrated semiconductor device module 10. Additionally or alternatively, the test interconnect path can be designed to test the stacking of different 3D integrated semiconductor device modules 10 (see, e.g. FIGs. 3A and 3B). Thus, the test interconnect path can serve for testing of a module or for testing of a stack of modules.

[0064] The above described device connections can have a size of 5 pm or below. Further, according to some embodiments, the ground connections can have a size of 10 pm or below. The test connections can be, for example, 30 pm or below or even 10 pm or below. The test connections can be sufficiently small to be in the active area of the 3D integrated semiconductor device, i.e. in areas with logic elements below the surface and in areas with a large plurality of small device connections having a small pitch.

[0065] FIGS. 2A and 2B show a 3D integrated semiconductor device module 10 having test connections 202, e.g. surface contact points (e.g. like first surface contact point 21 shown on FIG 1) or contact pads of interconnect paths for testing of the integrated semiconductor device module. An exemplary test sequence and a schematic signal for detecting, for example, secondary electrons is shown in FIG; 2B.

[0066] FIG. 2B shows an example of testing with electron beam 111 and particularly with vector scanning and beam blanking. At a first position, for example at the position of the test connection referenced with “beam no.1”, the electron beam is pulsed for charging and / or measuring. The electron beam 111 is vector scanned toa second position. For example, the second position can be any of the positions of test connections, e.g. contact pads for testing numbered as beam no. 2, 3, or 4. The electron beam 111 is unblanked (deflected on-axis or switched on). For example, the electron beam can be unblanked (deflected on-axis or switched on) for a period of time. A pulse of an electron beam can be provided on the second position. The electron beam is only directed to tests connections and / or device connections. Based upon such beam control, charging of dielectric material or semiconductor material, i.e. material other than of connections, is reduced or avoided.

[0067] According to embodiments of the present disclosure, a vector scanning with beam blanking or beam pulsing on the connections or surface contact points can be provided for testing of a 3D integrated semiconductor device module or a 3D integrated semiconductor device.

[0068] According to some embodiments, which can be combined with other embodiments described herein, vector scanning can result in positioning of the charged particle beam on an arbitrary sequence of positions on the integrated semiconductor device module. Additionally or alternatively, vector scanning can include pulsing of a charged particle beam for a period of time while directed onto the conductive pad, e.g. a test connection or device connection.

[0069] As shown in FIG: 2B, the test connections 202 and the device connections 232 can be provided in an active area 250. An active area is also shown in FIG: 2A. The active area is an area with e.g. a bus 220 and / or a logic element like a memory cell 210. For example, the active area extends of the portion of the semiconductor body 12 depicted in FIG. 2A. A 3D semiconductor integrated device module may further include an edge area, i.e. an area without active elements or logic elements (below the connections) in the area. In an edge area, also larger contact pads 292 for mechanical proving can be provided. There are no device connections in the edge area. Thus, mechanical probing cannot destroy device connections in this (edge) area.

[0070] According to an embodiments of the present disclosure, a 3D integrated semiconductor device module, particularly a high-bandwidth memory module, isprovided. The 3D integrated semiconductor device module includes semiconductor body having a first surface opposite a second surface, a plurality of device connections, one or more data buses coupled to the plurality of device connections, and a plurality of logic elements coupled to the one or more data buses. The 3D integrated semiconductor device module further includes a plurality of ground connections and a ground network coupled directly or indirectly to the plurality of ground connections. The 3D integrated semiconductor device module further includes a plurality of test connections, the plurality of test connections disconnected from the one or more data buses, and disconnected from the ground network, the plurality of test connections configured for voltage signal testing of the 3D integrated semiconductor device module, and a plurality of test interconnect path, each coupled to one or more of the plurality of test connections.

[0071] As shown in FIG. 2A, according to some embodiments, a first test interconnect path of the plurality of test interconnect paths 204 is connected to a first test connection 202 on the first surface includes a daisy chain towards the second surface and back towards the first surface and is connected to a second test connection 202 on the first surface 13. Additionally or alternatively, a second test interconnect path of the plurality of test interconnect paths 204 is connected to a third connection on the first surface 13 and a fourth test connection on the second surface 15, particularly to provide a through silicon via (TSV).

[0072] According to some embodiments, which can be combined with other embodiments described herein, the 3D integrated semiconductor device module includes an active area having the plurality of logic elements disposed therein, and an edge area outside of the active area or at least partially surrounding the active area, wherein the plurality of device connections are provided in the active area, the plurality of ground connections are provided in the active area, the plurality of test connections are provided in the active area. According to some embodiments, which can be combined with other embodiments described herein, the plurality of test connections can be distributed over the active area. According to some implementations, the 3D integrated semiconductor device module may include one or more probe connections provided in the edge area.

[0073] Embodiments of the present disclosure related to 3D integrated semiconductor devices having e.g. two or more 3D integrated semiconductor device modules. The 3D integrated semiconductor device can be a stacked 3D device, for example, a 3D DRAM stack or HBM.

[0074] A substrate may be formed of any suitable substrate material including but not limited to a lll-V compound semiconductor material, silicon (e.g., having a resistivity between about 1 and about 10 Ohm x cm, crystalline silicon (e.g., Si<100> or Si<111 >), silicon oxide, silicon germanium, doped or undoped silicon, undoped high resistivity silicon (e.g., float zone silicon having lower dissolved oxygen content and a resistivity between about 5000 and about 10000 ohm x cm), doped or undoped polysilicon, silicon nitride, silicon carbide. A substrate include in a 3D integrated device may also be of quartz, glass (e.g., borosilicate glass), sapphire, alumina, and / or ceramic materials. In some embodiments, the substrate 302 is a monocrystalline p-type or n-type silicon substrate. In one embodiment, the substrate 302 is a polycrystalline p-type or n-type silicon substrate.

[0075] FIG 3A shows a 3D semiconductor device 300 being a stack of 3D integrated semiconductor device modules 10. Four 3D semiconductor device modules as exemplarily shown in FIG. 2A are stacked on top of each other to form the 3D semiconductor device 300. A test connection 202 can be charged or measured with an electron beam. As shown, some of the test interconnect path can extend through one or more of the 3D semiconductor device modules. For example, a TSV can be provided. Thus, an electron beam test of the bonding 314 from one of the 3D semiconductor device modules, for example, the top module in FIG. 3A, to an adjacent 3D semiconductor device module, for example, the second module from the top in Fig. 3A can be provided. For example, an electron beam test can be performed after each stacking step of stacking the four modules and after stacking the module stack to a wafer.

[0076] By having additional top-down test interconnect paths and / or corresponding test connections, for example, vias as a 'design for testability’ an electron beam test tool can verify the interconnect quality. Defects or process variations of the completeinterconnect process of multiple 3D integrated semiconductor modules, e.g. stacked HBM chips, can be detected.

[0077] According to some embodiments, an electron beam test on the surface electrodes, i.e. test connections, connected to test interconnect paths, such as top-down connections and vias, a test can be provided after each stacking step, the full stack and for essentially all connections and test structures. According to some embodiments, which can be combined with other embodiments described herein, a die-to-wafer (DTW) stack can be electrically tested. An electron beam test can include the connection quality and parameter of the stack to wafer connection. FIG.3B shows three stacked 3D integrated semiconductor devices 300 mounted side-by-side on a wafer 350. FIG 3B exemplarily illustrates a DTW connection to be tested by electron beam test. A suitable location of the test networks, i.e. test interconnect paths enables a full wafer-die-coverage. Additionally or alternatively, information about uniformity of one or more bonding processes, i.e. connections, between 3D integrated semiconductor device modules can be provided. According to some embodiments, which can be combined with other embodiments described herein, a plurality of test connections can be distributed over a 3D integrated semiconductor device module. The plurality of test connections may include 100 test connections or more, such as 300 test connections or more, particularly 400 test connections or more.

[0078] One bond between adjacent 3D integrated semiconductor device modules is exemplarily labelled with reference numeral 314 in FIG. 3A. 3D integrated devices and / or wafer Level packaging (WLP) substrates have an increasing complexity. The design rules (feature size) are decreasing substantially. Accordingly, contact points, i.e. device connections for e.g. flip chip bonding, hybrid bonding, or chip mounting decrease in size and increase in complexity. The contact points can be connected to other surface contact points on a packaging substrate or between chip devices to interconnect. An electron beam test system can detect and classify defective electrical connections in the device modules, the devices or WLP substrates, such as silicon interposers. The defects may include opens, shorts or leakage defects and others.

[0079] According to an embodiment, a 3D integrated semiconductor device isx provided. The 3D integrated semiconductor device includes a first 3D integrated semiconductor device module according to embodiments of the present disclosure and a second 3D integrated semiconductor device module according to embodiments of the present disclosure. For example, a test connection of the first 3D integrated semiconductor device module can connect with a test connection of the second 3D integrated semiconductor device module.

[0080] According to some embodiments, which can be combined with other embodiments described herein, the first 3D integrated semiconductor device module and the second 3D integrated semiconductor device module can be provided in a first stack of 3D integrated semiconductor device modules. The 3D integrated semiconductor device can further include a second stack of 3D integrated semiconductor device module including further 3D integrated semiconductor device modules and an interposer, wherein the first stack of 3D integrated semiconductor device modules and the second stack of 3D integrated semiconductor device modules are coupled to the interposer side-by-side.

[0081] According to some embodiments, a 3D integrated semiconductor device can be stacked DRAM structures that can be integrated into high bandwidth memory (HBM) modules. The HBMs can have large parallel interconnect densities between memory dies and central processing unit (CPU) cores or logic dies.

[0082] Traditionally, HBM modules include a flip chip DRAM die stack interconnected to a logic die by a silicon interposer and solder bumps. Bandwidth between the DRAM die stack and the logic die is therefore limited by the size of the solder bumps and the pitch therebetween, which is generally larger than about 20 pm. A smaller pitch between memory die interconnections of an HBM module can be utilized e.g. with hybrid bonding and having test connections to provide stacked memory dies, such as the stacked DRAM structures according to embodiments of the present disclosure.

[0083] The wafer-to-wafer bonding of the modules or packages may be accomplished by planarizing the major surfaces of adjacent substrates (e.g. prior tosingulation) or packages (e.g. after singulation) and placing the major surfaces against one another while applying physical pressure, elevated temperatures, or an electrical field to the packages. Upon bonding, the one or more interconnections of each substrate, package, or module (e.g. 3D integrated semiconductor device module 10) directly contact one or more interconnections of an adjacent substrate, package, or module, thus forming electrically conducting paths that may span the thickness or height of the entire module, e.g. a DRAM structure. Wafer-to-wafer bonding of the packages or modules enables the stacking of semiconductor dies.

[0084] FIG. 4 is a schematic top view of an integrated semiconductor device module as described herein under test. Two stacks of 3D integrated semiconductor device modules 1o can be bonded to a wafer 350, e.g. an interposer or a wafer including logic elements. The top integrated semiconductor device module 10 has a top surface, e.g. first surface 13 shown in FIG. 2A, with a plurality of test connections (e.g. surface contact points) arranged in a 2-dimensional manner or 2-dimensional pattern. In FIG. 4 only the test connections are shown and the device connections and ground connections are omitted. The integrated semiconductor device module 10 is provided at a first die connection interface 31 for attaching a first die stack. A 3D integrated semiconductor device module 10 is provided at a second die connection interface 32 for attaching a second die stack.

[0085] In some embodiments, each first test connection of the first die connection interface 31 is connected to one respective test connection of the second die connection interface 32 by a device-to-device electrical interconnect path. For the sake of clarity, only the device-to-device electrical interconnect paths connecting the first and second die connection interfaces are depicted. According to some embodiments, which can be combined with other embodiments described herein, the first test connection (e.g. a surface contact point) may be connected to one second test connection (e.g. a surface contact point). Alternatively, the first test connection may be connected to two or more second test connections. The two or more second test connections can be probed with the electron beam, for example, after charge has been applied to the first test connection.

[0086] According to the testing method described herein, the charging electron beam 111 is directed, particularly focused, on a first test connection of a 3D integrated semiconductor device module at the first die connection interface 31 , and the charging electron beam 112 is directed, particularly focused, on the associated second test connection of a 3D integrated semiconductor device module at the second die connection interface 32. Signal electrons emitted from the second test connection can be detected for testing whether an “open” defect exists in the electrical interconnect path. Thereafter, the other test connections and corresponding test interconnect paths may be tested, particularly pairwise.

[0087] Alternatively or additionally, it can be tested in parallel or subsequently, whether the charging of one device-to-device electrical interconnect path leads to the charging of a surface contact point of another device-to-device electrical interconnect path, such that a “short” defect can be determined.

[0088] According to some embodiments, which can be combined with other embodiments described herein, test methods and / or apparatuses according to the present disclosure may be utilized during and / or after manufacturing of a integrated semiconductor device module. For example, a test may be applied on a integrated semiconductor device module that does not yet include all layers or structures. For example, a test may be conducted after a redistribution layer (RDL) has been manufactured and / or after a via layer has been manufactured. An RDL test and / or a via test can be provided. Yet further, a test may be provided on the finished integrated semiconductor device module. Yet further, a test may be provided on the finished integrated semiconductor device module has been stacked to another finished integrated semiconductor device module. Yet further, a test may be provided on the finished integrated semiconductor device, after the modules have been stacked and / or after the stacked modules are bonded to a wafer or interposer.

[0089] A test may be provided by charging (writing on) one or more portions, e.g. test connections or surface contact points, and by detecting the charge by means of signal electrons, i.e. reading a charge on an integrated semiconductor device module. The number of electrons emitted from the surface of the integrated semiconductor device module per irradiated electron, i.e. the total electron yield isenergy dependent. For a total electron yield of 1, the same number of electrons reach the surface of the integrated semiconductor device module as compared to the number of signal electrons being emitted from or scattered at the surface of the integrated semiconductor device module. There are two neutral energy values, a first neutral energy value and a second neutral energy value, for which the total electron yield equals 1, i.e. there is no charging. According to some embodiments, which can be combined with other embodiments described herein, the surface of the integrated semiconductor device module can be read, i.e. signal electrons can be detected, with an electron beam having one of the neutral energy values.

[0090] According to some embodiments, which can be combined with other embodiments described herein, directing an electron beam with the first landing energy on a portion of a integrated semiconductor device module can be a charging operation. The charging operation “writes” a charge to an electrical interconnect path or a network of electrical interconnect paths. Further, directing an electron beam with a second landing energy on a portion of the integrated semiconductor device module can be an operation for detecting signal electrons. The electron beam at the second landing energy may “read” a charge of an electrical interconnect path or a network of electrical interconnect paths.

[0091] According to some embodiments, which can be combined with other embodiments described herein, charging of portions of the integrated semiconductor device module is reduced or avoided during detection of signal electrons, i.e. reading of a charge. Particularly, influencing of a charge of electrical interconnect path or network of electrical interconnect paths is avoided or kept to a minimum while detecting signal electrons, for example, detecting the charge previously provided.

[0092] Embodiments of the present disclosure provide inter alia one or more of the further following advantages. A contact free electrical test of integrated semiconductor device modules as disclosed herein can be provided, wherein electrical charge can be controlled for electrical defect detection. In light of the flexibility of the electron beam, increased testing speed can be provided. A test including 100% of the electrical interconnection path is possible during volumeproduction. Further, the flexibility of the electron beam allows for testing and flexible setup for different module layouts and device layouts. The test methods and apparatuses disclosed herein are independent from test feature dimensions and further allow for being scalable to smaller dimensions, particularly if technical development moves towards smaller structure sizes. The testing of the integrated semiconductor device modules is damage free.

[0093] FIG. 5 shows an example of a 3D integrated semiconductor device module test, e.g. an HBM electrical test by an electron beam. FIG. 5 shows a portion of the apparatus 100 shown in FIG. 1 with a 3D integrated semiconductor device module test located in the stage 105. For testing a voltage signal reading (voltage contrast by secondary electron (SE) sensing) is provided. A charge of connections, e.g, surface contact points or contact pads charging interconnects or networks by an electron beam can be provided. For high-bandwidth memory (HBM) and other 3D integrated semiconductor devices an electrical test by an electron beam is influenced by the logic elements integrated into the HBM, which change the electrical signal behavior (VC) of the tested surface contacts. Accordingly, expected voltages measured with a electron beam test cannot be directly determined by considering the impedance (resistivity, capacity and inductivity) of interconnect paths and networks. This poses a challenge for electron beam test, as the logic elements interrupt a direct ohmic top to bottom connection. This means that it might not be possible to directly measure the integrity of the top-bottom connections including logic elements using an electron based method of testing.

[0094] The 3D integrated semiconductor device module shown in FIG. 5 shows surface connections to a bus coupled to a memory cell at a top surface. Further, a TSV structure is shown, while the silicon wafer is provided before grinding. The grinding level shown on FIG. 5 illustrates the exposure of the TSV after the grinding process. Thus, according to some embodiments, which can be combined with other embodiments described herein, an electron beam test may be provided on a 3D integrated semiconductor device module before finalizing the module.

[0095] One the one hand, the through silicon via TSV coactively couples to ground of the stage 105 through the silicon wafer before grinding. Thus, upon charging ofthe TSV with the electron beam, the voltage change on the TSV can be predicted and measured accordingly with voltage contrast measurements of the signal electrons.

[0096] On the other hand, the connections coupled to the network show a predetermined charging behavior over time. Even without a direct contact, e.g. with the logic elements, the charging of one or more device connections coupled to a bus (and directly or indirectly to logic devices) can be compared to the charging of a reference. The reference may be a neighboring die or the reference may be a comparison to reference die that has previously been measured.

[0097] Further, according to some embodiments, which can be combined with other embodiments described herein, the plurality of test connections and test interconnect paths can include a test structure 504. The test structure 504 can include a daisy chain structure as shown in FIG. 5. The test structure can include interconnect paths from the top to the bottom. At the bottom of the wafer a connection line to a further top-to-bottom interconnect path is provided. Within a network layer, a bus layer, or another layer over the substrate (or on top of the device) a connection to a yet further top-to-bottom interconnect path can be provided. This pattern can be repeated several times to provide a chain distributed over the device. Accordingly, the layout of the device can be tested by charging a first test connection at one side of the device and testing / reading at another side or a position remote from the first test connection. After grinding of the wafer, the bottom connection lines are removed and TSVs remain in the device.

[0098] According to an embodiment, a method of testing one or more 3D integrated semiconductor device modules with at least one charged particle beam column is provided. The method includes placing the 3D integrated semiconductor device module or the 3D integrated semiconductor device on a stage in a vacuum chamber and directing a charged particle beam of the at least charged particle beam column on at least one test connection of the one or more 3D integrated semiconductor device modules to provide a charge on the at least one test connection. The method further includes detecting signal electron signal of signal electrons provided upon impingement of the charged particle beam on the one or more 3D integratedsemiconductor device modules and determining a state information about the test connection depending on a drop or decline in the signal electron signal. For example, the drop or decline can be compared with a die-to-die comparison.

[0099] According to an embodiment, a method of testing one or more 3D integrated semiconductor device modules with at least one charged particle beam column is provided. The method includes placing one or more 3D integrated semiconductor device modules according to embodiments of the present disclosure or a 3D integrated semiconductor device according to embodiments of the present disclosure on a stage in a vacuum chamber. A charged particle beam of the at least charged particle beam column is directed on at least one test connection of the one or more 3D integrated semiconductor device modules to provide a charge on the at least one test connection. Signal electrons provided upon impingement of the charged particle beam on the one or more 3D integrated semiconductor device modules are detected. The method further includes testing the one or more integrated semiconductor device modules in the vacuum chamber based upon the detected signal electrons. For example, the one or more 3D integrated semiconductor device modules or the 3D integrated semiconductor device are electrically coupled to the stage. According to some embodiments, which can be combined with other embodiments described herein, the one or more 3D integrated semiconductor device modules or the 3D integrated semiconductor device can be capacitively coupled to the stage. For example, the stage can have a dielectric layer facing a 3D integrated semiconductor device module or the 3D integrated semiconductor device module can have a dielectric layer or semiconductor layer facing the stage.

[0100] FIG. 6 shows a flow chart illustrating a method of testing one or more 3D integrated semiconductor device modules with at least one charged particle beam column. At operation 602, one or more 3D integrated semiconductor device modules according to embodiments of the present disclosure or a 3D integrated semiconductor device according embodiments of the present disclosure are placed on a stage in a vacuum chamber. A charged particle beam of the at least charged particle beam column is directed on at least one test connection of the one or more3D integrated semiconductor device modules at operation 604 to provide a charge on the at least one test connection. At operation 606, signal electrons provided upon impingement of the charged particle beam on the one or more 3D integrated semiconductor device modules are detected. At operation 608, the one or more integrated semiconductor device modules in the vacuum chamber are tested based upon the detected signal electrons.

[0101] The electrical test with an electron beam can test anywhere on designed test networks or test connections (design for testability) and on the active networks as well, since no surface damages occurs. The design of special test networks (test connections and test interconnect paths) help to identify and control electrical contacts through several stacked 3D integrated semiconductor modules, e.g. HBM modules. The contacts to be tested can include hybrid bonding or die stacking with micro bumps.

[0102] According to some embodiments, which can be combined with other embodiments described herein, the one or more 3D integrated semiconductor device modules or the 3D integrated semiconductor device can be electrically coupled to the stage. For example, the one or more 3D integrated semiconductor device modules or the 3D integrated semiconductor device are capacitively coupled to the stage.

[0103] FIG. 7 shows a flow chart illustrating a method of testing a 3D integrated semiconductor device module or a 3D integrated semiconductor device with at least one charged particle beam column. At operation 702, a 3D integrated semiconductor device module or the 3D integrated semiconductor device is placed on a stage in a vacuum chamber. A charged particle beam of the at least charged particle beam column is directed on at least one test connection of the one or more 3D integrated semiconductor device modules at operation 704 to provide a charge on the at least one test connection. At operation 706, a signal electron signal of signal electrons provided upon impingement of the charged particle beam on the one or more 3D integrated semiconductor device modules is detected. A state information about the test connection is determined depending on a drop or declinein the signal electron signal at operation 708. For example, as illustrated by operation 710 the drop or decline can be compared with a die-to-die comparison.

[0104] In light of the contactless (and damage free) testing an electron beam test can test anywhere on designed test networks and on the active networks, i.e. device networks, as well. The test connections, device connections or ground connections can be provided in an active area of the 3D integrated semiconductor device module. A device connection, ground connection or test connection as referred to herein can be a “surface contact point” or “contact pad” that may be understood as an end point of an electrical interconnect path that is exposed at a surface of the integrated semiconductor device module, such that an electron beam can be directed on the connection for contactless charging or probing the electrical interconnect path. A device connection is configured to electrically contact a chip, a die, a smaller package, or other electrical components like capacitors, resistors, coils, or the like, that is to be placed on the surface of the integrated semiconductor device module, e.g. via hybrid bonding or soldering.

[0105] According to embodiments of the present disclosure, 100% of the electrical interconnect paths can be tested, particularly of the test interconnect paths. A fully non-defective integrated semiconductor device module is beneficial before stacking with other integrated semiconductor device modules. The electrical test with an electron beam can charge electrical network by its probe current, e.g. by vector scanning to connections (surface contact points or contact pads). The electrical test with an electron beam can sense the connection voltages by the voltage contrast method. By analyzing the networks individual and repeatable charging characteristics, it is possible to identify defects and process issues.

[0106] Embodiments of the present disclosure also provides the following advantage. An electrical measurements by mechanical probe contact has some test structures like daisy chains as it is not allowed to mechanical probe the active areas to avoid yield impact by scratches and contamination. Those daisy chain test structure are not required for non-contact electron beam test and may be removed. This saves space for the actual device functionality.While the foregoing is directed to some embodiments, other and further embodiments may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

1. CLAIMSWhat is claimed is:

1. A 3D integrated semiconductor device module, particularly a high-bandwidth memory module, comprising:a semiconductor body having a first surface opposite a second surface;a plurality of device connections;one or more data buses coupled to the plurality of device connections;a plurality of logic elements coupled to the one or more data buses;a plurality of ground connections;a ground network coupled directly or indirectly to the plurality of ground connections;a plurality of test connections, the plurality of test connections disconnected from the one or more data buses, and disconnected from the ground network, the plurality of test connections configured for voltage signal testing of the 3D integrated semiconductor device module; anda plurality of test interconnect paths, each coupled to one or more of the plurality of test connections.

2. The 3D integrated semiconductor device module of claim 1, wherein the plurality of logic elements are provided in one or more memory cells.

3. The 3D integrated semiconductor device module of any of claims 1 to 2, wherein the plurality of device connections are configured for hybrid bonding.

4. The 3D integrated semiconductor device module of any of claims 1 to 3, wherein the device connections have a size of 5 m or below.

5. The 3D integrated semiconductor device module of any of claims 1 to 4, wherein the ground connections have a size of 10 pm or below.

6. The 3D integrated semiconductor device module of any of claims 1 to 5, comprising:an active area having the plurality of logic elements disposed therein; andan edge area outside of the active area or at least partially surrounding the active area, wherein the plurality of device connections are provided in the active area, the plurality of ground connections are provided in the active area, the plurality of test connections are provided in the active area.

7. The 3D integrated semiconductor device module of any of claims 1 to 6, further comprising:one or more probe connections provided in the edge area.

8. The 3D integrated semiconductor device module of any of claims 1 to 7, wherein the plurality of test connections are distributed over the active area.

9. The 3D integrated semiconductor device module of any of claims 1 to 8, wherein a first test interconnect path of the plurality of test interconnect paths is connected to a first test connection on the first surface includes a daisy chaintowards the second surface and back towards the first surface and is connected to a second test connection on the first surface.

10. The 3D integrated semiconductor device module of any of claims 1 to 9, wherein a second test interconnect path of the plurality of test interconnect paths is connected to a third connection on the first surface and a fourth test connection on the second surface, particularly to provide a through silicon via (TSV).

11. A 3D integrated semiconductor device, comprising;a first 3D integrated semiconductor device module according to any of claims 1 to 10; anda second 3D integrated semiconductor device module according to any of claims 1 to 10.

12. The 3D integrated semiconductor device of claim 11, wherein a test connection of the first 3D integrated semiconductor device module connects with a test connection of the second 3D integrated semiconductor device module.

13. The 3D integrated semiconductor device of any of claims 11 to 12, wherein the first 3D integrated semiconductor device module and the second 3D integrated semiconductor device module are provided in a first stack of 3D integrated semiconductor device modules, and further comprising:a second stack of 3D integrated semiconductor device module comprising further 3D integrated semiconductor device modules; andan interposer, wherein the first stack of 3D integrated semiconductor device modules and the second stack of 3D integrated semiconductor device modules are coupled to the interposer side-by-side.

14. A method of testing one or more 3D integrated semiconductor device modules with at least one charged particle beam column, the method comprising:placing one or more 3D integrated semiconductor device modules according to any of claims 1 to 10 or a 3D integrated semiconductor device according to any of claims 11 to 13 on a stage in a vacuum chamber;directing a charged particle beam of the one at least charged particle beam column on at least one test connection of the one or more 3D integrated semiconductor device modules to provide a charge on the at least one test connection;detecting signal electrons provided upon impingement of the charged particle beam on the one or more 3D integrated semiconductor device modules; andtesting the one or more 3D integrated semiconductor device modules in the vacuum chamber based upon the detected signal electrons.

15. The method of claim 14, wherein the one or more 3D integrated semiconductor device modules or the 3D integrated semiconductor device are electrically coupled to the stage.

16. The method of any of claims 14 to 15, wherein the one or more 3D integrated semiconductor device modules or the 3D integrated semiconductor device are capacitively coupled to the stage.

17. The method of claim 16, wherein the stage has a dielectric layer facing a 3D integrated semiconductor device module or the 3D integrated semiconductor device module has a dielectric layer or a semiconductor layer facing the stage.

18. A method of testing a 3D integrated semiconductor device module or a 3D integrated semiconductor device with at least one charged particle beam column, the method comprising:placing the 3D integrated semiconductor device module or the 3D integrated semiconductor device on a stage in a vacuum chamber;directing a charged particle beam of the at least one charged particle beam column on at least one test connection of the one or more 3D integrated semiconductor device modules to provide a charge on the at least one test connection;detecting signal electron signal of signal electrons provided upon impingement of the charged particle beam on the one or more 3D integrated semiconductor device modules; anddetermining a state information about the at least one test connection depending on a drop or decline in the signal electron signal.

19. The method of claim 18, wherein the drop or decline is compared with a die-to-die comparison.

20. An apparatus for testing of an integrated semiconductor device module, comprising:a vacuum chamber;a stage within the vacuum chamber, the stage being configured to support the integrated semiconductor device module;a charged particle beam column configured to generate a charged particle beam, the charged particle beam column comprising:a lens assembly with an objective lens configured to focus the charged particle beam on the integrated semiconductor device module;a scanner stage configured to scan the charged particle beam to different positions on the integrated semiconductor device module; andan electron detector for detecting signal electrons emitted upon impingement of the charged particle beam on the integrated semiconductor device module; anda controller having a processor and a memory, storing instructions that, when executed by the processor, cause the apparatus to perform a method according to any of claims 14 to 19.

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