Electrowetting-on-dielectric apparatus with 3D embedded electrode, microfluidic chip and methods of manufacturing

Abstract

A digital microfluidic chip may include a modular, multi-layer dielectric stack, the dielectric stack including a plurality of sub-layers stacked in a Z-direction. The DMF chip may include at least one multi-layer electrode embedded within at least one electrode-insulating sub-layer of the dielectric stack, the multi-layer electrode comprising: a connection trace, an electrode spatially offset in the Z-direction from the connection trace, and the electrode and connection trace being located in different electrode-insulating sub-layers.

Description

PATENT Attorney Docket No. TUOE.P2013WO / 00678799ELECTROWETTING-ON-DIELECTRIC APPARATUS WITH 3D EMBEDDED ELECTRODE, MICROFLUIDIC CHIP AND METHODS OF MANUFACTURINGRELATED APPLICATIONS

[0001] This application claims priority to and the benefit of U.S. Provisional Patent Application No. 63 / 748,512, filed January 23, 2025 and entitled “Electrowetting-on-Dielectric Apparatus with 3D Embedded Electrode, Microfluidic Chip and Methods of Manufacturing”. This application also claims priority to and the benefit of U.S. Provisional Patent Application No. 63 / 762,399, filed February 24, 2025 and entitled “Systems for Long-Term Digital Microfluidic Chips, and Managing Macrophage Cellular Interactions Using Said Chips”. Each of the aforementioned applications are incorporated by reference in their entireties.BACKGROUND

[0002] Digital microfluidic (DMF) platforms based on electrowetting-on-dielectric (EWOD) enable programmable manipulation of discrete droplets on a flat electrode surface using electric fields. It allows precise control of droplets at nanoliter volumes and have been widely explored for mixing, moving, or splitting, commonly used in chemical synthesis, diagnostics, and cell-based assays.

[0003] DMF presents numerous benefits for chemical and biomedical use, generating interest about its potential in the field. For example, it provides an ideal setting for biochemical reactions and analytical procedures, accommodating a variety of reagents in different (small) quantities. This reduces the likelihood of human error, enhances procedural efficiency, enables complex assays of minute / scare amounts of reagents, and boosts throughput. The nanoscale operations of DMF significantly decrease reagent and sample usage.

[0004] Moreover, the small, portable design of DMF chips makes them suitable for onsite diagnostics and remote applications, establishing them as fruitful tools in modern biomedical research. The fundamental principle behind digital microfluidics is electrowetting on dielectric (EWOD), which allows controlled positioning, merging, splitting, and mixing by applying voltage to a droplet on a dielectric material to alter its wetting properties. Traditional DMF chips with single-layered metal coating face limitations in expanding the operation area because all contact traces run between electrodes to make contact with them, causing a tradeoff between operational voltages as the electrode array size increases.PATENT Attorney Docket No. TUOE.P2014WO / 00678799

[0005] Despite these advantages, conventional DMF chips remain constrained by three persistent limitations. First, planar electrode architectures restrict electrode density due to routing congestion, resulting in a trade-off between operational area and actuation voltage. Second, commonly used single-layer dielectric coatings suffer from dielectric breakdown, current leakage, and humidity-induced degradation, particularly under cell culture conditions. Third, failure of the dielectric or hydrophobic layers typically renders the entire chip unusable, leading to high costs, limited design iteration, and increased electronic waste.

[0006] The inherent problems with the current state of the technology are the high droplet actuation voltages, and the number of electrodes that could be fit with single layer fabrication on a standard glass slide. These limit the range of applications and decrease the throughput of operations.

[0007] Due to conventional fabrication methods, DMF chips have been manufactured on printed circuit boards (PCBs), which have large electrode gaps and trenches with low-cost fabrication. Consequently, their operational voltages are higher than desired for biomedical applications. These limitations hinder the reduction of actuation voltages required for droplet manipulation. Currently, there are various types of digital microfluidic chips, including those built on glass substrates with single-plane electrodes, on printed-circuit boards, or based on thin film transistors. These designs have different objectives and focuses, such as expanding the operating area, cost-effective production, performing complex experiments, or targeting specific assays. Nevertheless, these architectures need to be sufficiently advanced to integrate all these features into one advanced design by combining improvements in the dielectric layer to enhance its operation and robustness in biomedical applications, particularly in cell studies.

[0008] Inflammation is a fundamental biological response triggered when the body detects foreign materials or damage signals. Regulating inflammation involves a complex interplay of two major contributors: cells and biochemical molecules. Macrophage cells emerge as central to inflammation and tissue repair among the other key players. Upon encountering foreign materials or damage signals, macrophages undergo phenotypic changes that dictate their function. Initially, macrophages secreting biomarkers dominated by pro-inflammatory signals are recruited to clear debris and pathogens, followed by a transition to macrophages secreting biomarkers dominated by anti-inflammatory signals that promote tissue healing and resolution of inflammation. The inflammatory site undergoes continuous influx of newly recruited macrophages, which are not yet conditioned to a specific phenotype. Understanding the polarization process, as well as the inter-cellular signalling is challenging yet crucial for mitigating immune-related complications. In addition to cellular responses,PATENT Attorney Docket No. TUOE.P2014WO / 00678799 biochemical molecules such as immunosuppressants and regulatory drugs play a significant role in managing inflammation. Cost-effective testing of the new drug candidates presents additional challenges due to the sophisticated cell culture models and precise measurement techniques required to study macrophage behaviour. As an interesting example, TCB-2, a selective serotonin 5-HT2A receptor agonist, shows promise as a novel candidate for modulating immune response to reduce inflammation. While other compounds, such as psylocibin, have been studied as anti-inflammatory agents and are believed to express their activity through the 5-HT2A receptors, they also interact with other 5-HT receptors, making it hard to discriminate the effect of 5-HT2A specific role. TCB-2, on the other hand is a highly selective and highly potent agonist of the 5-HT2A receptor. However, research into TCB-2 has been limited so far, being only scarcely studied in anti-inflammatory potential and macrophage polarization modulation for the body immune system. Exploring the potential of TCB-2 could lead to the development of more targeted and effective therapies, ultimately reducing immune-related complications.

[0009] Traditional cell culturing well plates often involve laborious, expensive, and complex workflows, when it comes to studying the effects of drug candidates. While miniaturized cell cultures can better match biological scale and improve cost-efficiency, they often involve a trade-off between maintaining physiological relevance and ensuring spatial and temporal control in the experiments. This limitation restricts our understanding of macrophage behaviour and the ways to regulate the immune response. Digital microfluidic (DMF) chips have emerged as promising tools in biological studies, offering precise manipulation of cells and fluids at the microscale, facilitating the complex, dynamic microenvironments in nanolitervolume droplets. Despite these advantages of DMF chips, DMF chips have not been widely used in longer-term cell studies yet. This limited adoption is primarily due to the short lifespan of the chips when exposed to the high humidity and mild temperature conditions necessary for cell culturing.SUMMARY

[0010] The present work integrates architectural, materials, and process-level innovations into a unified digital microfluidic platform that simultaneously enables low-voltage operation, long-term biological compatibility, immune-cell interaction studies, and post-failure regeneration of chip functionality. The platform combines a three-dimensional embedded-electrode architecture with modular multilayer dielectric stacks and reversible surface functionalization strategies.PATENT Attorney Docket No. TUOE.P2014WO / 00678799

[0011] A digital microfluidic chip may include one or more of several layers: a base layer, a metal layer, an insulating layer that insulates electricity (dielectric layer), and a water-repellent layer. These layers help move nano-liter-volume liquid droplets using electricity. The electricity may be controlled with operational electrodes (flat square shaped electrodes) in the metal layer. Each electrode can be controlled independently via a dedicated contact pad, which is connected to the operational electrode by connection traces.Platform architecture and operating principle

[0012] In an aspect, at least some embodiments described herein, introduce a 3D-architectured digital microfluidic chip (also referred to as “3D2MF” and / or “digital microfluidic chip”) with multilayered dielectric. By embedding the electrodes and contact traces within on various layers (such as SiN layers) using microfabrication techniques on a glass substrate, the DMF chip achieves lower actuation voltages and expanded operational area.

[0013] Embodiments herein may provide enclosed DMF systems, including a top plate with transparent (such as, but not limited to, indium tin oxide) electrode and a hydrophobic layer (including, but not limited to, FluoroPei, Teflon, silane-based coatings, and / or PDMS), while the bottom plate enables the main droplet manipulation via reservoir electrodes, contact traces, and contact pads, and a top plate with a fully transparent ground electrode. The contact pads are spaced to be able to match the spacing of the contact pins of the power supply that we use to operate the chip. Both plates in the closed DMF system are coated with hydrophobic layers to reduce the actuation voltage by increasing the droplet contact angle.

[0014] The platform therefore may be based on a three-dimensional digital microfluidic architecture in which operational electrodes and their interconnects are embedded within insulating layers rather than being patterned on a single planar surface. Vertical electrical contacts through insulating layers enable individual addressing of actuation electrodes in an extended electrode array thanks to routing interconnects beneath the operational plane. Advantageously, this fabrication process flow decouples electrode density from lateral routing requirements and allows dense electrode arrays to be implemented without increasing electrode pitch, leading higher operational voltage. This architecture enables the electrodes to be spread widely without affecting their performance on glass, which is stable and doesn’t react with biological samples during use of the final manufactured digital microfluidic chip. The architecture of embodiments herein may advantageously reduce the gap between electrodes, which lowers the voltage needed to move the droplets. These improvements are particularly advantageous for biological and chemical experiments. Further, the architecture discussedPATENT Attorney Docket No. TUOE.P2014WO / 00678799 herein advantageously reduces the voltage needed to manipulate droplets by embedding the electrodes in silicon nitride, which served a secondary dielectric layer as silicon nitride is a good insulator. Application of a lower voltage is more convenient for handling droplets with sensitive biological samples such as cells and proteins. As compared to the previously introduced devices, our method allows for high throughput without needing high voltage. This results in a digital microfluidic chip that is more robust and requires less voltage to operate.

[0015] The platform may operate as a closed-system DMF, composed of a bottom substrate carrying the embedded electrode network and dielectric stack, and a top substrate incorporating a transparent ground electrode and hydrophobic coating. Application of an alternating voltage between selected bottom electrodes and the top ground electrode induces local modulation of the solid-liquid interfacial energy according to the Young-Lippmann relation, enabling controlled droplet transport, merging, splitting, and mixing.

[0016] Embedding the electrodes within the insulating layer, underneath dielectric layer, provides two additional functional advantages beyond routing efficiency. First, this formation improves insulation, polarization, and reduces pinhole formation, contributing to reduced actuation voltages. Second, it physically isolates the electrode network from the chip surface, allowing surface layers to be removed and re-deposited without damaging the electrical infrastructure. This architectural separation enables both long-term biological operation and chip regeneration.Dielectric stack engineering for low -voltage actuation and environmental robustness

[0017] The technology of digital microfluidics is based on the principle of electrowetting. Electrowetting allows to change the contact angle of a droplet by applying an electrical field through the electrode. To achieve electro wetting without a running electrical current through the droplet, we use a dielectric layer on top of the metal electrodes and a hydrophobic layer which increases the initial contact angle of the droplet and reduced the actuation voltage to manipulate the droplet. By applying voltage to the target area, the dielectric layer is polarized, forming an electric double layer at the liquid-solid interface. This reduces the surface tension, leading to a change in the contact angle. By controlling individual electrodes arranged in an array, we can manipulate tiny (nanoliter-volume) droplets, enabling their movement, dispensing, merging, and mixing with great efficiency. This process may be referred to as Electrowetting on Dielectric (EWOD).

[0018] In EWOD-based systems, the dielectric layer must simultaneously provide high capacitance, low leakage current, high breakdown voltage, and resistance to environmentalPATENT Attorney Docket No. TUOE.P2014WO / 00678799 stressors such as humidity, temperature, and ionic solutions. No single dielectric material satisfies all of these requirements across all experimental timescales. Accordingly, the platform employs modular multilayer dielectric stacks optimized for distinct operational regimes.

[0019] For dense electrode arrays and low-voltage operation, a multilayer dielectric stack composed of silicon nitride (SiN) and Parylene C may be employed. It should be appreciated that these materials are merely example materials, and the invention herein is not limited to just these materials. SiN provides high dielectric strength and mechanical stability, while Parylene C offers conformal coverage, highered polarization and reduced pinhole density. Finite-element simulations and experimental characterization demonstrate that this configuration enables reliable droplet actuation at voltages as low as approximately 50 V, while maintaining leakage currents below biologically relevant thresholds (<10 nA). Optimization of layer thicknesses minimizes electric field intensity within each dielectric layer and enhances long-term stability during repeated actuation cycles by optimizing the safety factor ( breakdown voltage / actuation voltage).

[0020] For extended biological experiments requiring continuous exposure to high humidity and physiological temperature, alternative dielectric stacks based on polymeric materials are utilized. In particular, combinations of polyvinylidene difluoride (PVDF) and SU-8 photoresist materials may be utilized. PVDF provides a high dielectric constant and low actuation voltage, while cross-linked SU-8 offers strong resistance to moisture penetration and mechanical degradation. The combined PVDF / SU-8 stacks demonstrate stable droplet actuation and minimal surface current for periods exceeding 60 days in incubator conditions, significantly outperforming conventional Parylene C-based dielectrics.

[0021] Advantageously, at least some of the dielectric sub-layers herein of the dielectric stack may be “modular” in that they are deposited above the embedded electrode architecture, allowing the dielectric composition to be selected, removed, and replaced according to experimental needs without altering the electrode layout. This modularity enables the same platform to support both short-term high-precision assays and long-term biological studies.Dielectric stack engineering for low -voltage actuation and environmental robustness

[0022] Traditional cell culturing well plates often involve laborious, expensive, and complex workflows, when it comes to studying the effects of drug candidates. While miniaturized cell cultures can better match biological scale and improve cost-efficiency, they often involve a trade-off between maintaining physiological relevance and ensuring spatial andPATENT Attorney Docket No. TUOE.P2014WO / 00678799 temporal control in the experiments. This limitation restricts our understanding of macrophage behaviour and the ways to regulate the immune response.

[0023] DMF chips have emerged as promising tools in biological studies, offering precise manipulation of cells and fluids at the microscale, facilitating the complex, dynamic microenvironments in nanoliter-volume droplets. Culturing biological cells using, a digital microfluidics chip requires that the chip is placed in an cell culture incubator, where constant temperature (37°C), high humidity (90-95%) conditions are present. Also, the chip is exposed to liquid droplets on the chip surface at all times during the cell culture. Those conditions can cause dielectric degradation, causing vaporized water to penetrate into the dielectric material and upon electric field application, resulting in the increase of conductivity of the dielectric material which eventually leads to a material break down. This compromises chip integrity, as well as the cell experiment in question. As such, despite advantages of DMF chips, DMF chips have not been widely used in longer-term cell studies yet. This limited adoption is primarily due to the short lifespan of the chips when exposed to the high humidity and mild temperature conditions necessary for cell culturing. Embodiments discussed herein, however, offer at least the following advantages: (1) embedding the electrodes and contact traces within silicon nitride (SiN) layers allows for an expandable operational area and a robust chip that can withstand continuous humidity and moderate temperature conditions required for cell-culture, and (2) a denser and more compact electrode arrangement combined with 3D-architectured dielectric layers leads to lower actuation voltages

[0024] Although the dielectric layer in conventional DMF chips prevents voltage dissipation to the top of the multilayer structure, conventional dielectric materials may not always provide adequate protection against humidity, which is crucial for cell culture applications. In some embodiments, culturing biological cells using a digital microfluidics chip requires that the chip is placed in an cell culture incubator, where constant temperature (37°C), high humidity (90-95%) conditions are present. Those conditions can cause dielectric degradation, causing vaporized water to penetrate into the dielectric material and upon electric field application, resulting in the increase of conductivity of the dielectric material which eventually leads to a material break down. This compromises chip integrity, as well as the cell experiment in question.

[0025] Polyvinylidene difluoride (PVDF) has been mostly preferred as a dielectric layer due to its high dielectric constant. However, the deposition technique and conditions affect the integrity of the PVDF layer, as well as the electrical stability of the material leading to inconsistent performance in cell culturing over extended periods.PATENT Attorney Docket No. TUOE.P2014WO / 00678799

[0026] The platform’s dielectric robustness and low-voltage operation enable direct integration of cell-based assays within digital microfluidic droplets. Human-derived macrophages and fibroblasts were cultured directly on the chip surface and subjected to controlled biochemical perturbations. Droplet-based delivery of cytoskeletal inhibitors and inflammatory stimuli enabled precise control of cellular microenvironments while reducing reagent consumption by more than two orders of magnitude compared to conventional wellplate assays.

[0027] In long-term experiments, naive macrophages were induced toward pro-inflammatory phenotypes and subsequently treated with candidate anti-inflammatory compounds. Single-cell cytokine profiling revealed dynamic modulation of TNF-a and IL-10 expression over time, demonstrating the platform’s suitability for studying immune polarization and intercellular signaling. The ability to maintain stable electrical performance under incubator conditions was essential for preserving cell viability and preventing unintended electrical stimulation artifacts.

[0028] These results establish the platform embodied by the systems and methods herein as a versatile tool for studying immune cell behavior, drug response, and cellular heterogeneity under tightly controlled spatiotemporal conditions.Failure modes in digital microfluidics and motivation for regeneration

[0029] Despite advances in dielectric engineering, digital microfluidic chips remain susceptible to performance degradation over time due to dielectric breakdown, biofouling, and surface contamination. Such failures are particularly costly because DMF fabrication requires cleanroom facilities, multiple lithographic steps, and specialized equipment. As a result, chips are typically discarded after failure, limiting experimental throughput and contributing to electronic waste.

[0030] Given that dielectric and hydrophobic layers are the primary failure points, while embedded electrodes and substrates often remain structurally intact, embodiments of the systems and methods discussed herein investigate whether chip functionality could be restored through selective removal and re-deposition of surface layers.

[0031] A regeneration protocol is described below to restore non-functional DMF chips by removing degraded hydrophobic and dielectric layers while preserving the embedded electrode architecture. The process includes sequential solvent-based stripping of hydrophobic and Parylene layers, ultrasonic cleaning, oxygen plasma ashing to remove organic residues, and reactive ion etching to selectively remove silicon nitride layers where required. FreshPATENT Attorney Docket No. TUOE.P2014WO / 00678799 dielectric and hydrophobic coatings are then deposited following standard fabrication protocols.

[0032] Chips were regenerated and reused for up to five cycles. After each cycle, surface roughness, dielectric breakdown voltage, and droplet actuation voltage were characterized. While a gradual increase in surface roughness was observed, the actuation voltage and dielectric robustness remained within operational ranges suitable for EWOD-based droplet manipulation. Scanning electron microscopy confirmed preservation of electrode integrity after repeated regeneration cycles.

[0033] Demonstrations of droplet transport and splitting on regenerated chips confirmed full recovery of microfluidic functionality. This regeneration capability significantly extends chip lifetime, reduces fabrication cost, and enables iterative design-test cycles that are otherwise impractical with single-use DMF platforms.BRIEF DESCRIPTION OF THE FIGURES

[0034] Figure 1 shows an example method of manufacturing a digital microfluidic chip, in embodiments.

[0035] Figure 2 depicts a schematical diagram showing each step of the method of Figure 1, in an embodiment.

[0036] Figure 3 is a perspective view showing various steps of the method of Figure 1.

[0037] Figure 4 is a top view an example DMF chip manufactured using the technique(s) discussed with respect to Figures 1 - 3.

[0038] Figure 5 shows a non-limiting example of the top plate of the DMF chip manufactured according to the method of Figure 1, in embodiments.

[0039] Figure 6 shows an example DMF chip manufactured using the technique(s) discussed with respect to Figures 1 - 5.

[0040] Figure 7 shows an actual DMF chip manufactured according to the method of Figure 1 electrowetting a droplet thereon.

[0041] Figure 8 shows an embodiment of a DMF chip having a dielectric stack with improved humidity resistance.

[0042] Figures 9A-D show the advantages of the dual dielectric layer stack discussed above by comparing different configurations of the dielectric stack (e.g., single layer Parylene C; single layer PVDF; single layer SU-8; first sub-layer SU-8 covered with second sub-layer PVDF; sub-layer PVDF covered with second sub-layer SU-8).PATENT Attorney Docket No. TUOE.P2014WO / 00678799

[0043] Fig. 10 is a color map of finite element analysis for electrical potential distribution on multilayered dielectric and electrical field distribution for dielectric layers and the droplet.

[0044] Figure 11 demonstrates the inverse proportion of the electrical potential distribution with regard to the dielectric constants of the materials described as capacitors in series.

[0045] Figure 12 depicts a chart showing the impact of the multilayer dielectric stack by measuring breakdown voltage, current leakage, and contact angle change.

[0046] Figure 13 is a box plot of the breakdown voltage of the multilayered dielectrics.

[0047] Figure 14 is a plot of current leakage measurement in the operational voltage range (n = 3).

[0048] Figure 15 shows 90° tilted microscope images of the droplets placed on multilayered dielectric stack.

[0049] Figure 16 shows workflow of a cell response experiment where unconditioned macrophages were introduced to a range between 0 and 4 gM of Cytochalasin D.

[0050] Figure 17 shows live-dead imaging of the macrophages after 24 h of culture on the DMF chip.

[0051] Figure 18 shows quantitative analysis of the cell area of macrophages and fibroblasts indicating the dissociation of the cell membrane.

[0052] Figure 19 shows DAPI (nucleus, blue)-Phalloidin (cytoskeleton, green) staining of the macrophages and fibroblasts after exposure to varying concentrations of Cytochalasin D.

[0053] Figure 20 shows cell response study of macrophage and fibroblast cells with cytochalasin D on well plates.

[0054] Figure 21 shows quantitative analysis of the cell area of macrophages and fibroblasts indicating the dissociation of the cell membrane (n = 25±15, each cell is analyzed individually).

[0055] In Figure 22, it shows quantifying macrophage cell viability on the DMF chip, where 86%, 92%, and 83% of the cell population was viable across three independent chip experiments, resulting in an average of 87% viable cell culture after 7 days.

[0056] Figures 22A-G show cell viability on a DMF chip and does control of potential anti-inflammatory treatment TCB-2.

[0057] Figure 23A shows Live-dead imaging of the cells after 7 days of culture in a well plate.PATENT Attorney Docket No. TUOE.P2014WO / 00678799

[0058] Figure 23B shows Quantitative analysis of negative (control condition, untreated) and positive (H2O2 treated cell culture to induce cell death) controls (n = 3).

[0059] Figure 23 C shows TNF-a cytokine release quantification under two concentration of inflammatory stimuli (n = 3,-300 individual cells per condition per n , ns = nonsignificant, **** p<0.001).

[0060] Figure 23D shows TNF-a cytokine release quantification in inflammatory cell culture, inflammatory cell culture treated with TCB-2 drug, negative control and TCB-2 only treatment control (n = 3,-300 individual cells per condition per n, **** p<0.001).

[0061] Figure 24A shows current leakage measurement in PVDF (1 pm) + SU-8 (5 pm) chips over the course of 60 days.

[0062] Figure 24B shows quantitative analysis of macrophage cytokine expression over the course of 7 days based on TNFa and IL-10 expressions (n = 3).

[0063] Figures 25 A-C show effect of high humidity and liquid exposure on material electrical and surface properties.

[0064] Figure 26A indicates current output response of PVDF dielectric upon application of voltage up to 1500 V.

[0065] Figure 26B indicates current output response of SU-8 dielectric upon application of voltage up to 3000 V.

[0066] Figure 26C indicates current output response of SU-8 + PVDF dielectric stack upon application of voltage up to 3000 V.

[0067] Figure 26D indicates current output response of SU-8 + PVDF dielectric stack upon application of voltage up to 3000 V.

[0068] Fig. 27 is a flowchart of an example method for recycling a digital microfluidic (DMF) chip.

[0069] Figure 28 shows a schematic diagram of the steps of the method of Fig. 27.

[0070] FIG. 29A shows average surface roughness values measured on glass substrates from Cycle 1 (new chip) to Cycle 5.

[0071] FIG. 29B shows breakdown voltage measurements of the dielectric layer from Cycle 2 to Cycle 5.

[0072] FIG. 29C shows actuation voltage required for droplet movement and splitting across recycling cycles.

[0073] FIG. 29D shows scanning electron microscope (SEM) images of a new DMF chip (Cycle 1) and a recycled chip, both shown at x 300 magnification.PATENT Attorney Docket No. TUOE.P2014WO / 00678799 DETAILED DESCRIPTION DMF Platform Architecture and Manufacturing

[0074] Figure 1 shows an example method 100 of manufacturing a digital microfluidic chip, in embodiments. Figure 2 depicts a schematical diagram 200 showing each step of flowchart 100, in an embodiment. Figure 3 is a perspective view showing various steps of the method of Figure 1. Figure 4 is a top view an example DMF chip 300 manufactured using the technique(s) discussed with respect to Figures 1 - 3. Figure 5 is cross-sectional views corresponding to section lines defined in Figure 4. Figure 6 shows an example DMF chip 300 manufactured using the technique(s) discussed with respect to Figures 1 - 5. Figures 1 and 2 are best viewed together with the following description. In Figure 2, not all instances of a given element are labeled with a reference number for clarity. For example, “substrate 202” is only referenced with “202” once, but it should be appreciated that for each step schematically shown the reference number “202” applies to the substrate unless otherwise stated. It should be appreciated that some of the steps described herein are not required, or additional steps may be included in the manufacturing method without departing from scope hereof. A series of photolithography processes, etching, and lift-off for layer patterning may be used to fabricate the bottom plate of the DMF chip. The masks utilized may have, but are not limited to, a resolution of 50800 DPI on a film photomask.

[0075] At step 102, a substrate 202 is provided. In one example, the substrate 202 is a glass substrate. In an example, substrate 202 is a double-size microscope glass substrate (52x75 mm, VWR). In an example, step 102 may include a sub-step of cleaning the glass substrate 202, for example by placing the substrate 202 in in an ultrasonic bath. The ultrasonic bath may include, but is not limited to Micro-90® cleaning solution at a 2% concentration, acetone, and isopropanol. Step 102 may include a sub-step of drying the substrate. For example, the substrate 202 may be dried using nitrogen and placed on a hotplate at 110 °C for 10 minutes. As another example, step 102 may include oxygen plasma treatment performed at 50 W for 2 minutes before photolithography. Oxygen plasma treatment at 50W for 2 minutes, and use of nitrogen, the temperature of 110 °C and period of 10 minutes, are merely exemplary and not intended to be limiting in scope.

[0076] At step 104, connection traces are provided. In embodiments, they may be provided on the substrate. In embodiments, they may be provided with one or more other layer(s) between the connection trace and the substrate. As an example of store 104, photolithography is used to pattern the desired connection trace(s), and then metal (such asPATENT Attorney Docket No. TUOE.P2014WO / 00678799 chromium with a thickness of 50 nm) is deposited on the cleaned glass substrate 202 (such as but not limited to using the Q300T D Plus sputter coater (Quorum, UK)) resulting in patterned connection traces 204 as shown in 104a-c of Figure 2. Chromium, the thickness of 50 nm, and the Q300T D Plus sputter coater are merely examples and not intended to be limiting in scope. Subsequently, the base metal layer, including contact pads and connection traces, is lifted off.

[0077] At step 106, one or more dielectric electrode-insulating sub-layers 206 of a dielectric stack having a plurality of sub-layers is deposited. In one non-limiting example of step 106, a 400 nm -thick silicon nitride layer, which insulates the metal layers of step 104, was deposited through plasma-enhanced chemical vapor deposition (PECVD). Contact and top plate contact pads deposited during step 104 may be shielded (e.g., using a metal frame) during step 106.

[0078] At step 108, vertical traces are patterned through the one or more dielectric electrode-insulating sub-layers of the dielectric stack of step 106. As a non-limiting example of step 108, photolithography (illustrated by 108a in Figure 2) and reactive-ion etching (RIE) (illustrated by 108b in Figure 2) for 2 minutes using, but not limited to, the PlasmaLab System 100 (Oxford Instruments, UK) are performed to open all-through holes on the silicon nitride layer for vertical addressing of each electrode.

[0079] At step 110, at least one electrode and corresponding vertical contact are provided for each of a plurality of multi-layer electrode embedded within at least one electrodeinsulating sub-layer of the dielectric stack. In an example, the electrodes 208 are spatially offset in the Z-direction from the connection traces 204 provided in step 104. The vertical contacts 210 extend in the Z-direction between the connection traces and the electrode. Each electrode 208 and respective connection trace 204 are respectively located in different dielectric electrode-insulating sub-layers of the dielectric stack. As an example of step 110, another photolithography step (illustrated by 110a in Figure 2) followed by a lift-off process (illustrated by 110c in Figure 2) patterned a 10 by 10 array of square-shaped operational electrodes with a 4 mm2 area and four large reservoirs. Between the photolithography and liftoff process, chromium and gold were sputter-coated with 10 nm and 80 nm thicknesses (illustrated by 108b in Figure 2), respectively, to pattern the second metal layer on the insulating layer.

[0080] At step 112, additional sub-layers of the dielectric stack are provided. In the non-limiting example shown in Figure 2, an additional electrode-insulating sub-layer 213 of silicon nitride with a thickness of 400 nm and an additional dielectric sub-layer, or layers 215, 216 of parylene C with a thickness of 1 pm were deposited to form the multilayered dielectricPATENT Attorney Docket No. TUOE.P2014WO / 00678799 stack. The resulting dielectric stack includes a plurality of dielectric sub-layers. In the example of Figure 2, there are 5 sub-layers shown: a first electrode-insulating sub-layer 211 having the connection trace 204 therein, a second electrode-insulating sub-layer 212 having the vertical contact 210 therethrough, a third electrode-insulating sub-layer 213 having the electrode 208 therein, a first additional dielectric sub-layer 214, and a second additional dielectric sub-layer 215. The additional sub-layers 214 and 215 may be a single layer and / or there may be more or fewer sub-layers and / or electrode-insulating sub-layers than shown in Figure 2.

[0081] The material of the dielectric sub-layers of the dielectric stack may vary other than those shown herein. For example, the dielectric layout of the dielectric sub-layers may be selected by characterizing SiN and Parylene C (PaC) layers based on the Young-Lippman equation:where, sris the dielectric constant, Lis the applied voltage, d is the dielectric layer thickness, yLMis the surface tension between the droplet and the medium interface, 0(F) and 0(0) are the contact angles of the droplet during and before applying voltage. According to this equation, the thickness of the dielectric stack has a logarithmic correlation with the voltage required to move a droplet.

[0082] Accordingly, other dielectric materials may be used for any one or more of the electrode-insulating sub-layers, or the additional sub-layers discussed herein, such as but not limited to PaC, poly vinylidene difluoride-co-hexafluoropropylene (PVDF-HFP), SU-8, and SiN, as well as derivatives of polydimethylsiloxane (PDMS), PDMS composites with graphene oxide particles, chosen for their dielectric properties and stability. However, these materials involve trade-offs between current leakage, breakdown voltage, and high actuation voltage, which would be factors considered for achieving efficient droplet manipulation during actuation. Achieving a dual function of low actuation voltage and high stability in a multilayer dielectric stack requires careful consideration of the dielectric properties and optimization of thickness.

[0083] Additional dielectric sub-layer 215 and / or 216 may have a capacity of polarizing upon application of electrical field but works also as an insulator, isolating the chip surface from direct current. Additional dielectric layer 215216 may be sub layers of different material. In a particular embodiment, the first material comprising polyvinylidene difluoride (PVDF); the second material comprising SU-8 photoresist. In embodiments, the first additional dielectric sub-layer 214 (e.g., the PVDF) is between the electrode-insulating sub-layers (e.g.,PATENT Attorney Docket No. TUOE.P2014WO / 00678799 211, 212, 213) and the second additional dielectric sub-layer 215 of the dielectric stack. However, in other embodiments, the second additional dielectric sub-layer 215 (e.g., SU-8) may be between the electrode-insulating sub-layer(s) (211, 212, and / or 213) and the first dielectric sub-layer 214 (e.g., PVDF) of the dielectric stack.

[0084] In particular embodiments, SiN is the material of the electrode-insulating sub-layer(s) (e.g., 211, 212, and / or 213), SiN is also the material of an additional dielectric sublayer (e.g., first additional dielectric sub-layer 214)(however this layer may not be included), and Parylene C is the material of a second additional dielectric sub-layer (e.g., second additional dielectric sub-layer 215). In another particular embodiment, SiN is the material of the electrode-insulating sub-layer(s) (e.g., 211, 212, and / or 213), PVDF is the material of an additional first dielectric sub-layer (e.g., first dielectric sub-layer 214), and SU-8 is the material of a second additional dielectric sub-layer (e.g., second additional dielectric sub-layer 215). In another particular embodiment, PVDF is the material of the electrode-insulating sub-layer(s) (e.g., 211, 212, and / or 213), PVDF is also the material of an additional dielectric sub-layer (e.g., first additional dielectric sub-layer 214)(however this layer may not be included), and SU-8 is the material of a second additional dielectric sub-layer (e.g., second additional dielectric sub-layer 215). Accordingly, it should be appreciated that various combinations of materials for the sub-layers of the dielectric stack are contemplated hereby.

[0085] At step 114, a coating layer is provided. In the non-limiting example shown in Figure 2, the surface was then spun-coated with Fluoropel 1604V (Cytonix) and baked in an oven at 180 °C for 10 minutes for the surface treatment. The DektakXT® Profiler was used to characterize the surface profile and thickness of the layers in each fabrication step. It should be appreciated that fluoropel, the 180 °C , and period of 10 minutes are merely examples and not limiting in scope.

[0086] At step 116, a top plate may be provided above the last layer of the dielectric stack. Figure 5 shows a non-limiting example of the top plate of the 3D2MF chip, including a glass substrate layer 502 coated with a layer 504 of indium tin oxide (ITO) at a size of 51 x 21.4 mm. A hydrophobic layer 506 (such as but not limited to FluoroPei PFC1601V-FS) is spun-coated on the coating layer 504. As shown in Figure 5, the coating layer 504 and the hydrophobic layer may form a window 508 by being patterned by plasma ashing to structure the hydrophilic window areas, which serve as cell culturing regions. The window 508 may, but is not required to, have an equal squared area to electrodes. During plasma ashing, the top plate may be shielded with a glass slide containing through-holes to remove the hydrophobic coating 506 and coating layer 504 from specific areas. Accordingly, the electrode 208 mayPATENT Attorney Docket No. TUOE.P2014WO / 00678799 include an array of electrodes 404, such as shown in Figures 3 and 4. The top plate may including a plurality of windows 508 therein, each window aligned with an electrode 208 of the array of electrodes.

[0087] A DMF chip therefore includes: a modular, multi-layer dielectric stack, the dielectric stack including a plurality of sub-layers (e.g., dielectric 206 and 212) stacked in a Z-direction. At least one multi-layer electrode (e.g., the combination of any one or more of connection trace 204, and / or electrode 208, and / or vertical contact 210) embedded within at least one electrode-insulating sub-layer of the dielectric stack. The multi-layer electrode may include a connection trace (e.g., 204), an electrode (e.g., 208) spatially offset in the Z-direction from the connection trace, and the electrode and connection trace being located in different dielectric sub-layers. The multi-layer electrode may further include a vertical contact 210 coupling the electrode to the connection trace.

[0088] The at least one electrode-insulating sub-layer may include a first electrodeinsulating sub-layer, a second electrode-insulating sub-layer, and a third electrode-insulating sub-layer. The connection trace 204 may extending within the first electrode sub-layer. The electrode 208 may extend within the third electrode-insulating sub-layer. The vertical contact 210 may extend through the second electrode-insulating sub-layer in the Z-direction between the connection trace and the electrode. Dielectric material of the second electrode-insulating sub-layer may be located between the electrode and the connection trace, as shown in Figure 2.

[0089] The at least one multi-layer electrode 208 being one of a plurality of multilayer electrodes arranged in an array 404 within the dielectric stack. Advantageously, each connection trace of each electrode within the plurality of multi-layer electrode array may be located within the same sub-layers of the dielectric stack. Each connection trace coupled to a respective contact pad 406 located outside of an operational area of the dielectric stack. A controller 402 may be coupled to each contact pad and operable to implement electrowetting using the electrodes 208.

[0090] The dielectric stack may include an additional dielectric sub-layer, the additional dielectric sub-layer positioned above the third electrode-insulating sub-layer in the Z-direction. The first electrode-insulating sub-layer, the second electrode-insulating sub-layer, and the third sub-layer may include a first dielectric material. The additional comprising sublayer may include a second dielectric material different than the first dielectric material. The first dielectric material may be an inorganic dielectric material. The first dielectric material may be silicon nitride. The second dielectric material may be a conformal polymer dielectricPATENT Attorney Docket No. TUOE.P2014WO / 00678799 material. The second dielectric material may be Parylene C. The first dielectric material may have a first thickness of 400nm or less and the second dielectric material having a second thickness of 0.5pm or less. The first dielectric material may have a first thickness of 400nm or less and the second dielectric material having a second thickness of 1pm or less. The first dielectric material having a first thickness of 400nm or less and the second dielectric material having a second thickness of 2pm or less.

[0091] The multi-layer dielectric stack and the multi-layer electrode may be manufactured on a substrate layer (e.g., 202), the dielectric stack positioned above the substrate layer in the Z-direction. The substrate layer may be glass.

[0092] The DMF chip may further include a coating layer 216, the coating layer positioned above the dielectric stack in the Z-direction. The coating layer 216 may include a hydrophobic layer. The hydrophobic layer may include FluoroPei. The coating layer 216 may have a thickness of between about 50 nm and about 100 nm.

[0093] The manufactured DMF chip according to method 100 may be coupled to a controller for operation. Controller 402, for example, may be coupled to each contact pad having a respective connection trace to an electrode. Controller 402 may further be operably coupled to non-transitory memory that stores instructions that, when executed by the controller 402, control the DMF chip to implement electrowetting to actuate and move droplets across the electrodes. The digital microfluidic chip may thus operates to actuate fluid between the at least one multi-layer electrode and another multi-layer electrode at an actuation voltage of 1000V or less, optionally 50V or less, optionally at by alternating current at 10kHz.

[0094] For example, the machine readable instructions, when executed by the controller 402, may manipulate droplets, using the at least one multi-layer electrode, by electrowetting to deliver controlled biochemical stimulation to immune cells at the respective culture sites corresponding to a location of one or more of the electrodes. As another example, the instructions, when executed by the controller, may cause dynamic modulation of immune cell state by sequentially delivering droplets comprising a candidate immunomodulatory compound at a controlled concentration and subsequently removing or adjusting the compound by electrowetting actuation of selective ones of the at least one electrode.

[0095] In an example including multiple culture sites, the controller 402 coupled to the at least one multi-layer electrode and machine readable instructions that, when executed by the controller, may manipulate droplets, using the at least one multi-layer electrode, by electrowetting to deliver controlled biochemical stimulation to immune cells at the respective culture site. The controlled biochemical stimulation comprises contacting macrophages with aPATENT Attorney Docket No. TUOE.P2014WO / 00678799 biochemical stimulator to induce a pro inflammatory polarization. The biochemical stimulator may include lipopolysaccharide (LPS) at a final concentration of about 0.5-2 pg / mL or interferon y (IFN y) at a final concentration of about 10-30 ng / mL. Each of the at least one culture site may be functionalized to promote cell adhesion and provides optical access through a top plate of the DMF chip, thereby enabling quantification of cytokine secretion at a single cell level. The at least one culture sites may be configured to support population level cytokine quantification by aggregating signals from multiple cells within the at least one culture sites. The cytokines may include one or more of tumor necrosis factor a (TNF a) or interleukin 10 (IL 10). Thus, the instructions, when executed by the controller 402, causing dynamic modulation of immune cell state by sequentially delivering droplets comprising a candidate immunomodulatory compound at a controlled concentration and subsequently removing or adjusting the compound by electrowetting actuation of selective ones of the at least one electrode. The examples discussed below support these electrowetting and controlled biochemical stimulation to immune cell features.

[0096] The DMF chip may further include a top plate 501 as a top-most layer of the DMF chip in the Z-direction. The dielectric stack and the at least one multi-layer electrode are components of a bottom plate of the DMF chip. The top plate may include including a transparent ground electrode. The top plate may include an indium tin oxide (ITO) layer having sections corresponding to locations of one or more electrodes, the sections having portions of the ITO layer removed therefrom. Thus, where the electrode is part of an array of electrodes, the top plate may include a plurality of windows 508 therein, each window aligned with an electrode of the array of electrodes.DMF Chip with dual sub-layer dielectric stack embodiments:

[0097] Other embodiments of the dielectric stack may be implemented without departing from the scope hereof. For example, Figure 8 shows an embodiment of a DMF chip having a dielectric stack with improved humidity resistance. DMF chip 800 includes a substrate layer 802, an electrode layer 804 having an electrode and corresponding electrode-insulating dielectric layer (or sub-layer(s)), and a first dielectric layer 806 and a second dielectric layer 808, and a coating layer 810. A droplet 812 is shown above coating layer 810. Substrate layer 802 may be the same as substrate layer 202, discussed above. Electrode layer 804 may include the electrode-insulating sub-layers discussed above with respect to Figures 2-7, such as connection trace 204, electrode 208, and vertical contact 210 in respective first, third, and second dielectric electrode-insulating sub-layers of the dielectric stack. However, inPATENT Attorney Docket No. TUOE.P2014WO / 00678799 embodiments, the electrode layer 810 need not have the multi-layer electrode format, but instead may be a single-layer electrode. Coating layer 810 may be the same as coating layer 216. Herein, if an element is described as “may be the same as” it means the corresponding description of the “same as” element applies thereto (e.g., the description of substrate layer 202 applies to substrate layer 802, and vice versa). Although not shown, DMF chip 800 may include a top plate which may be the same as top plate 501 discussed herein.

[0098] The following description of first dielectric layer 806 and a second dielectric layer 808 may apply to the additional dielectric layers 214 and 215 discussed above. First dielectric layer 806 may be a first material, and the second dielectric layer 808 may be a second material. In a particular embodiment, the first material comprising polyvinylidene difluoride (PVDF); the second material comprising SU-8 photoresist. In embodiments, the first dielectric sub-layer (e.g., the PVDF) is between the electrode layer and the second dielectric sub-layer. However, in other embodiments, the second dielectric sub-layer (e.g., SU-8) may be between the electrode layer and the first dielectric sub-layer.

[0099] This paragraph may be an example of step 112 discussed above. In a particular embodiment to manufacture the dielectric stack layers 806 and 808, a solution of polyvinylidene fluoride (PVDF) at a concentration of 200 mg / mL in N, N-dimethylformamide was spin-coated onto the chip surface at 1000 rpm for 1 minute to form a thin layer. Subsequently, the coating was evaporated for 60 minutes at 60°C to enhance nucleation and baked for 30 minutes at 110°C. Following this, the chips were rapidly removed from the hot plate to facilitate rapid cooling. For SU-8 3005 coating, the photoresist was spin-coated onto the chip surface at 4000 rpm to achieve a 5 pm film thickness and processed according to the manufacturer’s instructions. Upon completion of the deposition process, SU-83005 was hard-baked at 200°C for 30 minutes, with a gradual heating and cooling rate of approximately 2°C per minute. For dielectric stacks, in one embodiment, each material was fully processed as described above before spin-coating the next layer.

[0100] The first dielectric sub-layer 806 may have a first thickness and the second dielectric sub-layer 808 having a second thickness, the first thickness being less than the second thickness. In at least some embodiments, the ratio of the first thickness (e.g., thickness of the PVDF material, or some other material) to the second thickness (e.g., thickness of SU-8 material, or some other material) is 1:5.

[0101] Figures 9A-D show the advantages of the dual dielectric layer stack discussed above by comparing different configurations of the dielectric stack (e.g., single layer Parylene C; single layer PVDF; single layer SU-8; first sub-layer SU-8 covered with second sub-layerPATENT Attorney Docket No. TUOE.P2014WO / 00678799 PVDF; sub-layer PVDF covered with second sub-layer SU-8). In particular, Figure 9A shows a schematic overview of material types and layer thicknesses (not to the scale); Figure 9B shows the surface profile for each material combination, where G denotes measured mean roughness of the surface; Figure 9C shows droplet actuation voltage determined by water contact angle as a function of voltage (n = 3); and Figure 9D shows the breakdown voltage of the dielectric material characterized by current as a function of voltage (n = 3). All parameters were characterized for SU-8 3005, polyvinylidene fluoride (PVDF), and combination of these materials. The grey shade represents the standard deviation.

[0102] Figures 25A-C show effect of high humidity and liquid exposure on material electrical and surface properties. In particular, Figure 25A shows quantitative analysis of current over 7 days for the materials and their combinations; Figure 25B shows surface profile of the DMF chips before and after storing chips at 37 °C and 95% humidity and actuating them under these environmental conditions; Figure 25C shows quantitative characterization of the surface roughness over time. The chips were stored 37°C and 95% humidity (n = 3 for each sample) actuated with previously calculated actuation voltage every day for 20 seconds. All parameters were characterized for SU-8 3005, polyvinylidene fluoride (PVDF), and combination of these materials.

[0103] In Figure 25, dielectric stacks were placed in an incubator for 60 days and actuate them for 20 seconds every 24 h with the minimum actuation voltage determined per material earlier in this work. 20 second actuation intervals was chosen in order to have a measurement of the stabilized current output over the course of an average time for which the electrodes could be actuated in a DMF operation. The samples were actuated at three different fixed spots using 0.2 M NaCl and the current in the droplet was monitored using a source measure unit (SMU). Evaporation of the droplets were prevented by placing a wet tissue lining the petri dish around the DMF chip. Over the entire duration of water resistance assay the chip was kept in a direct contact with the humidified tissue and with three 0.2 M NaCl droplets on the surface. In the first 7 days, 1 pm-thick PVDF samples showed no detectable material breakdown patterns. However, the current output stayed in the range of 100-500 pA / 4 mm2 with a standard deviation of 456 pA (Figure 25A). In alignment with our previous voltagecurrent measurements, the consistent high current output without irregular spikes (sustained increases in current) indicates the conductive-like nature of PVDF at the studied voltages, attributed to its high dielectric constant. A similar voltage-current trend was observed in the 5 pm-thick SU-8 and SU-8 + PVDF samples as well. Initial current output was recorded as 1.9 pA / 4 mm2for SU-8 and 4.9 nA / 4 mm2for SU-8 + PVDF on day 1, and these values increasedPATENT Attorney Docket No. TUOE.P2014WO / 00678799 gradually over the course of 7 days, reaching at 79 pA / 4 mm2(SD = 100 pA) over 7 days for SU-8 and 40 pA / 4 mm2(SD = 39 pA) over 7 days for SU-8 + PVDF (n = 3, Figure 25A). For all PVDF, SU-8, and SU-8 + PVDF samples inter-sample deviation was relatively high when compared to PVDF + SU-8 dielectric stack. In a contrast, PVDF + SU-8 dielectric stack maintained the lowest current output of 9 nA / 4 mm2on average and 15 nA / 4 mm2at 7 days, with a low inter-sample deviation (SD = 4.8 nA) over the 7 days. A single layer of 7 pm-thick Parylene C served as a control group as this configuration is commonly used in commercially available DMF chips. Upon fabrication, Parylene C surface was smooth with no observable pinholes or defects and had an average surface roughness of 59 nm (n = 3, STD = 22 nm). After 7 days at incubator, cracks became visible on the material (Figure 25B), and the surface roughness increased to 2.2 pm when accounting the breakdown cracks (n = 3, STD = 2 pm) (Fig. 25C). Thus, complete breakdown of Parylene C samples occurred within the first 3 days (n=3). The material appeared observably browned, and the water droplet underwent electrolysis and evaporation while high current output levels were measured in the droplet after the breakdown (Fig. 10A).

[0104] The current output results were confirmed with surface profile analysis of the materials (Fig. 25B, Fig. 25C). The surface profilometry allows for a visual comparison of the surface properties of the dielectric before and after exposure to cell culture incubator, where the chips are exposed to liquids and humidity. Upon both fabrication and after 7 days in an incubator, no visible defects were detected on 1 pm-thick PVDF samples, but the average surface roughness increased 5-folds, from an initial value of 52 nm to 273 nm (n = 3, STD = 22 nm at day 0, STD = 85 nm at day 7). SU-8 samples with 5 pm thickness showed fewer changes on the surface after 7 days in the incubator. The initial surface roughness of the SU-8 samples was 93 nm, and it remained the same after 7 days, while the standard deviation increased from 35 nm to 63 nm (n = 3). Therefore, SU-8 facilitated a good resistance to water and humidity-containing environments, yet the current output performance of SU-8 was not consistent due to its dielectric destabilization and high current output near actuation voltages. The surface roughness of SU-8 +PVDF dielectric stack increased 3 -folds in the course of 7 days, from an initial value of 42 nm to 145 nm (n = 3, STD = 15 nm at day 0, STD = 69 nm at day 7). This change may be attributed to the PVDF top layer, as the PVDF surface characterization in this work also confirm a 5-fold roughness increase after exposure to the incubator environment. The PVDF + SU-8 sample provides the most stable surface roughness conditions. The initial surface roughness increased only 1.6 fold from 40 nm to 64 nm after 7 days in incubator.PATENT Attorney Docket No. TUOE.P2014WO / 00678799

[0105] In a test over 60 days, results show that out of 6 initial samples, 4 remained stable for 60 days, with no dielectric breakdown and maximum current output not surpassing 20 nA. One sample showed early signs of destabilization, inconsistent with the rest of the data, likely due to a fabrication defect or dust contamination at the measured spot. Interestingly, the surface roughness of the PVDF + SU-8 dielectric stack after 60 days exposure reached 112 nm, denoting only a 2.8-fold decrease from the initial value (n = 4, STD = 57 nm) (Fig. 25C). As a result, PVDF + SU-8 dielectric stack showed a significantly improved performance in electrical stability and humidity resistance up to 60 days.

[0106] Figures 26A-D show voltage current response and breakdown voltage of dielectric materials and dielectric material stacks. Figure 26A indicates current output response of PVDF dielectric upon application of voltage up to 1500 V. No dielectric breakdown is detected, with the current output rising in direct correlation to voltage increase. Figure 26B indicates current output response of SU-8 dielectric upon application of voltage up to 3000 V. Breakdown is detected by the spiked increase in the current output at 800 V. Figure 26C indicates current output response of SU-8 + PVDF dielectric stack upon application of voltage up to 3000 V. Breakdown is detected by the spiked increase in the current output at 1400 V. Figure 26D indicates current output response of SU-8 + PVDF dielectric stack upon application of voltage up to 3000 V. Breakdown is detected by the spiked increase in the current output at 100 V.

[0107] The PVDF sub-layer (e.g., 806) and the SU-8 sub-layer (e.g., 808) may have 1 pm and 5 pm thicknesses, respectively. Such layer thicknesses were selected based on the dielectric properties and estimated actuation voltages compared to the commercially available chips. These layers may be coated with a 65 nm-thick hydrophobic Fluoropel layer (e.g., coating layer 810) before the measurements (SD = 11 nm, n = 2). The surface roughness of the 1 pm-thick PVDF layer was 40 nm (Figure 9B). We measured no breakdown up until 1500 V and an actuation voltage of 70 V (Figure 9C) on this layer. We attribute this to the Young-Lippman equation (Eq. 1, above), which indicates that reduced layer thickness results in lower actuation voltages. While the breakdown measurement might not reflect the DMF chip actuation due to the use of copper tape and not direct measurement of current in the solution on the surface of dielectric material, the voltage-current measurement performed in a saline solution droplet also reflected no evident breakdown up to 200 V, accompanied however by a high current output. Thus, applying 70 V actuation voltage resulted in a surface current of 100 pA / 4 mm2, showing a moderate conductive behaviour of the material, which could potentially affect cellular response as it exceeds the threshold of 2 pA. Testing shows high variation in thePATENT Attorney Docket No. TUOE.P2014WO / 00678799 current levels in the surface current, with an average of 21 pA / 4 mm2 and 132% standard deviation (Figure 9D), and as such, a dual -di electric layer (e.g., 806 and 808) is advantageous over a single dielectric PVDF layer. Once fully polymerized, SU-8 transitions to a glass-like state, providing isolation from humidity. The SU-8 layer exhibited a surface roughness of 100 nm without any visible structural defects after fabrication (Figure 9B). The breakdown voltage and actuation voltage of the SU-8 layer were measured as 800 V (Figure 9B) and 90 V (Figure 9D), respectively. The lower breakdown voltage and higher actuation voltage were expected, because the dielectric strength of SU-8 is 160 V / pm, which is lower than that of PVDF (400-450 V / pm). Testing also measured the surface current as 2.6 pA / 4 mm2at the actuation voltage, as well as a high increase after 110 V to 8 pA with further dielectric destabilization and high current output between 180 V and 200 V (Figure 9D). Due to the high current-value with respect to the minimum cell current detection limit, as well as showing steep increase at voltages close to the actuation voltage, the dual-dielectric layer is also advantageous over just a single SU-8 layer.

[0108] Accordingly, the embodiment of Figure 8 integrates SU-8 sub-layer (808) and a PVDF sub-layer (806) to leverage on their respective strengths, including PVDF’s high dielectric constant and breakdown resistance and SU-8’s notable water resistance, while mitigating their limitations — namely, the electrical fragility of SU-8 and the semi-conductive properties of PVDF. This approach enables achieving an optimized dielectric stack with minimal layer thickness. As discussed herein, the first dielectric sub-layer 806 may be PVDF, and the second dielectric sub-layer 808 may be SU-8. However, the materials may be switched without departing from the scope hereof (e.g., PVDF as the base dielectric with SU-8 as the top layer (PVDF + SU-8), and vice versa). Both dielectric stacks showed significant improvements over the individual dielectrics, with no current leakage up to 200 V (Figure 9D). The surface current output did not surpass 10 nA / 4 mm2 for the SU-8 + PVDF dielectric stack and 30 nA / 4 mm2 for the PVDF + SU 8 dielectric stack. The breakdown voltage for the SU-8 + PVDF dielectric stack was 1400 V (Figure 9C), while that of the PVDF + SU-8 dielectric stack was 1600 V (Fig. 26D), indicating cumulative dielectric strengths of 233 V / pm and 267 V / pm, respectively. The surface roughness was approximately 100 nm for the SU-8 + PVDF stack and 50 nm for the PVDF + SU-8 stack (Fig. 9B), suggesting that the higher surface roughness of SU-8 can be mitigated by spin-coating it onto the PVDF layer. Both dielectric stacks required approximately 100 V for droplet actuation, with the water contact angle change from the resting state exceeding 30° (Figure 9C). The higher actuation voltage results from the increased thickness of the dielectric stack compared to the previously characterized singlePATENT Attorney Docket No. TUOE.P2014WO / 00678799 layers. The surface current levels are more than 60 folds lower than a lowest reference value proved to not affect cell viability when cells are stimulated by an electro-conductive surface (2 pA)19, making the stack safe to use with biological samples without influencing the results by the chip actuation. The actuation voltage is also comparable to the commercially available Parylene C, which typically requires 90-100 V for droplet actuationlO. Both samples demonstrated similar performance, showing good electrical stability, no current leakage, and an actuation voltage comparable to commercial DMF chips with Parylene C dielectric layers.

[0109] Accordingly, compared to a chip with just Parylene C, and when that chip is exposed to high humidity of the cell culture incubator and permanent contact with the sample droplets (cell culture media), the humidity over a span of 1-3 days seeps into the material and once the electrode underneath is activated, makes the material conductive, causing it to break. By uniquely combining PVDF and SU-8 dielectric materials such as described with respect to Figure 8, the two materials work in synergy to protect the sample from any water penetration from the environment, as well as from any breakage caused by the use of higher voltages, preventing the material degradation and sample electrolysis caused by direct current.

[0110] The PVDF+SU-8 dielectric stack notably outperformed single material samples and commercial dielectric material samples in electrical stability, showing no signs of degradation or current leakage up to 200 V. As the actuation voltage required to use the chip with the PVDF+SU-8 dielectric stack was calculated to be 100V and no breakdown or current leakage was detected until 200V, indicate a large safety range of the chip use. Additionally, when tested over a longer period of time, 4 out of 6 samples did not show any increase in surface current or breakdown over 60 days, showing the potential of the reported dielectric stack to support complex cell studies that can require lengthy differentiation and priming times, as well as development of organoids. PVDF+SU-8 dielectric stack also showed the least alteration in surface roughness after exposure to water and humidity, with a 1.6 fold-increase and 2.8 fold-increase in roughness after 7 days and 60 days of humidity exposure, respectively when compared to the material before any actuation or humidity and heat exposure. As such, the digital microfluidic chip(s) discussed herein exhibit stable electrical performance under about 90% humidity and about 37 degrees Celsius for 60 or more days. This is an advantage because it shows that the surface profile of the dielectric stack does not alter under the aforementioned conditions applied. On the other hand, the commercial material shows a 37.3-fold-increase in surface roughness after 7 days.PATENT Attorney Docket No. TUOE.P2014WO / 00678799 Example 1: DMF generated using the method of Figure 1:[OHl] The following discusses a non-limiting working example of a DMF chip according to the method of Figure 1. The characteristics, such as thicknesses, materials, size, etc. in this working example are non-limiting in scope. However, it should be appreciated that characteristics of this working example may apply to other embodiments as well. A closed DMF system is provided and includes a top and bottom glass plate (standard double glass slide, 50.8 x 76.2 mm). The top plate consists of a 155 ± 20 nm-thick indium tin oxide (ITO) layer, serving as a transparent ground electrode for imaging ease, and a 65 ± 11 nm-thick hydrophobic Fluoropel layer. Of course, the thicknesses and materials may vary depending on the desired application. The bottom plate may include the electrodes, multilayer dielectric, and hydrophobic layers that were fabricated as described above. The functional area of DMF chip, in one non limiting example, is a 10 x 10 array of operation electrodes with a 2 mm edge size and four reservoirs functioning as the inlet and outlet of the operational area. In the DMF chip, SiN was used as the interface between the 3D electrode architecture by embedding all metal components except the contact pads. Thus, the first component of the multilayer dielectric was SiN, as the first deposition on top of the electrodes. Vertical contact is established between the first and second layers of the individual electrodes by creating 1 mm2 windows in the insulator SiN layer by reactive ion etching. The layers connect through a vertical contact point per each actuation electrode, while the rest of the structure was electrically isolated thanks to the SiN layer. This geometry served as the basis of expanding the area of actuation electrodes because the connection traces could be structured at the bottom layer, leaving extra space at the top surface.DMF Performance Analysis

[0112] The following discussion provides analysis on certain characteristics of the DMF manufactured utilizing features of the method of Figure 1, including the dielectric stack configuration of Figures 2-7 and / or 8. To have a robust and functional multilayered dielectric stack in the DMF chip, comprehensive optimization studies were performed by combining computational and experimental characterizations.

[0113] Figure 10 shows a layer thicknesses evaluation result on a DMF manufactured according to the method of Figure 1. First, the layer thicknesses were evaluated through finite element analysis (FEA) by means of the electrical potential and electrical field distribution on the multilayered dielectric and a droplet placed on top of it. Fig. 10 is a color map of finite element analysis for electrical potential distribution on multilayered dielectric and electricalPATENT Attorney Docket No. TUOE.P2014WO / 00678799 field distribution for dielectric layers and the droplet. The majority of the electric potential dissipates in the PaC layer (1 pm), while the SiN layer (400 nm) increases the stability of the multistack. The numbers indicated in each layer represent the estimated electrical field on these layers.

[0114] Figure 11 demonstrates the inverse proportion of the electrical potential distribution with regard to the dielectric constants of the materials described as capacitors in series. As shown, the electrical potential dropped to near zero at the dielectric-droplet interface for each thickness combination.

[0115] Table 1, below, demonstrates that the maximum electric fields on SiN and PaC in the DMF chip manufactured according to the method of Figure 1 can be reduced to below 50 V pm-1 and 100 V pm-1, respectively, with an applied voltage of 100 V in FEA by altering the thicknesses. Although dielectric layers prevent the current flow during actuation, they still generate an indirect electric field, which has previously reported potential effects on cells and can be utilized for several applications, such as stimulating or trapping cells. To quantify this effect in the DMF chip, the estimated electrical field strength on the dielectric layers is calculated and droplets during electrowetting (Table 1) and then the potential impact of the electrical field on the cells if they were exposed for extended periods is assessed. These effects may be mitigated by removing the ITO coating from the top plate of DMF chip at the designated, addressable, cell culture areas, preventing electrical field interference with the cells.Table 1: Computational study on COMSOL Multiphysics showing the electrical field strength on dielectric layers and the droplet upon the application of 100 V.Pa SiN SiN PaC Droplet [pm] [pm] [V m'1] [V m'1] [V m'1] 0 0.05 1.99E+09 - 1744.5 0 0.10 9.99E+08 - 873.62 0 0.20 5.00E+08 - 437.16 0 0.40 2.50E+08 - 218.66 0.5 0.05 8.09E+07 1.92E+08 70.759 0.5 0.10 7.77E+07 1.84E+08 68.009PATENT Attorney Docket No. TUOE.P2014WO / 00678799 0.5 0.20 7.21E+07 1.71E+08 63.104 0.5 0.40 6.30E+07 1.50E+08 55.149 1 0.05 4.12E+07 9.79E+07 36.112 1 0.10 4.04E+07 9.60E+07 35.382 1 0.20 3.87E+07 9.22E+07 34.006 1 0.40 3.61E+07 8.56E+07 31.554 2 0.05 2.09E+07 4.95E+07 18.245 2 0.10 2.06E+07 4.90E+07 18.056 2 0.20 2.02E+07 4.80E+07 17.691 2 0.40 1.94E+07 4.61E+07 17.004

[0116] Figure 12 depicts a chart showing the impact of the multilayer dielectric stack by measuring breakdown voltage, current leakage, and contact angle change. Figure 13 is a box plot of the breakdown voltage of the multilayered dielectrics. 16 different combinations of multilayered dielectrics were fabricated onto glass substrates, containing multiple thicknesses of SiN, PaC, which were later coated with a hydrophobic layer. Along with the multilayered dielectrics, we fabricated a single-layer dielectric, PaC, with a thickness of 7 pm as a reference point for comparison.

[0117] Referring to Figure 13, dielectric breakdown voltage serves as a key indicator of the robustness of dielectrics during liquid handling (e.g., droplet manipulation on the DMF chip). The thicknesses of both PaC and SiN layers have a major impact on dielectric breakdown voltage. Notably, the thickness of SiN has a more significant effect on samples with PaC thickness greater than 1 pm. The sample combining 2 pm PaC and 400 nm SiN exhibits a higher breakdown voltage than the reference sample, which contains only 7 pm PaC. Based on these observations, the dielectric robustness of the multilayer dielectric stack may be optimized by increasing the SiN thickness after optimizing PaC thickness. Although breakdown voltage is a key parameter, it is not the only indicator of high-performance dielectrics. A higher dielectric constant can also contribute to improved performance, as there is a significant correlation between the dielectric constant and the leakage current of dielectric materials.PATENT Attorney Docket No. TUOE.P2014WO / 00678799

[0118] Figure 14 is a plot of current leakage measurement in the operational voltage range (n = 3). Current leakage refers to the unintended flow of current through dielectric layers, with or without dielectric breakdown, and it is undesired for DMF applications. The thickness of the PaC layer impacts preventing current leakage, as indicated by the comparison of dielectric constants and leakage measurements. We observed leakage currents exceeding the threshold even in the absence of breakdown for some combinations where the PaC layer was thinner than 1 pm.

[0119] Figure 15 shows 90° tilted microscope images of the droplets placed on multilayered dielectric stack. The droplets were actuated with 50 V during the measurement. Each condition was repeated 3 times. Figure 15 shows changes in droplet contact angle upon actuation, as maximizing the contact angle change is crucial for minimizing the energy required for manipulation, inferred from the Young-Lippmann Equation. The contact angle changes of droplets on multilayered dielectrics are stimulated by sweeping voltage from 0 to 200 V.

[0120] Thus, PaC thickness had a significant influence on the change in contact angle, enabling a lower actuation voltage. This effect is reflected by a steeper slope in the curves shown in Figure 12. The absolute average slopes of samples with 1 pm and 2 pm PaC layers are 0.780V-l and 0.520V-l, respectively, and this slope was measured at 0.360V-l for the reference sample with only 7pm PaC layer. As such, in an embodiment, = 1 pm PaC thickness and 400 nm SiN thickness maintained optimal dielectric stability, minimal current leakage, and low actuation voltage at 50 V, making DMF chip suitable for cell culture applications.

[0121] The connection traces being spatially offset from the electrode within the electrode-insulating sub-layers of the dielectric stack advantageously enables contact traces running beneath multiple electrodes, yet linked to just a single electrode, such as shown in Figures 3 and 4. When a specific connection trace needs to couple with a given electrode, a vertical contact extends through the respective electrode-insulating sub-layer of the dielectric stack. These vertical connections are formed by having contact between connection traces and electrodes via through-openings in an sub-layer of the dielectric stack. The dielectric is insulating, such as a silicon nitride layer, and thus serves to prevent electrical short circuits by isolating the contact traces from other electrodes. Moreover, it is shown that ITO coating in the top plate may be removed in certain areas corresponding to a respective electrode where, at each ITO-removed section is prepared for cell culturing (example of which is discussed below).

[0122] In the specific example of Figures 2-6 and 8, not all electrodes have a corresponding ITO-patterned (e.g., ITO-removed) section of the top plate designated for cellPATENT Attorney Docket No. TUOE.P2014WO / 00678799 culturing, but instead only 8 electrodes have an associated ITO-removed section of the top plate. Thus, each cell culture site is spatially offset in the X and Y directions, but still separated from one another. Moreover, actuation of the electrodes still enables electrowetting and movement of droplets and other actuatable medium between culture sites. For example, any od the DMF chips discussed herein may include a plurality of addressable culture sites. There may be at least one reagent reservoir region corresponding to one or more of the addressable culture sites. The at least one electrode of these DMF chips is arranged to meter, route, merge, and split droplets so as to provide time varying stimulation regimens to immune cells at the culture sites of Figure 7, for example, depicts droplet motion to an actuated electrode is demonstrated with four video snapshots.Example 2: Cell-based assays using DMF Platform:

[0123] The DMF platforms discussed herein address the realization that most conventional digital microfluidic chips face challenges in balancing low actuation voltage, dielectric robustness, and minimal current leakage, thereby limiting their effectiveness and use for biological applications. The DMFs herein incorporating a multilayer dielectric stack (including, but not limited to, silicon nitride and Parylene C) achieve an optimal balance of these properties. The 3D architecture and compact electrode design create two-fold more operational space, while the multilayer dielectric structure reduces actuation voltages down to 50 V, which demotes a stable 2-fold reduction to conventional standards. Finite element analysis was employed to optimize the dielectric thicknesses, ensuring minimal current leakage under 10 nA, which is 100-folds below the biological detection threshold. Experimental validation was conducted through droplet actuation and water contact angle characterizations, identifying the optimal dielectric composition as 400-nm thick silicon nitride and 1-pm thick Parylene C layer. To utility of 3D2MF chip in biological assays was demonstrated by culturing human-derived macrophages and fibroblasts to varying concentrations of Cytochalasin D. Results indicated comparable cytotoxicity results to conventional well plate assays, while utilizing over 2 order of magnitude less sample volume. This advancement expands the application of digital microfluidics in cell-based assays and broader biomedical research.

[0124] The working-example fabricated chips were used in a cell response experiment as a proof-of-concept study. The cell response of fibroblasts to different concentrations of cytochalasin D, which is known to disturb the cytoskeleton by binding actin filaments. First, we sterilized and cleaned both plates by exposing UV and rinsing with MilliQ water. Cells were seeded on eight separate spots on the fibronectin-functionalized hydrophilicPATENT Attorney Docket No. TUOE.P2014WO / 00678799 areas of the top plate and incubated them for one day to attach. Specifically, THP-1 cells with a density of 2.5E5 mL-1 were differentiated by adding 50 ng mL-1 phorbol 12-myristate 13-acetate (PMA) to the cell culture medium. After incubating for 24 h, we fully refreshed the cell culture medium and allowed the cells rest and differentiate for another 48 h. The cells were then detached by incubating them in Accutase for 30 min. The detachment / dissociation process was halted by adding an equal or greater volume of cell culture medium to the cell suspension in Accutase. The aliquot with detached cells was centrifuged and diluted to match a density of 6.0E5 cells mL-1. This density is chosen to be able to seed 500 cells in each microwell. After that, we assembled the top plate into our bottom plate, which has electrodes for electrowetting. We introduced cell medium droplets containing four different concentrations of cytochalasin D to the cell culture areas by manipulating droplets on the chip. After incubating cell cultures for four hours with cytochalasin-contained droplets, we disassembled the plates and stained the cell culture areas on the top plate with DAPI and Phalloidin 488. We observed that 2 pM concentration severely disturbed the actin network of fibroblasts under a microscope. Increasing the cytochalasin D concentration resulted in strong disruption of fibroblast cytoskeletons. The digital microfluidic chip produced enabled the advantage of precisely diluting cytochalasin D into different concentrations in nanoliter-volumed droplets and bring these droplets in contact with cells for cell culturing.

[0125] There has been a growing interest in digital microfluidics for their potential application in biological and chemical experiments. The embodiments of the DMF chip platform discussed herein are highly desirable for incorporating into cell studies to achieve high throughput and automation in complex experiments, particularly when: the analytes are limited, and / or precise dilution is necessary at pM concentrations.

[0126] Figure 16 shows workflow of a cell response experiment where unconditioned macrophages were introduced to a range between 0 and 4 pM of Cytochalasin D. Figure 17 shows live-dead imaging of the macrophages after 24 h of culture on the DMF chip. Live cells are stained with CellTracker Green. The total number of cells is accessed by brightfield. Scale bar 20 pm (n = 3). Cell viability was tested on both actuated and non-actuated DMF chips to determine whether the cell culture conditions on the chip or residual current from electrode actuation negatively affected cell viability. Cell viability on the DMF chip had an 87% ratio of live cells (Figure 17), indicative of a healthy cell culture. Additionally, the residual current detected from the electrode activation was in the single-digit nA range, hundreds of times lower than any known biological detection threshold.PATENT Attorney Docket No. TUOE.P2014WO / 00678799

[0127] The experiment sought to understand the cytotoxic effect of Cytochalasin D on the cells forming immediate immune responses, namely macrophages and fibroblasts. Cytochalasin D disturbs the cell cytoskeleton by binding to actin filaments. This creates a condition of impaired actin polymerization within the cell, resulting in the cytoskeleton appearing fragmented when observed under a microscope, as well as the cell body losing its integrity and ability to gain the native morphology. As the actin polymerization has different rates, as well as organizational levels across different types of cells, understanding the dosedependent response of different cell types, can be crucial for understanding their sensitivity to the stimuli. For example, highly migratory cell types, such as fibroblasts and immune cells (macrophages, neutrophils), have higher actin polymerization rates as compared to non-migratory cells, such as epithelial and endothelial cells.

[0128] Macrophages and fibroblasts are both key cell types involved in immune response and fibrosis, possessing high migration potential but belonging to two distinct cell groups — immune and mesenchymal, respectively. Therefore, their responses to different doses of Cytochalasin D are expected to vary. Therefore, the cell-response assay as shown in Figure 16 was designed in order to test the difference in cell type response to different doses of cytochalasin D. The areas containing cells and cell culture medium were mixed with Cytochalasin D containing culture media droplets to obtain the final concentrations of 0, 1, 2, and 4 pM Cytochalasin per droplet (total droplet volume was 1.7 pL). The selected concentrations were based on reported values for fibroblasts and macrophages. A concentration of 0 pM served as a negative control, showing the native morphology of each cell type, while 4 pM is expected to severely disrupt the cytoskeleton and alter cell morphology in both cell types, acting as a positive control for the experiment. Visual analysis of macrophages at 0 pM revealed a circular morphology with minimal cytoplasmic expansion, which is typical of nonpolarized macrophages (MO phenotype). Moreover, the actin organization was not entirely uniform, displaying brighter clusters likely representing podosomes, which are commonly abundant in macrophages and can appear as bright actin aggregates in imaging. When macrophages are stimulated with 1 pM Cytochalasin D, no noticeable changes were observed; cell size and fluorescence distribution appeared similar to those in the 0 pM control.

[0129] Figure 18 shows quantitative analysis of the cell area of macrophages and fibroblasts indicating the dissociation of the cell membrane, (n = 25±15, each cell is analyzed individually). Figure 18 demonstrates that the cell area of the macrophages stimulated with 1 pM Cytochalasin D was not significantly different from the control. However, at 2 pM, the differences were observed more clearly. Figure 19 shows DAPI (nucleus, blue)-PhalloidinPATENT Attorney Docket No. TUOE.P2014WO / 00678799 (cytoskeleton, green) staining of the macrophages and fibroblasts after exposure to varying concentrations of Cytochalasin D. Figure 19 shows that the cytoplasm is more fragmented, as well as the actin clusters are seen more clearly and agglomerated on only one side of a cell. A 2 gM cytochalasin D concentration induced a significant decrease in the cell area with an average of 0.336 ratio of the control cells’ area (SE = 0.218). Finally, the 4 pM cytochalasin D produced the expected strong effect with the cell cytoplasm being almost undetectable, and the cell area is on average 0.268 folds of the native cell area (SE = 0.247).

[0130] Human dermal fibroblasts at 0 pM presented the native morphology with a widespread, elongated cell body, as well as a dense highly organized cytoskeleton with pronounced actin fibers. However, already at 1 pM cytochalasin D a substantial difference was observed. While overall, the cells appeared to maintain a similar border shape to untreated fibroblasts, the cytoskeleton was seen to lose its organization, and structural fibers were instead distributed in a random firework-like shape. The cell area also decreased 0.45 folds of the untreated fibroblast size. These differences were even more prominent when the fibroblasts are treated with 2 pM cytochalasin D, causing a complete loss of the typical border shape and of any actin organization, adopting fully firework-like shape with no interconnection in between multiple actin expansions. The cells showed a 0.75-fold decrease, with a remaining cell area of only 0.25 (SE = 0.124) of the original cell size. Finally, at 4 pM, while the loss of structured cytoskeleton remained, the actin staining was observed to lose intensity as well as volume, indicative of cells’ progressive loss of the cytoplasmic content.

[0131] Figure 20 shows cell response study of macrophage and fibroblast cells with cytochalasin D on well plates. Figure 21 shows quantitative analysis of the cell area of macrophages and fibroblasts indicating the dissociation of the cell membrane (n = 25±15, each cell is analyzed individually). Cytochalasin D assay was validated on a well plate in order to confirm the reliability of the DMF-run cell assays, as well as lower cell number per sample (Figures 20-21). For both fibroblasts and macrophages, the same trends and results were observed, where cell treatment with increasing Cytochalasin D concentration caused an increase in cell cytoskeleton disorganization, as well as overall decrease in the cell area, the well plate assay with 1 pM Cytochalasin D induced a significant decrease in fibroblasts but not in macrophages. However, 2 pM and 4 pM concentrations caused noticeable actin disorganization, loss of cytoplasmic structural integrity, and a significant, progressive reduction in cell area with increasing cytochalasin D concentration.

[0132] Interestingly, cytochalasin D is known to affect more cells in the G1 point of the cell cycle related to the cell growth. This can be a potential explanation for the higherPATENT Attorney Docket No. TUOE.P2014WO / 00678799 sensitivity of fibroblasts to cytochalasin D when compared to macrophages. Fibroblasts, being rapidly growing and replicating cells, exhibit higher sensitivity to Cytochalasin D-induced morphological changes. In contrast, THP-1 -differentiated macrophages enter a quiescent state and remain non-replicating in GO, making them more resistant to Cytochalasin D. As a result, significant morphological changes in macrophages are only observed at higher concentrations (2 PM). The consistency of the results obtained from both the well plate and DMF chip in the cytochalasin D assay demonstrates the potential of DMF chips for conducting parallel biomolecular assays, enabling simultaneous analysis of cell-biomolecule interactions under various conditions.

[0133] This working example evidences that the DMF chip embodiments discussed herein, with the optimized multilayer dielectric stack, represents a significant advancement in digital microfluidic technology. By incorporating SiN and PaC layers, we successfully achieved, for the first time, a challenging balance of low actuation voltage, enhanced dielectric robustness, and minimized current leakage, positioning the system as an efficient platform for biological applications. The 3D architecture and compact electrode design doubled the operational area while reducing actuation voltages to as low as 50 V. Finite element analysis guided the precise optimization of dielectric thicknesses to achieve these performance improvements. Validation experiments demonstrated the chip’s capability for reliable droplet manipulation and cell culture applications, with Cytochalasin D exposure assays yielding cytotoxicity results comparable to conventional well plate methods, yet requiring over two orders of magnitude less sample volume. The DMF chip’s ability to maintain cell viability and perform parallel biomolecular assays with minimal interference to cell health underscores its potential as a versatile and efficient tool for conducting reproducible analyses of cellular behavior and biomarker responses.Example 3: Modelling of anti-inflammatory potential in activated macrophages:

[0134] The DMF chips discussed herein, including but not limited to the humidityresistant dielectric stack shown in Figure 8, may be used to implement a bioassay device, a cell culture, or bioassay method. The following utilizes the DMF chips disclosed herein to implement model the macrophage inflammatory response in DMF platform and evaluate the anti-inflammatory potential of TCB-2 in activated macrophages. Therefore, the DMF chips discussed herein (whether just including the additional dielectric layers discussed in Figure 8, or also including the multi-layer electrode configuration of Figures 2-7) a powerful approach that can bring spatiotemporal control to cell culture experiments for up to 60 days. The DMFPATENT Attorney Docket No. TUOE.P2014WO / 00678799 chips herein leverage dielectric stacks above the electrodes, providing a higher dielectric constant for an increased capacitance of the material that allows to decrease the actuation voltage, as well as functional strength to increase the breakdown voltage.

[0135] Figures 22A-G show cell viability on a DMF chip and does control of potential anti-inflammatory treatment TCB-2. In particular, Fig. 22A shows live-dead imaging of the cells after 7 days of culture on the DMF platform. Green arrows point to examples of live cell and white arrows point to example of dead cells. Scale bar 20 pm in Fig. 22B shows quantitative analysis of positive and negative controls (n = 3). Fig. 22C shows cell morphology characterization. All parameters were normalized and represented as fold-change to the control condition (n=3). Fig. 22D shows TNF-a expression in of TCB-2 stimulated and unstimulated macrophages (n = 3, 100-300 individual cells per condition per n , ns - nonsignificant, **** p<0.0001). Fig. 22E shows IL-10 expression of TCB-2 stimulated and unstimulated macrophages (n =3, 100-300 individual cells per condition per n, ns - nonsignificant, **** p<0.0001). Fig. 22F shows naive macrophage population before stimulation and zoomed-in format. Nuclei was stained with DAPI and Actin filaments were stained with phalloidin. Scale bar 200 pm (left) and 20 pm (right) (Fig. 22G) pro-inflammatory stimulated macrophages after the stimulation day and the zoomed-in format. Nuclei was stained with DAPI and Actin filaments were stained with phalloidin.

[0136] In Figure 22, it shows quantifying macrophage cell viability on the DMF chip, where 86%, 92%, and 83% of the cell population was viable across three independent chip experiments, resulting in an average of 87% viable cell culture after 7 days. As such, average cell viability is maintained above 80% following electrowetting on dielectric (EWOD). The viable cell ratio was higher than in the well-plate control tested under the same conditions, where cell viability was observed to be 72%. DMF platform supported a unique cell microenvironment where daily media refreshment through passive dispensing removed dead or damaged cells with compromised attachment, maintaining a cell culture free of cellular debris and associated inflammatory biomarkers.

[0137] Figures 23 A-D show cell viability and TCB-2 potential drug testing control on a well plate. Figure 23 A shows Live-dead imaging of the cells after 7 days of culture in a well plate. The live cells are stained with CellTracker Green (green colour), and the dead cell are stained with ZombieRed dye (red colour). Scale bar 100 pm. Figure 23B shows Quantitative analysis of negative (control condition, untreated) and positive (H2O2 treated cell culture to induce cell death) controls (n = 3). Figure 23C shows TNF-a cytokine release quantification under two concentration of inflammatory stimuli (n = 3, 100-300 individual cells per conditionPATENT Attorney Docket No. TUOE.P2014WO / 00678799 per n , ns = nonsignificant, **** p<0.001). Figure 23D shows TNF-a cytokine release quantification in inflammatory cell culture, inflammatory cell culture treated with TCB-2 drug, negative control and TCB-2 only treatment control (n = 3, 100-300 individual cells per condition pern, **** p<0.001).

[0138] Typically, in laboratory conditions inflammatory response in macrophages is induced by the lipopolysaccharide (LPS, endotoxin from gram-negative bacteria) and Interferon-gamma (INF-y, pro-inflammatory macrophage cytokine). A calibration experiment with two distinct inflammatory conditions was tested using the DMF chip embodiments herein where 100 ng / mL of LPS and 10 ng / mL of INF-y was applied for the first condition and 1 pg / mL LPS and 20 ng / mL INF-y was applied for the second condition. Next, the TNF-a cytokine release was quantified. While the lower concentration of LPS and INF-y did not induce a significant increase in TNF-a release, the higher concentration led to a statistically significant 1.2-fold increase in TNF-a (tumour necrosis factor a, SD = 0.09). Increased production and release of TNF-a by macrophages is generally associated with a pro-inflammatory phenotype. (Fig. 23D). Therefore, for the following experiments, cells were stimulated with 1 pg / mL of LPS and 20 ng / mL INF-y in order to promote cellular polarization into a pro-inflammatory phenotype and increase TNF-a production. The induction of pro-inflammatory phenotype in macrophages was then accessed on a cell culture using the DMF chip platform embodiments discussed herein. After 7 days in culture, cells induced into a pro-inflammatory state with 1 pg / mL LPS and 20 ng / mL INF-y, without additional treatment (Ml condition - orange bar), were analysed for TNF-a and IL- 10 cytokine release. TNF-a quantification showed a 1.1-fold increase (SD = 0.37) (Figure 22D), consistent with the cytokine release profile characteristic of pro-inflammatory macrophages26 while IL- 10 levels showed no significant change (Figure 22E), aligning with its typical upregulation only in antiinflammatory macrophages27. While the standard deviation values vary in between on-chip result and well plate results, it is to note that while DMF platform has a benefit of working with low population of cells that allows for a more individual analysis, it also comes at a cost of in a possibly high average deviation of a heterogenous population. As the population is positively skewed when the pro-inflammatory phenotype is induced (only small part of the population is seen to have a strong cytokine release response as seen on figure 24B), the observed standard deviation is affected by the smaller sample size.

[0139] Macrophage phenotype changes were also assessed through morphological analysis. Key factors such as cell area, perimeter (to evaluate membrane rugosity or irregularity), cell body compactness (indicating solidity or spread of the cell body), eccentricityPATENT Attorney Docket No. TUOE.P2014WO / 00678799 (reflecting roundness or elongation), and extent (a measure of shape regularity) provide insights into cell health and phenotype profile. The morphological data was confirmed through Cell Profiler analysis (Figure 22C), which revealed that cells stimulated into a pro-inflammatory phenotype exhibited a 1.6-fold increase in average area and a 1.5-fold increase in perimeter compared to untreated cells. Unstimulated cells displayed a more rounded shape with minor protrusions, which is a characteristic of typical macrophage morphology (Figures 22F, 22G). In contrast, the macrophage population stimulated into the pro-inflammatory phenotype showed a more elongated profile, with cells adopting a less circular, spindle-shaped morphology. These cells exhibited higher compactness (1.4-fold increase), increased eccentricity (1.1-fold increase), and reduced extent (0.86-fold decrease), all indicative of a more elongated and less spherical cell morphology consistent with the reported characteristics of pro-inflammatory macrophages. Altogether, the pronounced morphological alterations of the cell, upregulation of TNF-a cytokine release as well as unaltered IL- 10 cytokine release support the conclusion that the model discussed herein represents a population of pro-inflammatory macrophages.Example 3: Evaluating the anti-inflammatory potential of TCB-2 in activated macrophages:

[0140] The DMF chips herein may be used to enable EWOD of a plurality of droplets containing mammalian cells being cultured therein. The potential anti-inflammatory drug used in this study, TCB-2, is a selective serotonin 5-HT2A receptor agonist which is a receptor consistently expressed in immune cells, including macrophages. Traditional activation of the 5-HT2A receptor leads to increased inflammation and has an anxiogenic effect. Interestingly, when the same receptor is activated by psychedelic molecules, the effect is reversed, leading to a pronounced anti-inflammatory activity that inhibits the TNF-a pathway. Although other 5-HT2A agonists have been previously explored, TCB-2, as a potent and selective receptor agonist, remains largely understudied. Its anti-inflammatory potential has primarily been investigated in animal studies, with limited research at the cellular level.

[0141] Figures 24A-B show results from a long-term digital microfluidic platform. Figure 24A shows current leakage measurement in PVDF (1 pm) + SU-8 (5 pm) chips over the course of 60 days. Figure 24B shows quantitative analysis of macrophage cytokine expression over the course of 7 days based on TNFa and IL- 10 expressions (n = 3).

[0142] To assess the potential anti-inflammatory activity of TCB-2, using the DMF chips herein, THP-1 cells were treated with the 5 pM of the drug 24 hours after the pro-inflammatory phenotype induction. The treatment concentration of 5 pM was chosen based onPATENT Attorney Docket No. TUOE.P2014WO / 00678799 the average dose of psychedelic treatments used in cellular studies. The interval was introduced to allow the cells to undergo full polarization, enabling the assessment of TCB-2 activity on an already established inflammatory state rather than its preventive effects. After 24 hours of TCB-2 treatment on the activated macrophages, the cell media was replaced with a stimulus-free medium and allowed the cells to rest and establish a phenotype for an additional 24 hours. At the end of this period, we measured the cytokines expressed by the cell population and found that TCB-2 was able to reduce TNF-a expression to control population levels, with a foldchange of 0.95 in comparison with the control (SD = 0.3, n = 3, Figure 24D), with a significant decrease of the cytokine expression as compared to the pro-inflammatory state and no significant fold-change from the unstimulated macrophages. Additionally, TCB-2 significantly increased the expression of the anti-inflammatory cytokine IL-10 by 1.1-fold (SD = 0.26, n = 3, Figure 22E) compared to both the control and pro-inflammatory cell populations. These results indicate that TCB-2 has the potential to treat established inflammation and influence the polarization state of macrophages, possibly driving them toward a more anti-inflammatory phenotype. This result was further validated on a well plate assay, where the inflammatory treatment induced a 1.1 fold increase in TNF-a secretion (SD = 0.09), However, this increase was negated by TCB-2 treatment, with the Ml+TCB-2 condition showing no significant difference (1-fold change) compared to the control condition (SD = 0.06). Additionally, treatment with TCB-2 alone on unstimulated macrophages did not induce any increase in TNF-a release, maintaining a fold-change of 1 compared to the control condition (SD = 0.03) (Fig.23D). While the fold-change between conditions may not appear high, it is important to note that the data represent average cytokine release values per cell population.

[0143] Monocyte and macrophage populations are known to be highly heterogeneous, with only a portion of the population expressing a specific phenotype. This effect is also seen in the single cell analysis data in Fig. 24B where the bigger part of population does not express any higher amount of either TNF-a, nor IL- 10. However, only a subset of the cell population exhibits a pronounced response, showing either an increase in TNF-a release upon inflammatory induction or an anti-inflammatory response following treatment with TCB-2.

[0144] Additionally, THP-1 cells are known to secrete lower levels of TNF-a when compared to the primary macrophages, as well as decreasing their capacity of cytokine release rapidly days after the differentiation. Since the full assay reported in the study takes 7 days, the cytokine spike is not as pronounced, allowing however to see the differences on a more reactive subset of cell population. It is interesting to note that TCB-2 treatment appears to increase IL-10 cytokine expression not only in inflammation-reactive cells, but also in the cell populationPATENT Attorney Docket No. TUOE.P2014WO / 00678799 that did not show any pronounced pro-inflammatory response by an increase in TNF-a release, possibly showing a potential for the drug use for anti-inflammatory phenotype induction in macrophages instead of only reducing the pro-inflammatory response.

[0145] Furthermore, on chip treatment with TCB-2 reduces the morphological changes in the cells, decreasing both cell area and perimeter. The cell area and perimeter exhibited a 1.1-fold increase compared to unstimulated cells, with the area and perimeter being reduced by 0.5 and 0.4 units, respectively, relative to pro-inflammatory-polarized macrophages (1.6 times increase in area and 1.5 increase in perimeter from unstimulated cells). The values for compactness and eccentricity also decreased to 1.2-fold and 1-fold compared to the unstimulated cells, indicating differences of 0.2 and 0.1 from the pro-inflammatory-polarized macrophages(1.4 times increase in compactness and 1.1 increase in eccentricity), respectively (Fig. 22C). These findings demonstrate that TCB-2 fundamentally influences the cell response in terms of cytokine expression, while reversing morphological changes to near pre-treatment levels. The TCB-2 -treated cells exhibit smaller, more regular, and circular shapes, typical of unstimulated or anti-inflammatory macrophage phenotypes.

[0146] This document therefore also discloses a compound that acts as an agonist of 5-HT2A receptor in a mammal, wherein the compound binds to 5-HT2A receptor at an affinity that is at least 2-folds, or at least 10 folds, stronger than the compound’s affinity with other 5-HT receptors. The compound, in at least some embodiments, is 4-Bromo-3,6-dimethoxybenzocyclobuten-l-yl)methylamine hydrobromide (TCB-2). A method of treating or preventing a disease in a mammal may comprise administering to the mammal an effective amount of the above compound(s). In particular embodiments, the compound exhibits an antiinflammatory effect when administered to the mammal.Recycling of DMF Chips

[0147] Digital microfluidic chips are essential instruments in the field of biomedical engineering, chemical analysis, and numerous other applications due to their capability to manipulate minute liquid volumes with precision. However, despite their significant utility, these chips frequently face challenges such as dielectric breakdown or biofouling, which undermine their functionality and necessitate their disposal. Dielectric breakdown is characterized by the failure of the insulating layer within the chip, resulting in electrical malfunctions. Conversely, biofouling involves the accumulation of biological substances on the surface of the chip, leading to the obstruction of fluid movement and contamination of samples. Fabrication of these chips is demanding because it requiresPATENT Attorney Docket No. TUOE.P2014WO / 00678799 cleanrooms, labor-intensive processes and costly equipment. The fabrication processes, which include techniques such as soft lithography, photolithography, etching and lift-off, necessitate precision and specialized equipment. Furthermore, the process comprises multiple stages, including design, prototyping, testing, and validation, which are time-consuming. The disposal of these damaged chips substantially increases costs for laboratories and industries that depend on these devices for their research, limits the research-oriented specific designs, and also contributes to electronic waste negatively, posing significant environmental challenges. The trade-off between the high requirements to produce more functional chips with enhanced robustness and the increasing costs associated with these requirements significantly limits their potential for widespread use.

[0148] At least some embodiments herein also address these issues by developing a sustainable methodology for the refabrication (recycling) of digital microfluidic chips affected by dielectric breakdown or biofouling. The following recycling embodiments enable to restore the functionality of these chips, thereby intensifying the use of these chips in biomedical research and encouraging more complex designs to be fabricated.

[0149] Fig. 27 is a flowchart of an example method 2700 for recycling a digital microfluidic (DMF) chip. Method 2700 may be used to recycle the DMF chips discussed above in Figures 1-8, for example. When DMF chips are affected by dielectric breakdown, biofouling, or otherwise are not functionally working, method 2700 may be implemented. Figure 28 shows a schematic diagram 2800 of the steps of method 2700. Figures 29A-D show a working example of a chip recycled five times using the method 2700 of Figure 27. FIG. 29A shows average surface roughness values measured on glass substrates from Cycle 1 (new chip) to Cycle 5. FIG. 29B shows breakdown voltage measurements of the dielectric layer from Cycle 2 to Cycle 5. FIG. 29C shows actuation voltage required for droplet movement and splitting across recycling cycles. FIG. 29D shows scanning electron microscope (SEM) images of a new DMF chip (Cycle 1) and a recycled chip, both shown at *300 magnification.

[0150] At step 2702, method 2700 removes a cover layer and one or more sublayers of a dielectric stack of the DMF chip to expose a bottom plate of the DMF chip. As an example of 2702, coating layer 216, first additional dielectric sub-layer 214 and second additional dielectric sub-layer 215 of the DMF chip discussed in FIG. 2 are removed. As another example of step 2702, coating layer 810, second dielectric layer 808, and first dielectric layer 806 of the DMF chip discussed in FIG. 8 are removed. As such, it should be appreciated that method 2700 may work with a multi-layer electrode embodiment, or withoutPATENT Attorney Docket No. TUOE.P2014WO / 00678799 a multi-layer electrode. However, regardless of the electrode configuration, during method 2700 integrity of the at least one multi-layer electrode is maintained. The removed cover layer in step 2702 may be a hydrophobic layer. The removed one or more sub-layers in step 2702 may be one or more of: a polyvinylidene difluoride (PVDF) sub-layer, a SU-8 photoresist sub-layer, a Parylene C sub-layer, or a Silicon Nitride sub-layer. Removing the cover layer and one or more sub-layers of the dielectric stack may include one or more of wet etching, peeling off, or dry-etching.

[0151] At step 2704, the exposed bottom plate of the DMF chip is cleaned. In a non-limiting example, cleaning may include one or more of: plasma ashing or ultrasonic cleaning.

[0152] At step 2706, new sub-layers of the dielectric stack are recoated on the cleaned bottom layer. The new sub-layers may be the same or different material as the removed sub-layers.

[0153] At step 2708, a new cover layer is recoated. The recoated layer may be may be a hydrophobic layer. The recoated layer may be the same or different material as the removed cover layer.

[0154] Methd 2700 may be repeated for one or more recycling iterations. For example, Figure 29 shows five recycling iterations. After each recycling iteration, method 2700 may include testing actuation voltage and breakdown voltage to verify operation of the recycled DMF chip.

[0155] Table 2, below, shows a working example of implementation of method 2700.Table 2: Example Flow of Method 2700:PATENT Attorney Docket No. TUOE.P2014WO / 00678799COMBINATION OF FEATURES:

[0156] (Al) In an embodiment of a first aspect hereof, a digital microfluidic (DMF) chip includes: a modular, multi-layer dielectric stack, the dielectric stack including a plurality of sub-layers stacked in a Z-direction; at least one multi-layer electrode embedded within at least one electrode-insulating sub-layer of the dielectric stack, the multi-layer electrode comprising: a connection trace, an electrode spatially offset in the Z-direction from the connection trace, and the electrode and connection trace being located in different electrode-insulating sub-layers.

[0157] (A2) In the embodiment (Al), the DMF chip further comprises a substrate layer, the dielectric stack positioned above the substrate layer in the Z-direction.

[0158] (A3) In the embodiment (A2), the substrate layer includes glass.

[0159] (A4) In any embodiment (A1)-(A3) the at least one electrode-insulating sub-layer includes a first electrode-insulating sub-layer, a second electrode-insulating sublayer, and a third electrode-insulating sub-layer; the connection trace extends within the first electrode-insulating sub-layer; the electrode extends within the third electrode-insulating sublayer; and, vertical contact extends through the second electrode-insulating sub-layer in the Z-direction between the connection trace and the electrode.

[0160] (A5) In any embodiment (A4), dielectric material of the second electrodeinsulating sub-layer is located between the electrode and the connection trace.

[0161] (A6) In any embodiment (A1)-(A5), the dielectric stack includes an additional dielectric sub-layer, the additional dielectric sub-layer positioned above the third electrode-insulating sub-layer in the Z-direction.

[0162] (A7) In any embodiment (A1)-(A6), the first electrode-insulating sublayer, the second electrode-insulating sub-layer, and the third electrode-insulating sub-layer comprising a first dielectric material; the additional sub-layer comprising a second dielectric material different than the first dielectric material.

[0163] (A8) In any embodiment (A1)-(A7), the DMF chip further including a coating layer, the coating layer positioned above the dielectric stack in the Z-direction.

[0164] (A9) In any embodiment (A8), the coating layer comprising a hydrophobic layer.

[0165] (A10) In any embodiment (A9), the hydrophobic layer comprising FluoroP el.PATENT Attorney Docket No. TUOE.P2014WO / 00678799

[0166] (Al 1) In any embodiment (A8)-(A10), the coating layer having a thickness of between about 50 nm and about 100 nm.

[0167] (A12) In any embodiment (Al)-(Al l),at least one sub-layer of the dielectric stack being an inorganic dielectric, optionally silicon nitride.

[0168] (A13) In any embodiment (A1)-(A12), at least one sub-layer of the dielectric stack being a conformal polymer dielectric layer, optionally Parylene C.

[0169] (A14) In any embodiment (A1)-(A13), characterized by one of: the first dielectric material having a first thickness of 400nm or less and the second dielectric material having a second thickness of 0.5pm or less; the first dielectric material having a first thickness of 400nm or less and the second dielectric material having a second thickness of 1 m or less; the first dielectric material having a first thickness of 400nm or less and the second dielectric material having a second thickness of 2pm or less.

[0170] (Al 5) In any embodiment (A1)-(A14), the at least one multi-layer electrode being one of a plurality of multi-layer electrodes arranged in an array within the dielectric stack.

[0171] (A16) In any embodiment (A15), each connection trace of each electrode within the plurality of multi-layer electrodes being located within the same sub-layers of the dielectric stack.

[0172] (Al 7) In any embodiment (A15)-(A16), each connection trace being coupled to a respective contact pad located outside of an operational area of the dielectric stack.

[0173] (Al 8) In any embodiment (A1)-(A17), the DMF chip further includes: a top plate as a top-most layer of the DMF chip in the Z-direction; wherein the dielectric stack and the at least one multi-layer electrode are components of a bottom plate of the DMF chip.

[0174] (Al 9) In any embodiment (Al 8), the top plate including a transparent ground electrode.

[0175] (A20) In any embodiment (A18)-(A19), the top plate including an indium tin oxide (ITO) layer having sections corresponding to locations of one or more electrodes, the sections having portions of the ITO layer removed therefrom.

[0176] (A21) In any embodiment (A18)-(A20), the electrode including an array of electrodes; the top plate including a plurality of windows therein, each window aligned with an electrode of the array of electrodes.

[0177] (A22) In any embodiment (A1)-(A21), characterized in that the digital microfluidic chip operates to actuate fluid between the at least one multi-layer electrode andPATENT Attorney Docket No. TUOE.P2014WO / 00678799 another multi-layer electrode at an actuation voltage of 1000V or less, optionally 50V or less., optionally with alternating current at 10kHz.

[0178] (A23) In any embodiment (A1)-(A22), at least some sub-layers of the plurality of sub-layers including polymeric dielectric material having high dielectric constant and humidity resistance.

[0179] (A24) In any embodiment (A1)-(A23), at least one sub-layer of the plurality of sub-layers including polyvinylidene difluoride (PVDF); at least another sub-layer of the plurality of sub-layers comprising SU-8 photoresist.

[0180] (A25) In any embodiment (A24), the PVDF sub-layer being between the at least one electrode-insulating sub-layer and the SU-8 photoresist sub-layer.

[0181] (A26) In any embodiment (A1)-(A25), characterized in that the digital microfluidic chip exhibits stable electrical performance about 90% humidity and about 37 degrees Celsius for 60 or more days.

[0182] (A27) In any embodiment (A1)-(A26), the DMF chip including: a plurality of addressable culture sites, at least one reagent reservoir region corresponding to one or more of the addressable culture sites; wherein the at least one electrode is arranged to meter, route, merge, and split droplets so as to provide time-varying stimulation regimens to immune cells at the culture sites.

[0183] (A28) A biological cell-based assay comprising: the DMF chip of any of embodiment (A1)-(A27); a plurality of droplets containing mammalian cells being cultured therein.

[0184] (A29) In any embodiment (A28), wherein average cell viability is maintained above 80% following electrowetting on dielectric (EWOD).

[0185] (A30) In any embodiment (A1)-(A29), the DMF chip forming at least one hydrophilic window defining at least one respective culture site aligned to the at least one multi-layer electrode, further comprising a controller coupled to the at least one multi-layer electrode and machine readable instructions that, when executed by the controller, manipulate droplets, using the at least one multi-layer electrode, by electrowetting to deliver controlled biochemical stimulation to immune cells at the respective culture site.

[0186] (A31) In any embodiment (A30), wherein the controlled biochemical stimulation comprises contacting macrophages with a biochemical stimulator to induce a pro-inflammatory polarization.PATENT Attorney Docket No. TUOE.P2014WO / 00678799

[0187] (A32) In any embodiment (A31), the biochemical stimulator comprising lipopolysaccharide (LPS) at a final concentration of about 0.5-2 pg / mL or interferon-y (IFN-y) at a final concentration of about 10-30 ng / mL.

[0188] (A33) In any embodiment (A31)-(A32), wherein each of the at least one culture site is functionalized to promote cell adhesion and provides optical access through a top plate of the DMF chip, thereby enabling quantification of cytokine secretion at a singlecell level.

[0189] (A34) In any embodiment (A31)-(A33), wherein the at least one culture sites are configured to support population-level cytokine quantification by aggregating signals from multiple cells within the at least one culture sites.

[0190] (A35) In any embodiment (A31)-(A34), wherein the cytokines comprise one or more of tumor necrosis factor-a (TNF-a) or interleukin- 10 (IL- 10).

[0191] (A36) In any embodiment (A30), the instructions, when executed by the controller, causing dynamic modulation of immune-cell state by sequentially delivering droplets comprising a candidate immunomodulatory compound at a controlled concentration and subsequently removing or adjusting the compound by electrowetting actuation of selective ones of the at least one electrode.

[0192] (A37) In any embodiment (A1)-(A36), at least some layers of the multilayer dielectric stack being modular.

[0193] (B 1) In an embodiment of a second aspect hereof, a method for recycling a digital microfluidic (DMF) chip, includes: (a) removing a cover layer and one or more sublayers of a dielectric stack of the DMF chip to expose a bottom plate of the DMF chip; (b) cleaning the exposed bottom plate of the DMF chip; (c) recoating new sub-layers of the dielectric stack; and, (d) recoating a new cover layer;.

[0194] (B2) In the embodiment (Bl), the bottom plate includes one or more multilayer electrodes embedded within at least one electrode-insulating sub-layer of the dielectric stack, the multi-layer electrode comprising: a connection trace, and an electrode spatially offset in a Z-direction from the connection trace.

[0195] (B3) In either embodiment (B1)-(B2), the cover layer is a hydrophobic layer.

[0196] ((B4) In any of the embodiments (B1)-(B3), the one or more sub-layers include one or more of: a polyvinylidene difluoride (PVDF) sub-layer, a SU-8 photoresist sub-layer, a Parylene C sub-layer, or a Silicon Nitride sub-layer.PATENT Attorney Docket No. TUOE.P2014WO / 00678799

[0197] (B5) In any of the embodiments (B1)-(B4), the clean the exposed bottom plate of the DMF chip including one or more of: plasma ashing or ultrasonic cleaning.

[0198] (B6) In any of the embodiments (B1)-(B5), removing the cover layer and one or more sub-layers of the dielectric stack including one or more of wet etching, peeling off, or dry-etching.

[0199] (B7) In any of the embodiments (B1)-(B6), the method further including repeating (a)-(d) for at least one additional recycling iteration; and after each recycling iteration, testing actuation voltage and breakdown voltage to verify operation of the recycled DMF chip.

[0200] (B8) In any of the embodiments (B1)-(B7), characterized in that integrity of the at least one multi-layer electrode is maintained during (a)-(d).

[0201] (B9) In any of the embodiments (B1)-(B8), the DMF chip recycled being any of the DMF chip embodiments of the first aspect.

[0202] (Cl) In an embodiment of a third aspect hereof, a method for manufacturing a digital microfluidic chip, includes: forming a multi-layer electrode by: forming a connection trace at a first electrode-insulating sub-layer of a dielectric layer; after forming the connection trace, forming an electrode in another electrode-insulating sub-layer of the dielectric stack, the connection trace and the electrode spatially offset from each other in the Z-Direction.

[0203] (C2) In the embodiment (Cl), where the multi-layer electrode is one of a plurality of multi-layer electrodes arranged in an array in the dielectric layer.

[0204] (C3) In the embodiment (C1)-(C2), the connection trace being formed on a substrate layer.

[0205] (C4) In any the embodiment (C3), the substrate layer being glass.

[0206] (C5) In any embodiment (C1)-(C4), the forming the connection trace including: patterning a connection-trace photolithography layer to desired shape of the connection trace; and depositing metal material over the connection-trace photolithography layer; lifting off the connection-trace photolithography layer to yield the connection trace.

[0207] (C6) In any embodiment (C1)-(C5), the forming a vertical contact including: depositing the second electrode-insulating sub-layer over the connection trace; patterning a vertical-contact photolithography layer to desired shape of the vertical contact; etching the second electrode-insulating sub-layer to expose the connection trace according to the patterned vertical-contact photolithography layer; patterning an electrodePATENT Attorney Docket No. TUOE.P2014WO / 00678799 photolithography layer to a desired shape of the electrode; depositing additional metal to yield vertical contact and the electrode; and lifting off the electrode photolithography layer.

[0208] (C7) In any embodiment (C1)-(C6), further comprising depositing a coating layer, the coating layer positioned above the dielectric layer in the Z-direction.

[0209] (C8) In any embodiment (C7), the coating layer comprising a hydrophobic layer.

[0210] (C9) In any embodiment (C8), the hydrophobic layer comprising FluoroP el.

[0211] (CIO) In any embodiment (C7)-(C9), the coating layer having a thickness of 65nm ± 1 Inm.

[0212] (Cl 1) In any embodiment (Cl)-(C10), further comprising depositing a fourth dielectric sub-layer over the third electrode-insulating sub-layer in the Z-direction.

[0213] (C12) In any embodiment (Cl 1), the first electrode-insulating sub-layer, second electrode-insulating sub-layer, and the third electrode-insulating sub-layer being a first dielectric material; the fourth sub-layer being a second dielectric material different than the first dielectric material.

[0214] (C13) In any embodiment (C12), the first dielectric material being silicon nitride.

[0215] (C14) In any embodiment (C12)-(C13), the second dielectric material being Parylene C.

[0216] (C15) In any embodiment (C12)-(C14), characterized by one of: the first dielectric material having a first thickness of 400nm or less and the second dielectric material having a second thickness of 0.5pm or less; the first dielectric material having a first thickness of 400nm or less and the second dielectric material having a second thickness of 1 m or less; the first dielectric material having a first thickness of 400nm or less and the second dielectric material having a second thickness of 2pm or less.

[0217] (C16) In any embodiment (C1)-(C15), the method further including depositing a top-plate as a top-most layer of the digital microfluidic chip.

[0218] (C17) In any embodiment (C1)-(C16), the manufactured digital microfluidic chip being characterized by an alternating actuation voltage, that operates to actuate fluid between the three-dimensional electrode and another three-dimensional electrode, of 50V, less than 50V, between 50-100V, or less than 100V.PATENT Attorney Docket No. TUOE.P2014WO / 00678799

[0219] (C18) In any embodiment (C1)-(C17), the manufactured digital microfluidic chip including any feature described with respect to embodiment(s) of the first aspect.

[0220] (DI) In an embodiment of a fourth aspect hereof, a digital microfluidic chip includes: a substrate layer; an electrode layer mounted on the substrate layer; a dielectric layer covering the electrode layer, the dielectric layer including a first dielectric sub-layer comprising a first material and a second dielectric sub-layer comprising a second material different than the first material.

[0221] (D2) In the embodiment (DI), the first material includes polyvinylidene difluoride (PVDF); the second material includes SU-8 photoresist.

[0222] (D3) In any embodiment (D2), the first dielectric sub-layer being between the electrode layer and the second dielectric sub-layer.

[0223] (D4) In any embodiment (D2), the second dielectric sub-layer being between the electrode layer and the first dielectric sub-layer.

[0224] (D5) In any embodiment (D2)-(D4), the first dielectric sub-layer having a first thickness and the second dielectric sub-layer having a second thickness, the first thickness being less than the second thickness.

[0225] (D6) In any embodiment (D5), ratio of the first thickness to the second thickness being 1:5.

[0226] (D7) In any embodiment (D1)-(D6), further comprising a hydrophobic layer covering the dielectric layer.

[0227] (D8) In any embodiment (D7), further comprising a top plate covering the hydrophobic layer.

[0228] (D9) In any embodiment (D8), the electrode layer comprising an array of electrodes; the top plate including a plurality of windows therein, each window aligned with an electrode of the array of electrodes.

[0229] (D10) A bioassay comprising the digital microfluidic chip of any of embodiment (D1)-(D9).

[0230] (Dll) A cell culture or bioassay method comprising performing the cell culture or bioassay using the digital microfluidic chip of any of embodiment (D1)-(D9).

[0231] (D12) In any embodiment (Dl)-(Dl 1), the DMF chip including any feature of any embodiment of the first aspect.

[0232] (El) In an embodiment of a fifth aspect hereof, a method for manufacturing a digital microfluidic chip, includes: forming a first dielectric sub-layer, of aPATENT Attorney Docket No. TUOE.P2014WO / 00678799 dielectric stack, of a first material; and forming a second dielectric sub-layer, of the dielectric stack, of a second material; the first material being different than the second material.

[0233] (E2) In the embodiment (El), the first material including polyvinylidene difluoride (PVDF); the second material comprising SU-8 photoresist.

[0234] (E3) In any embodiment (E2), the forming the first dielectric sub-layer including spin-coating the PVDF onto a substrate.

[0235] (E4) In any embodiment (E2), the forming the second dielectric sub-layer including spin-coating the SU-8 photoresist onto the first dielectric sub-layer.

[0236] (E5) In any embodiment (E2), the forming the second dielectric sub-layer including spin-coating the SU-8 photoresist onto a substrate.

[0237] (E6) In any embodiment (E5), the forming the first dielectric sub-layer including spin-coating the PVDF onto the second dielectric sub-layer.

[0238] (E7) In any embodiment (E1)-(E6), further including providing a substrate layer; and patterning an array of electrodes on the substrate layer.

[0239] (E8) In any embodiment (E7), wherein the forming the first dielectric sublayer and the second dielectric sub-layer occurring after the patterning an array of electrodes such that the dielectric stack covers the array of electrodes.

[0240] (E9) In any embodiment (E1)-(E8), further including providing a top plate having a plurality of patterned hydrophilic windows.

[0241] (E10) In any embodiment (E9), the step of providing the top plate including aligning each hydrophilic window with an electrode of an array of electrodes of the digital microfluidic chip.

[0242] (El 1) In any embodiment (El)-(E10), the manufactured digital microfluidic chip including any feature described with respect to embodiment(s) of the first aspect.

[0243] (Fl) In an embodiment of a first aspect hereof, a compound that acts as an agonist of 5-HT2A receptor in a mammal, wherein the compound binds to 5-HT2A receptor at an affinity that is at least 2-folds, or at least 10 folds, stronger than the compound's affinity with other 5-HT receptors.

[0244] (F2) In the embodiment (Fl), wherein the compound is 4-Bromo-3,6-dimethoxybenzocyclobuten-l-yl)methylamine hydrobromide (TCB-2).

[0245] (F3) A method of treating or preventing a disease in a mammal, comprising administering to the mammal an effective amount of the compound of (Fl) or (F3).PATENT Attorney Docket No. TUOE.P2014WO / 00678799

[0246] (F4) In the embodiment (F3), wherein the compound of (Fl) or (F3) exhibits an anti-inflammatory effect when administered to the mammal.

[0247] (F5) In the embodiment (F4), wherein the compound is 4-Bromo-3,6-dimethoxybenzocyclobuten-l-yl)methylamine hydrobromide (TCB-2).

[0248] Changes may be made in the above methods and systems without departing from the scope hereof. It should thus be noted that the matter contained in the above description or shown in the accompanying drawings should be interpreted as illustrative and not in a limiting sense. The following claims are intended to cover all generic and specific features described herein, as well as all statements of the scope of the present method and system, which, as a matter of language, might be said to fall therebetween.

Claims

1. PATENT Attorney Docket No. TUOE.P2014WO / 00678799 CLAIMSWhat is claimed is:

1. A digital microfluidic (DMF) chip comprising:a multi-layer dielectric stack, the dielectric stack including a plurality of sub-layers stacked in a Z-direction;at least one multi-layer electrode embedded within at least one electrode-insulating sublayer of the dielectric stack, the multi-layer electrode comprising:a connection trace,an electrode spatially offset in the Z-direction from the connection trace, andthe electrode and connection trace being located in different electrodeinsulating sub-layers.

2. The DMF chip of claim 1, further comprising a substrate layer, the dielectric stack positioned above the substrate layer in the Z-direction.

3. The DMF chip of claim 2, the substrate layer comprising glass.

4. The DMF chip of any preceding claim,the at least one electrode-insulating sub-layer including a first electrode-insulating sublayer, a second electrode-insulating sub-layer, and a third electrode-insulating sub-layer;the connection trace extending within the first electrode-insulating sub-layer;the electrode extending within the third electrode-insulating sub-layer; and,vertical contact extending through the second electrode-insulating sub-layer in the Z-direction between the connection trace and the electrode.

5. The DMF chip of claim 4, wherein dielectric material of the second electrodeinsulating sub-layer is located between the electrode and the connection trace.PATENT Attorney Docket No. TUOE.P2014WO / 00678799 6. The DMF chip of claim 1, the dielectric stack comprising an additional dielectric sub-layer, the additional dielectric sub-layer positioned above the third electrodeinsulating sub-layer in the Z-direction.

7. The DMF chip of claim 6, the first electrode-insulating sub-layer, the second electrode-insulating sub-layer, and the third electrode-insulating sub-layer comprising a first dielectric material; the additional sub-layer comprising a second dielectric material different than the first dielectric material.

8. The DMF chip of any preceding claim, further comprising a coating layer, the coating layer positioned above the dielectric stack in the Z-direction.

9. The DMF chip of claim 8, the coating layer comprising a hydrophobic layer.

10. The DMF chip of claim 9, the hydrophobic layer comprising FluoroPei.

11. The DMF chip of claim 8, 9, or 10, the coating layer having a thickness of between about 50 nm and about 100 nm.

12. The DMF chip of any preceding claim, at least one sub-layer of the dielectric stack being an inorganic dielectric, optionally silicon nitride.

13. The DMF chip of any preceding claim, at least one sub-layer of the dielectric stack being a conformal polymer dielectric layer, optionally Parylene C.

14. The DMF chip of claim 7, 12, or 13, characterized by one of:the first dielectric material having a first thickness of 400nm or less and the second dielectric material having a second thickness of 0.5pm or less;the first dielectric material having a first thickness of 400nm or less and the second dielectric material having a second thickness of 1 m or less;the first dielectric material having a first thickness of 400nm or less and the second dielectric material having a second thickness of 2pm or less.

15. The DMF chip of any preceding claim, the at least one multi-layer electrode being one of a plurality of multi-layer electrodes arranged in an array within the dielectric stack.PATENT Attorney Docket No. TUOE.P2014WO / 00678799 16. The DMF chip of claim 15, each connection trace of each electrode within the plurality of multi-layer electrodes being located within the same sub-layers of the dielectric stack.

17. The DMF chip of claim 15 or 16, each connection trace coupled to a respective contact pad located outside of an operational area of the dielectric stack.

18. The DMF chip of any preceding claim, further comprising:a top plate as a top-most layer of the DMF chip in the Z-direction;wherein the dielectric stack and the at least one multi-layer electrode are components of a bottom plate of the DMF chip.

19. The DMF chip of claim 18, the top plate including a transparent ground electrode.

20. The DMF chip of claim 18 or 19, the top plate comprising an indium tin oxide (ITO) layer having sections corresponding to locations of one or more electrodes, the sections having portions of the ITO layer removed therefrom.

21. The DMF chip of claim 18, 19, or 20,the electrode comprising an array of electrodes;the top plate including a plurality of windows therein, each window aligned with an electrode of the array of electrodes.

22. The DMF chip of any preceding claim, characterized in that the digital microfluidic chip operates to actuate fluid between the at least one multi-layer electrode and another multi-layer electrode at an actuation voltage of 1000V or less, optionally 50V or less., optionally with alternating current at 10kHz.

23. The DMF chip of any preceding claim, at least some sub-layers of the plurality of sub-layers including polymeric dielectric material having high dielectric constant and humidity resistance.

24. The DMF chip of any preceding claim,PATENT Attorney Docket No. TUOE.P2014WO / 00678799 at least one sub-layer of the plurality of sub-layers comprising polyvinylidene difluoride (PVDF);at least another sub-layer of the plurality of sub-layers comprising SU-8 photoresist.

25. The DMF chip of claim 24, the PVDF sub-layer being between the at least one electrode-insulating sub-layer and the SU-8 photoresist sub-layer.

26. The DMF chip of any preceding claim, characterized in that the digital microfluidic chip exhibits stable electrical performance about 90% humidity and about 37 degrees Celsius for 60 or more days.

27. The DMF chip of any preceding claim, further comprising:a plurality of addressable culture sites, at least one reagent reservoir region corresponding to one or more of the addressable culture sites;wherein the at least one electrode is arranged to meter, route, merge, and split droplets so as to provide time-varying stimulation regimens to immune cells at the culture sites.

28. A biological cell-based assay comprising;the DMF chip of any of claims 1 through 27;a plurality of droplets containing mammalian cells being cultured therein.

29. The biological cell-based assay of claim 28, wherein average cell viability is maintained above 80% following electrowetting on dielectric (EWOD).

30. The DMF chip of any preceding claim, forming at least one hydrophilic window defining at least one respective culture site aligned to the at least one multi-layer electrode, further comprising a controller coupled to the at least one multi-layer electrode and machine readable instructions that, when executed by the controller, manipulate droplets, using the at least one multi-layer electrode, by electro wetting to deliver controlled biochemical stimulation to immune cells at the respective culture site.

31. The DMF chip of claim 30, wherein the controlled biochemical stimulation comprises contacting macrophages with a biochemical stimulator to induce a pro-inflammatory polarization.PATENT Attorney Docket No. TUOE.P2014WO / 00678799 32. The DMF chip of claim 31, the biochemical stimulator comprising lipopolysaccharide (LPS) at a final concentration of about 0.5-2 pg / mL or interferon-y (IFN-y) at a final concentration of about 10-30 ng / mL.

33. The DMF chip of claim 31, wherein each of the at least one culture site is functionalized to promote cell adhesion and provides optical access through a top plate of the DMF chip, thereby enabling quantification of cytokine secretion at a single-cell level.

34. The DMF chip of claim 33, wherein the at least one culture sites are configured to support population-level cytokine quantification by aggregating signals from multiple cells within the at least one culture sites.

35. The DMF chip of claim 33 or 34, wherein the cytokines comprise one or more of tumor necrosis factor-a (TNF-a) or interleukin- 10 (IL-10).

36. The DMF chip of claim 30, the instructions, when executed by the controller, causing dynamic modulation of immune-cell state by sequentially delivering droplets comprising a candidate immunomodulatory compound at a controlled concentration and subsequently removing or adjusting the compound by electrowetting actuation of selective ones of the at least one electrode.

37. A method for recycling a digital microfluidic (DMF) chip, comprising:(a) removing a cover layer and one or more sub-layers of a dielectric stack of the DMF chip to expose a bottom plate of the DMF chip;(b) cleaning the exposed bottom plate of the DMF chip;(c) recoating new sub-layers of the dielectric stack; and,(d) recoating a new cover layer;wherein the bottom plate includes one or more multi-layer electrodes embedded within at least one electrode-insulating sub-layer of the dielectric stack, the multi-layer electrode comprising:a connection trace, andan electrode spatially offset in a Z-direction from the connection trace.PATENT Attorney Docket No. TUOE.P2014WO / 00678799 38. The method of claim 37, the cover layer being a hydrophobic layer.

39. The method of either claim 37 or 38, the one or more sub-layers comprising one or more of: a polyvinylidene difluoride (PVDF) sub-layer, a SU-8 photoresist sub-layer, a Parylene C sub-layer, or a Silicon Nitride sub-layer.

40. The method of any of claims 37 through 39, the clean the exposed bottom plate of the DMF chip comprising one or more of: plasma ashing or ultrasonic cleaning.

41. The method of any of claims 37 through 40, removing the cover layer and one or more sub-layers of the dielectric stack comprising one or more of wet etching, peeling off, or dry-etching.

42. The method of any of claims 37 through 41, comprising repeating (a)-(d) for at least one additional recycling iteration; andafter each recycling iteration, testing actuation voltage and breakdown voltage to verify operation of the recycled DMF chip.

43. The method of any of claims 37 through 42, characterized in that integrity of the at least one multi-layer electrode is maintained during (a)-(d).

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