Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor capable of further improving reliability.　A multilayer ceramic capacitor 10 comprises a multilayer body 12 and an external electrode 30 formed on the multilayer body. A base electrode layer 32 of the external electrode 30 has an end surface electrode portion, and a wraparound electrode portion 40 that wraps around from a first end surface 12e and a second end surface 12f to at least one of a first main surface 12a, a second main surface 12b, a first side surface 12c, and a second side surface 12d. When a surface obtained by extending, in the length direction, a surface of the multilayer body not covered with the wraparound electrode portion is defined as a reference surface, the multilayer body has a first region 50 disposed in a planar shape inward from the reference surface, and a second region 52 disposed in a planar shape in a manner being adjacent to the first region on the inner side. The first region is disposed on the end surface electrode portion side as compared to at least an end portion part in the length direction. The content of silicon (Si) in the first region is greater than the content of silicon (Si) in the second region, the content of barium (Ba) in the first region is greater than the content of barium (Ba) in the second region, and the content of titanium (Ti) in the first region is smaller than the content of titanium (Ti) in the second region.

Description

Multilayer ceramic capacitor

[0001] This invention relates to a multilayer ceramic capacitor.

[0002] A general multilayer ceramic capacitor includes a laminate in which a plurality of dielectric layers and a plurality of internal electrode layers are laminated, and external electrodes formed on the outer surface of the laminate. The internal electrode layer is drawn out to the end face of the laminate and connected to the external electrode. The external electrode is composed of, for example, a base electrode layer formed by firing a conductive paste applied to the laminate and a plating layer formed on the outer surface of the base electrode layer.

[0003] When forming the plating layer, usually, wet plating such as electrolytic plating is applied, and for example, a nickel (Ni) plating layer and a tin (Sn) plating layer are formed. The nickel (Ni) plating layer is used to prevent the base electrode layer from being eroded by solder when the multilayer ceramic capacitor is mounted on a substrate or the like. The tin (Sn) plating layer is used to improve the wettability of the solder when the multilayer ceramic capacitor is mounted on a substrate or the like so that it can be easily mounted. There is a possibility that moisture may penetrate from the interface between the external electrode and the laminate of the multilayer ceramic capacitor into the interior due to the plating solution used for such wet plating. Also, in such a situation, when the multilayer ceramic capacitor is mounted on a mounting substrate and the mounting substrate is bent, it may affect the reliability of the multilayer ceramic capacitor.

[0004] Therefore, a multilayer ceramic capacitor as described in Patent Document 1 has been proposed. In this multilayer ceramic capacitor, a crystal containing an element constituting a glass component contained in the external electrode exists at the grain boundary between ceramic particles located at a portion contacting the edge of the external electrode in the ceramic body (laminate). By causing such a crystal to exist at the grain boundary between ceramic particles located at a portion contacting the edge of the external electrode, it is intended to suppress the intrusion of a plating solution or the like.

[0005] International Publication No. 14 / 097701

[0006] However, in recent years, the demand for reliability in multilayer ceramic capacitors has increased, and in addition to suppressing the intrusion of the plating solution, there is a need for further improvement in the reliability of multilayer ceramic capacitors.

[0007] Therefore, the primary objective of this invention is to provide a multilayer ceramic capacitor that can be made more reliable.

[0008] The multilayer ceramic capacitor according to this invention comprises a laminate including a plurality of laminated dielectric layers and a plurality of internal electrode layers, a laminate including a first main surface and a second main surface facing each other in the lamination direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the lamination direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the lamination direction and the width direction, and an external electrode electrically connected to the internal electrode layer and disposed on the laminate, wherein the external electrode includes a base electrode layer formed on the laminate, the base electrode layer includes a conductive metal and glass, and the base electrode layer includes end electrode portions formed on the laminate at the first end surface and the second end surface, and is continuous with the end electrode portions and is laminated by wrapping around from the first end surface and the second end surface to at least one of the first main surface, the second main surface, the first side surface and the second side surface. A multilayer ceramic capacitor having a wrap-around electrode portion formed on the body, the wrap-around electrode portion having an edge portion located at the tip that is longitudinally separated from a first end face and a second end face, and the laminate having a first region arranged planarly inward from the reference plane when the surface of the laminate not covered by the wrap-around electrode portion is extended longitudinally from the reference plane, and a second region arranged planarly adjacent to the first region further inward, wherein the first region is located at least on the end face electrode portion side than the edge portion in the longitudinal direction, the silicon (Si) content of the first region is greater than the silicon (Si) content of the second region, the barium (Ba) content of the first region is greater than the barium (Ba) content of the second region, and the titanium (Ti) content of the first region is less than the titanium (Ti) content of the second region.

[0009] According to the multilayer ceramic capacitor of the present invention, the laminate has a first region arranged planarly inward from the reference plane, when the surface of the laminate not covered by the wrap-around electrode portion is extended in the longitudinal direction, and a second region arranged planarly adjacent to the first region and inward, including the edge portion of the wrap-around electrode portion. The first region is positioned at least on the end-face electrode portion side of the edge portion in the longitudinal direction, the silicon (Si) content of the first region is greater than the silicon (Si) content of the second region, the barium (Ba) content of the first region is greater than the barium (Ba) content of the second region, and the titanium (Ti) content of the first region is less than the titanium (Ti) content of the second region. With the above configuration, the composite oxide constituting the first region is poorly soluble in water, which blocks the intrusion of moisture into the interior of the laminate, thereby suppressing the occurrence of cracks in the laminate and preventing failure of the multilayer ceramic capacitor. Furthermore, the above-described configuration has multiple structures consisting of a first region and a second region. Residual stress concentrated at the edges of each main surface and each side surface of the external electrode is released by fracture within the second region, thereby suppressing the propagation of cracks into the interior of the laminate. Consequently, by preventing the cracks from propagating into the interior of the laminate, short circuits between the internal electrode layers are suppressed. This improves the reliability of the multilayer ceramic capacitor.

[0010] This invention makes it possible to provide a multilayer ceramic capacitor that can be made more reliable.

[0011] The above-mentioned objectives, other objectives, features, and advantages of this invention will become even clearer from the following description of embodiments for carrying out the invention, with reference to the drawings.

[0012] This is an external perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. This is a cross-sectional view taken along line II-II in Figure 1. This is a cross-sectional view taken along line III-III in Figure 1. This is a partially enlarged cross-sectional view of part A in Figure 2.

[0013] An example of a multilayer ceramic capacitor according to an embodiment of this invention will be described. The multilayer ceramic capacitor of this embodiment is a two-terminal type multilayer ceramic capacitor.

[0014] Figure 1 is an external perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. Figure 2 is a cross-sectional view taken along line II-II in Figure 1. Figure 3 is a cross-sectional view taken along line III-III in Figure 1. Figure 4 is a partially enlarged cross-sectional view of part A in Figure 2.

[0015] The laminate 12 has a plurality of stacked dielectric layers 14 and a plurality of internal electrode layers 16. Furthermore, the laminate 12 has a first main surface 12a and a second main surface 12b facing the stacking direction x, a first side surface 12c and a second side surface 12d facing the width direction y perpendicular to the stacking direction x, and a first end surface 12e and a second end surface 12f facing the length direction z perpendicular to the stacking direction x and the width direction y.

[0016] It is preferable that the corners and edges of the laminate 12 are rounded. A corner is the part where three adjacent faces of the laminate 12 intersect, and an edge is the part where two adjacent faces of the laminate 12 intersect.

[0017] Furthermore, irregularities or other features may be formed on part or all of the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f. Moreover, the length z dimension of the laminate 12 is not necessarily longer than the width y dimension.

[0018] The laminate 12 has an effective layer portion 15a in which the internal electrode layers 16 face each other in the lamination direction x connecting the first main surface 12a and the second main surface 12b, a first outer layer portion 15b located between the internal electrode layer 16 closest to the first main surface 12a and the first main surface 12a, and a second outer layer portion 15c located between the internal electrode layer 16 closest to the second main surface 12b and the second main surface 12b.

[0019] The first outer layer 15b is located on the side of the first main surface 12a of the laminate 12 and is an assembly of multiple dielectric layers 14 located between the first main surface 12a and the internal electrode layer 16 closest to the first main surface 12a. The second outer layer 15c is located on the side of the second main surface 12b of the laminate 12 and is an assembly of multiple dielectric layers 14 located between the second main surface 12b and the internal electrode layer 16 closest to the second main surface 12b. The region sandwiched between the first outer layer 15b and the second outer layer 15c is the effective layer 15a.

[0020] The dimensions of the laminate 12 are not particularly limited, but it is preferable that the dimension in the length direction z is, for example, 0.2 mm or more and 5.0 mm or less, the dimension in the width direction y is, for example, 0.1 mm or more and 5.0 mm or less, and the dimension in the stacking direction x is, for example, 0.1 mm or more and 5.0 mm or less.

[0021] The dielectric layer 14 can be formed from a dielectric material, such as a ceramic material. Such dielectric materials include perovskite compounds represented by the general formula ABO3, where the A site is barium (Ba). As the dielectric material, for example, a dielectric ceramic containing components such as barium titanate (BaTiO3) can be used. When the above dielectric material is included as the main component, depending on the desired properties of the laminate 12, for example, manganese (Mn) compounds, iron (Fe) compounds, chromium (Cr) compounds, cobalt (Co) compounds, nickel (Ni) compounds, etc. may also be included.

[0022] The number of dielectric layers 14, including the effective layer portion 15a and the first and second outer layers 15b and 15c, is preferably, for example, 100 to 1000 layers.

[0023] The thickness of the dielectric layer 14 after firing is preferably, for example, 0.3 μm or more and 2.0 μm or less.

[0024] As shown in Figure 2, the laminate 12 has a plurality of internal electrode layers 16, for example, a plurality of substantially rectangular first internal electrode layers 16a and a plurality of second internal electrode layers 16b. The plurality of first internal electrode layers 16a and the plurality of second internal electrode layers 16b are embedded so as to be alternately arranged at equal intervals along the stacking direction of the laminate 12. The first internal electrode layers 16a and the second internal electrode layers 16b may be arranged parallel to the mounting surface or perpendicular to it.

[0025] The end of the first internal electrode layer 16a is exposed from the laminate 12 at the first end face 12e. The end of the second internal electrode layer 16b is exposed from the laminate 12 at the second end face 12f.

[0026] The internal electrode layer 16 contains a suitable conductive material, such as metals like nickel (Ni), copper (Cu), silver (Ag), palladium (Pd), and gold (Au), or alloys containing at least one of these metals, such as Ag-Pd alloys. The internal electrode layer 16 may further contain dielectric particles of the same composition as the ceramics contained in the dielectric layer 14.

[0027] The thickness of the internal electrode layer 16 is preferably, for example, 0.2 μm or more and 2.0 μm or less.

[0028] External electrodes 30 are arranged on the first end face 12e and the second end face 12f of the laminate 12. The external electrodes 30 have a first external electrode 30a and a second external electrode 30b.

[0029] The first external electrode 30a is connected to the first internal electrode layer 16a on the first end face 12e side. In this embodiment, the first external electrode 30a extends from the first end face 12e side and is positioned on a portion of the first main surface 12a side and a portion of the second main surface 12b side, as well as a portion of the first side surface 12c side and a portion of the second side surface 12d side.

[0030] The second external electrode 30b is connected to the second internal electrode layer 16b on the second end face 12f side. In this embodiment, the second external electrode 30b extends from the second end face 12f side and is positioned on a portion of the first main surface 12a side and a portion of the second main surface 12b side, as well as a portion of the first side surface 12c side and a portion of the second side surface 12d side.

[0031] Within the laminate 12, the first internal electrode layer 16a and the second internal electrode layer 16b face each other via the dielectric layer 14, thereby forming a capacitance. As a result, capacitance can be obtained between the first external electrode 30a to which the first internal electrode layer 16a is connected and the second external electrode 30b to which the second internal electrode layer 16b is connected, resulting in the characteristics of a capacitor.

[0032] The external electrode 30 includes a base electrode layer 32. Preferably, the external electrode 30 also includes a plating layer 34 formed on the base electrode layer 32.

[0033] The base electrode layer 32 has a first base electrode layer 32a and a second base electrode layer 32b.

[0034] The first base electrode layer 32a is connected to the first internal electrode layer 16a on the first end face 12e side of the laminate 12. In this embodiment, the first base electrode layer 32a is formed to extend from the first end face 12e side and cover a portion of the surface on the first main surface 12a side, the second main surface 12b side, the first side surface 12c side, and the second side surface 12d side.

[0035] The second base electrode layer 32b is connected to the second internal electrode layer 16b on the second end face 12f side of the laminate 12. In this embodiment, the second base electrode layer 32b is formed to extend from the second end face 12f side and cover a portion of the surface on the first main surface 12a side, the second main surface 12b side, the first side surface 12c side, and the second side surface 12d side.

[0036] The maximum thickness of the first and second underlay electrode layers 32a and 32b is preferably, for example, 3 μm to 200 μm.

[0037] Figure 3 shows the first external electrode 30a arranged over a portion of the first main surface 12a. Figure 3 is a cross-sectional view perpendicular to the first end surface 12e and the second end surface 12f. The configuration in which the first base electrode layer 32a is arranged over the first end surface 12e, the second main surface 12b, the first side surface 12c, and the second side surface 12d is the same as in Figure 4. The configuration in which the second external electrode 30b is arranged over the first main surface 12a, the second main surface 12b, the first side surface 12c, and the second side surface 12d is also the same as in Figure 4.

[0038] As shown in Figure 4, the base electrode layer 32 includes sintered glass 60 and a plurality of sintered conductive particles. The glass 60 contains a plurality of glass domains 61. The sintered glass domains 61 of the base electrode layer 32 include an oxide containing at least one element selected from, for example, boron (B), silicon (Si), barium (Ba), manganese (Mg), aluminum (Al), lithium (Li), zinc (Zn), calcium (Ca), bismuth (Bi), titanium (Ti), strontium (Sr), gallium (Ga), etc. The conductive particles of the base electrode layer 32 include sintered conductive metal (metal particles). The metallic component of the metal particles includes at least one selected from, for example, copper (Cu), copper (Cu) alloy, nickel (Ni), silver (Ag), palladium (Pd), Ag-Pd alloy, gold (Au), etc. Hereafter, conductive particles will be referred to as metal particles. The base electrode layer 32 may also consist of multiple layers.

[0039] Furthermore, the base electrode layer 32 has an end-face electrode portion and a wrap-around electrode portion 40.

[0040] The end face electrode portion is positioned on the first end face 12e and the second end face 12f, and on a surface that extends along the first end face 12e and the second end face 12f.

[0041] The wrap-around electrode portion 40 is continuous with the end face electrode portion and is formed on the laminate 12 by wrapping around from the first end face 12e and the second end face 12f to the first main surface 12a, the second main surface 12b, the first side surface 12c, and the second side surface 12d. In this embodiment, the wrap-around electrode portion 40 is formed on a part of the first main surface 12a, a part of the second main surface 12b, a part of the first side surface 12c, and a part of the second side surface 12d. The wrap-around electrode portion 40 may be formed on at least one of the surfaces of a part of the first main surface 12a, a part of the second main surface 12b, a part of the first side surface 12c, and a part of the second side surface 12d. In the example of Figure 4, the wrap-around electrode portion 40 is adjacent to the end face electrode portion via a surface extended along the first end face 12e (and the second end face 12f). The wrap-around electrode portion 40 is formed in a state in which multiple sintered metal particles and multiple sintered glass domains 61 are mixed together. As shown in Figure 4, a portion of the multiple glass domains 61 are located on the first main surface 12a (second main surface 12b, first side surface 12c, second side surface 12d) within the wrap-around electrode portion 40. The wrap-around electrode portion 40 and the laminate 12 are bonded mainly via each of the multiple glass domains 61 (each of a continuous glass domain 61) located on the first main surface 12a (second main surface 12b, first side surface 12c, second side surface 12d). In addition, the wrap-around electrode portion 40 and the laminate 12 may be bonded via multiple metal particles or the like. Furthermore, another portion of the multiple glass domains 61 are located in a dispersed state inside the wrap-around electrode portion 40. In addition, the multiple glass domains 61 may face the outer surface of the wrap-around electrode portion 40, or a portion of them may protrude from the outer surface.

[0042] The wrap-around electrode portion 40 has an edge portion 42. The edge portion 42 is located at the tip, which is distanced in the longitudinal direction z from the first end face 12e and the second end face 12f, respectively.

[0043] Here, as shown in Figure 4, the surface of the laminate 12 that is not covered by the wrap-around electrode portion 40 is defined as the laminate surface 18.

[0044] As shown in FIGS. 2 to 4, when the surface 18a of the laminate 12 is a reference surface that extends the laminate surface 18 in the longitudinal direction z, the laminate 12 includes a first region 50 that is disposed in a planar shape inward from this reference surface 18a. Further, the first region 50 is disposed on the end face electrode portion side of at least the edge portion 42 in the longitudinal direction z. The first region 50 contains a composite oxide. The composite oxide contains barium (Ba), titanium (Ti), silicon (Si), copper (Cu), calcium (Ca), zinc (Zn), and zirconium (Zr). The first region 50 is disposed on the first main surface 12a side, the second main surface 12b side, the first side surface 12c side, the second side surface 12d side, the first end face 12e side, and the second end face 12f side of the laminate 12.

[0045] In the first region 50 containing this composite oxide, in the firing process, as shown in FIG. 4, a through portion 50a may be disposed so as to penetrate through the glass domain 61 in the region where the film thickness is thin near the edge portion 42 of the wraparound electrode portion 40 of the base electrode layer 32 and be exposed on the surface. Further, in the first region 50 containing this composite oxide, a tip exposed portion 50b may be disposed so as to extend in the longitudinal direction z from the edge portion 42 of the wraparound electrode portion 40 of the base electrode layer 32 and be exposed on the laminate surface 18. The arrangement state of the first region 50 and the through portion 50a and the tip exposed portion 50b constituting the first region 50 greatly depends on the amount of glass frit contained in the base electrode layer 32 and the firing temperature. The larger the amount of glass in the paste for the base electrode layer used when forming the base electrode layer 32 and the higher the firing temperature, the easier it is to form the through portion 50a and the tip exposed portion 50b. Thereby, it is possible to further suppress the intrusion of moisture into the laminate 12.

[0046] In the process of firing the base electrode layer 32, by liquid-phase sintering, some components in the glass domain 61 of the base electrode layer 32 and some components existing in the grain boundaries 64 of the ceramic particles 62 move, diffuse, and exchange with each other, forming a first region 50 containing a composite oxide mainly composed of silicon (Si), titanium (Ti), and barium (Ba). Among the composite oxides contained in this first region 50, when the total content ratio of silicon (Si), titanium (Ti), and barium (Ba) is 100 at%, the ratio of silicon (Si) is preferably 25 at% or more and 50 at% or less, the ratio of titanium (Ti) is 10 at% or more and 30 at%, and the ratio of barium (Ba) is 25 at% or more and 50 at%.

[0047] The thickness of the first region 50 does not have to be uniform. That is, the thickness in the stacking direction x along the length direction z of the first region 50 disposed on the first major surface 12a side and the second major surface 12b side, or the thickness in the width direction y along the length direction z of the first region 50 disposed on the first side surface 12c side and the second side surface 12d side may have thick portions and thin portions. In order to more reliably suppress the intrusion of moisture, the thickness of the thin portion of the thickness of the first region 50 is preferably at least 1 μm or more and 5 μm or less. More preferably, it is 1 μm or more and 1.0 μm or less.

[0048] As shown in FIG. 4, the laminate 12 includes a second region 52 disposed planar so as to be adjacent to the first region 50 on its further inner side. The second region 52 contains a composite oxide. The composite oxide contains barium (Ba), titanium (Ti), silicon (Si), copper (Cu), calcium (Ca), zinc (Zn), and zirconium (Zr).

[0049] In the first region 50 and the second region 52, the content of each composite oxide is different. That is, the content of silicon (Si) in the first region 50 is more than the content of silicon (Si) in the second region 52. The content of barium (Ba) in the first region 50 is more than the content of barium (Ba) in the second region 52. The content of titanium (Ti) in the first region 50 is less than the content of titanium (Ti) in the second region 52.

[0050] The thickness of the second region 52 does not have to be substantially uniform. That is, the thickness in the stacking direction x along the length direction z of the second region 52 located on the first main surface 12a side and the second main surface 12b side, or the thickness in the width direction y along the length direction z of the second region 52 located on the first side surface 12c side and the second side surface 12d side, may have both thick and thin portions. In order to suppress the propagation of cracks that would cause cracks to form within the second region 52, it is preferable that the thickness of the thinner portions of the second region 52 be at least 1 μm or more and 5 μm or less. More preferably, it is 1 μm or more and 1.0 μm or less.

[0051] The thicknesses of the first region 50 and the second region 52 are measured as follows. For example, after exposing the cross-section of the multilayer ceramic capacitor 10 by polishing, the thicknesses are detected by performing a compositional analysis using EDX (energy dispersive X-ray spectroscopy). For example, region 50 is silicon (Si) rich, and this region can be identified by EDX mapping analysis. If the EDX machine has a length measuring function, the thickness can be measured using this function. Even if this function is not available, the number of pixels in the region can be determined from the mapping data, and the thickness can be calculated from the size of one pixel and the number of pixels.

[0052] Furthermore, the laminate 12 includes a third region 54 that is planarly arranged adjacent to the second region 52 on the inside. The third region 54 may have gaps in the grain boundaries 64 between the ceramic particles 62. The barium (Ba) content and titanium (Ti) content in the third region 54 are approximately the same.

[0053] If the glass components present at the grain boundaries 64 between some of the glass domains 61 in the base electrode layer 32 and the ceramic particles 62 undergo excessive reactions such as movement, diffusion, and exchange, gaps may form at the grain boundaries 64 of the ceramic particles 62, as shown in the third region 54 in Figure 4. This phenomenon of gap formation at the grain boundaries 64 of the ceramic particles 62 is highly dependent on the firing temperature; the higher the temperature, the more likely gaps are to form at the grain boundaries 64 of the ceramic particles 62. Furthermore, depending on the composition and firing conditions, gaps may not form at the grain boundaries 64 of the ceramic particles 62.

[0054] The first region 50 contains more silicon (Si), which constitutes the glass component, than the second region 52 and the third region 54. The second region 52 contains more titanium (Ti), which constitutes the ceramic component, than the first region 50 and the third region 54.

[0055] Each of the first to third regions 50 can be detected, for example, by polishing the multilayer ceramic capacitor 10 to expose its cross-section, and then performing a compositional analysis using a wavelength-dispersive X-ray analyzer (WDX). In addition, the portions where each of the first regions 50 exists can be detected, for example, by performing a compositional analysis using energy-dispersive X-ray spectroscopy (EDX) on the surface of the wrap-around electrode portion 40 of the underlay electrode layer 32 formed on the first main surface 12a, before forming the plating layer 34.

[0056] The plating layer 34 has a first plating layer 34a and a second plating layer 34b. The first plating layer 34a is arranged to cover the first underlay electrode layer 32a. The second plating layer 34b is arranged to cover the second underlay electrode layer 32b. The first plating layer 34a and the second plating layer 34b include at least one selected from, for example, copper (Cu), nickel (Ni), tin (Sn), silver (Ag), palladium (Pd), Ag-Pd alloy, gold (Au), etc.

[0057] The first plating layer 34a and the second plating layer 34b may be formed by multiple layers. In this case, the plating layer 34 preferably has a two-layer structure consisting of a lower plating layer made of nickel (Ni) plating formed on the base electrode layer 32 and an upper plating layer made of tin (Sn) plating formed on the lower plating layer.

[0058] In other words, the first plating layer 34a has a first lower plating layer and a first upper plating layer located on the surface of the first lower plating layer. The second plating layer 34b has a second lower plating layer and a second upper plating layer located on the surface of the second lower plating layer.

[0059] The lower plating layer made of nickel (Ni) is used to prevent the base electrode layer 32 from being corroded by solder when mounting the multilayer ceramic capacitor 10 to a substrate or the like. The upper plating layer made of tin (Sn) is used to improve the wettability of the solder when mounting the multilayer ceramic capacitor 10 to a substrate or the like, so that it can be mounted easily. The thickness of each layer of the upper and lower plating layers is preferably, for example, 2.0 μm or more and 15.0 μm or less.

[0060] The dimensions of the multilayer ceramic capacitor 10 are not particularly limited, but the length L dimension in the length direction z is, for example, 0.24 mm to 5.9 mm, the width W dimension in the width direction y is, for example, 0.12 mm to 5.7 mm, and the stacking T dimension in the stacking direction x is, for example, 0.12 mm to 5.7 mm. Note that the length L dimension in the length direction z is not necessarily longer than the width W dimension in the width direction y and the stacking T dimension in the stacking direction x.

[0061] The multilayer ceramic capacitor 10 shown in Figure 1 includes a first region 50 that includes the edge portion 42 of the wrap-around electrode portion 40 and is arranged planarly inward from the surface 18 of the laminate, and a second region 52 that is arranged planarly adjacent to the first region 50 and is located inside it. The silicon (Si) content of the first region 50 is greater than the silicon (Si) content of the second region 52. The barium (Ba) content of the first region 50 is greater than the barium (Ba) content of the second region 52. The titanium (Ti) content of the first region 50 is less than the titanium (Ti) content of the second region 52. With this configuration, the composite oxide constituting the first region 50 is poorly soluble in water, which blocks the intrusion of moisture into the interior of the laminate 12, thereby suppressing the occurrence of cracks in the laminate 12 and preventing failure of the multilayer ceramic capacitor 10.

[0062] Furthermore, the multilayer ceramic capacitor 10 shown in Figure 1 has a multi-layer structure consisting of a first region 50 and a second region 52. Residual stress concentrated at the edges of each main surface and each side surface of the external electrode 30 is released by fracture within the second region 52, thereby suppressing the propagation of cracks into the interior of the laminate 12. Consequently, since the propagation of such cracks into the interior of the laminate 12 is prevented, short circuits between the internal electrode layers 16 are suppressed. This improves the reliability of the multilayer ceramic capacitor 10.

[0063] Furthermore, in the multilayer ceramic capacitor 10 shown in Figure 1, if the structural range in which gaps occur at the grain boundaries 64 of the ceramic particles 62, such as in the third region 54, widens, it can cause failure of the multilayer ceramic capacitor 10 due to bending cracks and the like. Therefore, it is possible to achieve a structure in which the composite oxide constituting the first region 50 is formed while preventing gaps from occurring at the grain boundaries 64 of the ceramic particles 62 constituting the third region 54.

[0064] Next, a method for manufacturing the multilayer ceramic capacitor 10 will be described.

[0065] (Step 1) First, a dielectric sheet for the dielectric layer and a conductive paste for the internal electrode layer are prepared. The dielectric sheet for the dielectric layer is formed from a dielectric slurry mainly composed of barium titanate (BaTiO3), although this is not limited to the dielectric sheet. The conductive paste for the internal electrode layer is formed mainly composed of nickel (Ni), although this is not limited to the conductive paste. The dielectric sheet and the conductive paste for the internal electrode layer contain a binder and a solvent. The binder and solvent are composed of a resin component, and as the resin component, various known thermosetting resins such as epoxy resin, phenoxy resin, phenolic resin, urethane resin, and polyimide resin can be used.

[0066] (Step 2) Then, a conductive paste for the internal electrode layer is printed on the dielectric sheet in a predetermined pattern, for example, by screen printing or gravure printing. This prepares a dielectric sheet with the pattern of the first internal electrode layer formed on it, and a dielectric sheet with the pattern of the second internal electrode layer formed on it.

[0067] Furthermore, with regard to dielectric sheets, dielectric sheets for the outer layer, which do not have the pattern of the internal electrode layer printed on them, are also prepared.

[0068] A predetermined number of dielectric sheets for the outer layer, which do not have the pattern of the internal electrode layer printed on them, are stacked. On top of these, dielectric sheets with the pattern of the first internal electrode layer printed on them, and dielectric sheets with the pattern of the second internal electrode layer printed on them are sequentially stacked to form an effective layer portion. On top of this effective layer portion, a predetermined number of dielectric sheets for the outer layer, which do not have the pattern of the internal electrode layer printed on them, are stacked. This forms a laminated sheet having an effective layer portion and an outer layer portion.

[0069] (Step 3) Next, the laminated sheets are pressed in the lamination direction by means of a hydrostatic press or other means to produce a laminated block.

[0070] (Step 4) The laminated block is then cut to a predetermined size, thereby cutting out the laminated chips.

[0071] (Step 5) Next, the resin component in the laminated chip is removed. The degreasing temperature for removing the resin component in Step 5 is, for example, higher than 600°C and 1000°C or lower.

[0072] (Step 6) Next, the laminated chip is fired to produce the laminated body 12. The firing temperature of the laminated chip depends on the materials of the dielectric layer and the internal electrode layer, but is preferably, for example, higher than 950°C and 1400°C or lower. Through this firing, the pattern of the internal electrode layer and the dielectric sheet are fired to form the internal electrode layer 16 and the dielectric layer 14.

[0073] (Step 7) Next, the paste for the base electrode layer is applied to the first and second end faces 12e and 12f of the laminate 12 and fired, thereby forming the base electrode layer 32 of the external electrode 30.

[0074] The paste for the base electrode layer according to this embodiment comprises a resin, a plurality of conductive metal powders (metal powders), glass powder, and a solvent. The metal component of the metal powder includes, for example, at least one selected from copper (Cu), copper (Cu) alloy, nickel (Ni), silver (Ag), palladium (Pd), Ag-Pd alloy, gold (Au), etc.

[0075] As the resin, various known thermosetting resins can be used, such as acrylic resins, ethylcellulose resins, epoxy resins, phenoxy resins, phenolic resins, urethane resins, and polyimide resins.

[0076] The glass powder contains at least one element selected from, for example, boron (B), silicon (Si), barium (Ba), manganese (Mg), aluminum (Al), lithium (Li), zinc (Zn), calcium (Ca), bismuth (Bi), titanium (Ti), strontium (Sr), gallium (Ga), etc. The content of glass powder in the paste for the base electrode layer is 5% by weight or more and 20% by weight or less, relative to the total content of metal particles and various additives. The particle size of the glass powder is preferably 0.5 μm or more and 10 μm or less. The glass softening point is preferably 500°C or more and 1000°C or less.

[0077] The firing conditions for forming the base electrode layer 32 are preferably within the temperature range in which the binder decomposes, with a reducing atmosphere for metals and an oxidizing atmosphere for carbon. The firing temperature is preferably between 600°C and 1000°C. This allows for the formation of the first region 50 and the second region 52, which contain the composite oxide shown in Figure 4.

[0078] The solvent includes, for example, at least one of terpineol, dihydroterpineol, dihydroterpinyl acetate, propylene glycol phenyl ether, benzyl alcohol, texanol, and butyl carbitol acetate. The solvent species can be analyzed by measuring the generated gas using gas chromatography-mass spectrometry. Gas chromatography-mass spectrometry can be performed, for example, using an Agilent Technologies, Inc. mass spectrometer 7890A / 5975C (heated at 500°C).

[0079] In addition, the paste for the base electrode layer may contain various additives such as dispersants, plasticizers, anti-settling agents, and thixotropes.

[0080] The paste for the base electrode layer is manufactured by weighing and mixing resin, metal powder, glass powder, and solvent in a predetermined mixing ratio, and then dispersing and kneading them using a three-roll mill or the like.

[0081] Next, a method for forming a base electrode layer 32 using the base electrode layer paste 71 according to the above embodiment will be described. In this embodiment, first, as shown in Figure 7, the base electrode layer paste 71 is applied to the laminate 12 in the base electrode layer paste application step. Then, in the base electrode layer paste drying step, the base electrode layer paste 71 applied to the laminate 12 is dried to form a dried film. Then, in the degreasing step of the dried film, the resin component in the dried film is degreased to form a base electrode layer before sintering. After that, a firing step for metal sintering is carried out.

[0082] (Step 8) Next, a plating layer 34 is formed on the base electrode layer 32. The plating layer 34 is formed, for example, by sequentially laminating a nickel (Ni) plating layer and a tin (Sn) plating layer on the base electrode layer 32.

[0083] A multilayer ceramic capacitor 10 is manufactured using the manufacturing method described above. The paste for the base electrode layer of the multilayer ceramic capacitor 10 has the characteristics described above.

[0084] As described above, embodiments of the present invention are disclosed in the above description, but the present invention is not limited thereto. That is, without departing from the scope of the technical idea and objectives of the present invention, various modifications can be made to the embodiments described above in terms of mechanism, shape, material, quantity, position or arrangement, etc., and these are included in the present invention.

[0085] <1> A multilayer ceramic capacitor comprising: a laminate including a plurality of stacked dielectric layers and a plurality of internal electrode layers, the laminate including a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction and the width direction; and an external electrode electrically connected to the internal electrode layer and disposed on the laminate, wherein the external electrode includes a base electrode layer formed on the laminate, and the base electrode layer includes a conductive metal and glass, The base electrode layer has an end electrode portion formed on the laminate at the first end face and the second end face, and a wrap-around electrode portion that is continuous with the end electrode portion and is formed on the laminate by wrapping around from the first end face and the second end face to at least one of the first main surface, the second main surface, the first side surface and the second side surface, wherein the wrap-around electrode portion has an edge portion located at the tip that is distanced in the longitudinal direction from the first end face and the second end face, and the laminate has a first region arranged in a planar manner inward from the reference plane when the surface of the laminate not covered by the wrap-around electrode portion is extended in the longitudinal direction, and a second region arranged in a planar manner further inward and adjacent to the first region, wherein the first region is located at least on the end electrode portion side of the edge portion in the longitudinal direction, A multilayer ceramic capacitor in which the silicon (Si) content of the first region is greater than the silicon (Si) content of the second region, the barium (Ba) content of the first region is greater than the barium (Ba) content of the second region, and the titanium (Ti) content of the first region is less than the titanium (Ti) content of the second region.

[0086] <2> The multilayer ceramic capacitor according to <1>, wherein the respective content ratios of silicon (Si), titanium (Ti), and barium (Ba) contained in the first region are such that, when their total is 100 at%, silicon (Si) is 25 at% or more and 50 at%, titanium (Ti) is 10 at% or more and 30 at%, and barium (Ba) is 25 at% or more and 50 at%.

[0087] <3> The multilayer ceramic capacitor according to <1> or <2>, wherein the first region further comprises copper (Cu), calcium (Ca), zinc (Zn), and zirconium (Zr).

[0088] <4> The multilayer ceramic capacitor according to any one of <1> to <3>, wherein the second region further comprises copper (Cu), calcium (Ca), zinc (Zn), and zirconium (Zr).

[0089] <5> A multilayer ceramic capacitor according to any one of <1> to <4>, wherein the base electrode layer includes a plating layer.

[0090] <6> The multilayer ceramic capacitor according to any one of <1> to <5>, wherein the first region is arranged to penetrate the glass contained in the base electrode layer and be exposed on the surface of the base electrode layer.

[0091] <7> The multilayer ceramic capacitor according to any one of <1> to <6>, wherein the first region has a tip exposed portion that extends from the edge portion in the longitudinal direction and is exposed on the surface of the laminate.

[0092] <8> The multilayer ceramic capacitor according to any one of <1> to <5>, wherein the thinnest thickness of the first region is 0.1 μm or more and 1.0 μm or less.

[0093] <9> The thinnest thickness of the second region is 0.1 μm or more and 1.0 μm or less, as described in any of <1> to <8>, a multilayer ceramic capacitor.

[0094] 10: Multilayer ceramic capacitor 12: Laminate 12a, 12b: First and second main surfaces 12c, 12d: First and second side surfaces 12e: First and second end surfaces 14: Dielectric layer 15a: Effective layer portion 15b, 15b: First and second outer layers 16: Internal electrode layer 16a, 16b: First and second internal electrode layers 30: External electrode 30a, 30b: First and second external electrodes 32: Underlay electrode layer 32a, 32b: First and second underlay electrode layers 34: Plating layer 34a, 34b: First and second plating layers 40: Wrap-around electrode portion 42: Edge portion 50: First region 50a: Through portion 50b: Exposed tip portion 52: Second region 54: Third region 60: Glass 61: Glass domain 62: Ceramic particles 64: Grain boundary x: Lamination direction y: Width direction z: Length direction

Claims

A laminate comprising a plurality of stacked dielectric layers and a plurality of internal electrode layers, the laminate comprising a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction and the width direction, An external electrode electrically connected to the internal electrode layer and arranged in the laminate, In a multilayer ceramic capacitor, The external electrode includes a base electrode layer formed on the laminate, The aforementioned underlay electrode layer includes a conductive metal and glass. The base electrode layer has an end electrode portion formed on the laminate at the first end face and the second end face, and a wrap-around electrode portion that is continuous with the end electrode portion and is formed on the laminate by wrapping around from the first end face and the second end face to at least one of the first main surface, the second main surface, the first side surface and the second side surface, wherein the wrap-around electrode portion has an edge portion located at the tip that is longitudinally separated from the first end face and the second end face. The laminated body is When the surface of the laminate that is not covered by the wrapping electrode portion is extended in the longitudinal direction and used as a reference plane, a first region is arranged in a planar manner inward from the reference plane, It comprises a second region arranged planarly so as to be further inward and adjacent to the first region, The first region is located in the longitudinal direction at least on the end face electrode side of the edge portion, A multilayer ceramic capacitor in which the silicon (Si) content of the first region is greater than the silicon (Si) content of the second region, the barium (Ba) content of the first region is greater than the barium (Ba) content of the second region, and the titanium (Ti) content of the first region is less than the titanium (Ti) content of the second region. 　 The multilayer ceramic capacitor according to claim 1, wherein the respective content ratios of silicon (Si), titanium (Ti), and barium (Ba) contained in the first region are such that, when their total is 100 at%, silicon (Si) is 25 at% or more and 50 at%, titanium (Ti) is 10 at% or more and 30 at%, and barium (Ba) is 25 at% or more and 50 at%. 　 The multilayer ceramic capacitor according to claim 1 or claim 2, wherein the first region further comprises copper (Cu), calcium (Ca), zinc (Zn), and zirconium (Zr). 　 The multilayer ceramic capacitor according to claim 1 or claim 2, wherein the second region further comprises copper (Cu), calcium (Ca), zinc (Zn), and zirconium (Zr). 　 The multilayer ceramic capacitor according to claim 1 or claim 2, wherein the underlying electrode layer includes a plating layer. 　 The multilayer ceramic capacitor according to claim 1 or claim 2, wherein the first region is arranged to penetrate the glass contained in the base electrode layer and be exposed on the surface of the base electrode layer. 　 The multilayer ceramic capacitor according to claim 1 or claim 2, wherein the first region has a tip exposed portion that extends from the edge portion in the longitudinal direction and is exposed on the surface of the laminate. 　 The multilayer ceramic capacitor according to claim 1 or claim 2, wherein the thinnest thickness of the first region is 0.1 μm or more and 1.0 μm or less. 　 The multilayer ceramic capacitor according to claim 1 or claim 2, wherein the thinnest thickness of the second region is 0.1 μm or more and 1.0 μm or less.

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