Inspection system

Abstract

Provided is technology that enables in-line inspection of a semiconductor layer formed between laminated structures in a semiconductor device such as a CFET. This computer system measures the respective luminances of a plurality of semiconductor layers when the plurality of semiconductor layers are irradiated with an electron beam, acquires first image data that includes the plurality of semiconductor layers, acquires statistical data by performing an operation on the respective luminances of the plurality of semiconductor layers, and determines the presence or absence of a defect with respect to the plurality of semiconductor layers, on the basis of the deviation of the respective luminances of the plurality of semiconductor layers from the statistical data.

Description

Inspection system

[0001] The present invention relates to an inspection system, and particularly to an inspection system that inspects an inspection object by irradiating an electron beam.

[0002] In recent years, in semiconductor devices, as new structures of n-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and p-type MOSFETs, three-dimensional structures called GAAFETs (Gate All Around Field Effect Transistors) have been developed. In addition, three-dimensional structures called CFETs (Complementary Field Effect Transistors), in which n-type MOSFETs and p-type MOSFETs are stacked vertically, have also been developed.

[0003] GAAFETs and CFETs have a plurality of stacked structures and a plurality of semiconductor layers formed between the plurality of stacked structures. The stacked structure includes a plurality of channel layers stacked apart from each other and a gate electrode surrounding the periphery of the plurality of channel layers via a plurality of gate insulating films. The semiconductor layer constitutes a source region or a drain region of the MOSFET and is formed, for example, by an epitaxial growth method.

[0004] As the height of the stacked structure increases, the aspect ratio increases, making it difficult to form a normal semiconductor layer between each stacked structure. In particular, the aspect ratio of the CFET is about twice that of the GAAFET.

[0005] For example, Non-Patent Document 1 discloses a GAAFET and a technique for forming a semiconductor layer between each stacked structure by an epitaxial growth method. Non-Patent Document 1 also discloses problems such as the problem that the semiconductor layer grows excessively, the problem that the semiconductor layer does not grow to a desired thickness, the problem that voids are formed inside the semiconductor layer, or the problem that the semiconductor layer is not connected to each channel layer of adjacent stacked structures.

[0006] J. Micro / Nanopattern. Mater. Metrol.

[0007] To evaluate the quality of semiconductor layers formed by epitaxial growth, inspection techniques such as atomic force microscopy (AFM), secondary ion mass spectrometry (SIMS), high-resolution X-ray diffraction (HRXRD), and cross-sectional transmission electron microscopy (X-TEM) are used. However, there is a need for a technology that can inspect the semiconductor layers formed between each stacked structure in a semiconductor wafer during manufacturing without damaging the semiconductor device.

[0008] Other challenges and novel features will become apparent from the description and accompanying drawings in this specification.

[0009] A brief overview of some of the representative embodiments disclosed in this application is as follows:

[0010] An inspection system according to one embodiment includes a computer system that performs inspection of an object to be inspected using image data obtained by irradiating the object to be inspected with an electron beam. The object to be inspected is a plurality of semiconductor layers formed between a plurality of stacked structures. Each of the plurality of stacked structures has a plurality of channel layers stacked apart from each other on a semiconductor substrate, and a gate electrode formed on the semiconductor substrate so as to surround the plurality of channel layers via a plurality of gate insulating films. In one of the stacked structures, if the semiconductor layer connected to one end of the plurality of channel layers constitutes a source region, the semiconductor layer connected to the other end of the plurality of channel layers constitutes a drain region. When the electron beam is irradiated onto the plurality of semiconductor layers, the computer system measures the brightness of each of the plurality of semiconductor layers, acquires first image data including the plurality of semiconductor layers, obtains statistical data by calculating the brightness of each of the plurality of semiconductor layers, and determines whether or not there are defects in the plurality of semiconductor layers based on the deviation of the brightness of each of the plurality of semiconductor layers from the statistical data.

[0011] An inspection system according to one embodiment includes a computer system that performs inspection of an object to be inspected using image data obtained by irradiating the object with an electron beam. The object to be inspected is a plurality of semiconductor layers formed between a plurality of stacked structures. Each of the plurality of stacked structures has a plurality of channel layers stacked apart from each other on a semiconductor substrate, and a gate electrode formed on the semiconductor substrate so as to surround the plurality of channel layers via a plurality of gate insulating films. In one of the stacked structures, if the semiconductor layer connected to one end of the plurality of channel layers constitutes a source region, the semiconductor layer connected to the other end of the plurality of channel layers constitutes a drain region. The computer system includes a learning model that has learned the relationship between the feature quantities of each of the plurality of semiconductor layers and the presence or absence of defects. When the plurality of semiconductor layers are irradiated with the electron beam, the computer system acquires the feature quantities of each of the plurality of semiconductor layers and inputs the acquired feature quantities into the learning model to determine whether or not there are defects in the plurality of semiconductor layers.

[0012] According to one embodiment, semiconductor layers formed between each stacked structure can be inspected in line.

[0013] This is a schematic diagram showing the inspection system in Embodiment 1. This is a schematic diagram showing other configurations of the inspection system in Embodiment 1. This is a schematic diagram showing other configurations of the inspection system in Embodiment 1. This is a perspective view showing a CFET in Embodiment 1. This is a cross-sectional view showing a CFET in Embodiment 1. This is a cross-sectional view showing a CFET in Embodiment 1. This is a cross-sectional view showing how electrons scatter when an electron beam is irradiated onto a semiconductor layer in Embodiment 1. This is a graph showing the results of a simulation by the present inventors. This is a flowchart for acquiring image data in Embodiment 1. This is a schematic diagram showing an example of an operation screen including a GUI screen in Embodiment 1. This is a flowchart for determining the presence or absence of defects in Embodiment 1. This is image data acquired in Embodiment 1. This is a schematic diagram showing a GUI screen in Embodiment 1. This is a schematic diagram showing the defect density distribution on a wafer in Embodiment 1. This is a flowchart for performing machine learning in Embodiment 2. This is a schematic diagram showing how a learning model is created by machine learning in Embodiment 2. This is a flowchart for determining the presence or absence of defects using the learning model in Embodiment 2. This is a schematic diagram showing how a defect is determined using the learning model created by machine learning in Embodiment 2. This is a flowchart for performing learning using a neural network in Embodiment 2. This is a schematic diagram showing how a learning model is created by a neural network in Embodiment 2. This is a schematic diagram showing how the presence or absence of defects is determined using the learning model created by the neural network in Embodiment 2.

[0014] The embodiments will be described in detail below with reference to the drawings. In all the drawings used to describe the embodiments, the same reference numerals are used for members having the same function, and repeated descriptions of them will be omitted. In addition, in the following embodiments, descriptions of the same or similar parts will not be repeated unless it is particularly necessary.

[0015] Furthermore, the X, Y, and Z directions described in this application intersect and are orthogonal to each other. In this application, the Z direction is described as the vertical direction, thickness direction, or depth direction of a certain structure.

[0016] (Embodiment 1) <Inspection System> Figure 1 is a schematic diagram showing the inspection system 1 in Embodiment 1. The inspection system 1 includes a charged particle beam device such as a scanning electron microscope (SEM).

[0017] As shown in Figure 1, the inspection system 1 comprises an electron gun 2, a focusing lens 3, a focusing lens 4, a deflector 5, an objective lens 6, a stage 8, a detector 9, an electron beam control system 10, an image generation system 11, a computer system 16, and an input / output device 20.

[0018] The electron gun 2 is capable of irradiating an electron beam (charged particle beam) EB1. The stage 8 can mount a sample 7. With the sample 7 mounted on the stage 8, the sample 7 can be observed by irradiating it with the electron beam EB1 from the electron gun 2. The electron beam EB1 emitted from the electron gun 2 is focused by focusing lenses 3 and 4, scanned over the sample 7 by the deflector 5, and focused by the objective lens 6. The electron beam control system 10 is electrically connected to the electron gun 2, focusing lenses 3 and 4, the deflector 5, the objective lens 6, and the stage 8, and controls their operation.

[0019] The detector 9 can detect backscattered electrons EB2 emitted from the sample 7 as a signal when the sample 7 is irradiated with an electron beam EB1. The image generation system 11 is electrically connected to the detector 9 and includes a signal conversion unit 12, a contrast adjustment unit 13, a brightness calculation unit 14, and an image generation unit 15. The signal conversion unit 12 converts the backscattered electrons EB2 into a signal. The contrast adjustment unit 13 measures the contrast of the sample 7 based on the signal. The brightness calculation unit 14 measures the brightness of the sample 7 from the contrast. The image generation unit 15 generates image data of the sample 7 from the brightness.

[0020] The computer system 16 includes a data processing unit 17, an image processor 18, and a memory storage unit 19. The data processing unit 17 and the image processor 18 are arithmetic processing units including semiconductor integrated circuits such as a CPU. The memory storage unit 19 is capable of storing information on multiple inspection targets, and each piece of information is associated with the others. The information on inspection targets includes, for example, the irradiation conditions of the electron beam EB1, contrast, brightness, image data, coordinates, dimensions, and area.

[0021] The computer system 16 is electrically connected to the electron beam control system 10 and the image generation system 11, and controls them. Therefore, it can also be said that the control performed by the electron beam control system 10 and the image generation system 11 is performed by the computer system 16.

[0022] The input / output device 20 is electrically connected to the computer system 16. By using the input / output device 20, the user can input various types of information into the computer system 16 and output various types of information from the computer system 16.

[0023] In some cases, another computer system 30 may be connected to the inspection system 1 via a network. Computer system 30 has the same functions as computer system 16. If image data has been acquired by inspection system 1, the inspection target can also be performed on computer system 30. In other words, the inspection target can be performed outside of inspection system 1.

[0024] Figures 2 and 3 show other configurations of the inspection system 1. In the inspection system 1 of Figure 1, high-angle backscattered electrons EB2 emitted from the sample 7 are directly detected by the detector 9.

[0025] The inspection system 1 in Figure 2 includes a deflector 21. The deflector 21 deflects high-angle backscattered electrons EB2, and the deflected backscattered electrons EB2 are detected by the detector 9. The detector 9 of the inspection system 1 in Figure 3 can detect backscattered electrons EB2 emitted over a wide range from the sample 7. From the detected backscattered electrons EB2, backscattered electrons EB2 at any angle α can be selected. The inspection system 1 used in subsequent inspections may have any configuration as shown in Figure 1, Figure 2, or Figure 3.

[0026] <Structure of CFET> The structure of the CFET will be described below with reference to Figures 4 to 6. Sample 7 of Embodiment 1 is a semiconductor wafer having multiple chip regions, and each of the multiple chip regions contains multiple CFETs.

[0027] As shown in Figure 4, the CFET includes a plurality of stacked structures LM formed on a semiconductor substrate SUB, and a plurality of semiconductor layers EPp1 and EPn1 formed between the plurality of stacked structures LM. The stacked structures LM have a plurality of channel layers CHn and CHp, and a gate electrode GE. The plurality of channel layers CHn and CHp are stacked on the semiconductor substrate SUB, spaced apart from each other. The gate electrode GE is formed on the semiconductor substrate SUB so as to surround the plurality of channel layers CHn and CHp via a plurality of gate insulating films GI, which will be described later.

[0028] In the CFET of Embodiment 1, an n-type MOSFET 2Q is stacked on top of a p-type MOSFET 1Q. However, the p-type MOSFET 1Q may be stacked on top of the n-type MOSFET 2Q.

[0029] The channel layer CHn is made of silicon into which n-type impurities have been introduced, for example, and constitutes the channel region of MOSFET 1Q. The semiconductor layer EPp1 is formed by epitaxial growth and is made of silicon into which p-type impurities have been introduced, for example. The semiconductor layer EPp1 is connected to multiple channel layers CHn of two adjacent stacked structures LM in the X direction. In one stacked structure LM, if the semiconductor layer EPp1 connected to one end of the multiple channel layers CHn constitutes the source region of MOSFET 1Q, then the semiconductor layer EPp1 connected to the other end of the multiple channel layers CHn constitutes the drain region of MOSFET 1Q.

[0030] The channel layer CHp is made of silicon into which p-type impurities have been introduced, for example, and constitutes the channel region of MOSFET 2Q. The semiconductor layer EPn1 is formed by epitaxial growth and is made of silicon into which n-type impurities have been introduced, for example. The semiconductor layer EPn1 is connected to multiple channel layers CHp of two adjacent stacked structures LM in the X direction. In one stacked structure LM, if the semiconductor layer EPn1 connected to one end of the multiple channel layers CHp constitutes the source region of MOSFET 2Q, then the semiconductor layer EPn1 connected to the other end of the multiple channel layers CHp constitutes the drain region of MOSFET 2Q.

[0031] As shown in Figure 5, first, a semiconductor layer EPp1 is formed between each stacked structure LM. Then, as shown in Figure 6, an insulating film IF2 is formed on the semiconductor layer EPp1, and a semiconductor layer EPn1 is formed on the insulating film IF2 between each stacked structure LM. Therefore, semiconductor layers EPp1 and EPn1 are electrically isolated. The insulating film IF2 is, for example, a silicon oxide film.

[0032] The detailed cross-sectional structures of MOSFETs 1Q and 2Q will be explained using Figure 6. As shown in Figure 6, a gate insulating film GI is formed between the multiple channel layers CHn and the gate electrode GE. The gate insulating film GI is, for example, a silicon oxide film or a high-dielectric-constant film having a higher dielectric constant than the silicon oxide film, or a laminated film of a silicon oxide film and a high-dielectric-constant film. Examples of high-dielectric-constant films include hafnium oxide film, hafnium silicate film, aluminum oxide film, and hafnium aluminate film.

[0033] The gate electrode GE is, for example, a metal film consisting of a tantalum nitride film, a titanium-aluminum film, a titanium nitride film, a tungsten film, or an aluminum film, or a laminated film formed by appropriately stacking these metal films.

[0034] A sidewall spacer SW1 is formed between the multiple channel layers CHn, specifically between the gate electrode GE and the semiconductor layer EPp1. The sidewall spacer SW1 is made of an insulating film, such as a silicon nitride film. Therefore, the gate electrode GE and the semiconductor layer EPp1 are electrically isolated. When forming the semiconductor layer EPp1 by epitaxial growth, the silicon layer grows starting from the edges of the multiple channel layers CHn exposed from the sidewall spacer SW1. The thickness of the semiconductor layer EPp1 is, for example, 80 nm or more and 120 nm or less.

[0035] Furthermore, an element isolation section STI is formed in the semiconductor substrate SUB. The element isolation section STI consists of a groove formed in the semiconductor substrate SUB and an insulating film embedded in the groove. As shown in Figure 4, the semiconductor layer EPp1 and the gate electrode GE are formed on the element isolation section STI. Therefore, the semiconductor layer EPp1 and the gate electrode GE are electrically isolated from the semiconductor substrate SUB.

[0036] Of the multiple channel layers CHn, an insulating film IF1 is formed on the uppermost channel layer CHn. The insulating film IF1 is made of an insulating film such as a silicon oxide film. Multiple channel layers CHp are formed on the insulating film IF1.

[0037] A gate insulating film GI is formed between multiple channel layers CHp and the gate electrode GE. A sidewall spacer SW1 is formed between the multiple channel layers CHp, and between the gate electrode GE and the semiconductor layer EPn1. Therefore, the gate electrode GE and the semiconductor layer EPn1 are electrically isolated. When forming the semiconductor layer EPn1 by epitaxial growth, the silicon layer grows starting from the edges of the multiple channel layers CHp exposed from the sidewall spacer SW1. The thickness of the semiconductor layer EPn1 is, for example, 80 nm or more and 120 nm or less.

[0038] Furthermore, a sidewall spacer SW2 is formed on the side surface of the gate electrode GE, which is formed on the uppermost channel layer CHp among the multiple channel layers CHp, via a gate insulating film GI. The sidewall spacer SW1 is made of an insulating film such as a silicon nitride film.

[0039] Because the height of the stacked structure LM is high and the aspect ratio is high, it is difficult to form normal semiconductor layers EPp1 and EPn1 between each stacked structure LM. As a result, defective semiconductor layers EPp2 and EPn2 may be formed, as shown in Figures 5 and 6.

[0040] The defects described herein include forms such as excessive growth of semiconductor layers EPp2 and EPn2, failure to grow to the desired thickness, formation of voids within semiconductor layers EPp2 and EPn2, and failure of semiconductor layers EPp2 and EPn2 to connect to the respective channel layers CHn and CHp of the adjacent stacked structure LM.

[0041] <Inspection of Semiconductor Layers> In Embodiment 1, the inspection target of the inspection performed using the inspection system 1 is a plurality of semiconductor layers EP. It is determined whether the plurality of semiconductor layers EP are normal semiconductor layers EPp1 and EPn1 without defects, or semiconductor layers EPp2 and EPn2 that have defects. Here, the semiconductor layers EPp1 and EPp2 shown in Figure 6 are used as the plurality of semiconductor layers EP, but the same inspection can be performed on semiconductor layers EPn1 and EPn2.

[0042] Figure 7 shows the state of electrons being scattered when an electron beam EB1 having different energies is irradiated onto a semiconductor layer EP. Here, the direction from perpendicular to the surface of the semiconductor substrate SUB (0 deg) to parallel to the surface of the semiconductor substrate SUB (90 deg) is shown. The "high angle" mentioned later means the range of 0 deg to 30 deg.

[0043] When an electron beam EB1 having an energy of 500 eV is irradiated, the electrons are scattered within a range of about 10 nm from the surface of the semiconductor layer EP. Among the scattered electrons, the high-angle backscattered electrons EB2 are emitted from the space surrounded by the stacked structure LM.

[0044] When an electron beam EB1 having an energy of 2 keV is irradiated, the electrons penetrate into the semiconductor layer EP or stay inside the stacked structure LM. The electrons are scattered within a range of about 50 nm from the surface of the semiconductor layer EP. Among the scattered electrons, the high-angle backscattered electrons EB2 are emitted from the space surrounded by the stacked structure LM.

[0045] When an electron beam EB1 having an energy of 10 keV is irradiated, the electrons pass through the semiconductor layer EP, are scattered inside the semiconductor substrate SUB, and lose energy.

[0046] Figure 8 shows the relationship between the energy of the electron beam EB1 and the contrast measured from the signal of the backscattered electrons EB2 detected by the detector 9. Figure 8 also shows the angle of the backscattered electrons EB2.

[0047] As shown in Figure 8, when the energy of the electron beam EB1 is 2 keV, the contrast is maximized. By obtaining a higher contrast, high-precision image data can be acquired. For example, when the energy of the electron beam EB1 is 1.0 keV or more and 3.5 keV or less, a high contrast can be obtained. Also, when the emission angle of the backscattered electrons EB2 is 0 deg or more and 30 deg or less, a high contrast can be obtained.

[0048] Figure 9 shows the acquisition flow of image data. First, in steps S1 to S4, after calculating the correspondence information of contrast and luminance using a reference sample, in steps S5 to S8, the image data of the inspection target is acquired. The reference sample is an arbitrary semiconductor wafer.

[0049] In step S1, an electron beam EB1 under predetermined conditions is irradiated onto a plurality of semiconductor layers EP in the reference sample. As the predetermined conditions, the energy of the electron beam EB1 is set to, for example, 1.0 keV or more and 3.5 keV or less. In step S2, the backscattered electrons EB2 emitted from the plurality of semiconductor layers EP are detected as signals. In step S3, the contrast and luminance of each of the plurality of semiconductor layers EP are measured from the detected signals. In step S4, the measured correspondence information of contrast and luminance is stored in the memory storage unit 19.

[0050] In step S5, an electron beam EB1 under the same conditions as in step S1 is irradiated onto a plurality of semiconductor layers EP that are the inspection target. In step S6, the backscattered electrons EB2 emitted from the plurality of semiconductor layers EP are detected as signals.

[0051] In step S7, first, the contrast and luminance of each of the plurality of semiconductor layers EP are measured from the detected signals. Next, as shown in FIG. 10, the brightest semiconductor layer 104 and the darkest semiconductor layer 105 on the image are selected. Histogram 106 shows the luminance distribution of semiconductor layer 104, and histogram 107 shows the luminance distribution of semiconductor layer 105.

[0052] Here, the contrast is set and the luminance is corrected so that the luminance does not saturate. That is, the contrast is adjusted so that the maximum luminance and the minimum luminance of the plurality of semiconductor layers EP can be measured. For example, by operating the adjustment unit 103 on the GUI screen 101 so that the maximum luminance on histogram 106 does not exceed "255" and the minimum luminance on histogram 107 does not fall below "0", a contrast adjustment value 102 is obtained.

[0053] In step S8, image data corresponding to the multiple semiconductor layer EPs is acquired with the brightness of each of the multiple semiconductor layer EPs corrected based on the contrast adjustment value 102 and the correspondence information between contrast and brightness defined in step S4.

[0054] Figure 11 shows the defect detection flow. First, in step S11, similar to steps S4 to S8 in Figure 9, when the electron beam EB1 is irradiated onto multiple semiconductor layers EP, the contrast and brightness of each of the multiple semiconductor layers EP are measured, and image data including the multiple semiconductor layers EP is acquired. As shown in Figure 12, the image data includes a semiconductor layer 108 without defects and a semiconductor layer 109 with defects. There are various variations in semiconductor layers 108 and 109.

[0055] In step S12, the dimensions and area of ​​each of the multiple semiconductor layer EPs are measured. In step S13, statistical data is obtained by calculating the luminance of each of the multiple semiconductor layer EPs. The statistical data includes at least the average luminance, the 3σ of luminance, or the luminance histogram.

[0056] In step S14, as shown in Figure 13, the type of data for which a threshold should be set is selected by selecting checkbox 111 on GUI screen 110. Additionally, the lower threshold limit 113 and the upper threshold limit 114 are set on GUI screen 112. These thresholds are then applied to the statistical data.

[0057] In step S15, the presence or absence of defects is determined for multiple semiconductor layer EPs based on the deviation in brightness of each of the multiple semiconductor layer EPs from statistical data. Specifically, the presence or absence of defects is determined for multiple semiconductor layer EPs based on thresholds set in the statistical data.

[0058] In step S16, defect information for multiple semiconductor layer EPs is output. Steps S11 to S15 can also be used to determine the presence or absence of defects for all semiconductor layer EPs within a single chip region, and for all chip regions within a semiconductor wafer. For example, as shown in Figure 14, the defect density within each chip region 116 within the semiconductor wafer can be extracted and displayed on the GUI screen 115 to create a defect density distribution within the semiconductor wafer.

[0059] As described above, according to Embodiment 1, semiconductor layers EP formed between each stacked structure LM can be inspected in-line on a semiconductor wafer during manufacturing without damaging semiconductor devices such as CFETs.

[0060] In Embodiment 1, the inspection target shown using the inspection system 1 was a plurality of semiconductor layers EP contained in a CFET, but the inspection target may also be a plurality of semiconductor layers EP contained in a GAAFET. In the case of a GAAFET, MOSFET 1Q and MOSFET 2Q are not stacked but are arranged adjacent to each other in a plan view.

[0061] (Embodiment 2) The inspection system 1 in Embodiment 2 will be described below with reference to Figures 15 to 18. In the following description, the differences from Embodiment 1 will be mainly explained, and points that overlap with Embodiment 1 will not be explained.

[0062] In Embodiment 2, a learning model 206 created by artificial intelligence is used to determine whether or not defects are present in multiple semiconductor layer EPs. Figure 15 shows a flowchart for creating the learning model 206 using machine learning.

[0063] First, in step S21, similar to steps S4 to S8 in Figure 9, when the electron beam EB1 is irradiated onto the multiple semiconductor layers, the contrast and brightness of each of the multiple semiconductor layers are measured, and image data including the multiple semiconductor layers is acquired. As shown in Figure 16, the image data includes the defect-free semiconductor layer 201 and the defective semiconductor layers 202, 203, and 204.

[0064] In step S22, the dimensions and area of ​​each of the multiple semiconductor layers 201, 202, 203, and 204 are measured. In step S23, statistical data is obtained by calculating the brightness of each of the multiple semiconductor layers 201, 202, 203, and 204. The statistical data includes at least the average brightness, the 3σ of brightness, or the brightness histogram. In Embodiment 2, the obtained statistical data is used as feature quantities for each of the multiple semiconductor layers 201, 202, 203, and 204.

[0065] Furthermore, cross-sectional observations are performed on multiple semiconductor layers 201, 202, 203, and 204 using a TEM device, and cross-sectional image data is acquired to confirm whether or not defects exist in the multiple semiconductor layers 201, 202, 203, and 204. This information regarding the presence or absence of defects is linked to the image data in Figure 16.

[0066] In step S24, information regarding the presence or absence of defects is labeled to the feature quantities of each of the multiple semiconductor layers 201, 202, 203, and 204. As shown in the datasheet in Figure 16, for each of the multiple semiconductor layers 201, 202, 203, and 204, the presence or absence of defects is linked in the label 205a column, and the feature quantities of each of the multiple semiconductor layers 201, 202, 203, and 204 are linked in the feature quantity 205b column.

[0067] In step S25, machine learning is performed using a datasheet like the one shown in Figure 16 to train the learning model 206.

[0068] In step S26, it is determined whether the defect detection accuracy of the learning model 206 is sufficient. For example, if the detection accuracy is 90% or higher, it is determined that the machine learning of the learning model 206 is sufficient. If the detection accuracy is low, the number of samples, such as multiple semiconductor layers 201, 202, 203, and 204, is increased, and the learning model 206 is further trained.

[0069] In step S27, the learning model 206, which is deemed to have sufficient judgment accuracy, is stored in the memory storage unit 19. In this way, the computer system 16 is equipped with a learning model 206 that has learned the relationship between the feature quantities of each of the multiple semiconductor layers and the presence or absence of defects.

[0070] Figure 17 shows the defect detection flow using the learning model 206. First, in step S31, when the electron beam EB1 is irradiated onto multiple semiconductor layers, the contrast and brightness of each of the multiple semiconductor layers are measured, and image data including the multiple semiconductor layers is acquired.

[0071] As shown in Figure 18, in step S32, the feature quantities of each of the multiple semiconductor layers are acquired. In step S33, the acquired feature quantities are input to the learning model 206 to determine whether or not defects are present in the multiple semiconductor layers. The learning model 206 is the trained model saved in step S27 described above. Therefore, in step S34, defect information for the multiple semiconductor layers is automatically output from the learning model 206.

[0072] As described above, in Embodiment 2, as in Embodiment 1, the semiconductor layer EP formed between each stacked structure LM can be inspected in-line on the semiconductor wafer during manufacturing without damaging semiconductor devices such as CFETs.

[0073] (Modified Version) The inspection system 1 in a modified version of Embodiment 2 will be described below with reference to Figures 19 to 21. Figure 19 shows a flowchart for creating a learning model 206 using a neural network.

[0074] First, as shown in Figure 20, in step S41, when the electron beam EB1 is irradiated onto the multiple semiconductor layers, the contrast and brightness of each of the multiple semiconductor layers are measured, and image data 209 including the multiple semiconductor layers is acquired.

[0075] In step S42, each region of multiple semiconductor layers is selectively extracted from the image data 209 as multiple extracted image data 210. The extracted image data 210 are, for example, image data of semiconductor layer 201, semiconductor layer 202, semiconductor layer 203, or semiconductor layer 204 shown in Figure 16.

[0076] If it is difficult to acquire cross-sectional image data using a TEM device, and if manual labeling is costly, classification is possible based on the differences and similarities of the features of the image data 210, even without training data. In step S43, the features of multiple extracted image data 210 are acquired, and the features of the multiple extracted image data 210 are used to train the learning model 206 using a neural network.

[0077] In the simplest case, it outputs two classes (Normal, Defect type). If you want to further differentiate the defect types, it is possible to have more than two classes (Normal, Defect type 1, Defect type 2), as shown in judgment result 213. For example, if the neural network outputs a vector of output values ​​(0.96, 0.03, 0.01), the first component of the vector will be the highest value, so the class referred to in this example will be "Normal".

[0078] In step S44, it is determined whether the defect detection accuracy of the learning model 206 is sufficient. In step S45, the learning model 206 that has been determined to have sufficient detection accuracy is stored in the memory storage unit 19.

[0079] Figure 21 shows how the presence or absence of defects is determined using a modified learning model 206. First, when the electron beam EB1 is irradiated onto multiple semiconductor layers, the contrast and brightness of each of the multiple semiconductor layers are measured, and image data 211 including the multiple semiconductor layers is acquired.

[0080] Next, each region of multiple semiconductor layers is selectively extracted from the image data 211 as multiple extracted image data 212. Feature quantities are obtained from the multiple extracted image data 212, and these obtained feature quantities are input to the learning model 206 to determine whether defects are present in the multiple semiconductor layers. Defect information for the semiconductor layers is automatically output from the learning model 206 as the determination result 213.

[0081] Furthermore, the accuracy 214 for determining the presence or absence of defects in the semiconductor layer can also be displayed in the judgment result 213. In the example in Figure 21, the semiconductor layer corresponding to a certain extracted image data 212 is determined to be defect-free with a probability of 96%. It is also possible to display the accuracy 214 for each type of defect in the semiconductor layer.

[0082] Although the present invention has been specifically described above based on the embodiments described above, the present invention is not limited to the embodiments described above and can be modified in various ways without departing from the spirit of the invention.

[0083] 1. Inspection system 2. Electron gun 3, 4. Focusing lenses 5. Deflector 6. Objective lens 7. Sample 8. Stage 9. Detector 10. Electron beam control system 11. Image generation system 12. Signal conversion unit 13. Contrast adjustment unit 14. Brightness calculation unit 15. Image generation unit 16. Computer system 17. Data calculation unit 18. Image processor 19. Memory storage unit 20. Input / output device 21. Deflector 30. Other computer systems 101. GUI screen for adjusting contrast 102. Contrast adjustment value 103. Adjustment unit 104. Brightest semiconductor layer 105. Darkest semiconductor layer 106, 107. Histogram 108. Normal semiconductor layer 109. Defective semiconductor layer 110. GUI screen for setting data type (feature) 111. Checkbox 112. GUI screen for setting threshold for data type (feature) 113 Lower threshold limit 114 Upper threshold limit 115 GUI screen for displaying defect density for each chip region 116 Chip region 201 Normal semiconductor layer 202, 203, 204 Semiconductor layer with defects 205a Label (presence or absence of defects) 205b Feature quantity 206 Learning model 207 Feature quantity 208 Judgment result 209 Image data 210 Extracted image data 211 Image data 212 Extracted image data 213 Judgment result 1Q p-type MOSFET 2Q n-type MOSFET CHn n-type channel layer CHp p-type channel layer EB1 Electron beam EB2 Backscattered electrons EP Semiconductor layer EPn1 n-type semiconductor layer EPn2 n-type semiconductor layer with defects EPp1 p-type semiconductor layer EPp2 p-type semiconductor layer with defects GE Guard gate GI Gate insulating film LM: Stacked structure; STI: Element isolation section; SUB: Semiconductor substrate; SW1, SW2: Sidewall spacers

Claims

1. An inspection system comprising a computer system that performs an inspection of an object to be inspected using image data obtained by irradiating the object to be inspected with an electron beam, wherein the object to be inspected is a plurality of semiconductor layers formed between a plurality of stacked structures, each of the plurality of stacked structures having: a plurality of channel layers stacked apart from each other on a semiconductor substrate, and a gate electrode formed on the semiconductor substrate so as to surround the plurality of channel layers via a plurality of gate insulating films, wherein in one of the stacked structures, if the semiconductor layer connected to one end of the plurality of channel layers constitutes a source region, the semiconductor layer connected to the other end of the plurality of channel layers constitutes a drain region, and the computer system measures the brightness of each of the plurality of semiconductor layers when the electron beam is irradiated onto the plurality of semiconductor layers, acquires first image data including the plurality of semiconductor layers, acquires statistical data by calculating the brightness of each of the plurality of semiconductor layers, and determines whether or not there are defects in the plurality of semiconductor layers based on the deviation of the brightness of each of the plurality of semiconductor layers from the statistical data.

2. An inspection system according to claim 1, wherein the statistical data includes at least an average value of luminance, 3σ of luminance, or a histogram of luminance.

3. An inspection system according to claim 2, wherein the computer system determines whether or not defects are present in the plurality of semiconductor layers based on thresholds set in the statistical data.

4. An inspection system according to claim 1, comprising: an electron gun capable of irradiating an electron beam; and a detector capable of detecting backscattered electrons emitted from an object to be inspected as a signal when the electron beam is irradiated onto the object to be inspected, wherein the computer system is capable of measuring the contrast and brightness of the object to be inspected based on the detected signal, and is capable of generating image data of the object to be inspected.

5. An inspection system according to claim 4, wherein the electron beam irradiated onto the plurality of semiconductor layers has energy to penetrate into the interior of each of the plurality of semiconductor layers, and the backscattered electrons are emitted from between the plurality of stacked structures.

6. An inspection system according to claim 5, wherein the electron beam irradiated onto the plurality of semiconductor layers has an energy such that it remains inside the plurality of stacked structures.

7. An inspection system according to claim 4, wherein the electron beam irradiated onto the plurality of semiconductor layers has an energy of 1.0 keV or more and 3.5 keV or less.

8. An inspection system according to claim 1, wherein the first image data is acquired in a state in which the brightness of each of the plurality of semiconductor layers is corrected based on a contrast adjustment value adjusted to measure the maximum brightness and minimum brightness of the plurality of semiconductor layers and predetermined correspondence information between contrast and brightness.

9. An inspection system according to claim 1, wherein each of the plurality of semiconductor layers is formed by an epitaxial growth method.

10. An inspection system according to claim 1, wherein when n-type impurities are introduced into the plurality of channel layers, p-type impurities are introduced into the plurality of semiconductor layers, and when p-type impurities are introduced into the plurality of channel layers, n-type impurities are introduced into the plurality of semiconductor layers.

11. An inspection system according to claim 10, wherein the plurality of stacked structures and the plurality of semiconductor layers constitute a CFET or a GAAFET.

12. An inspection system comprising a computer system that performs an inspection of an object to be inspected using image data obtained by irradiating the object to be inspected with an electron beam, wherein the object to be inspected is a plurality of semiconductor layers formed between a plurality of stacked structures, each of the plurality of stacked structures having: a plurality of channel layers stacked apart from each other on a semiconductor substrate, and a gate electrode formed on the semiconductor substrate so as to surround the plurality of channel layers via a plurality of gate insulating films, wherein in one of the stacked structures, the semiconductor layer connected to one end of the plurality of channel layers constitutes a source region, and the semiconductor layer connected to the other end of the plurality of channel layers constitutes a drain region, the computer system comprises a learning model that has learned the relationship between the feature quantities of each of the plurality of semiconductor layers and the presence or absence of defects, and the computer system acquires the feature quantities of each of the plurality of semiconductor layers when the electron beam is irradiated onto the plurality of semiconductor layers, and inputs the acquired feature quantities into the learning model to determine whether or not there are defects in the plurality of semiconductor layers.

13. An inspection system according to claim 12, wherein, when causing the learning model to learn the feature quantities of each of the plurality of semiconductor layers, the computer system acquires first image data including the plurality of semiconductor layers, selectively extracts each of the regions of the plurality of semiconductor layers from the first image data as a plurality of extracted image data, and causes the learning model to learn the feature quantities of the plurality of extracted image data by a neural network.

14. An inspection system according to claim 12, comprising: an electron gun capable of irradiating an electron beam; and a detector capable of detecting backscattered electrons emitted from an object to be inspected as a signal when the electron beam is irradiated onto the object to be inspected, wherein the computer system is capable of measuring the contrast and brightness of the object to be inspected based on the detected signal, and is capable of generating image data of the object to be inspected.

15. An inspection system according to claim 14, wherein the electron beam irradiated onto the plurality of semiconductor layers has energy to penetrate into the interior of each of the plurality of semiconductor layers, and the backscattered electrons are emitted from between the plurality of stacked structures.

16. An inspection system according to claim 15, wherein the electron beam irradiated onto the plurality of semiconductor layers has an energy such that it remains inside the plurality of stacked structures.

17. An inspection system according to claim 14, wherein the electron beam irradiated onto the plurality of semiconductor layers has an energy of 1.0 keV or more and 3.5 keV or less.

18. An inspection system according to claim 12, wherein each of the plurality of semiconductor layers is formed by an epitaxial growth method.

19. An inspection system according to claim 12, wherein when n-type impurities are introduced into the plurality of channel layers, p-type impurities are introduced into the plurality of semiconductor layers, and when p-type impurities are introduced into the plurality of channel layers, n-type impurities are introduced into the plurality of semiconductor layers.

20. An inspection system according to claim 19, wherein the plurality of stacked structures and the plurality of semiconductor layers constitute a CFET or a GAAFET.

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