Transistor and semiconductor device

Abstract

This transistor comprises: a first electrode; a second electrode; a third electrode positioned between the first electrode and the second electrode; a first insulating film positioned between the first electrode and the third electrode, and / or between the second electrode and the third electrode; and a crystal oxide semiconductor that penetrates at least the first insulating film and connects the first electrode and the second electrode. The crystal oxide semiconductor includes a first region that neighbors the third electrode without contacting the same, and a second region that neighbors the first insulating film with or without contacting the same, and the average carrier concentration in the second region is relatively higher in comparison with the first region.

Description

Transistors and semiconductor devices

[0001] This invention relates to transistors and semiconductor devices. Specifically, this invention relates to transistors and semiconductor devices that can improve contact resistance.

[0002] Transistors using an amorphous oxide semiconductor layer, such as indium gallium zinc oxide (IGZO), as the channel are known (Patent Documents 1 and 2). When such an oxide semiconductor layer is used as the channel, a high-resistance metal oxide layer may form between the oxide semiconductor layer and the metal electrode, increasing the contact resistance between the oxide semiconductor layer and the metal electrode. To suppress the increase in contact resistance, Patent Documents 1 and 2 propose interposing a specific oxide layer between the oxide semiconductor layer and the metal electrode.

[0003] Japanese Patent Publication No. 2017-168623 Japanese Patent Publication No. 2019-134077

[0004] However, conventional technologies, including those described in Patent Documents 1 and 2, had room for further improvement in terms of improving contact resistance in transistors.

[0005] One of the objectives of the present invention is to provide transistors and semiconductor devices that can improve contact resistance.

[0006] As a result of diligent research, the inventors have found that the above problems can be solved by using a crystalline oxide semiconductor as the oxide semiconductor and selectively increasing the average carrier concentration in regions that tend to cause contact resistance within the oxide semiconductor, and have completed the present invention. According to the present invention, the following transistors and the like can be provided. 1. A transistor comprising: a first electrode; a second electrode; a third electrode located between the first electrode and the second electrode; a first insulating film located between the first electrode and the third electrode and / or between the second electrode and the third electrode; and a crystalline oxide semiconductor that penetrates at least the first insulating film and connects the first electrode and the second electrode, wherein the crystalline oxide semiconductor includes a first region adjacent to the third electrode without contact and a second region adjacent to the first insulating film with or without contact, and the average carrier concentration in the second region is relatively higher than that in the first region. 2. 1. The transistor according to claim 1, wherein the crystalline oxide semiconductor is provided in a columnar shape penetrating the first insulating film and the third electrode, the first region is the region in the crystalline oxide semiconductor penetrating the third electrode, and the second region is the region in the crystalline oxide semiconductor penetrating the first insulating film. 3. The transistor according to claim 1, wherein the first electrode, the first insulating film, the third electrode, the first insulating film, and the second electrode are stacked in this order, the crystalline oxide semiconductor is provided in a columnar shape penetrating the first insulating film and the third electrode, the first region is the region in the crystalline oxide semiconductor penetrating the third electrode, and the second region is the region in the crystalline oxide semiconductor penetrating the first insulating film. 4. The transistor according to claim 2 or 3, wherein the length in the height direction of the columnar crystalline oxide semiconductor is 2 to 1000 nm. 5. The transistor according to any one of claims 2 to 4, wherein in the columnar crystalline oxide semiconductor, the ratio of the height of the first region to the height of the second region is 10:1 to 1:1. 6. A transistor according to any one of 1 to 5, wherein the composition ratio of the metal elements constituting the crystalline oxide semiconductor is substantially the same in the first region and the second region.7. The transistor according to 6, wherein the first region includes a highly crystallized region having a relatively higher degree of crystallinity compared to the crystalline oxide semiconductor of the second region. 8. The transistor according to 7, wherein, in each FFT pattern obtained by fast Fourier transforming images obtained by irradiating the same area of ​​the first and second regions with an electron beam, the variation X of the FFT pattern calculated by the following formula is greater in the second region than in the first region: X = [Σ(luminance - average value of luminance in the FFT region)]. ２] / number of samples (wherein the above formula, the FFT region is the region of the FFT pattern obtained by fast Fourier transforming the image, the brightness is the brightness of each spot in the FFT region, and the number of samples is the number of electron beam irradiations to obtain the image.) 9. The transistor according to 8, wherein the crystal orientation in the electron diffraction pattern obtained by irradiating the crystalline oxide semiconductor with an electron beam includes a cubic crystal structure of indium oxide and is composed of at least one of the (211), (222), (400), (440), and (622) planes. 10. The transistor according to any one of 1 to 9, wherein the average hydrogen concentration in the second region is relatively higher than that in the first region. 11. A transistor according to any one of 1 to 10, wherein at least one of the first electrode and the second electrode is selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), aluminum (Al), silicon (Si), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), germanium (Ge), molybdenum (Mo), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), tantalum (Ta), iridium (Ir), platinum (Pt), tungsten (W), titanium (Ti), titanium nitride (TiN), aluminum nitride (AlN), manganese nitride (MnN), molybdenum nitride (MoN), and nickel nitride (Ni3N). 12. A transistor according to any one of 1 to 10, wherein at least one of the first electrode and the second electrode is at least one selected from the group consisting of iron (Fe), cobalt (Co), nickel (Ni), palladium (Pd), titanium (Ti), and titanium nitride (TiN). 13. A transistor according to any one of 1 to 12, further comprising a second insulating film provided between the third electrode and the crystalline oxide semiconductor. 14. The ratio of the average carrier concentration of the second region to the average carrier concentration of the first region (average carrier concentration of the second region / average carrier concentration of the first region) is 2 to 10. ４The transistor according to any one of 1 to 13. 15. The ratio of the average carrier concentration of the second region to the average carrier concentration of the first region (average carrier concentration of the second region / average carrier concentration of the first region) is 10 to 10 ４ The transistor according to 14. 16. The average carrier concentration in the first region is 10 １４ to 10 １８ cm －３ and the average carrier concentration in the second region is 10 １７ to 10 ２２ cm －３ The transistor according to any one of 1 to 15. 17. The ratio of the average hydrogen concentration of the second region to the average hydrogen concentration of the first region (average hydrogen concentration of the second region / average hydrogen concentration of the first region) is 5 to 5×10 ３18. A transistor according to any one of 1 to 17, wherein the crystalline oxide semiconductor includes a bixbyte crystal structure. 19. A transistor according to any one of 1 to 18, wherein the crystalline oxide semiconductor mainly contains indium oxide. 20. A transistor according to any one of 1 to 19, wherein the crystalline oxide semiconductor includes Ga or Al. 21. A transistor according to any one of 1 to 19, wherein the crystalline oxide semiconductor includes Ga. 22. A transistor according to any one of 1 to 19, wherein the crystalline oxide semiconductor includes Ga and Al. 23. A transistor according to any one of 1 to 22, wherein the crystalline oxide semiconductor is a polycrystalline oxide semiconductor. 24. A transistor according to any one of 1 to 22, wherein the crystalline oxide semiconductor is a single-crystal oxide semiconductor. 25. A transistor according to any one of 1 to 24, wherein the crystalline oxide semiconductor is a crystalline oxide semiconductor formed by atomic layer deposition. 26. A semiconductor device including a transistor according to any one of 1 to 25. 27. A semiconductor device according to 26, which is a semiconductor memory device.28. A device comprising: a first electrode; a second electrode; a third electrode located between the first electrode and the second electrode; a first insulating film located between the first electrode and the third electrode and / or between the second electrode and the third electrode; and a crystalline oxide semiconductor that penetrates at least the first insulating film and connects the first electrode and the second electrode, wherein the crystalline oxide semiconductor includes a bixbyte crystal structure, the crystalline oxide semiconductor includes a first region adjacent to the third electrode without contact, and a second region adjacent to the first insulating film with or without contact, the average carrier concentration in the second region is relatively higher than that in the first region, the composition ratio of the metal elements constituting the crystalline oxide semiconductor is substantially the same in the first region and the second region, and the first region includes a highly crystallized region with a relatively higher degree of crystallinity compared to the crystalline oxide semiconductor in the second region. In each FFT pattern obtained by irradiating the same area of ​​the first and second regions with an electron beam and performing a fast Fourier transform on the resulting image, the variation X of the FFT pattern calculated by the following formula is greater in the second region than in the first region: X = 1 / number of samples × Σ (luminance - average luminance in the FFT region). ２(However, in the above formula, the FFT region is the region of the FFT pattern obtained by performing a fast Fourier transform on the image, the brightness is the brightness of each spot in the FFT region, and the sampling number is the number of electron beam irradiations performed to obtain the image.) Transistor. 29. A transistor comprising: a first electrode; a second electrode; a third electrode located between the first electrode and the second electrode; a first insulating film located between the first electrode and the third electrode and / or between the second electrode and the third electrode; and a crystalline oxide semiconductor that penetrates at least the first insulating film and connects the first electrode and the second electrode, wherein the crystalline oxide semiconductor includes a bixbyte crystal structure, the crystalline oxide semiconductor includes a first region adjacent to the third electrode without contact, and a second region adjacent to the first insulating film with or without contact, the average carrier concentration in the second region being relatively higher than that in the first region, the average hydrogen concentration in the second region being relatively higher than that in the first region, and at least one of the first electrode and the second electrode being at least one selected from the group consisting of iron (Fe), cobalt (Co), nickel (Ni), palladium (Pd), titanium (Ti), and titanium nitride (TiN).

[0007] According to the present invention, it is possible to provide transistors and semiconductor devices that can improve contact resistance.

[0008] This is a schematic perspective view showing a cross-section of a transistor according to the first embodiment. This is a schematic cross-sectional view of a transistor according to the first embodiment. This is a diagram illustrating an example of a method for manufacturing a transistor according to the first embodiment. This is a diagram showing an example of a circuit configuration of a semiconductor memory device.

[0009] The transistors and semiconductor devices of the present invention will be described in detail below. In this specification, "x to y" represents a numerical range of "x or more, and y or less". The upper and lower limits described for the numerical range can be combined in any way. Furthermore, it is possible to combine two or more non-conflicting embodiments of the embodiments of the present invention described below, and an embodiment that combines two or more embodiments is also an embodiment of the embodiments of the present invention.

[0010] 1. Transistor A transistor according to one aspect of the present invention comprises: a first electrode; a second electrode; a third electrode located between the first electrode and the second electrode; a first insulating film located between the first electrode and the third electrode and / or between the second electrode and the third electrode; and a crystalline oxide semiconductor that penetrates at least the first insulating film and connects the first electrode and the second electrode, wherein the crystalline oxide semiconductor includes a first region adjacent to the third electrode without contact and a second region adjacent to the first insulating film with or without contact, and the average carrier concentration in the second region is relatively higher than that in the first region. The transistor according to this aspect provides the effect of improving contact resistance. In the crystalline oxide semiconductor, the second region is further away from the third electrode, which functions as a gate electrode, than from the first region. Therefore, even when a gate voltage is applied to the third electrode, carriers are inherently less likely to be induced in the second region, making it prone to contact resistance. However, as mentioned above, the higher average carrier concentration in the second region compared to the first region prevents high contact resistance in the second region, thereby improving the contact resistance of the transistor. During transistor manufacturing, by utilizing the properties of crystalline oxide semiconductors (the property of crystallization), post-annealing can be performed under specific conditions, or the average hydrogen concentration in the second region can be relatively increased, thereby increasing the average carrier concentration in the second region compared to the first region and maintaining that state. In comparison, if an amorphous oxide semiconductor such as IGZO is used as the semiconductor, the semiconductor is not crystalline, so it is presumed that the above-mentioned average carrier concentration condition cannot be met, and the above-mentioned improvement in contact resistance will not occur.

[0011] An example of a transistor according to this embodiment (first embodiment) will be described below with reference to Figures 1 and 2. Figure 1 is a schematic perspective view showing a cross-section of the transistor according to the first embodiment. Figure 2 is a schematic cross-sectional view of the transistor. In this embodiment, the transistor 10 includes a first electrode 11, a second electrode 12, a third electrode 13, first insulating films 14a and 14b, and a crystalline oxide semiconductor 15. The third electrode 13 is located between the first electrode 11 and the second electrode 12.

[0012] Of the first insulating films 14a and 14b, one first insulating film 14a is located between the first electrode 11 and the third electrode 13. As a result, the first electrode 11 and the third electrode 13 are electrically insulated by the first insulating film 14a. The other first insulating film 14b is located between the second electrode 12 and the third electrode 13. As a result, the second electrode 12 and the third electrode 13 are electrically insulated by the first insulating film 14b.

[0013] In the region shown in Figure 2, the third electrode 13 is positioned between the first insulating film 14a and the first insulating film 14b. However, outside the region shown in Figure 2, the first insulating film 14a and the first insulating film 14b may be in contact with each other, forming a single layer. In this case, the third electrode 13 does not need to be positioned between the first insulating film 14a and the first insulating film 14b in that region.

[0014] The crystalline oxide semiconductor 15 penetrates at least the first insulating films 14a and 14b and is provided to connect the first electrode 11 and the second electrode 12. In addition to the first insulating films 14a and 14b, the crystalline oxide semiconductor 15 may also penetrate the third electrode 13. Here, the crystalline oxide semiconductor 15 is provided in a columnar shape, penetrating the first insulating film 14a, the third electrode 13, and the first insulating film 14b in this order. In this case, it is preferable that the third electrode 13 surrounds the entire circumference of the crystalline oxide semiconductor 15 (around the periphery in the direction perpendicular to the length direction) in a portion of the length direction of the crystalline oxide semiconductor 15 (the central portion in the example of Figure 2) via the second insulating film 16 described later. This makes it easier to prevent leakage current even if the channel length of the crystalline oxide semiconductor 15 described later is shortened. At the same time, it is also advantageous in terms of miniaturization. Furthermore, the length direction of the crystalline oxide semiconductor 15 as referred to here may be the vertical direction in Figure 2 (the direction connecting the first electrode and the second electrode), the direction along the channel length described later, the thickness direction of the laminate in which the first insulating film 14a, the third electrode 13, and the first insulating film 14b are stacked in this order, and, if the crystalline oxide semiconductor 15 is columnar, the height direction of the columnar structure.

[0015] The transistor 10 further comprises a second insulating film 16 provided at least between the third electrode 13 and the crystalline oxide semiconductor 15. The second insulating film 16 may be provided between the third electrode 13 and the crystalline oxide semiconductor 15 to insulate them. In addition to being provided between the third electrode 13 and the crystalline oxide semiconductor 15, the second insulating film 16 may also be provided, for example, between the first insulating films 14a, 14b and the crystalline oxide semiconductor 15. Here, the second insulating film 16 is provided so as to surround the entire circumference of the side surface of the columnar crystalline oxide semiconductor 15.

[0016] From one perspective, the transistor 10 can be described as having a laminate in which a first insulating film 14a, a third electrode 13, and the first insulating film 14b are stacked in this order, with a through-hole penetrating the laminate in the thickness direction (up and down direction in Figures 1 and 2), the inner circumferential surface of the through-hole being covered with a cylindrical second insulating film 16, and the inside of the cylindrical second insulating film 16 being filled with a crystalline oxide semiconductor 15.

[0017] The dimensions of the transistor 10 may be designed as appropriate depending on its application. The channel length of the crystalline oxide semiconductor 15 is, for example, 1 nm to 10 μm, preferably 2 to 1000 nm, more preferably 3 to 100 nm, even more preferably 4 to 50 nm, even more preferably 5 to 30 nm, and even more preferably 6 to 20 nm. The channel length of the crystalline oxide semiconductor 15 is the length of the crystalline oxide semiconductor 15 along the thickness direction (vertical direction in Figures 1 and 2) of the laminate in which the first insulating film 14a, the third electrode 13, and the first insulating film 14b are stacked in this order, and may coincide with the distance between the first electrode 11 and the second electrode 12. If the crystalline oxide semiconductor 15 is columnar, the channel length of the crystalline oxide semiconductor 15 corresponds to the height direction of the columnar structure. The channel length of the crystalline oxide semiconductor 15 can be measured by processing the relevant area with a focused ion beam (FIB) to expose it and observing the cross-section with a transmission electron microscope (TEM).

[0018] The channel width of the crystalline oxide semiconductor 15 is, for example, 1 nm to 1000 nm, preferably 2 nm to 500 nm. The channel width of the crystalline oxide semiconductor 15 is the length of the crystalline oxide semiconductor 15 along the direction perpendicular to the thickness direction (for example, the left-right direction in Figure 2) of the laminate in which the first insulating film 14a, the third electrode 13, and the first insulating film 14b are stacked in this order. As shown in Figures 1 and 2, if the channel width of the crystalline oxide semiconductor 15 is not constant with respect to the channel length direction, the channel width of the crystalline oxide semiconductor 15 may be the average width along the channel length direction. The average width along the channel length direction is the average value obtained when the channel width is measured at 10 or more locations along the channel length direction. If the crystalline oxide semiconductor 15 is columnar, the channel width of the crystalline oxide semiconductor 15 corresponds to the width of the columnar structure. Furthermore, if the channel width of the crystalline oxide semiconductor 15 differs depending on the observation direction (for example, if the channel width differs when observed from a direction perpendicular to the plane of Figure 2 and when observed from the left or right direction in Figure 2), the channel width when observed from at least one direction may be within the above range.

[0019] The thickness of the second insulating film 16 is, for example, 1 Å to 500 nm, preferably 1 nm to 100 nm. In order to suppress the capacitance of the second insulating film 16 from becoming a parasitic component, the thickness of the second insulating film 16 may be 50 nm or less, 10 nm or less, or 2 nm or less. The channel width of the crystalline oxide semiconductor 15 and the thickness of the second insulating film 16 can be measured in the same manner as the channel length.

[0020] In transistor 10, the first electrode 11 can function as a source electrode, and the second electrode 12 can function as a drain electrode. In other examples, the first electrode 11 can function as a drain electrode, and the second electrode 12 can function as a source electrode. The third electrode 13 can function as a gate electrode. The crystalline oxide semiconductor 15 can function as a channel (current path) of transistor 10. For example, when a gate voltage is applied to the third electrode 13, which is the gate electrode, the first electrode 11 and the second electrode 12 are electrically connected by the crystalline oxide semiconductor 15, and transistor 10 is in the ON state. When no gate voltage is applied, the electrical connection between the first electrode 11 and the second electrode 12 by the crystalline oxide semiconductor 15 is released, and transistor 10 is in the OFF state.

[0021] Furthermore, in this specification, "electrically connected" includes cases where a connection is made via "something that has some kind of electrical function." Here, "something that has some kind of electrical function" is not particularly limited as long as it enables the exchange of electrical signals between the connected objects.

[0022] In the transistor 10, the crystalline oxide semiconductor 15 is provided to connect the first electrode 11 and the second electrode 12. "Provided to connect the first electrode 11 and the second electrode 12" means that it is provided in a state in which the first electrode 11 and the second electrode 12 can be electrically connected. Therefore, the crystalline oxide semiconductor 15 does not need to be in physical contact with the first electrode 11 and the second electrode 12; for example, a conductive material may be provided between the crystalline oxide semiconductor 15 and the first electrode 11 and / or the second electrode 12.

[0023] The crystalline oxide semiconductor 15 can be any crystalline oxide capable of functioning as a semiconductor. Specifically, metal oxides are examples. Examples of metals contained in metal oxides include In, Ga, Zn, Al, Sn, etc. Specific examples of metal oxides include indium oxide (IO), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium gallium aluminum oxide (IGAO), indium gallium tin zinc oxide (IGTZO), and indium tin zinc oxide (ITZO).

[0024] In one embodiment, the crystalline oxide semiconductor 15 contains indium atoms (In). In one embodiment, the ratio of indium atoms to the total metal atoms contained in the crystalline oxide semiconductor 15 is 80 atomic% or more, 90 atomic% or more, or 95 atomic% or more. The content (atomic ratio) of each metal element in the crystalline oxide semiconductor 15 can be analyzed by TEM-EDS (Energy Dispersive X-ray Spectroscopy) measurement using an electron microscope.

[0025] In one embodiment, the crystalline oxide semiconductor 15 contains indium oxide as its main component. "Containing indium oxide as its main component" means that more than 50% by mass of the material constituting the crystalline oxide semiconductor is indium oxide.

[0026] In one embodiment, the crystalline oxide semiconductor 15 comprises indium oxide (IO), indium gallium oxide (IGO), or indium gallium aluminum oxide (IGAO). In one embodiment, the indium oxide content of the crystalline oxide semiconductor 15 may be 55% by mass or more, 60% by mass or more, 70% by mass or more, 80% by mass or more, 90% by mass or more, 95% by mass or more, 97% by mass or more, 98% by mass or more, or 99% by mass, or 100% by mass.

[0027] In one embodiment, the crystalline oxide semiconductor 15 further contains a trivalent metal. The trivalent metal is preferably Ga and Al, with Ga being more preferred. In one embodiment, the crystalline oxide semiconductor 15 further contains Ga or Al, may contain Ga, may contain Al, or may contain both Ga and Al. In one embodiment, the atomic ratio of the trivalent metal to all metal elements contained in the crystalline oxide semiconductor 15 ([trivalent metal] / ([trivalent metal] + [all metal elements other than the trivalent metal]) × 100) may be 0 to 30 at%, 1 to 25 at%, 2 to 22 at%, or 3 to 20 at%. Here, "trivalent metal" may be read as Ga and Al. In one embodiment, the atomic ratio of Ga to all metal elements contained in the crystalline oxide semiconductor 15 ([Ga] / ([Ga] + [all metal elements other than Ga]) × 100) may be 0 to 30 at%, 1 to 25 at%, 2 to 22 at%, or 3 to 20 at%. In one embodiment, the atomic ratio of Al to all metal elements contained in the crystalline oxide semiconductor 15 ([Al] / ([Al] + [all metal elements other than Al]) × 100) may be 0 to 30 at%, 1 to 25 at%, 2 to 22 at%, or 3 to 20 at%.

[0028] In one embodiment, the crystalline oxide semiconductor 15 further contains one or more additive elements selected from B, Si, Sc, Zn, Ce, Y, Zr, Sn, Sm, Hf, Ta, and Yb. In one embodiment, the atomic ratio of the total amount of additive elements to the total amount of metal elements contained in the crystalline oxide semiconductor 15 ([total amount of additive elements] / ([total amount of additive elements] + [total metal elements other than additive elements]) × 100) is 0 to 10 at%, and may be 0.1 to 8 at%, 0.5 to 5 at%, or 1 to 3 at%.

[0029] In one embodiment, the crystalline oxide semiconductor 15 includes a bixbite crystal structure. The presence or absence of a bixbite structure can be determined based on the X-ray diffraction pattern in X-ray diffraction (XRD) or the electron diffraction spots in electron diffraction. In one embodiment, the crystalline oxide semiconductor 15 has a bixbite crystal structure. ２ O ３ Includes phase.

[0030] In one embodiment, the crystalline oxide semiconductor 15 is a polycrystalline oxide semiconductor or a single-crystal oxide semiconductor. In one embodiment, the crystalline oxide semiconductor 15 is a polycrystalline oxide semiconductor. In one embodiment, the crystalline oxide semiconductor 15 is a single-crystal oxide semiconductor.

[0031] Here, whether a crystalline oxide semiconductor is a polycrystalline oxide semiconductor or a single-crystal oxide semiconductor can be determined, for example, by electron backscatter diffraction (EBSD). If the crystal orientations measured by EBSD are aligned and no grain boundaries are observed, it can be determined to be a single-crystal oxide semiconductor. Conversely, if grain boundaries are observed, it can be determined to be a polycrystalline oxide semiconductor. When the difference in crystal orientation between two adjacent measurement points exceeds 5°, it can be defined that a grain boundary exists between them.

[0032] By making the crystalline oxide semiconductor 15 as described above, for example, the selective increase in the average carrier concentration in the second regions 18a and 18b, which will be described later, is effectively promoted, and the contact resistance of the transistor 10 tends to be further improved.

[0033] Each of the first electrode 11, the second electrode 12, and the third electrode 13 is not particularly limited as long as they are conductors. Examples of conductors include indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), aluminum (Al), silicon (Si), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), germanium (Ge), molybdenum (Mo), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), tantalum (Ta), iridium (Ir), platinum (Pt), tungsten (W), titanium (Ti), titanium nitride (TiN), aluminum nitride (AlN), manganese nitride (MnN), molybdenum nitride (MoN), and nickel nitride (Ni) ３ Examples include N).

[0034] In one embodiment, at least one of the first electrode 11 and the second electrode 12 is selected from the group consisting of iron (Fe), cobalt (Co), nickel (Ni), palladium (Pd), titanium (Ti), and titanium nitride (TiN). Since these materials have the property of absorbing hydrogen, the hydrogen concentration in the second region can be selectively increased by forming at least one of the first electrode 11 and the second electrode 12 using these materials while absorbing hydrogen.

[0035] Each of the first insulating films 14a, 14b and the second insulating film 16 is not particularly limited as long as it contains an insulator or is a film made of an insulator. Examples of insulators include aluminum oxide, magnesium oxide, silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Furthermore, each of the first insulating films 14a, 14b, and the second insulating film 16 may be a laminated film of the above materials. The insulating films may also contain La, N, Zr, etc. The insulators contained in the first insulating films 14a, 14b, and the second insulating film 16 may be the same or different from each other.

[0036] As described above, the transistor of this embodiment has the effect of improving contact resistance. This will be explained below with particular reference to Figure 2.

[0037] As shown by the dotted line in Figure 2, the crystalline oxide semiconductor 15 includes a first region 17 that is adjacent to (proximally adjacent to) the third electrode 13 without contact, and second regions 18a and 18b that are adjacent to (proximally adjacent to) the two first insulating films 14a and 14b, respectively, without contact. In this example, the first region 17 can also be said to be a region defined in correspondence with the formation range of the third electrode 13 in the thickness direction (vertical direction in Figure 2). The second regions 18a and 18b can also be said to be regions defined in correspondence with the formation range of the two first insulating films 14a and 14b, respectively, in the thickness direction (vertical direction in Figure 2). In this example, the first region 17 is adjacent to the third electrode 13 via the second insulating film 16. The second regions 18a and 18b are adjacent to the first insulating films 14a and 14b, respectively, via the second insulating film 16. From a certain perspective, the first region 17 of the crystalline oxide semiconductor 15 is closer to the third electrode 13 than the second regions 18a and 18b. Also, the second region 18a of the crystalline oxide semiconductor 15 is closer to the first insulating film 14a than the first region 17. Similarly, the second region 18b of the crystalline oxide semiconductor 15 is closer to the first insulating film 14b than the first region 17. Note that the second regions 18a and 18b do not necessarily have to be adjacent to the first insulating films 14a and 14b without contact; in other embodiments, they may be adjacent to the first insulating films 14a and 14b while in contact with them.

[0038] In this embodiment, the crystalline oxide semiconductor 15 is provided in a columnar shape, penetrating the first insulating film 14a, the third electrode 13, and the first insulating film 14b. Here, the first region 17 is the region in the crystalline oxide semiconductor 15 that penetrates the third electrode 13. The second region 18a is the region in the crystalline oxide semiconductor 15 that penetrates the first insulating film 14a. Similarly, the second region 18b is the region in the crystalline oxide semiconductor 15 that penetrates the first insulating film 14b. From a certain viewpoint, the first region 17 is the region in the crystalline oxide semiconductor 15 that is surrounded laterally by the third electrode 13. The second region 18a is the region in the crystalline oxide semiconductor 15 that is surrounded laterally by the first insulating film 14a. Similarly, the second region 18b is the region in the crystalline oxide semiconductor 15 that is surrounded laterally by the first insulating film 14b.

[0039] In one embodiment, the ratio of the height of the first region to the height of the second region in the crystalline oxide semiconductor 15 is, for example, 10:1 to 1:1, preferably 8:1 to 1:1. The ratio of the first region to the second region of the crystalline oxide semiconductor 15 can be measured by processing the relevant area with a focused ion beam (FIB) to expose it and observing the cross-section with a transmission electron microscope (TEM). In one embodiment, the ratio of the thickness of the third electrode 13 along the crystalline oxide semiconductor 15 to the thickness of the first insulating film 14a and / or the thickness of the first insulating film 14b is, for example, 10:1 to 1:1 (thickness of the third electrode 13:thickness of the first insulating film 14a, thickness of the third electrode 13:thickness of the first insulating film 14b), preferably 8:1 to 1:1.

[0040] In the first and second regions, it is preferable that the composition ratio of the metal elements constituting the crystalline oxide semiconductor 15 is substantially the same. "Identical composition ratio of metal elements" means that the types of metal elements constituting the crystalline oxide semiconductor are the same, and their content ratios are also the same. Furthermore, "substantially" identical composition of metal elements means that, excluding unavoidable impurities, the composition ratio of metal elements is the same. It is preferable that the crystalline oxide semiconductor 15 is formed by a continuous process in the first and second regions, and that no process that changes the carrier concentration, such as ion implantation, is performed in only one of the regions.

[0041] In this embodiment, the average carrier concentration in the second region 18a of the crystalline oxide semiconductor 15 is relatively higher than that in the first region 17, and / or, the average carrier concentration in the second region 18b of the crystalline oxide semiconductor 15 is relatively higher than that in the first region 17. This improves the contact resistance of the transistor 10. That is, the second regions 18a and 18b are further away from the third electrode 13, which functions as the gate electrode, compared to the first region 17. Therefore, even when a gate voltage is applied to the third electrode 13, carriers are inherently less likely to be induced in the second regions 18a and 18b, making them prone to contact resistance. However, as described above, by selectively increasing the average carrier concentration in the second regions 18a and 18b, it is prevented that the contact resistance in the second regions 18a and 18b becomes high, thereby improving the contact resistance of the transistor 10. As will be detailed later, during transistor manufacturing, by utilizing the properties of crystalline oxide semiconductors (the property of crystallization), post-annealing can be performed under specific conditions, or the average hydrogen concentration in the second region can be relatively increased, thereby increasing the average carrier concentration in the second region compared to the first region, and this state can be maintained. In comparison, if an amorphous oxide semiconductor such as IGZO is used as the semiconductor, the semiconductor is not crystalline, so it is presumed that the above-mentioned average carrier concentration condition cannot be met, and the above-mentioned improvement in contact resistance will not occur.

[0042] The average carrier concentration is the average value of the carrier concentration in each region. If the crystalline oxide semiconductor 15 is an n-type semiconductor, the carrier concentration is the electron density. If the crystalline oxide semiconductor 15 is a p-type semiconductor, the carrier concentration is the hole density. The average value of the carrier concentration can be measured and calculated by the following method. First, the cross-section of the crystalline oxide semiconductor 15 is processed so that it becomes a flat observation surface with irregularities of 1 nm or less, and then immediately transported into a high vacuum and measured with a scanning tunneling microscope. At this time, the tunnel current is measured by sweeping along the channel length direction of the crystalline oxide semiconductor 15 in the order of, for example, the second region 18a, the first region 17, and the second region 18b. This tunnel current can be quantified as a carrier concentration distribution using the CITS method (Current Imaging Tunneling Spectroscopy). The average value of the carrier concentration in each region is obtained as the arithmetic mean of the measured values ​​at five measurement points. That is, during measurement, each region is divided into five equal parts in the vertical direction (channel length direction), and each is used as a CITS measurement point. Furthermore, in the crystalline oxide semiconductor 15, the relative higher average carrier concentration in the second region 18a compared to the first region 17, and the relative higher average carrier concentration in the second region 18b compared to the first region 17, can be determined by the tunneling current flowing when scanning the surface of each region using a STEM (scanning tunneling electron microscope). When using a STEM, a two-dimensional carrier concentration distribution can be observed with a spatial resolution of 1 nm. Therefore, not only can the relative average carrier concentrations in the first region 17 and the second regions 18a and 18b be determined, but the absolute values ​​of the average carrier concentrations in each region can also be determined.

[0043] In one embodiment, the average carrier concentration in the first region 17 is 10 １４ ~10 １８ cm －３ In one embodiment, the average carrier concentration in the second region 18a and / or the second region 18b is 10 １７ cm －３ Preferably 10 １７ ~10 ２２ cm －３In one embodiment, the ratio of the average carrier concentration of the second region 18a to the average carrier concentration of the first region 17 (average carrier concentration of the second region 18a / average carrier concentration of the first region 17), and / or the ratio of the average carrier concentration of the second region 18b to the average carrier concentration of the first region 17 (average carrier concentration of the second region 18b / average carrier concentration of the first region 17) is between 2 and 10. ４ And preferably 10 to 10 ４ More preferably 10 to 3 × 10 ３ In one embodiment, the average carrier concentration in the first region 17 is 10 １４ ~10 １８ cm －３ The mean carrier concentration in the second region 18a and / or the second region 18b is 10 １７ cm －３ Preferably 10 １７ ~10 ２２ cm －３ The ratio of the average carrier concentration of the second region 18a to the average carrier concentration of the first region 17 (average carrier concentration of the second region 18a / average carrier concentration of the first region 17), and / or the ratio of the average carrier concentration of the second region 18b to the average carrier concentration of the first region 17 (average carrier concentration of the second region 18b / average carrier concentration of the first region 17) is between 2 and 10. ４ And preferably 10 to 10 ４ More preferably 10 to 3 × 10 ３ That is the case.

[0044] In one embodiment, the crystalline oxide semiconductor 15 has a relatively higher average hydrogen concentration in the second region 18a compared to the first region 17, and / or the crystalline oxide semiconductor 15 has a relatively higher average hydrogen concentration in the second region 18b compared to the first region 17. By increasing the average hydrogen concentration in the second region 18a and / or the second region 18b compared to the first region 17, the average carrier concentration in the second region 18a and / or the second region 18b tends to increase further. This further improves the contact resistance of the transistor 10. In addition, since the crystalline oxide semiconductor 15 has a smaller hydrogen diffusion constant than the amorphous oxide semiconductor, the difference in average hydrogen concentration described above is stably maintained. As described later, the average hydrogen concentration in the second regions 18a and 18b can be increased by setting the film deposition conditions (e.g., hydrogen partial pressure, etc.) of the first insulating films 14a and 14b to specific conditions. Furthermore, in the crystalline oxide semiconductor 15, it can be determined by secondary ion mass spectrometry (SIMS) that the average hydrogen concentration in the second region 18a is relatively higher than that in the first region 17, and that the average hydrogen concentration in the second region 18b is relatively higher than that in the first region 17. When using SIMS, not only can the relative average hydrogen concentrations in the first region 17 and the second regions 18a and 18b be determined, but the absolute value of the average hydrogen concentration in each region can also be obtained. The average hydrogen concentration is obtained as the arithmetic mean of the measured values ​​(hydrogen concentration) at five measurement points in each region. That is, for measurement, each region is divided into five equal parts in the vertical direction (channel length direction), and each is used as a SIMS measurement point.

[0045] In one embodiment, the average hydrogen concentration in the second region 18a and / or the second region 18b is 1 × 10⁻¹⁶ ２１ atoms / cm ３ Above, a comfortable 2 x 10 ２１ atoms / cm ３ More preferably 5 x 10 ２１ atoms / cm ３That concludes the explanation. In one embodiment, the average hydrogen concentration in the first region 17 is relatively lower than that in the second region 18a and / or the second region 18b. In one embodiment, the ratio of the average hydrogen concentration of the second region 18a to the average hydrogen concentration of the first region 17 (average hydrogen concentration of the second region 18a / average hydrogen concentration of the first region 17), and / or the ratio of the average hydrogen concentration of the second region 18b to the average hydrogen concentration of the first region 17 (average hydrogen concentration of the second region 18b / average hydrogen concentration of the first region 17) is 5 to 5 × 10⁻¹⁰. ３ Preferably 10 to 3 × 10 ３ More preferably, 20 to 2 × 10 ３ In one embodiment, the average hydrogen concentration in the second region 18a and / or the second region 18b is 1 × 10⁻¹⁶. ２１ atoms / cm ３ Above, a comfortable 2 x 10 ２１ atoms / cm ３ More preferably 5 x 10 ２１ atoms / cm ３ The above conditions are met, and the ratio of the average hydrogen concentration of the second region 18a to the average hydrogen concentration of the first region 17 (average hydrogen concentration of the second region 18a / average hydrogen concentration of the first region 17), and / or the ratio of the average hydrogen concentration of the second region 18b to the average hydrogen concentration of the first region 17 (average hydrogen concentration of the second region 18b / average hydrogen concentration of the first region 17) is 5 to 5 × 10 ３ Preferably 10 to 3 × 10 ３ More preferably, 20 to 2 × 10 ３ That is the case.

[0046] The average hydrogen concentration can also be measured for the insulating films (first insulating films 14a, 14b, and second insulating film 16). The measurement method is the same as the measurement method described for the crystalline oxide semiconductor 15. In one embodiment, the average hydrogen concentration in the first insulating film 14a and / or the first insulating film 14b is, for example, 5 × 10⁻¹⁶. ２２ atoms / cm ３ The following is true: 2 × 10 ２２ atoms / cm ３ Below, 1 x 10 ２２ atoms / cm ３ Below, 5 x 10 ２１atoms / cm ３ Hereinafter, 1×10 ２１ atoms / cm ３ Hereinafter, 5×10 ２０ atoms / cm ３ Hereinafter, or 1×10 ２０ atoms / cm ３ Hereinafter may also be applicable. The average hydrogen concentration in the first insulating film 14a and / or the first insulating film 14b is, for example, for example 5×10 １８ atoms / cm ３ or more, 1×10 １９ atoms / cm ３ or more, 5×10 １９ atoms / cm ３ or more, 1×10 ２０ atoms / cm ３ or more, 5×10 ２０ atoms / cm ３ or more, or 1×10 ２１ atoms / cm ３ or more may also be applicable.

[0047] In one embodiment, the average hydrogen concentration in the second insulating film 16 is, for example, 1×10[[ID=4​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​Below, 5 x 10 ２０ atoms / cm ３ The following, or 1 x 10 ２０ atoms / cm ３ The following is also acceptable.

[0048] In one embodiment, the crystallinity of the crystalline oxide semiconductor 15 in the first region 17 is relatively higher than that of the second region 18a and / or the second region 18b. That is, the first region 17 includes a highly crystallinity region in which the crystallinity is relatively higher compared to that of the crystalline oxide semiconductor in the second region 18a and / or the second region 18b. The degree of crystallinity can be compared, for example, by determining the variation in the FFT pattern obtained by performing a fast Fourier transform (FFT) on an image obtained by irradiating with an electron beam. The shape of the spot image obtained by electron diffraction indicates the degree of crystallinity and quality of the crystal; a sharp, clear spot indicates high crystallinity, while a blurred, spread-out spot indicates low crystallinity or a non-uniform structure. For example, in one embodiment, in each FFT pattern obtained by performing a fast Fourier transform on images obtained by irradiating the same area of ​​the first and second regions with an electron beam, the variation X of the FFT pattern calculated by the following formula is larger in the second region than in the first region. X = [Σ(Brightness - Average value of brightness in the FFT region)] ２ ] / number of samples (wherein the above formula, the FFT region is the region of the FFT pattern obtained by performing a fast Fourier transform on the above image, the brightness is the brightness of each spot in the FFT region, and the number of samples is the number of electron beam irradiations performed to obtain the image. The number of samples is assumed to be 5. Therefore, the above formula can also be expressed as follows.)

[0049]

[0050] When obtaining an FFT pattern, it is preferable to measure by aligning the orientation of the crystal planes on the observation surface in the first and second regions. It is also preferable to select the measurement position so that no crystal grain boundaries are present in the electron beam spot. Furthermore, it is preferable to calculate the variation X of the FFT pattern by, for example, measuring five points in each of the first and second regions and determining the average value for each region. If it is difficult to align the orientation of the crystal planes on the observation surface in the first and second regions, or if it is difficult to exclude crystal grain boundaries from the electron beam spot, the brightness of the FFT pattern should be corrected by a conventionally known method.

[0051] In one embodiment, the crystal orientation in the electron diffraction pattern obtained by irradiating the crystalline oxide semiconductor 15 with an electron beam includes the cubic crystal structure of indium oxide and is composed of at least one of the (211), (222), (400), (440), and (622) planes.

[0052] An example of a manufacturing method for the transistor 10 according to this embodiment is described below, but the manufacturing method is not limited to this example.

[0053] Figure 3 illustrates an example of a method for manufacturing the transistor 10 according to this embodiment. Figure 3(a) shows the second electrode 12 and the insulating film 19 supporting the second electrode 12 formed by a known method, as shown in Figures 1 and 2. Although not shown in Figure 3(a), the second electrode 12 and the insulating film 19 may be formed on another substrate. Furthermore, the second electrode 12 may be connected to an element outside the transistor according to this embodiment.

[0054] Next, as shown in Figure 3(b), the first insulating film 14b, the third electrode 13, and the first insulating film 14a are formed in this order. At this time, as will be described later, the third electrode 13 may be formed to be connected to the word line. Alternatively, the third electrode 13 itself may be used as the word line.

[0055] The first insulating film 14b is formed by depositing a film containing the above-mentioned insulator using various methods such as chemical vapor deposition (CVD), plasma CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), sol-gel method, and coating method.

[0056] The third electrode 13 is formed by depositing a conductive material such as tungsten, as described above. The third electrode 13 may be patterned into any shape. The pattern of the third electrode 13 may be formed during film deposition, or it may be formed by etching after film deposition.

[0057] The first insulating film 14a is formed by depositing a film containing the above-mentioned insulator using various methods such as chemical vapor deposition (CVD), plasma CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), sol-gel method, and coating method.

[0058] Next, as shown in Figure 3(c), through-holes H are formed by etching, penetrating the first insulating film 14a, the third electrode 1, and the first insulating film 14b. Various etching methods, such as dry etching and wet etching, may be used to form the through-holes H. Alternatively, a resist may be deposited on the first insulating film 14a before etching to define the region where the through-holes H will be formed.

[0059] Next, as shown in Figure 3(d), a second insulating film 16 containing the above-described insulator is formed by various methods such as chemical vapor deposition (CVD), plasma CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), sol-gel method, and coating method.

[0060] Next, as shown in Figure 3(e), a crystalline oxide semiconductor 15 is formed in the through-hole H where the second insulating film 16 is formed. Methods for forming the crystalline oxide semiconductor 15 include chemical vapor deposition (CVD), plasma CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), sol-gel method, and coating method. Note that CVD methods include metal-organic CVD (MO-CVD), inductively coupled plasma CVD (ICP-CVD), and mist CVD. PVD methods include DC sputtering, AC sputtering, RF sputtering, ICP sputtering, reactive sputtering, and ion plating.

[0061] However, the oxide semiconductor 15 formed in the process shown in Figure 3(e) may be amorphous or crystalline. If an amorphous oxide semiconductor is formed in Figure 3(e), the oxide semiconductor will be crystallized in one of the subsequent processes. The crystalline oxide semiconductor 15 may be formed by performing post-annealing, as described later, after forming the amorphous oxide semiconductor. The crystalline oxide semiconductor 15 may be formed by performing post-annealing after the formation of the amorphous oxide semiconductor, or post-annealing may be performed after the oxide semiconductor has crystallized and the crystalline oxide semiconductor 15 has been formed. Alternatively, the crystalline oxide semiconductor 15 may be formed without post-annealing, or post-annealing may be performed after the crystalline oxide semiconductor 15 has been formed to adjust the crystallinity of the crystalline oxide semiconductor 15.

[0062] It is preferable to perform post-annealing on the oxide semiconductor formed in the process shown in Figure 3(e). Post-annealing can be performed after the deposition of the oxide semiconductor film, for example, after or before the formation of the first electrode 11 in the subsequent step. The state of the oxide semiconductor before post-annealing may be amorphous or crystalline. The post-annealing atmosphere may contain nitrogen or oxygen and may be under vacuum or air. The post-annealing temperature is preferably 250°C to 600°C, more preferably 300°C to 500°C, and even more preferably 350°C to 450°C. The post-annealing time is 5 minutes to 2 hours, preferably 30 minutes to 1 hour. By setting the post-annealing conditions as described above, the selective increase in the average carrier concentration in the second regions 18a and 18b can be effectively promoted. To relatively improve the average carrier concentration in the second regions 18a and 18b, it is preferable to adjust the heating rate, holding time at the maximum temperature, cooling rate, etc., during post-annealing. For example, by setting specific conditions such as shortening the holding time at the maximum temperature during post-annealing or accelerating the cooling rate, it is possible to effectively promote the selective increase in the average carrier concentration in the second regions 18a and 18b described above. This is because, under the above specific conditions, crystallization begins later in the second regions 18a and 18b, which are adjacent to the first insulating films 14a and 14b, where the temperature rise is slower, compared to the first region 17 adjacent to the easily conductive third electrode 13, and the effect (non-uniformity) due to such a delay in crystallization is preserved. As a result, the average carrier concentration in the second regions 18a and 18b selectively increases, and this state is maintained.

[0063] Next, as shown in Figure 3(f), a first electrode 11 is formed on the upper layer of the crystalline oxide semiconductor 15 by a known method. The first electrode 11 may be patterned into any shape. The first electrode 11 may have a pattern formed during film deposition, or it may have a pattern formed by etching after film deposition.

[0064] As described above, a transistor 10 as shown in Figures 1 and 2 can be obtained.

[0065] In the manufacturing method described above, the crystalline oxide semiconductor 15 is formed in the through-hole H where the second insulating film 16 is formed. Therefore, atomic layer deposition (ALD) is preferred as the method for forming the crystalline oxide semiconductor 15. Atomic layer deposition (ALD) is a thin film formation method in which a process of alternately exposing a raw material (sometimes called a precursor) containing a metal element constituting the film to be deposited (here, the crystalline oxide semiconductor 15) and an oxidizing agent to the substrate surface constitutes one cycle, forming one atomic layer in one cycle, and repeating this cycle until the desired film thickness is achieved. Therefore, by using ALD, a dense crystalline oxide semiconductor 15 can be formed even in the second region 18b near the second electrode 12, away from the opening, in the through-hole H where the second insulating film 16 is formed. This further reduces the contact resistance between the crystalline oxide semiconductor 15 and the second electrode 12. Furthermore, by sequentially changing the ALD film formation conditions, a selective increase in the average carrier concentration in the second regions 18a and 18b can be effectively promoted.

[0066] A single atomic layer deposition cycle of ALD may include the following four steps: (1) The precursor, which is the raw material, is vaporized in a container and introduced into the chamber. A predetermined system pressure is applied and the precursor is reacted with the OH groups on the substrate surface or film surface for a predetermined time to adsorb single molecules. If the vapor pressure of the precursor is low, the container containing the precursor may be heated to promote vaporization, and if the vapor pressure of the precursor is high, the container containing the precursor may be cooled to suppress vaporization and adjust the process. (2) Unreacted raw materials and by-product gases are removed from the chamber by purging with an inert gas, and one atomic layer is deposited. (3) A reactive gas is introduced into the chamber, and the metal of the precursor is oxidized using heat, plasma, etc. (4) Unreacted oxidizing agents and by-product gases are removed by purging with an inert gas. After step (4), the process returns to step (1), and steps (1) to (4) may be repeated until the desired film thickness is achieved.

[0067] When performing ALD, various ALD devices can be used. Specifically, examples include devices that can supply a precursor by bubbling, and devices that have a vaporization chamber. Also, devices that can perform plasma treatment on the reactive gas (oxidizer) can be used. Furthermore, not only single-wafer devices equipped with a film deposition chamber, but also devices that can process multiple sheets simultaneously using a batch furnace may be used.

[0068] Examples of ALD precursors include organometallic (e.g., AlMe) ３ ), metal hydrides (e.g., AshH ３ ), metal alkoxides (for example, Ti(OCHMe ２ ) ４ ), metal amides (for example, Ti (NME ２ ) ４ ), β-diketonate (for example, Co(acac) ２ ), metallocene (for example, MgCp ２ Examples include metal amidinates, etc. Various metal compounds are commercially available for use as ALD precursors, and one should select a precursor and oxidizing agent that can form the desired film.

[0069] Examples of precursors include compounds of silicon or metals, which consist of one or more compounds selected from the group consisting of compounds used as organic ligands, such as alkyl compounds, alcohol compounds, glycol compounds, β-diketone compounds, cyclopentadiene compounds, and organic amine compounds.

[0070] Examples of precursor metal species include lithium, sodium, potassium, magnesium, calcium, strontium, barium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, manganese, iron, ruthenium, cobalt, rhodium, iridium, nickel, palladium, platinum, copper, silver, gold, zinc, boron, aluminum, silicon, indium, gallium, germanium, tin, lead, antimony, bismuth, scandium, ruthenium, yttrium, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium.

[0071] If the oxide semiconductor 15 contains indium atoms (In), an In-containing precursor may be used. If the oxide semiconductor 15 contains other metals, a precursor containing those metals may be used. When forming an oxide semiconductor using two or more metals, there are two methods: vaporizing and supplying each component independently (sometimes referred to as the "single-source method") and vaporizing and supplying a mixed raw material in which multi-component raw materials are pre-mixed to a desired composition (sometimes referred to as the "cocktail-source method"). In the single-source method, it is preferable that each precursor used has similar thermal and / or oxidative decomposition behavior. In the cocktail-source method, it is preferable that each precursor has similar thermal and / or oxidative decomposition behavior and does not undergo alteration due to chemical reactions during mixing.

[0072] The following are examples of compounds that can be used as organic ligands for precursors. Furthermore, depending on the valency of the central metal, multiple ligands from the following list may coordinate. In a precursor, when multiple ligands coordinate to the central metal, these ligands may be identical to each other, or two or more ligands may be combined.

[0073] Alkyl compounds used as organic ligands for precursors include methyl, ethyl, propyl, isopropyl, butyl, 2-butyl, isobutyl, 3-butyl, pentyl, isopentyl, and 3-pentyl.

[0074] Alcohol compounds used as organic ligands for precursors include alkyl alcohols such as methanol, ethanol, propanol, isopropyl alcohol, butanol, 2-butyl alcohol, isobutyl alcohol, 3-butyl alcohol, pentyl alcohol, isopentyl alcohol, and 3-pentyl alcohol; 2-methoxyethanol, 2-ethoxyethanol, 2-butoxyethanol, 2-(2-methoxyethoxy)ethanol, 2-methoxy-1-methylethanol, 2-methoxy-1,1-dimethylethanol, 2-ethoxy-1,1-dimethylethanol, 2-isopropoxy-1,1-dimethylethanol, and 2-butoxy Examples include ether alcohols such as -1,1-dimethylethanol, 2-(2-methoxyethoxy)-1,1-dimethylethanol, 2-propoxy-1,1-diethylethanol, 2-s-butoxy-1,1-diethylethanol, and 3-methoxy-1,1-dimethylpropanol; and dialkylamino alcohols such as dimethylaminoethanol, ethylmethylaminoethanol, diethylaminoethanol, dimethylamino-2-pentanol, ethylmethylamino-2-pentanol, dimethylamino-2-methyl-2-pentanol, ethylmethylamino-2-methyl-2-pentanol, and diethylamino-2-methyl-2-pentanol.

[0075] Examples of glycol compounds used as organic ligands for precursors include 1,2-ethanediol, 1,2-propanediol, 1,3-propanediol, 2,4-hexanediol, 2,2-dimethyl-1,3-propanediol, 2,2-diethyl-1,3-propanediol, 1,3-butanediol, 2,4-butanediol, 2,2-diethyl-1,3-butanediol, 2-ethyl-2-butyl-1,3-propanediol, 2,4-pentanediol, 2-methyl-1,3-propanediol, 2-methyl-2,4-pentanediol, 2,4-hexanediol, and 2,4-dimethyl-2,4-pentanediol.

[0076] Examples of β-diketone compounds used as organic ligands for precursors include acetylacetone, hexane-2,4-dione, 5-methylhexane-2,4-dione, heptane-2,4-dione, 2-methylheptane-3,5-dione, 5-methylheptane-2,4-dione, 6-methylheptane-2,4-dione, 2,2-dimethylheptane-3,5-dione, 2,6-dimethylheptane-3,5-dione, 2,2,6-trimethylheptane-3,5-dione, 2,2,6,6-tetramethylheptane-3,5-dione, octane-2,4-dione, 2,2,6-trimethyloctane-3,5-dione, 2,6-dimethyloctane-3,5-dione, 2,9-dimethylnonane-4,6-dione, and 2-methyl-6-ethyl Examples include alkyl-substituted β-diketones such as decane-3,5-dione and 2,2-dimethyl-6-ethyldecane-3,5-dione; fluorine-substituted alkyl β-diketones such as 1,1,1-trifluoropentane-2,4-dione, 1,1,1-trifluoro-5,5-dimethylhexane-2,4-dione, 1,1,1,5,5,5-hexafluoropentane-2,4-dione, and 1,3-diperfluorohexylpropane-1,3-dione; and ether-substituted β-diketones such as 1,1,5,5-tetramethyl-1-methoxyhexane-2,4-dione, 2,2,6,6-tetramethyl-1-methoxyheptane-3,5-dione, and 2,2,6,6-tetramethyl-1-(2-methoxyethoxy)heptane-3,5-dione.

[0077] Examples of cyclopentadiene compounds used as organic ligands for precursors include cyclopentadiene, methylcyclopentadiene, ethylcyclopentadiene, propylcyclopentadiene, isopropylcyclopentadiene, butylcyclopentadiene, 2-butylcyclopentadiene, isobutylcyclopentadiene, 3-butylcyclopentadiene, dimethylcyclopentadiene, and tetramethylcyclopentadiene.

[0078] Examples of organic amine compounds used as organic ligands for precursors include methylamine, ethylamine, propylamine, isopropylamine, butylamine, 2-butylamine, 3-butylamine, isobutylamine, dimethylamine, diethylamine, dipropylamine, diisopropylamine, ethylmethylamine, propylmethylamine, and isopropylmethylamine.

[0079] In addition, metal halogen compounds (e.g., InCl ３ InBr ３ InF ３ (etc.) may be used as precursors. When multiple halogens coordinate to a metal, these halogens may be identical to each other, or two or more halogens may be combined. In addition, some of the halogens may be replaced with hydrogen.

[0080] Examples of indium-containing precursors include InCl ３ , TMIn (trimethyl indium), TEIn (triethyl indium), InCp (cyclopentadienyl indium (I)), InEtCp (ethylcyclopentadienyl indium(I)), In(acac) ３ (indium acetylacetonate), In(tmhd) ３ (indium 2,2,6,6-tetramethyl-3,5-heptanedionate), In[( ｉ PrN) ２ CNR ２ ] ３(R=Me) (indium-tris-guanidinates), Et ２ InN (TMS) ２ (diethyl[bis-(trimethylsilyl)amido]indium), INCA(diethyl[1,1,1-trimethyl-N- (trimethylsilyl)silanaminato]indium), DADI([3-(dimethylamino)propyl]dimethyl indium), In(dmamp) ３ ((1-dimethylamino-2-methyl-2-propoxy)indium), Me ２ Examples include In(EDPA)(dimethyl(N-ethoxy-2,2-dimethylpropanamido)indium) and tris(N,N'-disosopropylacetamidinato)indium(III).

[0081] These ALD precursors may be used individually or in combination of two or more types.

[0082] The precursors described above can be manufactured according to known manufacturing methods. For example, when an alcohol compound is used as an organic ligand, the precursor can be manufactured by reacting the inorganic salt or hydrate of the aforementioned metal with an alkali metal alkoxide of the alcohol compound. Examples of the inorganic salt or hydrate of the metal include metal halides and nitrates. Examples of alkali metal alkoxides include sodium alkoxide, lithium alkoxide, and potassium alkoxide.

[0083] H is an oxidizing agent used in ALD. ２ O, O ２ , O ３ , O ２ Plasma, H ２ O plasma, hydrogen peroxide (H ２ O ２ Examples include the following. These oxidizing agents may be used individually or in combination of two or more.

[0084] When using two or more oxidizing agents, they may be used simultaneously, or they may be used individually while changing between them. For example, as an oxidizing agent, O ２ Plasma and H ２ By using two types of O plasma, ２ High mobility obtained when using plasma, and H ２ By using O plasma, it is possible to take advantage of both the reduction in carbon concentration and the improved stability of mobility during heat treatment. By using two or more oxidizing agents, high mobility and low carbon concentration can be adjusted. Depending on the desired effect, O ２ Plasma and H ２ The proportion of O-plasma used, the order of use, the number of cycles, etc., should be selected as appropriate.

[0085] The pressure in the system (inside the film deposition chamber) in step (1) can be set appropriately according to the type of precursor, substrate temperature, etc. For example, 1 to 10,000 Pa is preferred, 10 to 1,000 Pa is more preferred, 50 to 500 Pa is even more preferred, and 80 to 120 Pa is particularly preferred.

[0086] In one embodiment, in the film formation process, H is used as the oxidizing agent. ２ O plasma is used. In one embodiment, in the film formation process, O is used as the oxidizing agent. ２ Plasma is used. In one embodiment, in the film deposition process, O is used as the oxidizing agent. ３ These oxidizing agents are used. By using these oxidizing agents, it is possible to control the electrical properties of the oxide semiconductor film to a favorable state.

[0087] To vaporize the precursor, the container containing the precursor may be heated to a temperature at which the precursor is sufficiently vaporized, as needed. If a precursor with a high vapor pressure is used, the container containing the precursor may be cooled as needed. In one embodiment, the container containing the indium-containing precursor (e.g., triethylindium) is heated to a temperature in the range of 25 to 150°C. The above temperature is preferably in the range of 50 to 150°C, and more preferably in the range of 75 to 125°C.

[0088] In the manufacturing method described above, the substrate temperature during film formation is usually in the range of 50 to 600°C, preferably 85 to 500°C, more preferably 80 to 350°C, and even more preferably 100 to 250°C.

[0089] Furthermore, the amount of oxide semiconductor film grown per ALD process cycle varies depending on the type of precursor and reactive gas used during film formation, as well as the substrate temperature during film formation.

[0090] The growth rate per ALD process cycle is called Growth per Cycle (GPC), and can be calculated, for example, by measuring the film thickness of the oxide semiconductor after repeating 30 ALD cycles. Here, GPC changes depending on the combination of precursor, oxidizer, and substrate temperature, and also changes depending on the type of substrate. Therefore, the number of cycles can be set appropriately by taking these factors into consideration, as it depends on numerous factors such as the type and combination of precursor and oxidizer used, the type of substrate, the substrate temperature during film formation, and the desired film thickness.

[0091] Also, as an oxidizing agent, O ３ When using, the substrate temperature during film formation is preferably above 100°C, more preferably 110-250°C, 120-230°C, or 130-220°C. H is used as the oxidizing agent. ２ O plasma and O ２ When using plasma, the substrate temperature during film deposition is preferably 100 to 150°C.

[0092] Examples of inert gases used to purge unreacted raw materials and unreacted oxidizing agents include argon and nitrogen, and in the method of this embodiment, argon or nitrogen is preferred.

[0093] In step (3) above, it is preferable to generate a plasma of the reactive gas (oxidizer).

[0094] In the process shown in Figure 3(b) of the above-described manufacturing method, when forming the first insulating film 14a, the hydrogen concentration of the first insulating film 14a may be increased by adding hydrogen gas to the atmosphere during ALD or CVD film deposition, using a precursor containing a large amount of hydrogen, or by activating it with plasma. This allows hydrogen to be supplied from the first insulating film 14a to the second region 18a of the crystalline oxide semiconductor 15 via the second insulating film 16. This selectively increases the average hydrogen concentration of the second region 18a of the crystalline oxide semiconductor 15, and also increases the average carrier concentration. Furthermore, when forming the first insulating film 14b, the hydrogen concentration of the first insulating film 14b may be selectively increased by adding hydrogen gas to the atmosphere during film deposition. This allows hydrogen to be supplied from the first insulating film 14b to the second region 18b of the crystalline oxide semiconductor 15 via the second insulating film 16. This selectively increases the average hydrogen concentration of the second region 18b of the crystalline oxide semiconductor 15, and also increases the average carrier concentration. The hydrogen supply described above proceeds efficiently during the post-annealing of the crystalline oxide semiconductor 15. In particular, performing the post-annealing under the conditions described above promotes hydrogen supply, and the effects described above are exhibited more significantly.

[0095] The crystalline oxide semiconductor 15 is preferably a crystalline oxide semiconductor formed by atomic layer deposition (ALD) method. While crystalline oxide semiconductors formed by atomic layer deposition (ALD) method have different uniformity from crystalline oxide semiconductors formed by methods such as sputtering, it is impossible or impractical to specify the structural or characteristic differences in general terms.

[0096] The above description mainly shows the case in which the transistor has a first insulating film between the first electrode and the third electrode, and between the second electrode and the third electrode, but it is not limited to this. The transistor may have a first insulating film only between the first electrode and the third electrode, or between the second electrode and the third electrode. The second insulating film 16 may also be omitted. Furthermore, the transistor may have a structure other than the structure shown in Figures 1 to 3, as long as the effects of this embodiment are achieved.

[0097] 2. Semiconductor Devices A semiconductor device according to one aspect of the present invention includes a transistor according to one aspect of the present invention. The semiconductor device may comprise one or more transistors according to one aspect of the present invention. The semiconductor device according to this aspect has excellent electrical properties and high reliability because the contact resistance in the transistor can be improved. The type of semiconductor device is not particularly limited, but from the viewpoint of demonstrating the above effects significantly, it is preferable to have semiconductor memory devices such as volatile memories such as DRAM (Dynamic Random Access Memory) and SRAM (Static RAM); and non-volatile memories such as mask ROM (Read Only Memory), EPROM (Erasable Programmable ROM), EEPROM (Electrically Erasable Programmable ROM), flash memory (NOR type flash memory, NAND type flash memory), MRAM (Magnetoresistive RAM), FeRAM (Ferroelectric RAM), ReRAM (Resistive RAM), etc. Alternatively, the semiconductor device according to this embodiment may be a logic device such as TTL (Transistor-Transistor Logic), CMOS (Complementary Metal-Oxide-Semiconductor), BiCMOS, PLD (Programmable Logic Device), FPGA (Field Programmable Gate Array), CPU (Central Processing Unit), or MPU (Microprocessor Unit). Furthermore, since the transistor according to one embodiment of the present invention has a vertical structure, it is suitable for densely arranging multiple transistors in a semiconductor memory device, and contributes to the miniaturization of the semiconductor memory device. Moreover, since the transistor according to one embodiment of the present invention uses an oxide semiconductor as the channel, it tends to have a small leakage current. Therefore, by using it in a semiconductor memory device, the capacitance of the capacitor can be reduced or the capacitor can be omitted. As a result, by using the transistor according to one embodiment of the present invention, the semiconductor memory device can be miniaturized.

[0098] Figure 4 shows an example of a circuit configuration of a semiconductor memory device equipped with a transistor according to one aspect of the present invention. As shown in Figure 4, the semiconductor memory device 50 includes a transistor 10, a capacitor 51, a word line WL, and a bit line BL. The source electrode of the transistor 10 is connected to the bit line BL. The drain electrode of the transistor 10 is connected to one end of the capacitor 51. The gate electrode of the transistor 10 is connected to the word line WL. The other end of the capacitor 51 is grounded. The bit line BL may be connected to the first electrode 11 of the transistor 10, or to the second electrode 12. The word line WL may be connected to the third electrode 13 of the transistor 10. One end of the capacitor 51 may be connected to the first electrode 11 of the transistor 10, or to the second electrode 12.

[0099] In the example shown in Figure 4, a single memory cell 52 is formed by a transistor 10 and a capacitor 51. The memory cell 52 can store data based on the charge held by the capacitor 51. Note that the configuration of the memory cell 52 is not limited to this example, and in other examples, the capacitor 51 is omitted. When the capacitor 51 is omitted, data can be stored based on the charge held by the transistor 10 itself. In addition, two or more transistors may be combined to form the memory cell 52. If the transistor 10 itself is to have the function of holding charge, for example, one or more of the configurations described below can be applied. (1) The second insulating film is made of hafnium oxide (HfO ２ ), zirconium oxide (ZrO ２ (2) Use a high dielectric constant insulator such as (Pb, La)(Zr, Ti)O ３ (PLZT), SrTiO ３(STO), yttria-stabilized zirconia (YSZ), and other ferroelectric materials are used. (3) Hysteresis is utilized by adding an element that forms an energy level within the gap of the crystalline oxide semiconductor to the crystalline oxide semiconductor. (4) Parasitic capacitance is utilized by arranging a part of the source electrode and / or drain electrode and a part of the gate electrode so that they face each other across an insulating film. In (4) above, for example, parasitic capacitance can be utilized by arranging a part of one of the source electrode and drain electrode and a part of the gate electrode so that they face each other across an insulating film. In this case, the other of the source electrode and drain electrode may be arranged away from the gate electrode (for example, the distance between the other of the source electrode and drain electrode and the gate electrode may be longer than the distance between one of the source electrode and drain electrode and the gate electrode). Here, in the crystalline oxide semiconductor, the above-mentioned second region may be formed in a region adjacent to the other of the source electrode and drain electrode.

[0100] The semiconductor memory device 50 can read data stored in the memory cell 52 to the bit line BL by controlling the word line WL, and can also write data transferred to the bit line BL to the memory cell 52. The semiconductor memory device 50 is configured to include a memory cell array (not shown) consisting of a plurality of memory cells 52.

[0101] Although several embodiments and / or examples of the present invention have been described in detail above, those skilled in the art will find it easy to make many modifications to these exemplary embodiments and / or examples without substantially departing from the novel teachings and effects of the present invention. Therefore, many of these modifications fall within the scope of the present invention. All references to the documents cited in this specification are incorporated herein by reference.

[0102] 10: Transistor 11: First electrode 12: Second electrode 13: Third electrode 14a, 14b: First insulating film 15: Crystal oxide semiconductor 16: Second insulating film 17: First region 18a, 18b: Second region 19: Insulating film 50: Semiconductor memory device 51: Capacitor 52: Memory cell WL: Word line BL: Bit line

Claims

1. A transistor comprising: a first electrode; a second electrode; a third electrode located between the first electrode and the second electrode; a first insulating film located between the first electrode and the third electrode and / or between the second electrode and the third electrode; and a crystalline oxide semiconductor that penetrates at least the first insulating film and connects the first electrode and the second electrode, wherein the crystalline oxide semiconductor includes a first region adjacent to the third electrode without contact and a second region adjacent to the first insulating film, with or without contact, and the average carrier concentration in the second region is relatively higher than that in the first region.

2. The transistor according to claim 1, wherein the crystalline oxide semiconductor is provided in a columnar shape penetrating the first insulating film and the third electrode, the first region being the region in the crystalline oxide semiconductor penetrating the third electrode, and the second region being the region in the crystalline oxide semiconductor penetrating the first insulating film.

3. The transistor according to claim 1, wherein the first electrode, the first insulating film, the third electrode, the first insulating film, and the second electrode are stacked in this order, the crystalline oxide semiconductor is provided in a columnar shape penetrating the first insulating film and the third electrode, the first region is the region in the crystalline oxide semiconductor penetrating the third electrode, and the second region is the region in the crystalline oxide semiconductor penetrating the first insulating film.

4. The transistor according to claim 2 or 3, wherein the length in the height direction of the columnar crystalline oxide semiconductor is 2 to 1000 nm.

5. The transistor according to any one of claims 2 to 4, wherein the crystalline oxide semiconductor arranged in a columnar shape has a ratio of the height of the first region to the height of the second region of 10:1 to 1:

1.

6. The transistor according to any one of claims 1 to 5, wherein the composition ratio of the metal elements constituting the crystalline oxide semiconductor is substantially the same in the first region and the second region.

7. The transistor according to claim 6, wherein the first region includes a highly crystallized region having a relatively higher degree of crystallinity compared to the crystalline oxide semiconductor of the second region.

8. In each FFT pattern obtained by performing a fast Fourier transform on images obtained by irradiating the same area of ​​the first and second regions with an electron beam, the variation X of the FFT pattern calculated by the following formula is greater in the second region than in the first region, as described in claim 7. X = [Σ(luminance - average value of luminance in the FFT region)] ２ ] / number of samples (wherein the above formula, the FFT region is the region of the FFT pattern obtained by fast Fourier transforming the image, the brightness is the brightness of each spot in the FFT region, and the number of samples is the number of electron beam irradiations performed to obtain the image. The number of samples shall be 5.) 9. The transistor according to claim 8, wherein the crystal orientation in the electron diffraction pattern obtained by irradiating the crystalline oxide semiconductor with an electron beam includes a cubic crystal structure of indium oxide and is composed of at least one of the (211), (222), (400), (440), and (622) planes.

10. The transistor according to any one of claims 1 to 9, wherein the average hydrogen concentration in the second region is relatively higher than that in the first region.

11. The transistor according to any one of claims 1 to 10, wherein at least one of the first electrode and the second electrode is at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), aluminum (Al), silicon (Si), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), germanium (Ge), molybdenum (Mo), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), tantalum (Ta), iridium (Ir), platinum (Pt), tungsten (W), titanium (Ti), titanium nitride (TiN), aluminum nitride (AlN), manganese nitride (MnN), molybdenum nitride (MoN), and nickel nitride (Ni3N).

12. The transistor according to any one of claims 1 to 10, wherein at least one of the first electrode and the second electrode is at least one selected from the group consisting of iron (Fe), cobalt (Co), nickel (Ni), palladium (Pd), titanium (Ti), and titanium nitride (TiN).

13. The transistor according to any one of claims 1 to 12, further comprising a second insulating film provided between the third electrode and the crystalline oxide semiconductor.

14. The ratio of the average carrier concentration of the second region to the average carrier concentration of the first region (average carrier concentration of the second region / average carrier concentration of the first region) is between 2 and 10. ４ The transistor according to any one of claims 1 to 13.

15. The ratio of the average carrier concentration of the second region to the average carrier concentration of the first region (average carrier concentration of the second region / average carrier concentration of the first region) is 10 to 10 ４ The transistor according to claim 14.

16. The average carrier concentration in the first region is 10 １４ to 10 １８ cm －３ and the average carrier concentration in the second region is 10 １７ to 10 ２２ cm －３ The transistor according to any one of claims 1 to 15.

17. The ratio of the average hydrogen concentration of the second region to the average hydrogen concentration of the first region (average hydrogen concentration of the second region / average hydrogen concentration of the first region) is 5 to 5 × 10⁻⁶. ３ The transistor according to any one of claims 1 to 16.

18. The transistor according to any one of claims 1 to 17, wherein the crystalline oxide semiconductor includes a bixbyte crystal structure.

19. The transistor according to any one of claims 1 to 18, wherein the crystalline oxide semiconductor contains indium oxide as the main component.

20. The transistor according to any one of claims 1 to 19, wherein the crystalline oxide semiconductor comprises Ga or Al.

21. The transistor according to any one of claims 1 to 19, wherein the crystalline oxide semiconductor includes Ga.

22. The transistor according to any one of claims 1 to 19, wherein the crystalline oxide semiconductor comprises Ga and Al.

23. The transistor according to any one of claims 1 to 22, wherein the crystalline oxide semiconductor is a polycrystalline oxide semiconductor.

24. The transistor according to any one of claims 1 to 22, wherein the crystalline oxide semiconductor is a single-crystal oxide semiconductor.

25. The transistor according to any one of claims 1 to 24, wherein the crystalline oxide semiconductor is a crystalline oxide semiconductor formed by atomic layer deposition.

26. A semiconductor device comprising a transistor according to any one of claims 1 to 25.

27. The semiconductor device according to claim 26, which is a semiconductor memory device.

28. A device comprising: a first electrode; a second electrode; a third electrode located between the first electrode and the second electrode; a first insulating film located between the first electrode and the third electrode and / or between the second electrode and the third electrode; and a crystalline oxide semiconductor that penetrates at least the first insulating film and connects the first electrode and the second electrode, wherein the crystalline oxide semiconductor includes a bixbyte crystal structure, the crystalline oxide semiconductor includes a first region adjacent to the third electrode without contact, and a second region adjacent to the first insulating film with or without contact, the average carrier concentration in the second region is relatively higher than that in the first region, the composition ratio of the metal elements constituting the crystalline oxide semiconductor is substantially the same in the first and second regions, and the first region includes a highly crystallized region with a relatively higher degree of crystallinity compared to the crystalline oxide semiconductor in the second region. In each FFT pattern obtained by irradiating the same area of ​​the first and second regions with an electron beam and performing a Fast Fourier Transform on the resulting image, the variation X of the FFT pattern calculated by the following formula is greater in the second region than in the first region: X = 1 / number of samples × Σ (luminance - average luminance in the FFT region) ２ (However, in the above formula, the FFT region is the region of the FFT pattern obtained by performing a fast Fourier transform on the image, the brightness is the brightness of each spot in the FFT region, and the sampling number is the number of electron beam irradiations performed to obtain the image.) Transistor.

29. A transistor comprising: a first electrode; a second electrode; a third electrode located between the first electrode and the second electrode; a first insulating film located between the first electrode and the third electrode and / or between the second electrode and the third electrode; and a crystalline oxide semiconductor that penetrates at least the first insulating film and connects the first electrode and the second electrode, wherein the crystalline oxide semiconductor includes a bixbyte crystal structure, the crystalline oxide semiconductor includes a first region adjacent to the third electrode without contact, and a second region adjacent to the first insulating film with or without contact, the average carrier concentration in the second region being relatively higher than that in the first region, the average hydrogen concentration in the second region being relatively higher than that in the first region, and at least one of the first electrode and the second electrode being at least one selected from the group consisting of iron (Fe), cobalt (Co), nickel (Ni), palladium (Pd), titanium (Ti), and titanium nitride (TiN).

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