Transistor and semiconductor device

Abstract

This transistor includes: a first electrode and a second electrode; a first crystal oxide semiconductor provided in contact with the first electrode and / or the second electrode; a second crystal oxide semiconductor connecting the first electrode and the second electrode via the first crystal oxide semiconductor; and a third electrode adjacent to the second crystal oxide semiconductor without being in contact therewith. The first electrode and the second electrode are laminated via at least a first insulating film. The lattice constant of the first crystal oxide semiconductor is larger than the lattice constant of the second crystal oxide semiconductor.

Description

Transistors and semiconductor devices

[0001] This invention relates to transistors and semiconductor devices. Specifically, this invention relates to transistors and semiconductor devices that can improve contact resistance.

[0002] Transistors using an amorphous oxide semiconductor layer, such as indium gallium zinc oxide (IGZO), as the channel are known (Patent Documents 1 and 2). When such an oxide semiconductor layer is used as the channel, a high-resistance metal oxide layer may form between the oxide semiconductor layer and the metal electrode, increasing the contact resistance between the oxide semiconductor layer and the metal electrode. To suppress the increase in contact resistance, Patent Documents 1 and 2 propose interposing a specific oxide layer between the oxide semiconductor layer and the metal electrode.

[0003] Japanese Patent Publication No. 2017-168623 Japanese Patent Publication No. 2019-134077

[0004] However, conventional technologies, including those described in Patent Documents 1 and 2, had room for further improvement in terms of improving contact resistance in transistors.

[0005] One of the objectives of the present invention is to provide transistors and semiconductor devices that can improve contact resistance.

[0006] As a result of diligent research, the present inventors have found that contact resistance can be improved by using a crystalline oxide semiconductor (second crystalline oxide semiconductor) as the oxide semiconductor, interposing a crystalline oxide semiconductor (first crystalline oxide semiconductor) between the oxide semiconductor and the electrode, and making the lattice constant of the first crystalline oxide semiconductor larger than that of the second crystalline oxide semiconductor, thereby completing the present invention. According to the present invention, the following transistors and the like can be provided: 1. A transistor comprising: a first electrode and a second electrode; a first crystalline oxide semiconductor provided in contact with the first electrode and / or the second electrode; a second crystalline oxide semiconductor connecting the first electrode and the second electrode via the first crystalline oxide semiconductor; and a third electrode adjacent to the second crystalline oxide semiconductor without contact with the second crystalline oxide semiconductor, wherein the first electrode and the second electrode are stacked with at least a first insulating film in between, and the lattice constant of the first crystalline oxide semiconductor is larger than that of the second crystalline oxide semiconductor. 2. The transistor according to 1, wherein the first crystalline oxide semiconductor has a higher average carrier concentration than the second crystalline oxide semiconductor. 3. 1. A transistor according to 1 or 2, wherein the composition of the metal elements constituting the first crystalline oxide semiconductor and the composition of the metal elements constituting the second crystalline oxide semiconductor are substantially the same. 4. A transistor according to 3, wherein the composition ratio of the metal elements constituting the first crystalline oxide semiconductor and the composition ratio of the metal elements constituting the second crystalline oxide semiconductor are substantially the same. 5. A transistor according to any one of 1 to 4, wherein the ratio of the lattice constant of the second crystalline oxide semiconductor to the lattice constant of the first crystalline oxide semiconductor is 0.940 or more and 0.999 or less. 6. A transistor according to any one of 1 to 5, wherein the thickness of the first crystalline oxide semiconductor is 2 nm or more and 100 nm or less. 7. A transistor according to any one of 1 to 6, further comprising a second insulating film provided between the third electrode and the second crystalline oxide semiconductor. 8. A transistor according to any one of 1 to 7, wherein the second crystalline oxide semiconductor penetrates at least the first insulating film.9. The transistor according to any one of 1 to 8, wherein the first electrode and the third electrode are stacked via the first insulating film, the third electrode and the second electrode are stacked via the third insulating film, and the second crystalline oxide semiconductor is provided in a columnar shape penetrating the first insulating film, the third electrode and the third insulating film. 10. The transistor according to any one of 1 to 6, wherein the second crystalline oxide semiconductor is provided in a columnar shape penetrating the first electrode and the first insulating film, and the inner circumferential surface and bottom surface of a recess formed from one end to the other of the columnar second crystalline oxide semiconductor are further provided with a second insulating film, and the third electrode is provided so as to fill the recess in which the second insulating film is formed. 11. A transistor according to any one of 1 to 10, wherein at least one of the first electrode and the second electrode is selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), aluminum (Al), silicon (Si), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), germanium (Ge), molybdenum (Mo), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), tantalum (Ta), iridium (Ir), platinum (Pt), tungsten (W), titanium (Ti), titanium nitride (TiN), aluminum nitride (AlN), manganese nitride (MnN), molybdenum nitride (MoN), and nickel nitride (Ni3N). 12. A transistor according to any one of 1 to 11, wherein at least one of the group consisting of the first crystalline oxide semiconductor and the second crystalline oxide semiconductor includes a Bixbyte crystal structure. 13. A transistor according to any one of 1 to 12, wherein at least one selected from the group consisting of the first crystalline oxide semiconductor and the second crystalline oxide semiconductor contains indium oxide as the main component. 14. A transistor according to any one of 1 to 13, wherein at least one selected from the group consisting of the first crystalline oxide semiconductor and the second crystalline oxide semiconductor contains Ga or Al.15. A transistor according to any one of 1 to 13, wherein at least one selected from the group consisting of the first crystalline oxide semiconductor and the second crystalline oxide semiconductor contains Ga. 16. A transistor according to any one of 1 to 13, wherein at least one selected from the group consisting of the first crystalline oxide semiconductor and the second crystalline oxide semiconductor contains Ga and Al. 17. A transistor according to any one of 1 to 16, wherein at least one selected from the group consisting of the first crystalline oxide semiconductor and the second crystalline oxide semiconductor is a polycrystalline oxide semiconductor. 18. A transistor according to any one of 1 to 16, wherein at least one selected from the group consisting of the first crystalline oxide semiconductor and the second crystalline oxide semiconductor is a single-crystal oxide semiconductor. 19. A transistor according to any one of 1 to 18, wherein at least one selected from the group consisting of the first crystalline oxide semiconductor and the second crystalline oxide semiconductor is a crystalline oxide semiconductor formed by atomic layer deposition. 20. A semiconductor device including the transistor according to any one of 1 to 19. 21. A semiconductor device according to 20, which is a semiconductor memory device. 22. A transistor comprising: a first electrode and a second electrode; a first crystalline oxide semiconductor provided in contact with the first electrode and / or the second electrode; a second crystalline oxide semiconductor connecting the first electrode and the second electrode via the first crystalline oxide semiconductor; and a third electrode adjacent to the second crystalline oxide semiconductor without contact with the second crystalline oxide semiconductor, wherein the first electrode and the second electrode are stacked with at least a first insulating film in between; the lattice constant of the first crystalline oxide semiconductor is greater than the lattice constant of the second crystalline oxide semiconductor; the composition ratio of the metal elements constituting the first crystalline oxide semiconductor and the composition ratio of the metal elements constituting the second crystalline oxide semiconductor are substantially the same; the ratio of the lattice constant of the second crystalline oxide semiconductor to the lattice constant of the first crystalline oxide semiconductor is 0.940 or more and 0.999 or less; the thickness of the first crystalline oxide semiconductor is 2 nm or more and 100 nm or less; and the first crystalline oxide semiconductor and the second crystalline oxide semiconductor include a bixbyte crystal structure.

[0007] According to the present invention, it is possible to provide transistors and semiconductor devices that can improve contact resistance.

[0008] This is a schematic perspective view showing a cross-section of a transistor according to the first embodiment. This is a schematic cross-sectional view of a transistor according to the first embodiment. This is a diagram illustrating an example of a method for manufacturing a transistor according to the first embodiment. This is a schematic perspective view showing a cross-section of a transistor according to the second embodiment. This is a schematic cross-sectional view of a transistor according to the second embodiment. This is a schematic perspective view showing a cross-section of a transistor according to the third embodiment. This is a schematic cross-sectional view of a transistor according to the third embodiment. This is a diagram showing an example of a circuit configuration of a semiconductor memory device.

[0009] The transistors and semiconductor devices of the present invention will be described in detail below. In this specification, "x to y" represents a numerical range of "x or more, and y or less". The upper and lower limits described for the numerical range can be combined in any way. Furthermore, it is possible to combine two or more non-conflicting embodiments of the embodiments of the present invention described below, and an embodiment that combines two or more embodiments is also an embodiment of the embodiments of the present invention.

[0010] 1. Transistor A transistor according to one aspect of the present invention comprises: a first electrode and a second electrode; a first crystalline oxide semiconductor provided in contact with the first electrode and / or the second electrode; a second crystalline oxide semiconductor connecting the first electrode and the second electrode via the first crystalline oxide semiconductor; and a third electrode adjacent to the second crystalline oxide semiconductor without contact with the second crystalline oxide semiconductor, wherein the first electrode and the second electrode are stacked with at least a first insulating film in between, and the lattice constant of the first crystalline oxide semiconductor is greater than the lattice constant of the second crystalline oxide semiconductor. The transistor according to this aspect provides the effect of improving contact resistance. More specifically, the transistor according to this aspect uses a crystalline oxide semiconductor (second crystalline oxide semiconductor) as the oxide semiconductor connecting the first electrode and the second electrode, and also interposes a crystalline oxide semiconductor (first crystalline oxide semiconductor) between the oxide semiconductor and the electrode, and the lattice constant of the first crystalline oxide semiconductor is greater than the lattice constant of the second crystalline oxide semiconductor. This method utilizes the fact that the resistance of the first crystalline oxide semiconductor, which has a relatively large lattice constant, is lower than that of the second crystalline oxide semiconductor, which has a relatively small lattice constant. Normally, when an oxide semiconductor is formed on a metal electrode, a high-resistance metal oxide layer is formed at the interface between the electrode (first electrode and / or second electrode) and the oxide semiconductor, which tends to increase contact resistance. However, in this embodiment, as described above, the resistance of the first crystalline oxide semiconductor in the region in contact with the electrode (first electrode and / or second electrode) is low, thus improving the contact resistance of the transistor.

[0011] (First Embodiment) An example of a transistor according to this embodiment (first embodiment) will be described below with reference to Figures 1 and 2. Figure 1 is a schematic perspective view showing a cross-section of the transistor according to the first embodiment. Figure 2 is a schematic cross-sectional view of the transistor. In this embodiment, the transistor 10 includes a first electrode 11, a second electrode 12, a third electrode 13, a first crystalline oxide semiconductor 151a, 151b, a second crystalline oxide semiconductor 152, a first insulating film 14a, and a third insulating film 14b. The first electrode 11 and the second electrode 12 are stacked with at least the first insulating film 14a (here, the first insulating film 14a and the third insulating film 14b) in between. In this context, "stacked" means that at least a portion of the first electrode 11 and at least a portion of the second electrode 12 are arranged along a direction perpendicular to the plane direction of the substrate (not shown) supporting the transistor 10. Also, although not shown, when multiple transistors 10 are connected in a planar manner (in the X-Y direction) (when multiple transistors 10 form a transistor array), at least a portion of the first electrode 11 and at least a portion of the second electrode 12 are arranged along a direction perpendicular to the plane direction (Z direction). At least a portion of the first insulating film 14a may be interposed between the first electrode 11 and the second electrode 12. The third electrode is provided adjacent to the second crystalline oxide semiconductor 152 without contact. The third electrode 13 is located between the first electrode 11 and the second electrode 12.

[0012] Of the first insulating film 14a and the third insulating film 14b, the first insulating film 14a is located between the first electrode 11 and the third electrode 13. As a result, the first electrode 11 and the third electrode 13 are electrically insulated by the first insulating film 14a. The third insulating film 14b is located between the second electrode 12 and the third electrode 13. As a result, the second electrode 12 and the third electrode 13 are electrically insulated by the third insulating film 14b.

[0013] In the region shown in Figure 2, the third electrode 13 is positioned between the first insulating film 14a and the third insulating film 14b. However, outside the region shown in Figure 2, the first insulating film 14a and the third insulating film 14b may be in contact with each other, forming a single layer. In this case, the third electrode 13 does not need to be positioned between the first insulating film 14a and the third insulating film 14b in that region.

[0014] The second crystalline oxide semiconductor 152 penetrates at least the first insulating film 14a and is provided to connect the first electrode 11 and the second electrode 12. In addition to the first insulating film 14a, the second crystalline oxide semiconductor 152 may also penetrate the third electrode 13 and / or the third insulating film 14b. Here, the second crystalline oxide semiconductor 152 is provided in a columnar shape, penetrating the first insulating film 14a, the third electrode 13, and the third insulating film 14b in this order. In this case, it is preferable that the third electrode 13 surrounds the side (around the circumference perpendicular to the length direction) of the second crystalline oxide semiconductor 152 over its entire circumference in a portion of the length direction of the second crystalline oxide semiconductor 152 (the central portion in the example of Figure 2) via the second insulating film 16 described later. This makes it easier to prevent leakage current even if the channel length of the crystalline oxide semiconductor 15 described later is shortened. At the same time, it is also advantageous in terms of miniaturization. Furthermore, the length direction of the crystalline oxide semiconductor 15 as referred to here may be the vertical direction in Figure 2 (the direction connecting the first electrode and the second electrode), the direction along the channel length described later, the thickness direction of the laminate in which the first insulating film 14a, the third electrode 13, and the first insulating film 14b are stacked in this order, and, if the crystalline oxide semiconductor 15 is columnar, the height direction of the columnar structure.

[0015] The transistor 10 further comprises a second insulating film 16 provided at least between the third electrode 13 and the second crystalline oxide semiconductor 152. The second insulating film 16 may be provided between the third electrode 13 and the second crystalline oxide semiconductor 152 to insulate them. In addition to being provided between the third electrode 13 and the second crystalline oxide semiconductor 152, the second insulating film 16 may also be provided, for example, between the first insulating film 14a and / or the third insulating film 14b and the second crystalline oxide semiconductor 152. Here, the second insulating film 16 is provided so as to surround the entire circumference of the columnar second crystalline oxide semiconductor 152.

[0016] The first crystalline oxide semiconductors 151a and 151b are provided in contact with the first electrode 11 and the second electrode 12, respectively. Specifically, the first crystalline oxide semiconductor 151a is laminated on the surface of the first electrode 11 facing the second crystalline oxide semiconductor 152. The first crystalline oxide semiconductor 151b is laminated on the surface of the second electrode 12 facing the second crystalline oxide semiconductor 152. The second crystalline oxide semiconductor 152 connects the first electrode 11 and the second electrode 12 via the first crystalline oxide semiconductors 151a and 151b. It is preferable that the second crystalline oxide semiconductor 152 is provided in contact with the first crystalline oxide semiconductors 151a and 151b.

[0017] From one perspective, it can be said that the transistor 10 has a through-hole that penetrates the thickness direction (up and down direction in Figures 1 and 2) of a laminate in which the first insulating film 14a, the third electrode 13, and the third insulating film 14b are stacked in this order, the inner circumferential surface of the through-hole is covered with a cylindrical second insulating film 16, and the inside of the cylindrical second insulating film 16 is filled with a second crystalline oxide semiconductor 152.

[0018] The dimensions of the transistor 10 may be designed as appropriate depending on its application. The channel length of the second crystalline oxide semiconductor 152 is, for example, 1 nm to 10 μm, preferably 2 to 1000 nm, more preferably 3 to 100 nm, even more preferably 4 to 50 nm, even more preferably 5 to 30 nm, and even more preferably 6 to 20 nm. The channel length of the second crystalline oxide semiconductor 152 is the length of the second crystalline oxide semiconductor 152 along the thickness direction (vertical direction in Figures 1 and 2) of the laminate in which the first insulating film 14a, the third electrode 13, and the third insulating film 14b are stacked in this order, and may coincide with the distance between the first electrode 11 and the second electrode 12 (or the distance between the first crystalline oxide semiconductors 151a and 151b). If the second crystalline oxide semiconductor 152 is columnar, the channel length of the second crystalline oxide semiconductor 152 corresponds to the height of the columnar structure. The channel length of the second crystalline oxide semiconductor 152 can be measured by exposing the relevant area by processing it with a focused ion beam (FIB) and observing the cross-section with a transmission electron microscope (TEM).

[0019] The channel width of the second crystalline oxide semiconductor 152 is, for example, 1 nm to 1000 nm, preferably 2 nm to 500 nm. The channel width of the second crystalline oxide semiconductor 152 is the length of the second crystalline oxide semiconductor 152 along the direction perpendicular to the thickness direction of the laminate in which the first insulating film 14a, the third electrode 13, and the third insulating film 14b are stacked in this order (for example, the left-right direction in Figure 2). As shown in Figures 1 and 2, if the channel width of the second crystalline oxide semiconductor 152 is not constant with respect to the channel length direction, the channel width of the second crystalline oxide semiconductor 152 may be the average width along the channel length direction. The average width along the channel length direction is the average value obtained when the channel width is measured at 10 or more locations along the channel length direction. If the second crystalline oxide semiconductor 152 is columnar, the channel width of the second crystalline oxide semiconductor 152 corresponds to the width of the columnar structure. Furthermore, if the channel width of the second crystalline oxide semiconductor 152 differs depending on the observation direction (for example, if the channel width differs when observed from a direction perpendicular to the plane of Figure 2 and when observed from the left or right direction in Figure 2), the channel width when observed from at least one direction may be within the above range.

[0020] The thickness of the second insulating film 16 is, for example, 1 Å to 500 nm, preferably 1 nm to 100 nm. In order to suppress the capacitance of the second insulating film 16 from becoming a parasitic component, the thickness of the second insulating film 16 may be 50 nm or less, 10 nm or less, or 2 nm or less.

[0021] The thickness of the first crystalline oxide semiconductors 151a and 151b is, for example, 1 Å to 500 nm, preferably 1 nm to 200 nm, and more preferably 2 nm to 100 nm. By having the thickness of the first crystalline oxide semiconductors 151a and 151b within the above range, the contact resistance between the electrodes (first electrode and / or second electrode) and the second crystalline oxide semiconductor can be further reduced.

[0022] The channel width of the second crystalline oxide semiconductor 152, the thickness of the second insulating film 16, and the thicknesses of the first crystalline oxide semiconductors 151a and 151b can be measured in the same manner as the channel length of the second crystalline oxide semiconductor 152.

[0023] In transistor 10, the first electrode 11 can function as a source electrode, and the second electrode 12 can function as a drain electrode. In other examples, the first electrode 11 can function as a drain electrode, and the second electrode 12 can function as a source electrode. The third electrode 13 can function as a gate electrode. The first crystalline oxide semiconductors 151a, 151b and the second crystalline oxide semiconductor 152 can function as channels (current paths) of transistor 10. For example, when a gate voltage is applied to the third electrode 13, which is the gate electrode, the first electrode 11 and the second electrode 12 are electrically connected by the first crystalline oxide semiconductors 151a, 151b and the second crystalline oxide semiconductor 152, and transistor 10 is in the ON state. When no gate voltage is applied, the electrical connection between the first electrode 11 and the second electrode 12 by the first crystalline oxide semiconductors 151a, 151b and the second crystalline oxide semiconductor 152 is released, and transistor 10 is in the OFF state.

[0024] Furthermore, in this specification, "electrically connected" includes cases where connections are made via "something that has some kind of electrical function." Here, "something that has some kind of electrical function" is not particularly limited as long as it enables the exchange of electrical signals between the connected objects.

[0025] One feature of this embodiment is that the lattice constants of the first crystalline oxide semiconductors 151a and 151b are greater than the lattice constant of the second crystalline oxide semiconductor 152. This utilizes the fact that the average carrier concentration is higher and the resistance value decreases in the first crystalline oxide semiconductors 151a and 151b, which have a relatively larger lattice constant than the second crystalline oxide semiconductor 152, which has a relatively smaller lattice constant. Normally, when an oxide semiconductor is formed on a metal electrode, a high-resistance metal oxide layer is formed at the interface between the electrode (first electrode 11 and / or second electrode 12) and the oxide semiconductor, and the contact resistance tends to increase. However, in this embodiment, as described above, the resistance value of the first crystalline oxide semiconductors 151a and 151b in the region in contact with the electrode (first electrode 11 and / or second electrode 12) is low, so the contact resistance of the transistor 10 can be improved. The lattice constant of the crystalline oxide semiconductor may be measured by micro-region XRD (micro-region X-ray diffraction) or electron diffraction at the relevant location. Examples of electron diffraction methods include SEM-EDX (scanning electron microscope energy-dispersive X-ray spectroscopy) and TEM-EDX (transmission electron microscope energy-dispersive X-ray spectroscopy), with TEM-EDX being preferred.

[0026] In one embodiment, the ratio of the lattice constant of the second crystalline oxide semiconductor 152 to the lattice constant of the first crystalline oxide semiconductors 151a and 151b (lattice constant of the second crystalline oxide semiconductor / lattice constant of the first crystalline oxide semiconductor) is, for example, 0.940 or more and 0.999 or less, preferably 0.950 or more and 0.990 or less, and more preferably 0.960 or more and 0.985 or less.

[0027] The crystalline oxide semiconductors used as the first crystalline oxide semiconductors 151a, 151b, and the second crystalline oxide semiconductor 152 can be any crystalline oxide capable of functioning as a semiconductor. The first crystalline oxide semiconductor 151a, the first crystalline oxide semiconductor 151b, and the second crystalline oxide semiconductor 152 may be independently selected from the crystalline oxide semiconductors exemplified below. The first crystalline oxide semiconductor 151a and the first crystalline oxide semiconductor 151b may be the same or different.

[0028] Examples of crystalline oxide semiconductors include metal oxides. Metals included in metal oxides include In, Ga, Zn, Al, and Sn. Specific examples of metal oxides include indium oxide (IO), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium gallium aluminum oxide (IGAO), indium gallium tin zinc oxide (IGTZO), and indium tin zinc oxide (ITZO).

[0029] In one embodiment, the crystalline oxide semiconductor contains indium atoms (In). In one embodiment, the ratio of indium atoms to the total metal atoms contained in the crystalline oxide semiconductor is 80 atomic% or more, 90 atomic% or more, or 95 atomic% or more. The content (atomic ratio) of each metal element in the crystalline oxide semiconductor can be analyzed by TEM-EDS (Energy Dispersive X-ray Spectroscopy) measurement using an electron microscope.

[0030] In one embodiment, the crystalline oxide semiconductor contains indium oxide as its main component. "Containing indium oxide as its main component" means that more than 50% by mass of the material constituting the crystalline oxide semiconductor is indium oxide.

[0031] In one embodiment, the crystalline oxide semiconductor comprises indium oxide (IO), indium gallium oxide (IGO), or indium gallium aluminum oxide (IGAO). In one embodiment, the crystalline oxide semiconductor may contain 55% by mass or more, 60% by mass or more, 70% by mass or more, 80% by mass or more, 90% by mass or more, 95% by mass or more, 97% by mass or more, 98% by mass or more, or 99% by mass, or 100% by mass.

[0032] In one embodiment, the crystalline oxide semiconductor further contains a trivalent metal. The trivalent metal is preferably Ga and Al, with Ga being more preferred. In one embodiment, the crystalline oxide semiconductor further contains Ga or Al, may contain Ga, may contain Al, or may contain both Ga and Al. In one embodiment, the atomic ratio of the trivalent metal to all metal elements contained in the crystalline oxide semiconductor ([trivalent metal] / ([trivalent metal] + [all metal elements other than the trivalent metal]) × 100) may be 0 to 30 at%, 1 to 25 at%, 2 to 22 at%, or 3 to 20 at%. Here, "trivalent metal" may be read as Ga and Al. In one embodiment, the atomic ratio of Ga to all metal elements contained in the crystalline oxide semiconductor ([Ga] / ([Ga] + [all metal elements other than Ga]) × 100) may be 0 to 30 at%, 1 to 25 at%, 2 to 22 at%, or 3 to 20 at%. In one embodiment, the atomic ratio of Al to all metal elements contained in the crystalline oxide semiconductor ([Al] / ([Al] + [all metal elements other than Al]) × 100) may be 0 to 30 at%, 1 to 25 at%, 2 to 22 at%, or 3 to 20 at%.

[0033] In one embodiment, the crystalline oxide semiconductor further includes one or more additive elements selected from B, Si, Sc, Zn, Ce, Y, Zr, Sn, Sm, Hf, Ta, and Yb. In one embodiment, the atomic ratio of the total amount of additive elements to the total amount of metal elements contained in the crystalline oxide semiconductor ([total amount of additive elements] / ([total amount of additive elements] + [total metal elements other than additive elements]) × 100) is 0 to 10 at%, and may be 0.1 to 8 at%, 0.5 to 5 at%, or 1 to 3 at%.

[0034] In one embodiment, the crystalline oxide semiconductor includes a bixbite crystal structure. The presence or absence of a bixbite structure can be determined based on the X-ray diffraction pattern in XRD or the electron diffraction spots in electron diffraction. In one embodiment, the crystalline oxide semiconductor is an In having a bixbite crystal structure. ２ O ３ Includes phase.

[0035] In one embodiment, the crystalline oxide semiconductor is a polycrystalline oxide semiconductor or a single-crystal oxide semiconductor. In one embodiment, the crystalline oxide semiconductor is a polycrystalline oxide semiconductor. In one embodiment, the crystalline oxide semiconductor is a single-crystal oxide semiconductor.

[0036] Here, whether a crystalline oxide semiconductor is a polycrystalline oxide semiconductor or a single-crystal oxide semiconductor can be determined, for example, by electron backscatter diffraction (EBSD). If the crystal orientations measured by EBSD are aligned and no grain boundaries are observed, it can be determined to be a single-crystal oxide semiconductor. Conversely, if grain boundaries are observed, it can be determined to be a polycrystalline oxide semiconductor. When the difference in crystal orientation between two adjacent measurement points exceeds 5°, it can be defined that a grain boundary exists between them.

[0037] The method for making the lattice constants of the first crystalline oxide semiconductors 151a and 151b larger than the lattice constant of the second crystalline oxide semiconductor 152 is not particularly limited. For example, one method is to use crystalline oxide semiconductors having a lattice constant larger than that of the second crystalline oxide semiconductor 152 as the first crystalline oxide semiconductors 151a and 151b. In this case, the first crystalline oxide semiconductors 151a and 151b and the second crystalline oxide semiconductor 152 can be made to be crystalline oxide semiconductors with different compositions. In one embodiment, the lattice constant of the second crystalline oxide semiconductor 152 may be made relatively smaller by using a crystalline oxide semiconductor doped with an element with a small atomic radius as the second crystalline oxide semiconductor 152. Another method involves different formation conditions for the first crystalline oxide semiconductors 151a, 151b and the second crystalline oxide semiconductor 152, such that the lattice constants of the first crystalline oxide semiconductors 151a and 151b are greater than the lattice constant of the second crystalline oxide semiconductor 152. In this case, the compositions of the first crystalline oxide semiconductors 151a and 151b and the second crystalline oxide semiconductor 152 may be substantially the same or different. In one embodiment, the lattice constant of the second crystalline oxide semiconductor 152 may be made relatively smaller by forming the first crystalline oxide semiconductors 151a and 151b using a vapor phase crystallization method and forming the second crystalline oxide semiconductor 152 using a solid phase crystallization method.

[0038] In this specification, solid-phase crystallization refers to a method of forming a crystalline oxide semiconductor by annealing after forming an amorphous oxide semiconductor, while vapor-phase crystallization refers to a method of forming a crystalline oxide semiconductor directly without going through the formation of an amorphous oxide semiconductor. Compared to a crystalline oxide semiconductor formed by solid-phase crystallization, a crystalline oxide semiconductor formed by vapor-phase crystallization has relatively larger strain in the crystal, and relatively larger lattice constant and carrier concentration. The solid-phase crystallization method and the vapor-phase crystallization method may be selected by appropriately adjusting the oxide semiconductor formation conditions described later. Specifically, a crystalline oxide semiconductor is formed by vapor-phase crystallization by selecting conditions under which the oxide semiconductor crystallizes at a low temperature.

[0039] In ２ O ３ A crystalline oxide semiconductor containing is exemplified and described. For example, (i) In formed by a vapor phase crystallization method ２ O ３ , (ii) In formed by a solid phase crystallization method ２ O ３ , and (iii) In doped (solid solution substitution) with Ga and / or Al ２ O ３ are taken as examples. Their lattice constants are (i) > (ii) > (iii), and the average carrier concentration is (i) > (ii) > (iii). It can be said that the higher the average carrier concentration, the lower the resistance value. Here, the layer of In ２ O ３ preferably has a bixbyite crystal structure.

[0040] Further, regarding (iii) In doped (solid solution substitution) with Ga and / or Al ２ O ３ in more detail, the higher the content of Ga and Al (atomic ratio to In), the smaller the lattice constant tends to be. Also, when the contents of Ga and Al are about the same, the lattice constant is larger when formed by the vapor phase crystallization method than when formed by the solid phase crystallization method.

[0041] For example, as the first crystalline oxide semiconductors 151a and 151b, vapor phase crystallized In ２ O ３ is used, and as the second crystalline oxide semiconductor 152, solid phase crystallized In ２ O ３、 or In doped (solid solution substitution) with Ga and / or Al ２ O ３ can be used. Also, for example, as the first crystalline oxide semiconductors 151a and 151b, vapor phase crystallized In ２ O ３ or solid phase crystallized In ２ O ３ is used, and as the second crystalline oxide semiconductor 152, In doped (solid solution substitution) with Ga and / or Al ２ O ３This can be used. Also, for example, as the first crystalline oxide semiconductors 151a and 151b, a vapor-phase crystallized oxide semiconductor (for example, In ２ O ３ It may be In which Ga and / or Al doped (solid solution substituted) ２ O ３ It may be so.) and use a solid-phase crystallized oxide semiconductor (for example, In) as the second crystalline oxide semiconductor 152. ２ O ３ It may be In which Ga and / or Al doped (solid solution substituted) ２ O ３ It may be the case that ) can be used. In this case, the first crystalline oxide semiconductors 151a and 151b and the second crystalline oxide semiconductor 152 may have substantially the same metal element composition.

[0042] For example, the composition of the metal elements constituting the first crystalline oxide semiconductors 151a and 151b may be substantially the same as the composition of the metal elements constituting the second crystalline oxide semiconductor 152. The composition ratios of the metal elements constituting these crystalline oxide semiconductors may be substantially the same. Furthermore, the composition of the metal elements constituting the first crystalline oxide semiconductor 151a may be substantially the same as the composition of the metal elements constituting the second crystalline oxide semiconductor 152. The composition ratios of the metal elements constituting these crystalline oxide semiconductors may be substantially the same. Furthermore, the composition of the metal elements constituting the first crystalline oxide semiconductor 151b may be substantially the same as the composition of the metal elements constituting the second crystalline oxide semiconductor 152. The composition ratios of the metal elements constituting these crystalline oxide semiconductors may be substantially the same. Furthermore, the composition of the metal elements constituting the first crystalline oxide semiconductor 151a may be substantially the same as the composition of the metal elements constituting the first crystalline oxide semiconductor 151b. The composition ratios of the metal elements constituting these crystalline oxide semiconductors may be substantially the same. In this specification, "identical composition of metal elements" means that the types of metal elements constituting the crystalline oxide semiconductor are identical. In this case, the content ratio of each metal element constituting the crystalline oxide semiconductor may also be identical. Furthermore, "substantially identical" composition of metal elements means that, excluding unavoidable impurities, the composition of metal elements is identical. Examples of unavoidable impurities include components leached from electrodes. Furthermore, "identical composition ratio of metal elements" means that the types of metal elements constituting the crystalline oxide semiconductor are identical, and their content ratios are also identical. Furthermore, "substantially identical" composition of metal elements means that, excluding unavoidable impurities, the composition ratio of metal elements is identical. Even with combinations of crystalline oxide semiconductors having substantially identical metal element compositions, the lattice constant can be adjusted by differentiating the film deposition process, as described above. By applying crystalline oxide semiconductors with substantially identical metal element compositions to the above-described components, manufacturing efficiency can be improved.

[0043] Each of the first electrode 11, the second electrode 12, and the third electrode 13 is not particularly limited as long as they are conductors. Examples of conductors include indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), aluminum (Al), silicon (Si), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), germanium (Ge), molybdenum (Mo), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), tantalum (Ta), iridium (Ir), platinum (Pt), tungsten (W), titanium (Ti), titanium nitride (TiN), aluminum nitride (AlN), manganese nitride (MnN), molybdenum nitride (MoN), and nickel nitride (Ni3N).

[0044] The first insulating film 14a, the third insulating film 14b, and the second insulating film 16 are not particularly limited as long as they contain an insulator or are films made of an insulator. Examples of insulators include aluminum oxide, magnesium oxide, silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Furthermore, the first insulating film 14a, the third insulating film 14b, and the second insulating film 16 may each be a laminated film of the above materials. The insulating films may also contain La, N, Zr, etc. The insulators contained in the first insulating film 14a, the third insulating film 14b, and the second insulating film 16 may be the same or different from each other.

[0045] In this embodiment, the first crystalline oxide semiconductors 151a and 151b are located further from the third electrode 13 than the second crystalline oxide semiconductor 152. Therefore, even when a gate voltage is applied to the third electrode 13, the vicinity regions of the first crystalline oxide semiconductors 151a and 151b are inherently less susceptible to carrier induction and tend to become contact-resistant. However, as described above, because the lattice constants of the first crystalline oxide semiconductors 151a and 151b are greater than those of the second crystalline oxide semiconductor 152, the average carrier concentration of the first crystalline oxide semiconductors 151a and 151b is selectively increased, preventing the vicinity regions of the first crystalline oxide semiconductors 151a and 151b from becoming contact-resistant. This also contributes to improving the contact resistance of the transistor 10.

[0046] The relatively large lattice constants of the first crystalline oxide semiconductors 151a and 151b selectively increase the average carrier concentration, making it possible to raise the average carrier concentration of the first crystalline oxide semiconductors 151a and 151b above that of the second crystalline oxide semiconductor 152. The average carrier concentration is the average value of the carrier concentrations in each oxide semiconductor. If the oxide semiconductor is an n-type semiconductor, the carrier concentration is the electron density. If the oxide semiconductor is a p-type semiconductor, the carrier concentration is the hole density. Furthermore, the fact that the average carrier concentration of the first crystalline oxide semiconductors 151a and 151b is higher than that of the second crystalline oxide semiconductor 152 can be determined by the tunneling current flowing when scanning the surface of each region using a STEM (scanning tunneling electron microscope). When using a STEM, a two-dimensional carrier concentration distribution can be observed with a spatial resolution of 1 nm. Therefore, not only can the relative average carrier concentrations of the first crystalline oxide semiconductors 151a and 151b and the second crystalline oxide semiconductor 152 be determined, but the absolute value of the average carrier concentration in each region can also be determined.

[0047] In one embodiment, the average carrier concentration in the second crystalline oxide semiconductor 152 is 10 １４ ~10 １８ cm －３ In one embodiment, the average carrier concentration in the first crystalline oxide semiconductor 151a and / or the first crystalline oxide semiconductor 151b is 10１７ cm －３ Preferably 10 １７ ~10 ２２ cm －３ In one embodiment, the ratio of the average carrier concentration of the first crystalline oxide semiconductor 151a to the average carrier concentration of the second crystalline oxide semiconductor 152 (average carrier concentration of the first crystalline oxide semiconductor 151a / average carrier concentration of the second crystalline oxide semiconductor 152), and / or the ratio of the average carrier concentration of the first crystalline oxide semiconductor 151b to the average carrier concentration of the second crystalline oxide semiconductor 152 (average carrier concentration of the first crystalline oxide semiconductor 151b / average carrier concentration of the second crystalline oxide semiconductor 152) is 2 to 10 ４ Preferably 5 to 5 × 10 ３ More preferably 10 to 3 × 10 ３ In one embodiment, the average carrier concentration in the second crystalline oxide semiconductor 152 is 10 １４ ~10 １８ cm －３ The average carrier concentration in the first crystalline oxide semiconductor 151a and / or the first crystalline oxide semiconductor 151b is 10 １７ cm －３ Preferably 10 １７ ~10 ２２ cm －３ The ratio of the average carrier concentration of the first crystalline oxide semiconductor 151a to the average carrier concentration of the second crystalline oxide semiconductor 152 (average carrier concentration of the first crystalline oxide semiconductor 151a / average carrier concentration of the second crystalline oxide semiconductor 152), and / or the ratio of the average carrier concentration of the first crystalline oxide semiconductor 151b to the average carrier concentration of the second crystalline oxide semiconductor 152 (average carrier concentration of the first crystalline oxide semiconductor 151b / average carrier concentration of the second crystalline oxide semiconductor 152) is between 2 and 10. ４ Preferably 5 to 5 × 10 ３ More preferably 10 to 3 × 10 ３ That is the case.

[0048] An example of a manufacturing method for the transistor 10 according to this embodiment is described below, but the manufacturing method is not limited to this example.

[0049] Figure 3 illustrates an example of a method for manufacturing the transistor 10 according to this embodiment. Figure 3(a) shows the state in which the first crystalline oxide semiconductor 151a, the second electrode 12, and the insulating film 19 supporting the second electrode 12 have been formed, as shown in Figures 1 and 2. Although not shown in Figure 3(a), the second electrode 12 and the insulating film 19 may be formed on a separate substrate. The second electrode 12 may also be connected to an element outside the transistor according to this embodiment. The insulating film 19 and the second electrode 12 can be formed by known methods. The first crystalline oxide semiconductor 151a can be formed by, for example, setting its composition or applying a vapor phase crystallization process so that its lattice constant is relatively large. Specific formation methods will be described later.

[0050] Next, as shown in Figure 3(b), the third insulating film 14b, the third electrode 13, and the first insulating film 14a are formed in this order. At this time, as will be described later, the third electrode 13 may be formed to be connected to the word line. Alternatively, the third electrode 13 itself may be used as the word line.

[0051] The third insulating film 14b is formed by depositing a film containing the above-mentioned insulator using various methods such as chemical vapor deposition (CVD), plasma CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), sol-gel method, and coating method.

[0052] The third electrode 13 is formed by depositing a conductive material such as tungsten, as described above. The third electrode 13 may be patterned into any shape. The pattern of the third electrode 13 may be formed during film deposition, or it may be formed by etching after film deposition.

[0053] The first insulating film 14a is formed by depositing a film containing the above-mentioned insulator using various methods such as chemical vapor deposition (CVD), plasma CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), sol-gel method, and coating method.

[0054] Next, as shown in Figure 3(c), through-holes H are formed by etching, penetrating the first insulating film 14a, the third electrode 1, and the third insulating film 14b. Various etching methods, such as dry etching and wet etching, may be used to form the through-holes H. Alternatively, a resist may be deposited on the first insulating film 14a before etching to define the region where the through-holes H will be formed.

[0055] Next, as shown in Figure 3(d), a second insulating film 16 containing the above-described insulator is formed by various methods such as chemical vapor deposition (CVD), plasma CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), sol-gel method, and coating method.

[0056] Next, as shown in Figure 3(e), a second crystalline oxide semiconductor 152 is formed in the through-hole H where the second insulating film 16 is formed. The second crystalline oxide semiconductor 152 can be formed by, for example, setting the composition or applying a solid-phase crystallization process so that its lattice constant is relatively small. Sputter deposition or atomic layer deposition (ALD) is preferred as the solid-phase crystallization process. Specific formation methods will be described later. When solid-phase crystallization is performed by sputter deposition, an amorphous film can be obtained by setting the substrate temperature to a relatively low temperature and introducing water into the introduction gas as needed. Then, by performing heat treatment to crystallize, a crystal with few defects can be obtained. In the case of ALD deposition, complete crystallization during film formation can be prevented by setting the substrate temperature to a relatively low temperature.

[0057] Next, as shown in Figure 3(f), a first crystalline oxide semiconductor 151a is formed on top of the second crystalline oxide semiconductor 152, and then a first electrode 11 is formed on top of the first crystalline oxide semiconductor 151a. The method for forming the first crystalline oxide semiconductor 151a is the same as the explanation for forming the first crystalline oxide semiconductor 151b. The first crystalline oxide semiconductor 151a may be patterned into any shape. The first crystalline oxide semiconductor 151a may have a pattern formed during film deposition, or it may have a pattern formed by etching after film deposition. The first electrode 11 can be formed by known methods. The first electrode 11 may be patterned into any shape. The first electrode 11 may have a pattern formed during film deposition, or it may have a pattern formed by etching after film deposition.

[0058] As described above, a transistor 10 as shown in Figures 1 and 2 can be obtained.

[0059] Methods for forming the first crystalline oxide semiconductor 151a, 151b and the second crystalline oxide semiconductor 152 include chemical vapor deposition (CVD), plasma CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), sol-gel method, and coating method. CVD methods include organometallic CVD (MO-CVD), inductively coupled plasma CVD (ICP-CVD), and mist CVD. PVD methods include DC sputtering, AC sputtering, RF sputtering, ICP sputtering, reactive sputtering, and ion plating.

[0060] The first crystalline oxide semiconductors 151a, 151b, and the second crystalline oxide semiconductor 152 may be crystalline oxide semiconductors formed by a vapor phase crystallization method or crystalline oxide semiconductors formed by a solid phase crystallization method. That is, the oxide semiconductors formed by the above method may be amorphous or crystalline. If an amorphous oxide semiconductor is formed, the oxide semiconductor will be crystallized in one of the subsequent steps.

[0061] When a crystalline oxide semiconductor is formed by a solid-phase crystallization method, a crystalline oxide semiconductor is formed by first forming an amorphous oxide semiconductor and then performing post-annealing as described below. Alternatively, a crystalline oxide semiconductor may be formed by performing post-annealing after the formation of an amorphous oxide semiconductor, or post-annealing may be performed after the oxide semiconductor has crystallized and a crystalline oxide semiconductor has been formed. Alternatively, a crystalline oxide semiconductor may be formed without post-annealing, or post-annealing may be performed after the formation of the crystalline oxide semiconductor to adjust the crystallinity of the crystalline oxide semiconductor.

[0062] Crystalline oxide semiconductors may be subjected to post-annealing. Post-annealing can be performed after the deposition of the oxide semiconductor film, for example, after or before the formation of the subsequent first electrode 11. The state of the oxide semiconductor before post-annealing may be amorphous or crystalline. The annealing atmosphere may contain nitrogen or oxygen and may be under vacuum or air. The annealing temperature is preferably 250°C to 600°C, more preferably 300°C to 500°C, and even more preferably 350°C to 450°C. The annealing time is 5 minutes to 2 hours, preferably 30 minutes to 1 hour.

[0063] In the manufacturing method described above, the second crystalline oxide semiconductor 152 is formed in the through-hole H where the second insulating film 16 is formed. Therefore, atomic layer deposition (ALD) is preferred as the method for forming the second crystalline oxide semiconductor 152. Atomic layer deposition (ALD) is a thin film formation method in which a process of alternately exposing a raw material (sometimes called a precursor) containing a metal element constituting the film to be deposited (here, the second crystalline oxide semiconductor 152) and an oxidizing agent to the substrate surface constitutes one cycle, forming one atomic layer in one cycle, and repeating this cycle until the desired film thickness is achieved. Therefore, by using ALD, a dense second crystalline oxide semiconductor 152 can be formed even in the region near the first crystalline oxide semiconductor 151b, away from the opening, in the through-hole H where the second insulating film 16 is formed. This further reduces the contact resistance between the second crystalline oxide semiconductor 152 and the first crystalline oxide semiconductor 151b. Furthermore, the first crystalline oxide semiconductors 151a and 151b may also be formed using atomic layer deposition (ALD).

[0064] A single atomic layer deposition cycle of ALD may include the following four steps: (1) The precursor, which is the raw material, is vaporized in a container and introduced into the chamber. A predetermined system pressure is applied and the precursor is reacted with the OH groups on the substrate surface or film surface for a predetermined time to adsorb single molecules. If the vapor pressure of the precursor is low, the container containing the precursor may be heated to promote vaporization, and if the vapor pressure of the precursor is high, the container containing the precursor may be cooled to suppress vaporization and adjust the process. (2) Unreacted raw materials and by-product gases are removed from the chamber by purging with an inert gas, and one atomic layer is deposited. (3) A reactive gas is introduced into the chamber, and the metal of the precursor is oxidized using heat, plasma, etc. (4) Unreacted oxidizing agents and by-product gases are removed by purging with an inert gas. After step (4), the process returns to step (1), and steps (1) to (4) may be repeated until the desired film thickness is achieved.

[0065] When performing ALD, various ALD devices can be used. Specifically, examples include devices that can supply a precursor by bubbling, and devices that have a vaporization chamber. Also, devices that can perform plasma treatment on the reactive gas (oxidizer) can be used. Furthermore, not only single-wafer devices equipped with a film deposition chamber, but also devices that can process multiple sheets simultaneously using a batch furnace may be used.

[0066] Examples of ALD precursors include organometallic (e.g., AlMe) ３ ), metal hydrides (e.g., AshH ３ ), metal alkoxides (for example, Ti(OCHMe ２ ) ４ ), metal amides (for example, Ti (NME ２ ) ４ ), β-diketonate (for example, Co(acac) ２ ), metallocene (for example, MgCp ２ Examples include metal amidinates, etc. Various metal compounds are commercially available for use as ALD precursors, and one should select a precursor and oxidizing agent that can form the desired film.

[0067] Examples of precursors include compounds of silicon or metals, which consist of one or more compounds selected from the group consisting of compounds used as organic ligands, such as alkyl compounds, alcohol compounds, glycol compounds, β-diketone compounds, cyclopentadiene compounds, and organic amine compounds.

[0068] Examples of precursor metal species include lithium, sodium, potassium, magnesium, calcium, strontium, barium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, manganese, iron, ruthenium, cobalt, rhodium, iridium, nickel, palladium, platinum, copper, silver, gold, zinc, boron, aluminum, silicon, indium, gallium, germanium, tin, lead, antimony, bismuth, scandium, ruthenium, yttrium, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium.

[0069] If the oxide semiconductor 15 contains indium atoms (In), an In-containing precursor may be used. If the oxide semiconductor 15 contains other metals, a precursor containing those metals may be used. When forming an oxide semiconductor using two or more metals, there are two methods: vaporizing and supplying each component independently (sometimes referred to as the "single-source method") and vaporizing and supplying a mixed raw material in which multi-component raw materials are pre-mixed to a desired composition (sometimes referred to as the "cocktail-source method"). In the single-source method, it is preferable that each precursor used has similar thermal and / or oxidative decomposition behavior. In the cocktail-source method, it is preferable that each precursor has similar thermal and / or oxidative decomposition behavior and does not undergo alteration due to chemical reactions during mixing.

[0070] The following are examples of compounds that can be used as organic ligands for precursors. Furthermore, depending on the valency of the central metal, multiple ligands from the following list may coordinate. In a precursor, when multiple ligands coordinate to the central metal, these ligands may be identical to each other, or two or more ligands may be combined.

[0071] Alkyl compounds used as organic ligands for precursors include methyl, ethyl, propyl, isopropyl, butyl, 2-butyl, isobutyl, 3-butyl, pentyl, isopentyl, and 3-pentyl.

[0072] Alcohol compounds used as organic ligands for precursors include alkyl alcohols such as methanol, ethanol, propanol, isopropyl alcohol, butanol, 2-butyl alcohol, isobutyl alcohol, 3-butyl alcohol, pentyl alcohol, isopentyl alcohol, and 3-pentyl alcohol; 2-methoxyethanol, 2-ethoxyethanol, 2-butoxyethanol, 2-(2-methoxyethoxy)ethanol, 2-methoxy-1-methylethanol, 2-methoxy-1,1-dimethylethanol, 2-ethoxy-1,1-dimethylethanol, 2-isopropoxy-1,1-dimethylethanol, and 2-butoxy Examples include ether alcohols such as -1,1-dimethylethanol, 2-(2-methoxyethoxy)-1,1-dimethylethanol, 2-propoxy-1,1-diethylethanol, 2-s-butoxy-1,1-diethylethanol, and 3-methoxy-1,1-dimethylpropanol; and dialkylamino alcohols such as dimethylaminoethanol, ethylmethylaminoethanol, diethylaminoethanol, dimethylamino-2-pentanol, ethylmethylamino-2-pentanol, dimethylamino-2-methyl-2-pentanol, ethylmethylamino-2-methyl-2-pentanol, and diethylamino-2-methyl-2-pentanol.

[0073] Examples of glycol compounds used as organic ligands for precursors include 1,2-ethanediol, 1,2-propanediol, 1,3-propanediol, 2,4-hexanediol, 2,2-dimethyl-1,3-propanediol, 2,2-diethyl-1,3-propanediol, 1,3-butanediol, 2,4-butanediol, 2,2-diethyl-1,3-butanediol, 2-ethyl-2-butyl-1,3-propanediol, 2,4-pentanediol, 2-methyl-1,3-propanediol, 2-methyl-2,4-pentanediol, 2,4-hexanediol, and 2,4-dimethyl-2,4-pentanediol.

[0074] Examples of β-diketone compounds used as organic ligands for precursors include acetylacetone, hexane-2,4-dione, 5-methylhexane-2,4-dione, heptane-2,4-dione, 2-methylheptane-3,5-dione, 5-methylheptane-2,4-dione, 6-methylheptane-2,4-dione, 2,2-dimethylheptane-3,5-dione, 2,6-dimethylheptane-3,5-dione, 2,2,6-trimethylheptane-3,5-dione, 2,2,6,6-tetramethylheptane-3,5-dione, octane-2,4-dione, 2,2,6-trimethyloctane-3,5-dione, 2,6-dimethyloctane-3,5-dione, 2,9-dimethylnonane-4,6-dione, and 2-methyl-6-ethyl Examples include alkyl-substituted β-diketones such as decane-3,5-dione and 2,2-dimethyl-6-ethyldecane-3,5-dione; fluorine-substituted alkyl β-diketones such as 1,1,1-trifluoropentane-2,4-dione, 1,1,1-trifluoro-5,5-dimethylhexane-2,4-dione, 1,1,1,5,5,5-hexafluoropentane-2,4-dione, and 1,3-diperfluorohexylpropane-1,3-dione; and ether-substituted β-diketones such as 1,1,5,5-tetramethyl-1-methoxyhexane-2,4-dione, 2,2,6,6-tetramethyl-1-methoxyheptane-3,5-dione, and 2,2,6,6-tetramethyl-1-(2-methoxyethoxy)heptane-3,5-dione.

[0075] Examples of cyclopentadiene compounds used as organic ligands for precursors include cyclopentadiene, methylcyclopentadiene, ethylcyclopentadiene, propylcyclopentadiene, isopropylcyclopentadiene, butylcyclopentadiene, 2-butylcyclopentadiene, isobutylcyclopentadiene, 3-butylcyclopentadiene, dimethylcyclopentadiene, and tetramethylcyclopentadiene.

[0076] Examples of organic amine compounds used as organic ligands for precursors include methylamine, ethylamine, propylamine, isopropylamine, butylamine, 2-butylamine, 3-butylamine, isobutylamine, dimethylamine, diethylamine, dipropylamine, diisopropylamine, ethylmethylamine, propylmethylamine, and isopropylmethylamine.

[0077] In addition, metal halogen compounds (e.g., InCl ３ InBr ３ InF ３ (etc.) may be used as precursors. When multiple halogens coordinate to a metal, these halogens may be identical to each other, or two or more halogens may be combined. In addition, some of the halogens may be replaced with hydrogen.

[0078] Examples of indium-containing precursors include InCl ３ , TMIn (trimethyl indium), TEIn (triethyl indium), InCp (cyclopentadienyl indium (I)), InEtCp (ethylcyclopentadienyl indium(I)), In(acac) ３ (indium acetylacetonate), In(tmhd) ３ (indium 2,2,6,6-tetramethyl-3,5-heptanedionate), In[( ｉ PrN) ２ CNR ２ ] ３(R=Me) (indium-tris-guanidinates), Et ２ InN (TMS) ２ (diethyl[bis-(trimethylsilyl)amido]indium), INCA(diethyl[1,1,1-trimethyl-N- (trimethylsilyl)silanaminato]indium), DADI([3-(dimethylamino)propyl]dimethyl indium), In(dmamp) ３ ((1-dimethylamino-2-methyl-2-propoxy)indium), Me ２ Examples include In(EDPA)(dimethyl(N-ethoxy-2,2-dimethylpropanamido)indium) and tris(N,N'-disosopropylacetamidinato)indium(III).

[0079] These ALD precursors may be used individually or in combination of two or more types.

[0080] The precursors described above can be manufactured according to known manufacturing methods. For example, when an alcohol compound is used as an organic ligand, the precursor can be manufactured by reacting the inorganic salt or hydrate of the metal mentioned above with an alkali metal alkoxide of the alcohol compound. Examples of the inorganic salt or hydrate of the metal include metal halides and nitrates. Examples of alkali metal alkoxides include sodium alkoxide, lithium alkoxide, and potassium alkoxide.

[0081] As an oxidizing agent used in ALD, H ２ O, O ２ , O ３ , O ２ Plasma, H ２ O plasma, hydrogen peroxide (H ２ O ２ Examples include the following. These oxidizing agents may be used individually or in combination of two or more.

[0082] When using two or more oxidizing agents, the two or more oxidizing agents may be used simultaneously, or may be used individually while changing the two or more oxidizing agents. For example, as the oxidizing agent, O ２ plasma and H ２ By using two types of O ２ plasma, the high mobility obtained when using O ２ plasma and the advantages of both the reduction in carbon concentration and the improvement in the stability of mobility against heat treatment obtained when using H ２ plasma can be utilized. By using two or more oxidizing agents, high mobility and low carbon concentration can be adjusted. Depending on the intended effect, the usage ratio, usage order, number of cycles, etc. of O ２ plasma and H ２ plasma may be appropriately selected.

[0083] The pressure of the system (inside the film formation chamber) in step (1) may be appropriately set according to the type of precursor, substrate temperature, etc. For example, 1 to 10,000 Pa is preferable, 10 to 1,000 Pa is more preferable, 50 to 500 Pa is further preferable, and 80 to 120 Pa is particularly preferable.

[0084] In one embodiment, in the film formation step, H ２ plasma is used as the oxidizing agent. In one embodiment, in the film formation step, O ２ plasma is used as the oxidizing agent. In one embodiment, in the film formation step, O ３ is used as the oxidizing agent. By using these oxidizing agents, the effect of being able to control the electrical characteristics of the oxide semiconductor film in a good state can be obtained.

[0085] To vaporize the precursor, the container containing the precursor may be heated at a temperature at which the precursor is sufficiently vaporized as necessary. When using a precursor with a high vapor pressure, the container containing the precursor may be cooled as necessary. In one embodiment, the container containing the indium-containing precursor (for example, triethylindium) is heated in the range of 25 to 150 °C. The above temperature is preferably in the range of 50 to 150 °C, more preferably in the range of 75 to 125 °C.

[0086] In the above manufacturing method, the substrate temperature during film formation is usually within the range of 50 to 600 °C, preferably 85 to 500 °C, more preferably 80 to 350 °C, and even more preferably 100 to 250 °C.

[0087] Note that the growth amount of the oxide semiconductor film per cycle of the ALD process varies depending on the precursor used during film formation, the type of reactive gas, and the substrate temperature during film formation. [[ID=?]] [[ID=?]]

[0088] The growth amount per cycle of the ALD process is called Growth per cycle (GPC), and can be calculated, for example, by measuring the film thickness of the oxide semiconductor when repeating 30 cycles of the ALD cycle. Here, GPC varies depending on the combination of the precursor, the oxidizing agent, and the substrate temperature, and also varies depending on the type of substrate. Therefore, the number of cycles described above varies depending on a number of factors such as the types of the precursor and the oxidizing agent and their combinations, the type of substrate, the substrate temperature during film formation, and the desired film thickness, and can be appropriately set in consideration of these factors.

[0089] Also, when using O ３ as the oxidizing agent, the substrate temperature during film formation is preferably above 100 °C, more preferably 110 to 250 °C, 120 to 230 °C, 130 to 220 °C. When using H ２ O plasma and O ２ plasma as the oxidizing agent, the substrate temperature during film formation is preferably 100 to 150 °C.

[0090] Examples of the inert gas for purging unreacted raw materials and unreacted oxidizing agents include argon, nitrogen, etc. In the method of this embodiment, argon or nitrogen is preferred.

[0091] In the above step (3), it is preferable to generate plasma of the reactive gas (oxidizing agent).

[0092] In this embodiment, it is preferable to adjust the formation conditions of the crystalline oxide semiconductors so that the lattice constants of the first crystalline oxide semiconductors 151a and 151b are greater than the lattice constant of the second crystalline oxide semiconductor 152. Formation conditions include the conditions during film formation of the oxide semiconductor, the composition of the oxide semiconductor, and whether or not post-annealing is performed after film formation of the oxide semiconductor and the conditions for such post-annealing.

[0093] (Second Embodiment) Next, another example of the transistor according to this embodiment (second embodiment) will be described with reference to Figures 4 and 5. Figure 4 is a schematic perspective view showing a cross-section of the transistor according to the second embodiment. Figure 5 is a schematic cross-sectional view of the transistor. In Figures 4 and 5, the same reference numerals as in Figures 1 and 2 indicate the same components, and unless otherwise specified, the descriptions given for Figures 1 and 2 will be incorporated by reference.

[0094] In the second embodiment, the transistor 10 includes a first electrode 11, a second electrode 12, a third electrode 13, a first crystalline oxide semiconductor 151a, 151b, a second crystalline oxide semiconductor 152, a first insulating film 14, and a second insulating film 16. At least a portion of the third electrode 13 is located between the first electrode 11 and the second electrode 12. At least a portion of the third electrode 13 may be located on the opposite side of the first electrode 11 from the second electrode 12, or on the opposite side of the second electrode 12 from the first electrode 11. The first insulating film 14 is located between the first electrode 11 and the second electrode 12. Here, the first electrode 11 and the second electrode 12 are stacked with the first insulating film 14 in between. As a result, the first electrode 11 and the second electrode 12 are electrically insulated by the first insulating film 14. The third electrode 13 is provided adjacent to the second crystalline oxide semiconductor 152 without contacting it. Specifically, the third electrode 13 is adjacent to the second crystalline oxide semiconductor 152 via a second insulating film 16 located between the third electrode 13 and the second crystalline oxide semiconductor 152. The second insulating film 16 may be provided between the third electrode 13 and the second crystalline oxide semiconductor 152 to insulate the third electrode 13 from the second crystalline oxide semiconductor 152.

[0095] The second crystalline oxide semiconductor 152 penetrates at least the first insulating film 14. Here, the second crystalline oxide semiconductor 152 is provided in a columnar shape, penetrating the first electrode 11 and the first insulating film 14 in that order. A recess is formed in the columnar second crystalline oxide semiconductor 152 from one end (upper side in Figures 4 and 5) to the other end (lower side in Figures 4 and 5), and the second insulating film 16 is formed on the inner circumferential surface and bottom surface of the recess. The third electrode 13 is provided to fill the recess where the second insulating film 16 is formed.

[0096] The first crystalline oxide semiconductors 151a and 151b are provided in contact with the first electrode 11 and the second electrode 12, respectively. Specifically, the first crystalline oxide semiconductor 151a is laminated on the surface of the first electrode 11 facing the second crystalline oxide semiconductor 152. The first crystalline oxide semiconductor 151b is laminated on the surface of the second electrode 12 facing the second crystalline oxide semiconductor 152. The second crystalline oxide semiconductor 152 connects the first electrode 11 and the second electrode 12 via the first crystalline oxide semiconductors 151a and 151b. It is preferable that the second crystalline oxide semiconductor 152 is provided in contact with the first crystalline oxide semiconductors 151a and 151b.

[0097] The dimensions of the transistor 10 may be designed as appropriate depending on its application. The channel length of the second crystalline oxide semiconductor 152 is, for example, 1 nm to 10 μm, preferably 2 nm to 1000 nm. The channel length of the second crystalline oxide semiconductor 152 is the length of the second crystalline oxide semiconductor 152 along the thickness direction (up and down direction in Figures 4 and 5) of the laminate in which the first electrode 11, the first insulating film 14, and the second electrode 12 are stacked in this order, and may coincide with the depth of the recess in the second crystalline oxide semiconductor 152.

[0098] The thickness of the second crystalline oxide semiconductor 152 is, for example, 1 nm to 500 nm, preferably 1 nm to 100 nm. The thickness of the second crystalline oxide semiconductor 152 may be the average thickness along the channel length direction. The average thickness along the channel length direction is the average value obtained when the thickness is measured at 10 or more locations along the channel length direction.

[0099] The thickness of the second insulating film 16 is, for example, 1 Å to 500 nm, preferably 1 nm to 100 nm. In order to suppress the capacitance of the second insulating film 16 from becoming a parasitic component, the thickness of the second insulating film 16 may be 50 nm or less, 10 nm or less, or 2 nm or less.

[0100] The thickness of the first crystalline oxide semiconductors 151a and 151b is, for example, 1 Å to 500 nm, preferably 1 nm to 200 nm, and more preferably 2 nm to 100 nm. By having the thickness of the first crystalline oxide semiconductors 151a and 151b within the above range, the contact resistance between the electrodes (first electrode and / or second electrode) and the second crystalline oxide semiconductor can be further reduced.

[0101] The channel length and channel width of the second crystalline oxide semiconductor 152, the thickness of the second insulating film 16, and the thicknesses of the first crystalline oxide semiconductors 151a and 151b can be measured in the same manner as in the first embodiment.

[0102] In the second embodiment as well, the lattice constants of the first crystalline oxide semiconductors 151a and 151b are greater than the lattice constant of the second crystalline oxide semiconductor 152. Therefore, as explained in the first embodiment, the resistance values ​​of the first crystalline oxide semiconductors 151a and 151b in the region that contacts the electrodes (first electrode 11 and / or second electrode 12) (a region that is inherently prone to contact resistance) are low, thus improving the contact resistance of the transistor 10.

[0103] The description in the first embodiment may be applied to the first electrode 11, the second electrode 12, the third electrode 13, the first insulating film 14, the first crystalline oxide semiconductors 151a and 151b, the second crystalline oxide semiconductor 152, and the second insulating film 16.

[0104] The method for manufacturing the transistor 10 according to the second embodiment is not particularly limited, and can be manufactured by known methods, with reference to the manufacturing method according to the first embodiment, except for the formation of the first crystalline oxide semiconductors 151a and 151b. For example, the transistor 10 according to the second embodiment may be manufactured as follows: After forming a laminate of the second electrode 12, the first insulating film 14, and the first electrode 11, through holes are formed so as to penetrate the first electrode 11 and the first insulating film 14. After forming the first crystalline oxide semiconductors 151a and 151b on the first electrode 11 and the second electrode 12, respectively, the second crystalline oxide semiconductor 152 is formed. Then, the second insulating film 16 and the third electrode 13 are formed. The first crystalline oxide semiconductors 151a and 151b can be formed, for example, by ALD, CVD, PVD, LPCVD, PECVD, etc., after forming the first electrode 11 and the second electrode. In particular, the ALD method allows for suitable film formation even inside through-holes, and the film formation rate is faster on the electrodes (first electrode 11 and second electrode 12) than on the insulating film (first insulating film 14). Therefore, the first crystalline oxide semiconductor 151a can be selectively formed on the first electrode 11, and the first crystalline oxide semiconductor 151b can be selectively formed on the second electrode. The reason why the film formation rate is faster on the electrodes than on the insulating film is that the reactivity between the precursor and the electrode is higher than the reactivity between the precursor and the insulating film. The method for forming the first electrode 11, the second electrode 12, the third electrode 13, the first insulating film 14, the first crystalline oxide semiconductors 151a and 151b, the second crystalline oxide semiconductor 152, and the second insulating film 16 may be based on the description in the first embodiment.

[0105] Next, another example of the transistor according to this embodiment (a third embodiment) will be described with reference to Figures 6 and 7. Figure 6 is a schematic perspective view showing a cross-section of the transistor according to the third embodiment. Figure 7 is a schematic cross-sectional view of the same transistor. In Figures 6 and 7, the same reference numerals as in Figures 1 and 2 indicate the same components, and unless otherwise specified, the descriptions given for Figures 1 and 2 will be incorporated by reference.

[0106] In the third embodiment, the transistor 10 includes a first electrode 11, a second electrode 12, a third electrode 13, first crystalline oxide semiconductors 151a and 151b, second crystalline oxide semiconductors 152 and 152', and a first insulating film 14. The third electrode 13 is located between the first electrode 11 and the second electrode 12. The first insulating film 14 is located between the first electrode 11 and the third electrode 13. Here, the first electrode 11 and the second electrode 12 are stacked with the first insulating film 14 in between. As a result, the first electrode 11 and the second electrode 12 are electrically insulated by the first insulating film 14. The third electrode 13 is provided so as to be adjacent to the second crystalline oxide semiconductors 152 and 152' without contact with them. Specifically, the third electrode 13 is adjacent to the second crystalline oxide semiconductors 152 and 152' via the first insulating film 14 located between the third electrode 13 and the second crystalline oxide semiconductors 152 and 152'. In this sense, it can be said that the first insulating film 14 in the third embodiment also serves the role of the second insulating film 16 in the first and second embodiments.

[0107] The first crystalline oxide semiconductors 151a and 151b are provided in contact with the first electrode 11 and the second electrode 12, respectively. Specifically, the first crystalline oxide semiconductor 151a is laminated on the surface of the first electrode 11 facing the second crystalline oxide semiconductors 152 and 152'. The first crystalline oxide semiconductor 151b is laminated on the surface of the second electrode 12 facing the second crystalline oxide semiconductors 152 and 152'. The second crystalline oxide semiconductors 152 and 152' connect the first electrode 11 and the second electrode 12 via the first crystalline oxide semiconductors 151a and 151b, respectively. It is preferable that the second crystalline oxide semiconductors 152 and 152' are provided in contact with the first crystalline oxide semiconductors 151a and 151b. In the examples shown in Figures 6 and 7, the first crystalline oxide semiconductors 151a and 151b are provided on the entire surface of the first electrode 11 and second electrode 12 on the second crystalline oxide semiconductor 152 and 152' side (including the portion connected to the first insulating film 14). However, in other examples, the first crystalline oxide semiconductors 151a and 151b may be provided only on the portion of the first electrode 11 and second electrode 12 on the second crystalline oxide semiconductor 152 and 152' side that is connected to the second crystalline oxide semiconductor 152 and 152'.

[0108] The dimensions of the transistor 10 may be designed as appropriate depending on its application. The channel lengths of the second crystalline oxide semiconductors 152 and 152' are, for example, 1 nm to 10 μm, preferably 2 nm to 1000 nm. The channel length of the second crystalline oxide semiconductor 152 is the length of the second crystalline oxide semiconductors 152 and 152' along the thickness direction (up and down direction in Figures 6 and 7) of the laminate in which the first electrode 11, the first insulating film 14, and the second electrode 12 are stacked in this order, and may coincide with the distance between the first electrode 11 and the second electrode 12 (or the distance between the first crystalline oxide semiconductors 151a and 151b).

[0109] The thickness of the second crystalline oxide semiconductor 152, 152' is, for example, 1 nm to 500 nm, preferably 1 nm to 100 nm. The thickness of the second crystalline oxide semiconductor 152 may be the average thickness along the channel length direction. The average thickness along the channel length direction is the average value obtained when the thickness is measured at 10 or more locations along the channel length direction.

[0110] The thickness of the first insulating film 14 is, for example, 1 Å to 500 nm, preferably 1 nm to 100 nm. In order to suppress the capacitance of the first insulating film 14 from becoming a parasitic component, the thickness of the first insulating film 14 may be 50 nm or less, 10 nm or less, or 2 nm or less.

[0111] The thickness of the first crystalline oxide semiconductors 151a and 151b is, for example, 1 Å to 500 nm, preferably 1 nm to 200 nm, and more preferably 2 nm to 100 nm. By having the thickness of the first crystalline oxide semiconductors 151a and 151b within the above range, the contact resistance between the electrodes (first electrode and / or second electrode) and the second crystalline oxide semiconductor can be further reduced.

[0112] The channel length and thickness of the second crystalline oxide semiconductors 152 and 152', the thickness of the first insulating film 14, and the thickness of the first crystalline oxide semiconductors 151a and 151b can be measured in the same manner as in the first embodiment.

[0113] In the third embodiment as well, the lattice constants of the first crystalline oxide semiconductors 151a and 151b are greater than the lattice constants of the second crystalline oxide semiconductors 152 and 152'. Therefore, as explained in the first embodiment, the resistance values ​​of the first crystalline oxide semiconductors 151a and 151b in the region that contacts the electrodes (first electrode 11 and / or second electrode 12) (a region that is inherently prone to contact resistance) are low, thus improving the contact resistance of the transistor 10.

[0114] With respect to the first electrode 11, the second electrode 12, the third electrode 13, the first insulating film 14, the first crystalline oxide semiconductors 151a and 151b, and the second crystalline oxide semiconductor 152, the descriptions in the first and second embodiments may be applied by reference.

[0115] The method for manufacturing the transistor 10 according to the third embodiment is not particularly limited, and except for the formation of the first crystalline oxide semiconductors 151a and 151b, it can be manufactured by known methods (for example, the method described in International Publication No. 2020 / 076850, etc.) while referring to the manufacturing method according to the first embodiment. The first crystalline oxide semiconductors 151a and 151b can be formed, for example, as described in the first embodiment. The methods for forming the first electrode 11, the second electrode 12, the third electrode 13, the first insulating film 14, the first crystalline oxide semiconductors 151a and 151b, and the second crystalline oxide semiconductor 152 can be based on the descriptions in the first and second embodiments.

[0116] The embodiments described above mainly show the case where the transistor is provided with a first crystalline oxide semiconductor for each of the first and second electrodes, but the invention is not limited to this. For example, the transistor may be provided with a first crystalline oxide semiconductor for only one of the first and second electrodes. The second insulating film 16 may also be omitted. Furthermore, the transistor may have a structure other than that shown in Figures 1 to 7, as long as the effects of this embodiment are achieved.

[0117] 2. Semiconductor Devices A semiconductor device according to one aspect of the present invention includes a transistor according to one aspect of the present invention. The semiconductor device may comprise one or more transistors according to one aspect of the present invention. The semiconductor device according to this aspect has excellent electrical properties and high reliability because the contact resistance in the transistor can be improved. The type of semiconductor device is not particularly limited, but from the viewpoint of demonstrating the above effects significantly, it is preferable to have semiconductor memory devices such as volatile memories such as DRAM (Dynamic Random Access Memory) and SRAM (Static RAM); and non-volatile memories such as mask ROM (Read Only Memory), EPROM (Erasable Programmable ROM), EEPROM (Electrically Erasable Programmable ROM), flash memory (NOR type flash memory, NAND type flash memory), MRAM (Magnetoresistive RAM), FeRAM (Ferroelectric RAM), ReRAM (Resistive RAM), etc. Alternatively, the semiconductor device according to this embodiment may be a logic device such as TTL (Transistor-Transistor Logic), CMOS (Complementary Metal-Oxide-Semiconductor), BiCMOS, PLD (Programmable Logic Device), FPGA (Field Programmable Gate Array), CPU (Central Processing Unit), or MPU (Microprocessor Unit). Furthermore, since the transistor according to one embodiment of the present invention can be fitted with a vertical structure as shown in each embodiment, it is suitable for densely arranging multiple transistors in a semiconductor memory device and contributes to the miniaturization of the semiconductor memory device. In addition, since the transistor according to one embodiment of the present invention uses an oxide semiconductor as the channel, it tends to have a small leakage current. Therefore, by using it in a semiconductor memory device, the capacitance of the capacitor can be reduced or the capacitor can be omitted.As a result, by using a transistor according to one aspect of the present invention, semiconductor memory devices can be miniaturized.

[0118] Figure 8 shows an example of a circuit configuration of a semiconductor memory device equipped with a transistor according to one aspect of the present invention. As shown in Figure 8, the semiconductor memory device 50 includes a transistor 10, a capacitor 51, a word line WL, and a bit line BL. The source electrode of the transistor 10 is connected to the bit line BL. The drain electrode of the transistor 10 is connected to one end of the capacitor 51. The gate electrode of the transistor 10 is connected to the word line WL. The other end of the capacitor 51 is grounded. The bit line BL may be connected to the first electrode 11 of the transistor 10, or to the second electrode 12. The word line WL may be connected to the third electrode 13 of the transistor 10. One end of the capacitor 51 may be connected to the first electrode 11 of the transistor 10, or to the second electrode 12.

[0119] In the example shown in Figure 8, a single memory cell 52 is formed by a transistor 10 and a capacitor 51. The memory cell 52 can store data based on the charge held by the capacitor 51. Note that the configuration of the memory cell 52 is not limited to this example, and in other examples, the capacitor 51 is omitted. When the capacitor 51 is omitted, data can be stored based on the charge held by the transistor 10 itself. In addition, two or more transistors may be combined to form the memory cell 52. If the transistor 10 itself is to have the function of holding charge, for example, one or more of the configurations described below can be applied. (1) The second insulating film is made of hafnium oxide (HfO ２ ), zirconium oxide (ZrO ２ (2) Use a high dielectric constant insulator such as (Pb, La)(Zr, Ti)O ３ (PLZT), SrTiO ３(STO), yttria-stabilized zirconia (YSZ), and other ferroelectric materials are used. (3) Hysteresis is utilized by adding an element that forms an energy level within the gap of the second crystalline oxide semiconductor to the second crystalline oxide semiconductor. (4) Parasitic capacitance is utilized by arranging a part of the source electrode and / or drain electrode and a part of the gate electrode so that they face each other across an insulating film. In (4) above, for example, parasitic capacitance can be utilized by arranging a part of one of the source electrode and drain electrode and a part of the gate electrode so that they face each other across an insulating film. In this case, the other of the source electrode and drain electrode may be arranged away from the gate electrode (for example, the distance between the other of the source electrode and drain electrode and the gate electrode may be longer than the distance between one of the source electrode and drain electrode and the gate electrode).

[0120] The semiconductor memory device 50 can read data stored in the memory cell 52 to the bit line BL by controlling the word line WL, and can also write data transferred to the bit line BL to the memory cell 52. The semiconductor memory device 50 is configured to include a memory cell array (not shown) consisting of a plurality of memory cells 52.

[0121] Although several embodiments and / or examples of the present invention have been described in detail above, those skilled in the art will find it easy to make many modifications to these exemplary embodiments and / or examples without substantially departing from the novel teachings and effects of the present invention. Therefore, many of these modifications fall within the scope of the present invention. All references to the documents cited in this specification are incorporated herein by reference.

[0122] 10: Transistor 11: First electrode 12: Second electrode 13: Third electrode 14, 14a: First insulating film 14b: Third insulating film 151a, 151b: First crystalline oxide semiconductor 152, 152': Second crystalline oxide semiconductor 16: Second insulating film 19: Insulating film 50: Semiconductor memory device 51: Capacitor 52: Memory cell WL: Word line BL: Bit line

Claims

1. A transistor comprising: a first electrode and a second electrode; a first crystalline oxide semiconductor provided in contact with the first electrode and / or the second electrode; a second crystalline oxide semiconductor connecting the first electrode and the second electrode via the first crystalline oxide semiconductor; and a third electrode adjacent to the second crystalline oxide semiconductor without contact with the second crystalline oxide semiconductor, wherein the first electrode and the second electrode are stacked with at least a first insulating film in between, and the lattice constant of the first crystalline oxide semiconductor is greater than the lattice constant of the second crystalline oxide semiconductor.

2. The transistor according to claim 1, wherein the first crystalline oxide semiconductor has a higher average carrier concentration than the second crystalline oxide semiconductor.

3. The transistor according to claim 1 or 2, wherein the composition of the metal elements constituting the first crystalline oxide semiconductor and the composition of the metal elements constituting the second crystalline oxide semiconductor are substantially the same.

4. The transistor according to claim 3, wherein the composition ratio of the metal elements constituting the first crystalline oxide semiconductor and the composition ratio of the metal elements constituting the second crystalline oxide semiconductor are substantially the same.

5. The transistor according to any one of claims 1 to 4, wherein the ratio of the lattice constant of the second crystalline oxide semiconductor to the lattice constant of the first crystalline oxide semiconductor is 0.940 or more and 0.999 or less.

6. The transistor according to any one of claims 1 to 5, wherein the thickness of the first crystalline oxide semiconductor is 2 nm or more and 100 nm or less.

7. The transistor according to any one of claims 1 to 6, further comprising a second insulating film provided between the third electrode and the second crystalline oxide semiconductor.

8. The transistor according to any one of claims 1 to 7, wherein the second crystalline oxide semiconductor penetrates at least the first insulating film.

9. The transistor according to any one of claims 1 to 8, wherein the first electrode and the third electrode are stacked with respect to the first insulating film, the third electrode and the second electrode are stacked with respect to the third insulating film, and the second crystalline oxide semiconductor is provided in a columnar shape penetrating the first insulating film, the third electrode and the third insulating film.

10. The transistor according to any one of claims 1 to 6, wherein the second crystalline oxide semiconductor is provided in a columnar shape penetrating the first electrode and the first insulating film, and the inner circumferential surface and bottom surface of a recess formed from one end to the other of the columnar second crystalline oxide semiconductor are further provided with the second insulating film, and the third electrode is provided so as to fill the recess in which the second insulating film is formed.

11. The transistor according to any one of claims 1 to 10, wherein at least one of the first electrode and the second electrode is at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), aluminum (Al), silicon (Si), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), germanium (Ge), molybdenum (Mo), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), tantalum (Ta), iridium (Ir), platinum (Pt), tungsten (W), titanium (Ti), titanium nitride (TiN), aluminum nitride (AlN), manganese nitride (MnN), molybdenum nitride (MoN), and nickel nitride (Ni3N).

12. The transistor according to any one of claims 1 to 11, wherein at least one selected from the group consisting of the first crystalline oxide semiconductor and the second crystalline oxide semiconductor includes a bixbyte crystal structure.

13. The transistor according to any one of claims 1 to 12, wherein at least one selected from the group consisting of the first crystalline oxide semiconductor and the second crystalline oxide semiconductor contains indium oxide as a main component.

14. The transistor according to any one of claims 1 to 13, wherein at least one selected from the group consisting of the first crystalline oxide semiconductor and the second crystalline oxide semiconductor comprises Ga or Al.

15. The transistor according to any one of claims 1 to 13, wherein at least one selected from the group consisting of the first crystalline oxide semiconductor and the second crystalline oxide semiconductor contains Ga.

16. The transistor according to any one of claims 1 to 13, wherein at least one selected from the group consisting of the first crystalline oxide semiconductor and the second crystalline oxide semiconductor comprises Ga and Al.

17. The transistor according to any one of claims 1 to 16, wherein at least one selected from the group consisting of the first crystalline oxide semiconductor and the second crystalline oxide semiconductor is a polycrystalline oxide semiconductor.

18. The transistor according to any one of claims 1 to 16, wherein at least one selected from the group consisting of the first crystalline oxide semiconductor and the second crystalline oxide semiconductor is a single-crystal oxide semiconductor.

19. The transistor according to any one of claims 1 to 18, wherein at least one selected from the group consisting of the first crystalline oxide semiconductor and the second crystalline oxide semiconductor is a crystalline oxide semiconductor formed by atomic layer deposition.

20. A semiconductor device comprising a transistor according to any one of claims 1 to 19.

21. The semiconductor device according to claim 20, which is a semiconductor memory device.

22. A transistor comprising: a first electrode and a second electrode; a first crystalline oxide semiconductor provided in contact with the first electrode and / or the second electrode; a second crystalline oxide semiconductor connecting the first electrode and the second electrode via the first crystalline oxide semiconductor; and a third electrode adjacent to the second crystalline oxide semiconductor without contact with the second crystalline oxide semiconductor, wherein the first electrode and the second electrode are stacked with at least a first insulating film in between; the lattice constant of the first crystalline oxide semiconductor is greater than the lattice constant of the second crystalline oxide semiconductor; the composition ratio of the metal elements constituting the first crystalline oxide semiconductor and the composition ratio of the metal elements constituting the second crystalline oxide semiconductor are substantially the same; the ratio of the lattice constant of the second crystalline oxide semiconductor to the lattice constant of the first crystalline oxide semiconductor is 0.940 or more and 0.999 or less; the thickness of the first crystalline oxide semiconductor is 2 nm or more and 100 nm or less; and the first crystalline oxide semiconductor and the second crystalline oxide semiconductor include a bixbyte crystal structure.

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