Transistor and semiconductor device

Abstract

This transistor includes: a first electrode and a second electrode; an oxide semiconductor that connects the first electrode and the second electrode; and a third electrode that is adjacent to but not in contact with the oxide semiconductor. The first electrode and the second electrode are laminated with at least a first insulating film interposed therebetween. The oxide semiconductor is a single crystal oxide semiconductor or a polycrystalline oxide semiconductor containing indium oxide as a main component and having a bixbyite structure.

Description

Transistors and semiconductor devices

[0001] This invention relates to transistors and semiconductor devices. Specifically, this invention relates to transistors and semiconductor devices with low operational variability.

[0002] Attempts are being made to apply transistors having channels made of CAAC-IGZO (indium gallium zinc oxide, which has a hexagonal structure when viewed from the c-axis direction and a layered structure when viewed from a direction perpendicular to the c-axis), an oxide semiconductor, to DRAM (Dynamic Random Access Memory) (Patent Document 1).

[0003] Furthermore, attempts have been made to apply zinc oxide-based semiconductors to transistor channels (Patent Document 2).

[0004] International Publication No. 2022 / 038447, Patent No. 5974800

[0005] In oxide semiconductors, hydrogen functions as a donor, so transistors using oxide semiconductors with a high hydrogen concentration as the channel layer tend to be normally-on (with a negative threshold voltage). In particular, in miniature transistors such as those used in DRAMs, the semiconductor film thickness is thin, the effect of hydrogen becomes greater, and variations in operation increase. Conventional technologies, including those described in Patent Documents 1 and 2, had room for further improvement in terms of suppressing variations in transistor characteristics.

[0006] One of the objectives of the present invention is to provide transistors and semiconductor devices with low operational variability.

[0007] As a result of diligent research, the present inventors have found that by using a single-crystal oxide semiconductor or polycrystalline oxide semiconductor having a bix-byte structure and primarily composed of indium oxide as the oxide semiconductor in a transistor, hydrogen diffusion into the oxide semiconductor can be suppressed, resulting in a reduction in variations in transistor characteristics, and have completed the present invention. According to the present invention, the following transistors and the like can be provided: 1. A transistor comprising: a first electrode and a second electrode; an oxide semiconductor connecting the first electrode and the second electrode; and a third electrode adjacent to the oxide semiconductor without contact with the oxide semiconductor, wherein the first electrode and the second electrode are stacked with at least a first insulating film in between, and the oxide semiconductor is a single-crystal oxide semiconductor or polycrystalline oxide semiconductor having a bix-byte structure and primarily composed of indium oxide. 2. The transistor according to 1, wherein the oxide semiconductor connects the first electrode and the second electrode by penetrating at least the first insulating film. 3. The transistor according to 1 or 2, further comprising a second insulating film provided between the third electrode and the oxide semiconductor. 4. 1. A transistor according to any one of 1 to 3, wherein the first electrode and the third electrode are stacked via the first insulating film, the third electrode and the second electrode are stacked via the third insulating film, the oxide semiconductor is provided in a columnar shape penetrating the first insulating film, the third electrode, and the third insulating film, and further comprises a second insulating film provided between the third electrode and the oxide semiconductor, the second insulating film being provided so as to surround at least a part of the columnar oxide semiconductor. 5. A transistor according to any one of 1 to 3, wherein the first electrode and the second electrode are stacked via the first insulating film, the oxide semiconductor has a tubular portion provided penetrating the first insulating film, and further comprises a second insulating film provided between the third electrode and the oxide semiconductor, the second insulating film has a tubular portion provided on the inner wall of the tubular portion of the oxide semiconductor, and the third electrode has a portion provided inside the tubular portion of the second insulating film. 6. A transistor according to any one of 1 to 5, wherein the channel length of the oxide semiconductor is 1 to 1000 nm.7. The transistor according to any one of 1 to 6, wherein the oxide semiconductor further comprises Ga or Al. 8. The transistor according to any one of 1 to 6, wherein the oxide semiconductor further comprises Ga. 9. The transistor according to any one of 1 to 6, wherein the oxide semiconductor further comprises Ga and Al. 10. The transistor according to any one of 1 to 9, wherein the atomic ratio of Ga to all metal elements contained in the oxide semiconductor ([Ga] / ([Ga] + [all metal elements other than Ga]) × 100) is 0.5 to 25 at%. 11. The transistor according to any one of 1 to 10, wherein the atomic ratio of Ga to all metal elements contained in the oxide semiconductor ([Ga] / ([Ga] + [all metal elements other than Ga]) × 100) is 3.0 to 10 at%. 12. The transistor according to any one of 1 to 11, wherein the number of grain boundaries in the oxide semiconductor is 0 to 5. 13. The transistor according to any one of 1 to 12, wherein the number of grain boundaries in the oxide semiconductor is 0. 14. A transistor according to any one of 1 to 12, wherein the number of grain boundaries in the oxide semiconductor is 1 to 5. 15. A transistor according to any one of 1 to 14, wherein the ratio of indium atoms to all metal atoms contained in the oxide semiconductor is 80 atomic% or more. 16. A transistor according to any one of 1 to 15, wherein the indium oxide content in the oxide semiconductor is 55 mass% or more. 17. The transistor according to any one of 1 to 16, wherein at least one of the first electrode and the second electrode is at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), aluminum (Al), silicon (Si), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), germanium (Ge), molybdenum (Mo), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), tantalum (Ta), iridium (Ir), platinum (Pt), tungsten (W), titanium (Ti), titanium nitride (TiN), aluminum nitride (AlN), manganese nitride (MnN), molybdenum nitride (MoN), and nickel nitride (Ni3N).18. A transistor according to any one of 1 to 17, wherein the oxide semiconductor is a crystalline oxide semiconductor formed by atomic layer deposition. 19. A semiconductor device comprising the transistor according to any one of 1 to 18. 20. A semiconductor device according to 19, comprising four or more of the transistors, wherein the coefficient of variation of the number of grain boundaries in the oxide semiconductor contained in each of the four adjacent transistors is 0.0 or more and 1.0 or less. 21. A semiconductor device according to 19 or 20, which is a semiconductor memory device. 22. A transistor comprising: a first electrode and a second electrode; an oxide semiconductor connecting the first electrode and the second electrode; and a third electrode adjacent to the oxide semiconductor without contact with the oxide semiconductor, wherein the first electrode and the second electrode are stacked with at least a first insulating film in between; the oxide semiconductor is a single-crystal oxide semiconductor or polycrystalline oxide semiconductor having a bix-byte structure and mainly composed of indium oxide; the channel length of the oxide semiconductor is 1 to 1000 nm; the oxide semiconductor contains Ga; the atomic ratio of Ga to all metal elements contained in the oxide semiconductor ([Ga] / ([Ga] + [all metal elements other than Ga]) × 100) is 0.5 to 20 at%; and the number of grain boundaries in the oxide semiconductor is 0 to 5.

[0008] According to the present invention, it is possible to provide transistors and semiconductor devices with small variations in operation.

[0009] This is a schematic perspective view showing a cross-section of a transistor according to the first embodiment. This is a schematic cross-sectional view of a transistor according to the first embodiment. This is a diagram illustrating an example of a method for manufacturing a transistor according to the first embodiment. This is a schematic perspective view showing a cross-section of a transistor according to the second embodiment. This is a schematic cross-sectional view of a transistor according to the second embodiment. This is a schematic perspective view showing a cross-section of a transistor according to the third embodiment. This is a schematic cross-sectional view of a transistor according to the third embodiment. This is a diagram showing an example of a circuit configuration of a semiconductor memory device. This is a diagram showing a-IGZO (amorphous-IGZO) and a-In using molecular dynamics simulation based on first-principles calculations. ２ O ３(Amorphous indium oxide), and c-In ２ O ３ This is the result of calculating the hydrogen diffusion properties of (crystal-indium oxide).

[0010] The transistors and semiconductor devices of the present invention will be described in detail below. In this specification, "x to y" represents a numerical range of "x or more, and y or less". The upper and lower limits described for the numerical range can be combined in any way. Furthermore, it is possible to combine two or more non-conflicting embodiments of the embodiments of the present invention described below, and an embodiment that combines two or more embodiments is also an embodiment of the embodiments of the present invention.

[0011] 1. Transistor A transistor according to one aspect of the present invention comprises: a first electrode and a second electrode; an oxide semiconductor connecting the first electrode and the second electrode; and a third electrode adjacent to the oxide semiconductor without contact with it, wherein the first electrode and the second electrode are stacked with at least a first insulating film in between, and the oxide semiconductor is a single-crystal oxide semiconductor or polycrystalline oxide semiconductor mainly composed of indium oxide and having a bix-byte structure. The transistor according to this aspect provides the effect of suppressing variations in operation. More specifically, the transistor according to this aspect is a single-crystal oxide semiconductor or polycrystalline oxide semiconductor in which the oxide semiconductor is a single-crystal oxide semiconductor or polycrystalline oxide semiconductor. Furthermore, the transistor according to this aspect is mainly composed of indium oxide and has a bix-byte structure crystal. On the other hand, CAAC-IGZO (indium gallium zinc oxide having a hexagonal structure when viewed from the c-axis direction and a layered structure when viewed from a direction perpendicular to the c-axis) used in Patent Document 1 did not adequately control variations in operation. Furthermore, while Patent Document 2 discloses a zinc oxide-based polycrystalline oxide semiconductor, it has not been commercialized due to the difficulty in controlling the transistor threshold. The present inventors have found that in oxide semiconductors, hydrogen diffusion in the oxide semiconductor is suppressed more in the crystalline state than in the amorphous state. This is thought to be because "amorphous" is less orderly than "crystalline," and areas without atomic order are more likely to become hydrogen diffusion pathways. Also, in crystalline oxide semiconductors, grain boundaries can become hydrogen diffusion pathways, so single-crystal oxide semiconductors are preferable to suppress hydrogen diffusion, and in polycrystalline oxide semiconductors, the fewer grain boundaries there are, the better. Furthermore, the diffusivity of hydrogen also differs depending on the composition of the oxide semiconductor. Indium oxide-based oxide semiconductors with a bixbyte structure have a slow hydrogen diffusion rate and tend to be less permeable to hydrogen, so it is thought that variations in operation can be reduced. In conventional oxide semiconductors, hydrogen diffuses easily, and variations in transistor characteristics can occur due to the diffusion of hydrogen contained in other layers, etc. In particular, in miniature transistors such as those used in DRAMs, the channel length is short, and the effects of hydrogen diffusion become significant.In contrast, in this embodiment, hydrogen diffusion into the oxide semiconductor as a channel layer is suppressed, thus preventing variations in transistor characteristics. Particularly in the case of fine transistors such as those applied to DRAMs, the channel length is shortened, but by applying a single-crystal oxide semiconductor or a polycrystalline oxide semiconductor to such fine channels, the number of grain boundaries can be reduced (or made zero), thus exhibiting a better effect in suppressing variations in transistor characteristics. Furthermore, in a semiconductor device containing multiple transistors of this embodiment, the variation in the number of grain boundaries in the oxide semiconductor contained in each transistor (the "coefficient of variation" described later) can be reduced, thus also achieving the effect of suppressing variations in the operation of the semiconductor device.

[0012] (First Embodiment) An example of a transistor according to this embodiment (first embodiment) will be described below with reference to Figures 1 and 2. Figure 1 is a schematic perspective view showing a cross-section of the transistor according to the first embodiment. Figure 2 is a schematic cross-sectional view of the transistor. In this embodiment, the transistor 10 includes a first electrode 11, a second electrode 12, a third electrode 13, an oxide semiconductor 15, a first insulating film 14a, a third insulating film 14b, and a second insulating film 16. The first electrode 11 and the second electrode 12 are stacked with at least the first insulating film 14a (here, the first insulating film 14a and the third insulating film 14b) in between. In this context, "stacked" means that at least a portion of the first electrode 11 and at least a portion of the second electrode 12 are arranged along a direction perpendicular to the plane direction of the substrate (not shown) supporting the transistor 10. Also, although not shown, when multiple transistors 10 are connected in a planar manner (in the X-Y direction) (when multiple transistors 10 form a transistor array), at least a portion of the first electrode 11 and at least a portion of the second electrode 12 are arranged along a direction perpendicular to the plane direction (Z direction). At least a portion of the first insulating film 14a (here, the first insulating film 14a and the third insulating film 14b) may be interposed between the first electrode 11 and the second electrode 12. The third electrode 13 is located between the first electrode 11 and the second electrode 12.

[0013] Of the first insulating film 14a and the third insulating film 14b, the first insulating film 14a is positioned between the first electrode 11 and the third electrode 13. As a result, the first electrode 11 and the third electrode 13 are electrically insulated by the first insulating film 14a. Further, the third insulating film 14b is positioned between the second electrode 12 and the third electrode 13. As a result, the second electrode 12 and the third electrode 13 are electrically insulated by the third insulating film 14b.

[0014] In the region shown in FIG. 2, the third electrode 13 is disposed between the first insulating film 14a and the third insulating film 14b. However, outside the region shown in FIG. 2, the first insulating film 14a and the third insulating film 14b may contact each other to form a single layer. In this case, the third electrode 13 may not be disposed between the first insulating film 14a and the third insulating film 14b in this region.

[0015] The oxide semiconductor 15 penetrates at least the first insulating film 14a and is provided so as to connect the first electrode 11 and the second electrode 12. The oxide semiconductor 15 may penetrate the third electrode 13 in addition to the first insulating film 14a and the third insulating film 14b. Here, the oxide semiconductor 15 is provided in a columnar shape penetrating the first insulating film 14a, the third electrode 13, and the third insulating film 14b in this order. In this case, the third electrode 13 preferably surrounds the side of the oxide semiconductor 15 (the periphery in the direction perpendicular to the length direction) over the entire circumference at a part in the length direction of the oxide semiconductor 15 (the central part in the example of FIG. 2) via the second insulating film 16 described later. As a result, it becomes easy to prevent leakage current even if the channel length of the oxide semiconductor 15 described later becomes short. At the same time, it is also advantageous in terms of miniaturization. Here, the length direction of the oxide semiconductor 15 may be the vertical direction in FIG. 2 (the direction connecting the first electrode and the second electrode), may be the direction along the channel length described later, may be the thickness direction of the laminate in which the first insulating film 14a, the third electrode 13, and the third insulating film 14b are laminated in this order, and may be the height direction of the columnar structure when the oxide semiconductor 15 is columnar.

[0016] The second insulating film 16 is provided between the third electrode 13 and the oxide semiconductor 15. The oxide semiconductor 15, the second insulating film 16, and the third electrode 13 are arranged in this order. By being provided between the third electrode 13 and the oxide semiconductor 15, the second insulating film 16 may insulate the third electrode 13 and the oxide semiconductor 15. The second insulating film 16 may also be provided, for example, between the first insulating film 14a and / or the third insulating film 14b and the oxide semiconductor 15, in addition to between the third electrode 13 and the oxide semiconductor 15. The second insulating film 16 is provided so as to surround the side surface of the columnar oxide semiconductor 15 over the entire circumference.

[0017] In a certain aspect, the transistor 10 has a through hole that penetrates a laminate in which the first insulating film 14a, the third electrode 13, and the third insulating film 14b are laminated in this order in the thickness direction of the laminate (the vertical direction in FIGS. 1 and 2), the inner peripheral surface of the through hole is covered with the cylindrical second insulating film 16, and it can also be said that the oxide semiconductor 15 is filled inside the cylindrical second insulating film 16.

[0018] The dimensions of the transistor 10 may be appropriately designed according to its use and the like. The channel length of the oxide semiconductor 15 is, for example, 1 nm to 10 μm, preferably 2 to 1000 nm, more preferably 3 to 100 nm, still more preferably 4 to 50 nm, still more preferably 5 to 30 nm, and still more preferably 6 to 20 nm. Incidentally, the channel length of the oxide semiconductor 15 is the length of the oxide semiconductor 15 along the thickness direction of the laminate (the vertical direction in FIGS. 1 and 2) in which the first insulating film 14a, the third electrode 13, and the third insulating film 14b are laminated in this order, and may coincide with the distance between the first electrode 11 and the second electrode 12. When the oxide semiconductor 15 is columnar, the channel length of the oxide semiconductor 15 corresponds to the height of the columnar structure. The channel length of the oxide semiconductor 15 may be measured by processing the corresponding portion with a focused ion beam (FIB) to expose it and observing the cross section with a transmission electron microscope (TEM).

[0019] The channel length of the oxide semiconductor 15 is not particularly limited, but is preferably 1 to 1000 nm, more preferably 1 to 500 nm, and more preferably 2 to 500 nm. By applying a single-crystal oxide semiconductor or a polycrystalline oxide semiconductor to the oxide semiconductor 15 that constitutes such a fine channel, the number of grain boundaries can be reduced (or made zero), so that the effect of suppressing hydrogen diffusion is better exhibited. The "channel length" of the oxide semiconductor 15 is the distance (length) between the first electrode 11 and the second electrode 12 connected by the oxide semiconductor 15 which is the channel.

[0020] The channel width of the oxide semiconductor 15 is, for example, 1 nm to 1000 nm, preferably 2 nm to 500 nm. The channel width of the oxide semiconductor 15 is the length of the oxide semiconductor 15 along the direction perpendicular to the thickness direction (for example, the left-right direction in Figure 2) of the laminate in which the first insulating film 14a, the third electrode 13, and the third insulating film 14b are stacked in this order. As shown in Figures 1 and 2, if the channel width of the oxide semiconductor 15 is not constant with respect to the channel length direction, the channel width of the oxide semiconductor 15 may be the average width along the channel length direction. The average width along the channel length direction is the average value obtained when the channel width is measured at 10 or more locations along the channel length direction. If the oxide semiconductor 15 is columnar, the channel width of the oxide semiconductor 15 corresponds to the width of the columnar structure. Furthermore, if the channel width of the oxide semiconductor 15 differs depending on the observation direction (for example, if the channel width differs when observed from a direction perpendicular to the plane of Figure 2 and when observed from the left or right direction in Figure 2), the channel width when observed from at least one direction may be within the above range.

[0021] The thickness of the second insulating film 16 is, for example, 1 Å to 500 nm, preferably 1 nm to 100 nm. In order to suppress the capacitance of the second insulating film 16 from becoming a parasitic component, the thickness of the second insulating film 16 may be 50 nm or less, 10 nm or less, or 2 nm or less within the above range. The channel width of the oxide semiconductor 15 and the thickness of the second insulating film 16 can be measured in the same manner as the channel length of the oxide semiconductor 15.

[0022] In transistor 10, the first electrode 11 can function as a source electrode, and the second electrode 12 can function as a drain electrode. In other examples, the first electrode 11 can function as a drain electrode, and the second electrode 12 can function as a source electrode. The third electrode 13 can function as a gate electrode. The oxide semiconductor 15 can function as a channel (current path) of transistor 10. For example, when a gate voltage is applied to the third electrode 13, which is the gate electrode, the first electrode 11 and the second electrode 12 are electrically connected by the oxide semiconductor 15, and transistor 10 is in the ON state. When no gate voltage is applied, the electrical connection between the first electrode 11 and the second electrode 12 by the oxide semiconductor 15 is released, and transistor 10 is in the OFF state.

[0023] Furthermore, in this specification, "electrically connected" includes cases where a connection is made via "something that has some kind of electrical function." Here, "something that has some kind of electrical function" is not particularly limited as long as it enables the exchange of electrical signals between the connected objects.

[0024] In the transistor 10, the oxide semiconductor 15 is provided to connect the first electrode 11 and the second electrode 12. "Provided to connect the first electrode 11 and the second electrode 12" means that it is provided in a state in which the first electrode 11 and the second electrode 12 can be electrically connected. Therefore, the oxide semiconductor 15 does not need to be in physical contact with the first electrode 11 and the second electrode 12; for example, a conductive material may be provided between the oxide semiconductor 15 and the first electrode 11 and / or the second electrode 12.

[0025] As described above, one feature of this embodiment is that the oxide semiconductor 15 is a single-crystal oxide semiconductor or polycrystalline oxide semiconductor having a bixbite structure and mainly composed of indium oxide. Therefore, as described above, the number of grain boundaries in the oxide semiconductor 15 can be significantly reduced, and furthermore, the number of grain boundaries can be reduced to zero. As a result, hydrogen diffusion is suppressed and variations in operation are reduced.

[0026] Furthermore, whether the oxide semiconductor 15 is a single-crystal oxide semiconductor or a polycrystalline oxide semiconductor can be determined using the TEM-ED mapping (Transmission Electron Microscopy Electron Diffraction Mapping) method. The TEM-ED mapping method is sometimes referred to as the ACOM-TEM (Automated Crystal Orientation Mapping Transmission Electron Microscopy) method. The following describes the measurement of oxide semiconductor films using the TEM-ED mapping method.

[0027] TEM-ED mapping is an analytical method that measures the crystal orientation within the measurement area of ​​an object by irradiating the measurement area with an electron beam and analyzing the electron diffraction pattern observed after passing through the object. By continuously analyzing the electron diffraction pattern at multiple measurement points within the measurement area, information regarding the crystal orientation within or between crystal grains can be obtained.

[0028] Furthermore, when applying the TEM-ED mapping method to the oxide semiconductor 15 of the transistor 10, a thin film sample including a cross-section of the oxide semiconductor 15 of the transistor 10 is used as the object to be measured (TEM sample). In addition, the TEM-ED mapping method is a measurement of a minute region using a TEM sample, and the measurement point where the electron diffraction pattern is observed is preferably the center point in the film thickness direction of the oxide semiconductor 15. The step interval is preferably, for example, 0.1 to 1 nm.

[0029] The TEM-ED mapping method provides information about crystal orientation, allowing for the definition of grain boundaries based on crystal orientation. A grain boundary is defined as existing between two measurement points when the difference in crystal orientation between the two points exceeds 5°. If the crystal orientations measured by TEM-ED mapping are consistent and no grain boundaries are detected, it can be determined that the material is a single-crystal oxide semiconductor. Conversely, if grain boundaries are detected, it can be determined that the material is a polycrystalline oxide semiconductor.

[0030] The number of grain boundaries in the oxide semiconductor 15 is preferably 0 to 5, more preferably 0 to 3, more preferably 0 to 1, and more preferably 0. The number of grain boundaries in the oxide semiconductor 15 may also be 1 or more, preferably 1 to 5. If the oxide semiconductor 15 has regions other than the channel region connecting the first electrode 11 and the second electrode 12, the number of grain boundaries should be counted not only in the channel region but also in the other regions. This is because hydrogen diffusion into the oxide semiconductor 15 can occur due to grain boundaries occurring outside the channel region. The number of grain boundaries is the number of grain boundaries confirmed when the entire oxide semiconductor 15 is measured by the TEM-ED described above.

[0031] As described above, the oxide semiconductor 15 is a single-crystal oxide semiconductor or polycrystalline oxide semiconductor having a bixbite structure and mainly composed of indium oxide. "Mainly composed of indium oxide" means that more than 50% by mass of the material constituting the crystalline oxide semiconductor is indium oxide. The presence or absence of a bixbite structure can be determined based on the X-ray diffraction pattern in X-ray diffraction (XRD) or the electron diffraction spots in electron diffraction (especially TEM-ED as described above). In one embodiment, the oxide semiconductor 15 is a polycrystalline oxide semiconductor. In one embodiment, the oxide semiconductor 15 is a single-crystal oxide semiconductor.

[0032] In one embodiment, the ratio of indium atoms to the total metal atoms contained in the oxide semiconductor 15 is 80 atomic% or more, 90 atomic% or more, or 95 atomic% or more. The content (atomic ratio) of each metal element in the oxide semiconductor 15 can be analyzed by TEM-EDS (Energy Dispersive X-ray Spectroscopy) measurement using an electron microscope.

[0033] In one embodiment, the oxide semiconductor 15 is a single-crystal oxide semiconductor or polycrystalline oxide semiconductor having a bixbite structure with indium oxide as the main component, and may contain other metal atoms. For example, in addition to indium oxide (IO), the oxide semiconductor 15 may also be indium gallium oxide (IGO), in which gallium is dissolved in the main component indium oxide, or indium gallium aluminum oxide (IGAO), in which gallium and aluminum are dissolved in the main component indium oxide. In one embodiment, the indium oxide content of the oxide semiconductor 15 may be 55% by mass or more, 60% by mass or more, 70% by mass or more, 80% by mass or more, 90% by mass or more, 95% by mass or more, 97% by mass or more, 98% by mass or more, or 99% by mass, or 100% by mass.

[0034] In one embodiment, the oxide semiconductor 15 contains a trivalent metal. The trivalent metal is preferably Ga and Al, with Ga being more preferred. In one embodiment, the crystalline oxide semiconductor further contains Ga or Al, may contain Ga, may contain Al, or may contain both Ga and Al. In one embodiment, the atomic ratio of the trivalent metal to all metal elements contained in the oxide semiconductor 15 ([trivalent metal] / ([trivalent metal] + [all metal elements other than the trivalent metal]) × 100) may be 0 to 30 at%, 0.5 to 25 at%, 1.0 to 22 at%, 1.5 to 20 at%, 2.0 to 15 at%, or 3.0 to 10 at%. Here, "trivalent metal" may be read as Ga and Al. In one embodiment, the atomic ratio of Ga to all metal elements contained in the oxide semiconductor 15 ([Ga] / ([Ga] + [all metal elements other than Ga]) × 100) may be 0 to 30 at%, 0.5 to 25 at%, 1.0 to 22 at%, 1.5 to 20 at%, 2.0 to 15 at%, or 3.0 to 10 at%. In one embodiment, the atomic ratio of Al to all metal elements contained in the oxide semiconductor 15 ([Al] / ([Al] + [all metal elements other than Al]) × 100) may be 0 to 30 at%, 0.5 to 25 at%, 1.0 to 22 at%, 1.5 to 20 at%, 2.0 to 15 at%, or 3.0 to 10 at%.

[0035] When the oxide semiconductor 15 contains Ga, it tends to enlarge the crystal grains of the oxide semiconductor 15 and reduce the number of crystal grain boundaries in the oxide semiconductor 15, which is therefore preferable.

[0036] In one embodiment, the oxide semiconductor 15 further contains one or more additive elements selected from B, Si, Sc, Zn, Ce, Y, Zr, Sn, Sm, Hf, Ta, and Yb. In one embodiment, the atomic ratio of the total amount of additive elements to the total amount of metal elements contained in the oxide semiconductor 15 ([total amount of additive elements] / ([total amount of additive elements] + [total metal elements other than additive elements]) × 100) is 0 to 10 at%, and may be 0.1 to 8 at%, 0.5 to 5 at%, or 1 to 3 at%.

[0037] In one embodiment, the oxide semiconductor 15 does not need to contain Zn. The atomic ratio of Zn to all metal elements contained in the oxide semiconductor 15 ([amount of Zn] / ([amount of Zn] + [amount of all metal elements other than Zn]) × 100) is 0 to 3 at%, and may be 0 to 1 at%, 0 to 0.1 at%, or 0 to 0.01 at%. By not including Zn in the oxide semiconductor 15, the diffusion rate of oxygen into the oxide semiconductor 15 can be suppressed, and it tends to be possible to provide transistors with even less variation.

[0038] By making the oxide semiconductor 15 as described above, hydrogen diffusion into the oxide semiconductor is further suppressed, and variations in the operation of the transistor 10 tend to be further suppressed.

[0039] Each of the first electrode 11, the second electrode 12, and the third electrode 13 is not particularly limited as long as they are conductors. Examples of conductors include indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), aluminum (Al), silicon (Si), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), germanium (Ge), molybdenum (Mo), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), tantalum (Ta), iridium (Ir), platinum (Pt), tungsten (W), titanium (Ti), titanium nitride (TiN), aluminum nitride (AlN), manganese nitride (MnN), molybdenum nitride (MoN), and nickel nitride (Ni3N).

[0040] The first insulating film 14a, the second insulating film 16, and the third insulating film 14b are not particularly limited as long as they contain an insulator or are films made of an insulator. Examples of insulators include aluminum oxide, magnesium oxide, silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Furthermore, the first insulating film 14a, the second insulating film 16, and the third insulating film 14b may each be a laminated film of the above materials. The insulating films may also contain La, N, Zr, etc. The insulators contained in the first insulating film 14a, the second insulating film 16, and the third insulating film 14b may be the same or different from each other.

[0041] An example of a manufacturing method for the transistor 10 according to this embodiment is described below, but the manufacturing method is not limited to this example.

[0042] Figure 3 illustrates an example of a method for manufacturing the transistor 10 according to this embodiment. Figure 3(a) shows the oxide semiconductor 15, the second electrode 12, and the insulating film 19 supporting the second electrode 12 as shown in Figures 1 and 2. Although not shown in Figure 3(a), the second electrode 12 and the insulating film 19 may be formed on another substrate. The second electrode 12 may also be connected to an element outside the transistor according to this embodiment. The insulating film 19 and the second electrode 12 can be formed by known methods.

[0043] Next, as shown in Figure 3(b), the third insulating film 14b, the third electrode 13, and the first insulating film 14a are formed in this order. At this time, as will be described later, the third electrode 13 may be formed to be connected to the word line. Alternatively, the third electrode 13 itself may be used as the word line.

[0044] The third insulating film 14b is formed by, for example, depositing a film containing the above-mentioned insulator by various methods such as chemical vapor deposition (CVD), plasma CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), sol-gel method, and coating method.

[0045] The third electrode 13 is formed by depositing a conductive material such as tungsten, as described above. The third electrode 13 may be patterned into any shape. The pattern of the third electrode 13 may be formed during film deposition, or it may be formed by etching after film deposition.

[0046] The first insulating film 14a is formed by depositing a film containing the above-mentioned insulator using various methods such as chemical vapor deposition (CVD), plasma CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), sol-gel method, and coating method.

[0047] Next, as shown in Figure 3(c), through-holes H are formed by etching, penetrating the first insulating film 14a, the third electrode 13, and the third insulating film 14b. Various etching methods, such as dry etching and wet etching, may be used to form the through-holes H. Alternatively, a resist may be deposited on the first insulating film 14a before etching to define the region where the through-holes H will be formed.

[0048] Next, as shown in Figure 3(d), a second insulating film 16 containing the above-described insulator is formed by various methods such as chemical vapor deposition (CVD), plasma CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), sol-gel method, and coating method.

[0049] Next, as shown in Figure 3(e), an oxide semiconductor 15 is formed in the through-hole H where the second insulating film 16 is formed. Methods for forming the oxide semiconductor 15 include chemical vapor deposition (CVD), plasma CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), sol-gel method, and coating method. Note that CVD methods include metalloorganic CVD (MO-CVD), inductively coupled plasma CVD (ICP-CVD), and mist CVD. PVD methods include DC sputtering, AC sputtering, RF sputtering, ICP sputtering, reactive sputtering, and ion plating. The oxide semiconductor 15 may also be formed as a crystalline oxide semiconductor by first forming an amorphous oxide semiconductor and then performing post-annealing as described later. A crystalline oxide semiconductor may be formed by performing post-annealing after the formation of an amorphous oxide semiconductor, or post-annealing may be performed after the oxide semiconductor has crystallized and a crystalline oxide semiconductor has been formed. Alternatively, a crystalline oxide semiconductor may be formed without post-annealing, or post-annealing may be performed after the formation of the crystalline oxide semiconductor to adjust the crystallinity of the crystalline oxide semiconductor.

[0050] It is preferable to perform post-annealing on the oxide semiconductor 15 formed in the process shown in Figure 3(e). Post-annealing can be performed after the deposition of the oxide semiconductor film, for example, after or before the formation of the first electrode 11 in a subsequent step. The state of the oxide semiconductor before post-annealing may be amorphous or crystalline. The annealing atmosphere may contain nitrogen or oxygen and may be under vacuum or air. The annealing temperature is preferably 250°C to 600°C, more preferably 300°C to 500°C, and even more preferably 350°C to 450°C. The annealing time is 5 minutes to 2 hours, preferably 30 minutes to 1 hour. The oxide semiconductor 15 can have fewer grain boundaries by being formed by atomic layer deposition (ALD), which will be described later. Furthermore, by performing post-annealing, a polycrystalline or single-crystal crystalline oxide semiconductor can be formed.

[0051] As a film deposition method that reduces the number of grain boundaries in the oxide semiconductor 15, it is effective to alternately stack an indium oxide layer and layers other than indium oxide, such as a gallium oxide layer and / or an aluminum oxide layer, using a single-source method (a method of forming an oxide semiconductor using two or more metals, in which each component is vaporized and supplied independently). This allows for appropriate division of the indium oxide layer, suppressing the formation of crystal nuclei and reducing the number of grain boundaries. However, if the number of layers other than the indium oxide layer is excessive, the oxide semiconductor 15 may not crystallize even after annealing. It is preferable to control the amount of layers other than the indium oxide layer (number of layers, or thickness per layer) within an appropriate range (a range in which the oxide semiconductor 15 does not become amorphous after annealing). Furthermore, it is preferable to adjust the type and number of layers so that the oxide semiconductor is amorphous immediately after deposition and crystallizes after annealing, as this reduces the likelihood of patterning defects during manufacturing. In the case of an indium oxide layer alone, crystallization is likely to occur during film formation. Therefore, from the viewpoint of suppressing patterning defects, it is preferable to appropriately include layers other than the indium oxide layer.

[0052] Next, as shown in Figure 3(f), a first electrode 11 is formed on the upper layer of the oxide semiconductor 15. The first electrode 11 may be patterned into any shape. The first electrode 11 may have a pattern formed during film deposition, or it may have a pattern formed by etching after film deposition.

[0053] As described above, a transistor 10 as shown in Figures 1 and 2 can be obtained.

[0054] In the first embodiment, the case was shown in which the second insulating film 16 completely surrounds the side surface of the columnar oxide semiconductor 15, but it is not necessarily limited to this, and for example, the second insulating film 16 may surround at least a part of the columnar oxide semiconductor 15.

[0055] In the manufacturing method described above, the oxide semiconductor 15 is formed in the through-hole H where the second insulating film 16 is formed. Therefore, atomic layer deposition (ALD) is preferred as the method for forming the oxide semiconductor 15. Atomic layer deposition (ALD) is a thin film formation method in which a process of alternately exposing a raw material (sometimes called a precursor) containing a metal element constituting the film to be deposited (here, the oxide semiconductor 15) and an oxidizing agent to the substrate surface constitutes one cycle, forming one atomic layer in one cycle, and repeating this cycle until the desired film thickness is achieved. Therefore, by using ALD, a dense oxide semiconductor 15 can be formed even in the region near the second electrode 12, which is far from the opening, in the through-hole H where the second insulating film 16 is formed.

[0056] One atomic layer deposition cycle of ALD may include the following four steps. (1) Vaporize the precursor (precursor) as a raw material in a container containing the precursor, introduce it into the chamber, apply a predetermined system pressure, react it with the OH groups on the substrate surface or film surface for a predetermined time, and adsorb single molecules. When the vapor pressure of the precursor is low, the container containing the precursor may be heated to promote vaporization. When the vapor pressure of the precursor is high, the container containing the precursor may be cooled to suppress vaporization for adjustment. (2) Remove unreacted raw materials and by-produced gases from the chamber by purging with an inert gas to deposit one atomic layer. (3) Introduce a reactive gas into the chamber and oxidize the metal of the precursor using heat, plasma, or the like. (4) Remove unreacted oxidizing agents and by-produced gases by purging with an inert gas. After step (4), return to step (1), and steps (1) to (4) may be repeated until the desired film thickness is achieved.

[0057] When performing ALD, various ALD apparatuses can be used. Specifically, for example, apparatuses capable of bubbling and supplying the precursor, and apparatuses having a vaporization chamber can be mentioned. In addition, apparatuses capable of performing plasma treatment or the like on the reactive gas (oxidizing agent) can be mentioned. Note that it is not limited to a single wafer type apparatus equipped with a film formation chamber, and an apparatus capable of simultaneously processing multiple wafers using a batch furnace may also be used.

[0058] Examples of the types of ALD precursors include organometals (e.g., AlMe ３ ), metal hydrides (e.g., AsH ３ ), metal alkoxides (e.g., Ti(OCHMe ２ ), metal amides (e.g., Ti(NMe ４ ), β-diketonates (e.g., Co(acac) ２ ), metallocenes (e.g., MgCp ４ ), metal amidinates, and the like. Various metal compounds are commercially available as ALD precursors, and a precursor and an oxidizing agent capable of forming the target film formation object may be selected. ２ ), metallocenes (e.g., MgCp ２ ), metal amidinates, and the like. Various metal compounds are commercially available as ALD precursors, and a precursor and an oxidizing agent capable of forming the target film formation object may be selected.

[0059] Examples of precursors include compounds of silicon or metals, which consist of one or more compounds selected from the group consisting of compounds used as organic ligands, such as alkyl compounds, alcohol compounds, glycol compounds, β-diketone compounds, cyclopentadiene compounds, and organic amine compounds.

[0060] Examples of precursor metal species include lithium, sodium, potassium, magnesium, calcium, strontium, barium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, manganese, iron, ruthenium, cobalt, rhodium, iridium, nickel, palladium, platinum, copper, silver, gold, zinc, boron, aluminum, silicon, indium, gallium, germanium, tin, lead, antimony, bismuth, scandium, ruthenium, yttrium, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium.

[0061] If the oxide semiconductor 15 contains indium atoms (In), an In-containing precursor may be used. If the oxide semiconductor 15 contains other metals, a precursor containing those metals may be used. When forming an oxide semiconductor using two or more metals, there are two methods: vaporizing and supplying each component independently (sometimes referred to as the "single-source method") and vaporizing and supplying a mixed raw material in which multi-component raw materials are pre-mixed to a desired composition (sometimes referred to as the "cocktail-source method"). In the single-source method, it is preferable that each precursor used has similar thermal and / or oxidative decomposition behavior. In the cocktail-source method, it is preferable that each precursor has similar thermal and / or oxidative decomposition behavior and does not undergo alteration due to chemical reactions during mixing.

[0062] The following are examples of compounds that can be used as organic ligands for precursors. Furthermore, depending on the valency of the central metal, multiple ligands from the following list may coordinate. In a precursor, when multiple ligands coordinate to the central metal, these ligands may be identical to each other, or two or more ligands may be combined.

[0063] Alkyl compounds used as organic ligands for precursors include methyl, ethyl, propyl, isopropyl, butyl, 2-butyl, isobutyl, 3-butyl, pentyl, isopentyl, and 3-pentyl.

[0064] Alcohol compounds used as organic ligands for precursors include alkyl alcohols such as methanol, ethanol, propanol, isopropyl alcohol, butanol, 2-butyl alcohol, isobutyl alcohol, 3-butyl alcohol, pentyl alcohol, isopentyl alcohol, and 3-pentyl alcohol; 2-methoxyethanol, 2-ethoxyethanol, 2-butoxyethanol, 2-(2-methoxyethoxy)ethanol, 2-methoxy-1-methylethanol, 2-methoxy-1,1-dimethylethanol, 2-ethoxy-1,1-dimethylethanol, 2-isopropoxy-1,1-dimethylethanol, and 2-butoxy Examples include ether alcohols such as -1,1-dimethylethanol, 2-(2-methoxyethoxy)-1,1-dimethylethanol, 2-propoxy-1,1-diethylethanol, 2-s-butoxy-1,1-diethylethanol, and 3-methoxy-1,1-dimethylpropanol; and dialkylamino alcohols such as dimethylaminoethanol, ethylmethylaminoethanol, diethylaminoethanol, dimethylamino-2-pentanol, ethylmethylamino-2-pentanol, dimethylamino-2-methyl-2-pentanol, ethylmethylamino-2-methyl-2-pentanol, and diethylamino-2-methyl-2-pentanol.

[0065] Examples of glycol compounds used as organic ligands for precursors include 1,2-ethanediol, 1,2-propanediol, 1,3-propanediol, 2,4-hexanediol, 2,2-dimethyl-1,3-propanediol, 2,2-diethyl-1,3-propanediol, 1,3-butanediol, 2,4-butanediol, 2,2-diethyl-1,3-butanediol, 2-ethyl-2-butyl-1,3-propanediol, 2,4-pentanediol, 2-methyl-1,3-propanediol, 2-methyl-2,4-pentanediol, 2,4-hexanediol, and 2,4-dimethyl-2,4-pentanediol.

[0066] Examples of β-diketone compounds used as organic ligands for precursors include acetylacetone, hexane-2,4-dione, 5-methylhexane-2,4-dione, heptane-2,4-dione, 2-methylheptane-3,5-dione, 5-methylheptane-2,4-dione, 6-methylheptane-2,4-dione, 2,2-dimethylheptane-3,5-dione, 2,6-dimethylheptane-3,5-dione, 2,2,6-trimethylheptane-3,5-dione, 2,2,6,6-tetramethylheptane-3,5-dione, octane-2,4-dione, 2,2,6-trimethyloctane-3,5-dione, 2,6-dimethyloctane-3,5-dione, 2,9-dimethylnonane-4,6-dione, and 2-methyl-6-ethyl Examples include alkyl-substituted β-diketones such as decane-3,5-dione and 2,2-dimethyl-6-ethyldecane-3,5-dione; fluorine-substituted alkyl β-diketones such as 1,1,1-trifluoropentane-2,4-dione, 1,1,1-trifluoro-5,5-dimethylhexane-2,4-dione, 1,1,1,5,5,5-hexafluoropentane-2,4-dione, and 1,3-diperfluorohexylpropane-1,3-dione; and ether-substituted β-diketones such as 1,1,5,5-tetramethyl-1-methoxyhexane-2,4-dione, 2,2,6,6-tetramethyl-1-methoxyheptane-3,5-dione, and 2,2,6,6-tetramethyl-1-(2-methoxyethoxy)heptane-3,5-dione.

[0067] Examples of cyclopentadiene compounds used as organic ligands for precursors include cyclopentadiene, methylcyclopentadiene, ethylcyclopentadiene, propylcyclopentadiene, isopropylcyclopentadiene, butylcyclopentadiene, 2-butylcyclopentadiene, isobutylcyclopentadiene, 3-butylcyclopentadiene, dimethylcyclopentadiene, and tetramethylcyclopentadiene.

[0068] Examples of organic amine compounds used as organic ligands for precursors include methylamine, ethylamine, propylamine, isopropylamine, butylamine, 2-butylamine, 3-butylamine, isobutylamine, dimethylamine, diethylamine, dipropylamine, diisopropylamine, ethylmethylamine, propylmethylamine, and isopropylmethylamine.

[0069] In addition, metal halogen compounds (e.g., InCl ３ InBr ３ InF ３ (etc.) may be used as precursors. When multiple halogens coordinate to a metal, these halogens may be identical to each other, or two or more halogens may be combined. In addition, some of the halogens may be replaced with hydrogen.

[0070] Examples of indium-containing precursors include InCl ３ , TMIn (trimethyl indium), TEIn (triethyl indium), InCp (cyclopentadienyl indium (I)), InEtCp (ethylcyclopentadienyl indium(I)), In(acac) ３ (indium acetylacetonate), In(tmhd) ３ (indium 2,2,6,6-tetramethyl-3,5-heptanedionate), In[( ｉ PrN) ２ CNR ２ ] ３(R=Me) (indium-tris-guanidinates), Et ２ InN (TMS) ２ (diethyl[bis-(trimethylsilyl)amido]indium), INCA(diethyl[1,1,1-trimethyl-N- (trimethylsilyl)silanaminato]indium), DADI([3-(dimethylamino)propyl]dimethyl indium), In(dmamp) ３ ((1-dimethylamino-2-methyl-2-propoxy)indium), Me ２ Examples include In(EDPA)(dimethyl(N-ethoxy-2,2-dimethylpropanamido)indium) and tris(N,N'-disosopropylacetamidinato)indium(III).

[0071] These ALD precursors may be used individually or in combination of two or more types.

[0072] The precursors described above can be manufactured according to known manufacturing methods. For example, when an alcohol compound is used as an organic ligand, the precursor can be manufactured by reacting the inorganic salt or hydrate of the aforementioned metal with an alkali metal alkoxide of the alcohol compound. Examples of the inorganic salt or hydrate of the metal include metal halides and nitrates. Examples of alkali metal alkoxides include sodium alkoxide, lithium alkoxide, and potassium alkoxide.

[0073] H is an oxidizing agent used in ALD. ２ O, O ２ , O ３ , O ２ Plasma, H ２ O plasma, hydrogen peroxide (H ２ O ２ Examples include the following. These oxidizing agents may be used individually or in combination of two or more.

[0074] When using two or more oxidizing agents, they may be used simultaneously, or they may be used individually while changing between them. For example, as an oxidizing agent, O ２ Plasma and H ２ By using two types of O plasma, ２ High mobility obtained when using plasma, and H ２ By using O plasma, it is possible to take advantage of both the reduction in carbon concentration and the improved stability of mobility during heat treatment. By using two or more oxidizing agents, high mobility and low carbon concentration can be adjusted. Depending on the desired effect, O ２ Plasma and H ２ The proportion of O-plasma used, the order of use, the number of cycles, etc., should be selected as appropriate.

[0075] The pressure in the system (inside the film deposition chamber) in step (1) can be set appropriately according to the type of precursor, substrate temperature, etc. For example, 1 to 10,000 Pa is preferred, 10 to 1,000 Pa is more preferred, 50 to 500 Pa is even more preferred, and 80 to 120 Pa is particularly preferred.

[0076] In one embodiment, in the film formation process, H is used as the oxidizing agent. ２ O plasma is used. In one embodiment, in the film formation process, O is used as the oxidizing agent. ２ Plasma is used. In one embodiment, in the film deposition process, O is used as the oxidizing agent. ３ These oxidizing agents are used. By using these oxidizing agents, it is possible to control the electrical properties of the oxide semiconductor film to a favorable state.

[0077] To vaporize the precursor, the container containing the precursor may be heated to a temperature at which the precursor is sufficiently vaporized, as needed. If a precursor with a high vapor pressure is used, the container containing the precursor may be cooled as needed. In one embodiment, the container containing the indium-containing precursor (e.g., triethylindium) is heated to a temperature in the range of 25 to 150°C. The above temperature is preferably in the range of 50 to 150°C, and more preferably in the range of 75 to 125°C.

[0078] In the manufacturing method described above, the substrate temperature during film formation is usually in the range of 50 to 600°C, preferably 85 to 500°C, more preferably 80 to 350°C, and even more preferably 100 to 250°C.

[0079] Furthermore, the amount of oxide semiconductor film grown per ALD process cycle varies depending on the type of precursor and reactive gas used during film formation, as well as the substrate temperature during film formation.

[0080] The growth rate per ALD process cycle is called Growth per Cycle (GPC), and can be calculated, for example, by measuring the film thickness of the oxide semiconductor after repeating 30 ALD cycles. Here, GPC changes depending on the combination of precursor, oxidizer, and substrate temperature, and also changes depending on the type of substrate. Therefore, the number of cycles can be set appropriately by taking these factors into consideration, as it depends on numerous factors such as the type and combination of precursor and oxidizer used, the type of substrate, the substrate temperature during film formation, and the desired film thickness.

[0081] Also, as an oxidizing agent, O ３ When using, the substrate temperature during film formation is preferably above 100°C, more preferably 110-250°C, 120-230°C, or 130-220°C. H is used as the oxidizing agent. ２ O plasma and O ２ When using plasma, the substrate temperature during film deposition is preferably 100 to 150°C.

[0082] Examples of inert gases used to purge unreacted raw materials and unreacted oxidizing agents include argon and nitrogen, and in the method of this embodiment, argon or nitrogen is preferred.

[0083] In step (3) above, it is preferable to generate a plasma of the reactive gas (oxidizer).

[0084] (Second Embodiment) Next, another example of the transistor according to this embodiment (second embodiment) will be described with reference to Figures 4 and 5. Figure 4 is a schematic perspective view showing a cross-section of the transistor according to the second embodiment. Figure 5 is a schematic cross-sectional view of the transistor. In Figures 4 and 5, the same reference numerals as in Figures 1 and 2 indicate the same components, and unless otherwise specified, the descriptions given for Figures 1 and 2 will be incorporated by reference.

[0085] In the second embodiment, the transistor 10 includes a first electrode 11, a second electrode 12, a third electrode 13, an oxide semiconductor 15, a first insulating film 14, and a second insulating film 16. At least a portion of the third electrode 13 is located between the first electrode 11 and the second electrode 12. At least a portion of the third electrode 13 may be located on the opposite side of the first electrode 11 from the second electrode 12, or on the opposite side of the second electrode 12 from the first electrode 11. The first insulating film 14 is located between the first electrode 11 and the second electrode 12. Here, the first electrode 11 and the second electrode 12 are stacked with the first insulating film 14 in between. As a result, the first electrode 11 and the second electrode 12 are electrically insulated by the first insulating film 14. The third electrode 13 is provided adjacent to the oxide semiconductor 15 without contacting it. Specifically, the third electrode 13 is adjacent to the oxide semiconductor 15 via the second insulating film 16. The second insulating film 16 may be provided between the third electrode 13 and the oxide semiconductor 15 to insulate the third electrode 13 from the oxide semiconductor 15.

[0086] The oxide semiconductor 15 penetrates at least the first insulating film 14 and is provided to connect the first electrode 11 and the second electrode 12. Here, the oxide semiconductor 15 is provided in a columnar shape, penetrating the first electrode 11 and the first insulating film 14 in that order. The columnar oxide semiconductor 15 has a recess formed from one end (upper side in Figures 4 and 5) to the other end (lower side in Figures 4 and 5), and the second insulating film 16 is formed on the inner circumferential surface and bottom surface of the recess. The third electrode 13 is provided to fill the recess where the second insulating film 16 is formed. From one viewpoint, it can also be said that the oxide semiconductor 15 has a cylindrical portion provided penetrating the first insulating film 14, the second insulating film 16 has a cylindrical portion provided on the inner wall of the cylindrical portion of the oxide semiconductor 15, and the third electrode 13 has a portion provided inside the cylindrical portion of the second insulating film 16.

[0087] In the second embodiment as well, the oxide semiconductor 15 is a single-crystal oxide semiconductor or a polycrystalline oxide semiconductor. Therefore, hydrogen diffusion in the oxide semiconductor 15 can be suppressed, and variations in operation can be suppressed.

[0088] The dimensions of the transistor 10 may be designed as appropriate depending on its application. The channel length of the oxide semiconductor 15 is, for example, 1 nm to 10 μm, preferably 2 nm to 1000 nm. The channel length of the oxide semiconductor 15 is the length of the oxide semiconductor 15 along the thickness direction (vertical direction in Figures 4 and 5) of the laminate in which the first electrode 11, the first insulating film 14, and the second electrode 12 are stacked in this order, and may coincide with the depth of the recess in the oxide semiconductor 15.

[0089] The thickness of the oxide semiconductor 15 is, for example, 1 nm to 500 nm, preferably 1 nm to 100 nm. The thickness of the oxide semiconductor 15 may be the average thickness along the channel length. The average thickness along the channel length is the average value obtained when the thickness is measured at 10 or more locations along the channel length.

[0090] The thickness of the second insulating film 16 is, for example, 1 Å to 500 nm, preferably 1 nm to 100 nm. In order to suppress the capacitance of the second insulating film 16 from becoming a parasitic component, the thickness of the second insulating film 16 may be 50 nm or less, 10 nm or less, or 2 nm or less.

[0091] The channel length and thickness of the oxide semiconductor 15, and the thickness of the second insulating film 16, can be measured in the same manner as in the first embodiment.

[0092] The first electrode 11, the second electrode 12, the third electrode 13, the first insulating film 14, the second insulating film 16, and the oxide semiconductor 15 may be described by reference to the first embodiment.

[0093] The method for manufacturing the transistor 10 according to the second embodiment is not particularly limited, and can be manufactured by known methods with reference to the manufacturing method according to the first embodiment, except that the oxide semiconductor 15 is made of a single-crystal oxide semiconductor or a polycrystalline oxide semiconductor. For example, the transistor 10 according to the second embodiment may be manufactured as follows: After forming a laminate of the second electrode 12, the first insulating film 14, and the first electrode 11, through holes are formed so as to penetrate the first electrode 11 and the first insulating film 14. After forming the oxide semiconductor 15, the second insulating film 16 and the third electrode 13 are formed. As a method for making the oxide semiconductor 15 a single-crystal oxide semiconductor or a polycrystalline oxide semiconductor, the method described in the first embodiment can be mentioned.

[0094] Next, another example of the transistor according to this embodiment (a third embodiment) will be described with reference to Figures 6 and 7. Figure 6 is a schematic perspective view showing a cross-section of the transistor according to the third embodiment. Figure 7 is a schematic cross-sectional view of the same transistor. In Figures 6 and 7, the same reference numerals as in Figures 1 and 2 indicate the same components, and unless otherwise specified, the descriptions given for Figures 1 and 2 will be incorporated by reference.

[0095] In this third embodiment, the transistor 10 comprises a first electrode 11, a second electrode 12, a third electrode 13, oxide semiconductors 15, 15', and a first insulating film 14. The third electrode 13 is located between the first electrode 11 and the second electrode 12. The first insulating film 14 is located between the first electrode 11 and the third electrode 13. Here, the first electrode 11 and the second electrode 12 are stacked with the first insulating film 14 in between. As a result, the first electrode 11 and the second electrode 12 are electrically insulated by the first insulating film 14. The third electrode 13 is provided so as to be adjacent to the oxide semiconductors 15, 15' without contact with them. Specifically, the third electrode 13 is adjacent to the oxide semiconductors 15, 15' via the first insulating film 14 located between the third electrode 13 and the oxide semiconductors 15, 15'. In this sense, it can be said that the first insulating film 14 in the third embodiment also serves the role of the second insulating film 16 in the first and second embodiments.

[0096] The oxide semiconductors 15 and 15' connect the first electrode 11 and the second electrode 12, respectively.

[0097] In the third embodiment as well, the oxide semiconductor 15 is a single-crystal oxide semiconductor or a polycrystalline oxide semiconductor. Therefore, hydrogen diffusion in the oxide semiconductor 15 can be suppressed, and variations in operation can be suppressed.

[0098] The dimensions of the transistor 10 may be designed as appropriate depending on its application. The channel lengths of the oxide semiconductors 15 and 15' are, for example, 1 nm to 10 μm, preferably 2 nm to 1000 nm. The channel length of the oxide semiconductor 15 is the length of the oxide semiconductors 15 and 15' along the thickness direction (up and down direction in Figures 6 and 7) of the laminate in which the first electrode 11, the first insulating film 14, and the second electrode 12 are stacked in this order, and may coincide with the distance between the first electrode 11 and the second electrode 12.

[0099] The thickness of the oxide semiconductors 15 and 15' is, for example, 1 nm to 500 nm, preferably 1 nm to 100 nm. The thickness of the oxide semiconductor 15 may be the average thickness along the channel length. The average thickness along the channel length is the average value obtained when the thickness is measured at 10 or more locations along the channel length.

[0100] The thickness of the first insulating film 14 is, for example, 1 Å to 500 nm, preferably 1 nm to 100 nm. In order to suppress the capacitance of the first insulating film 14 from becoming a parasitic component, the thickness of the first insulating film 14 may be 50 nm or less, 10 nm or less, or 2 nm or less.

[0101] The channel length and thickness of the oxide semiconductors 15 and 15', and the thickness of the first insulating film 14, can be measured in the same manner as in the first embodiment.

[0102] With respect to the first electrode 11, the second electrode 12, the third electrode 13, the first insulating film 14, and the oxide semiconductor 15, the descriptions in the first and second embodiments may be applied. With respect to the first insulating film 14, the description of the second insulating film 16 in the first and second embodiments may be applied.

[0103] The method for manufacturing the transistor 10 according to the third embodiment is not particularly limited, and can be manufactured by referring to known methods (for example, the method described in International Publication No. 2020 / 076850, etc.) while referring to the manufacturing method according to the first embodiment, except that the oxide semiconductor 15 is made of a single-crystal oxide semiconductor or a polycrystalline oxide semiconductor. The method for making the oxide semiconductor 15 a single-crystal oxide semiconductor or a polycrystalline oxide semiconductor is the method described in the first embodiment. The methods for forming the first electrode 11, the second electrode 12, the third electrode 13, the first insulating film 14, and the oxide semiconductor 15 may be adapted from the descriptions in the first and second embodiments. The method for forming the first insulating film 14 may be adapted from the descriptions of the second insulating film 16 in the first and second embodiments.

[0104] 2. Semiconductor Devices A semiconductor device according to one aspect of the present invention includes a transistor according to one aspect of the present invention. The semiconductor device according to this aspect can suppress hydrogen diffusion in the oxide semiconductor in the transistor, thus suitably achieving normally-off and high reliability. The type of semiconductor device is not particularly limited, but from the viewpoint of demonstrating the above-mentioned effects significantly, it is preferable to use semiconductor memory devices such as volatile memories such as DRAM (Dynamic Random Access Memory) and SRAM (Static RAM); and non-volatile memories such as mask ROM (Read Only Memory), EPROM (Erasable Programmable ROM), EEPROM (Electrically Erasable Programmable ROM), flash memory (NOR type flash memory, NAND type flash memory), MRAM (Magnetoresistive RAM), FeRAM (Ferroelectric RAM), ReRAM (Resistive RAM), etc. Alternatively, the semiconductor device according to this embodiment may be a logic device such as TTL (Transistor-Transistor Logic), CMOS (Complementary Metal-Oxide-Semiconductor), BiCMOS, PLD (Programmable Logic Device), FPGA (Field Programmable Gate Array), CPU (Central Processing Unit), or MPU (Microprocessor Unit). Furthermore, since the transistor according to one embodiment of the present invention can be fitted with a vertical structure as shown in each embodiment, it is suitable for densely arranging multiple transistors in a semiconductor memory device and contributes to the miniaturization of the semiconductor memory device. In addition, since the transistor according to one embodiment of the present invention uses an oxide semiconductor as the channel, it tends to have a small leakage current. Therefore, by using it in a semiconductor memory device, the capacitance of the capacitor can be reduced or the capacitor can be omitted. As a result, by using the transistor according to one embodiment of the present invention, the semiconductor memory device can be miniaturized.

[0105] Semiconductor devices can contain a large number of transistors. For example, a DRAM contains hundreds of millions of memory cells, and the transistors that make up these memory cells also number in the hundreds of millions. In addition, DRAM uses multiple transistors other than memory cells. To suppress variations in the operation of semiconductor devices, it is preferable to suppress variations in the performance of each transistor. To this end, it is preferable to reduce the number of grain boundaries in the oxide semiconductor, as well as to reduce the variation in the number of grain boundaries in the oxide semiconductor between each transistor. For example, it is preferable to suppress variations in the number of grain sizes in the oxide semiconductor contained in each of the multiple transistors contained in a semiconductor device. More specifically, when a semiconductor device contains four or more transistors, the coefficient of variation of the number of grain boundaries in the oxide semiconductor contained in each of the four adjacent transistors is, for example, 0.0 or more and 1.0 or less, preferably 0.0 or more and 0.8 or less, more preferably 0.0 or more and 0.6 or less, and even more preferably 0.0 or more and 0.4 or less. The coefficient of variation is a value calculated by calculating the ratio of the standard deviation to the mean ((standard deviation) / (mean)) for the number of grain boundaries in each oxide semiconductor.

[0106] To reduce the variation in the number of grain boundaries in the oxide semiconductor between each transistor, it is preferable to reduce the surface roughness of the underlying layer on which the oxide semiconductor film is deposited. Regarding surface roughness, it is preferable that the maximum height difference of the surface is less than 0.5 nm. A maximum height difference of less than 0.5 nm further suppresses variations in crystal nucleus formation, and tends to suppress variations in the crystal size of the oxide semiconductor film. The maximum height difference of the surface can be calculated from a cross-sectional TEM.

[0107] Figure 8 shows an example of a circuit configuration of a semiconductor memory device equipped with a transistor according to one aspect of the present invention. As shown in Figure 8, the semiconductor memory device 50 includes a transistor 10, a capacitor 51, a word line WL, and a bit line BL. The source electrode of the transistor 10 is connected to the bit line BL. The drain electrode of the transistor 10 is connected to one end of the capacitor 51. The gate electrode of the transistor 10 is connected to the word line WL. The other end of the capacitor 51 is grounded. The bit line BL may be connected to the first electrode 11 of the transistor 10, or to the second electrode 12. The word line WL may be connected to the third electrode 13 of the transistor 10. One end of the capacitor 51 may be connected to the first electrode 11 of the transistor 10, or to the second electrode 12.

[0108] In the example shown in Figure 8, a single memory cell 52 is formed by a transistor 10 and a capacitor 51. The memory cell 52 can store data based on the charge held by the capacitor 51. Note that the configuration of the memory cell 52 is not limited to this example, and in other examples, the capacitor 51 is omitted. When the capacitor 51 is omitted, data can be stored based on the charge held by the transistor 10 itself. In addition, two or more transistors may be combined to form the memory cell 52. If the transistor 10 itself is to have the function of holding charge, for example, one or more of the configurations described below can be applied. (1) The second insulating film is made of hafnium oxide (HfO ２ ), zirconium oxide (ZrO ２ (2) Use a high dielectric constant insulator such as (Pb, La)(Zr, Ti)O ３ (PLZT), SrTiO ３(STO), yttria-stabilized zirconia (YSZ), and other ferroelectric materials are used. (3) Hysteresis is utilized by adding an element that forms an energy level within the gap of the oxide semiconductor to the oxide semiconductor. (4) Parasitic capacitance is utilized by arranging a part of the source electrode and / or drain electrode and a part of the gate electrode so that they face each other across an insulating film. In (4) above, for example, parasitic capacitance can be utilized by arranging a part of one of the source electrode and drain electrode and a part of the gate electrode so that they face each other across an insulating film. In this case, the other of the source electrode and drain electrode may be arranged away from the gate electrode (for example, the distance between the other of the source electrode and drain electrode and the gate electrode may be longer than the distance between one of the source electrode and drain electrode and the gate electrode).

[0109] The semiconductor memory device 50 can read data stored in the memory cell 52 to the bit line BL by controlling the word line WL, and can also write data transferred to the bit line BL to the memory cell 52. The semiconductor memory device 50 is configured to include a memory cell array (not shown) consisting of a plurality of memory cells 52.

[0110] The following describes embodiments of the present invention, but the present invention is not limited to these embodiments. Molecular dynamics simulations based on first-principles calculations are used to obtain a-IGZO (amorphous-IGZO) and a-In ２ O ３ (Amorphous indium oxide), and c-In ２ O ３ Figure 9 shows the results of calculating the hydrogen diffusivity of (crystal-indium oxide: mainly composed of indium oxide and having a bixbite structure). In Figure 9, the horizontal axis represents time, and the vertical axis represents the mean square displacement (MSD, the part enclosed in < > in the following equation) in the Einstein relation relating to the diffusion coefficient, indicating the diffusivity of hydrogen atoms.

[0111]

[0112] In the above equation, D is the diffusion coefficient, T is time, d is the number of dimensions (=3), t is the simulation time, and r(t) is the coordinate at t. The result in Figure 9 is a-IGZO from a-In ２ O ３ The hydrogen diffusion rate is lower in a-In ２ O ３ More c-In ２ O ３ This indicates that the hydrogen diffusion rate is lower. The reason for this is thought to be that "amorphous" is less orderly than "crystalline," and the areas without atomic order are more likely to become hydrogen diffusion pathways. Also, a-In ２ O ３ Compared to a-IGZO, hydrogen diffusion in oxide semiconductors is suppressed. The reason for this is that a-IGZO has a-In ２ O ３ In comparison, the large variation in the size of the constituent metal elements makes it easier for hydrogen diffusion pathways to form in the amorphous state. Also, zinc oxide reacts more readily with hydrogen than indium oxide, which may be another reason for its easier incorporation of hydrogen. From these results, it is thought that if the oxide semiconductor is a single-crystal oxide semiconductor or polycrystalline oxide semiconductor with a bix-byte structure and mainly composed of indium oxide, hydrogen diffusion into the oxide semiconductor as a channel layer is suppressed, thereby preventing variations in transistor characteristics.

[0113] Although several embodiments and / or examples of the present invention have been described in detail above, those skilled in the art will find it easy to make many modifications to these exemplary embodiments and / or examples without substantially departing from the novel teachings and effects of the present invention. Therefore, many of these modifications fall within the scope of the present invention. All references to the documents cited in this specification are incorporated herein by reference.

[0114] 10: Transistor 11: First electrode 12: Second electrode 13: Third electrode 16: Second insulating film 14, 14a: First insulating film 14b: Third insulating film 15, 15': Oxide semiconductor 19: Insulating film 50: Semiconductor memory device 51: Capacitor 52: Memory cell WL: Word line BL: Bit line

Claims

1. A transistor comprising: a first electrode and a second electrode; an oxide semiconductor connecting the first electrode and the second electrode; and a third electrode adjacent to the oxide semiconductor without contact with the oxide semiconductor, wherein the first electrode and the second electrode are stacked with at least a first insulating film in between, and the oxide semiconductor is a single-crystal oxide semiconductor or polycrystalline oxide semiconductor having a bixbyte structure and mainly composed of indium oxide.

2. The transistor according to claim 1, wherein the oxide semiconductor penetrates at least the first insulating film to connect the first electrode and the second electrode.

3. The transistor according to claim 1 or 2, further comprising a second insulating film provided between the third electrode and the oxide semiconductor.

4. The transistor according to any one of claims 1 to 3, wherein the first electrode and the third electrode are stacked with respect to the first insulating film, the third electrode and the second electrode are stacked with respect to the third insulating film, the oxide semiconductor is provided in a columnar shape penetrating the first insulating film, the third electrode, and the third insulating film, and further comprises a second insulating film provided between the third electrode and the oxide semiconductor, the second insulating film being provided so as to surround at least a portion of the columnar oxide semiconductor.

5. The transistor according to any one of claims 1 to 3, wherein the first electrode and the second electrode are stacked with respect to the first insulating film, the oxide semiconductor has a cylindrical portion provided through the first insulating film, and further comprises a second insulating film provided between the third electrode and the oxide semiconductor, the second insulating film having a cylindrical portion provided on the inner wall of the cylindrical portion of the oxide semiconductor, and the third electrode having a portion provided inside the cylindrical portion of the second insulating film.

6. The transistor according to any one of claims 1 to 5, wherein the channel length of the oxide semiconductor is 1 to 1000 nm.

7. The transistor according to any one of claims 1 to 6, wherein the oxide semiconductor further comprises Ga or Al.

8. The transistor according to any one of claims 1 to 6, wherein the oxide semiconductor further comprises Ga.

9. The transistor according to any one of claims 1 to 6, wherein the oxide semiconductor further comprises Ga and Al.

10. The transistor according to any one of claims 1 to 9, wherein the atomic ratio of Ga to all metal elements contained in the oxide semiconductor ([Ga] / ([Ga] + [all metal elements other than Ga]) × 100) is 0.5 to 25 at%.

11. The transistor according to any one of claims 1 to 10, wherein the atomic ratio of Ga to all metal elements contained in the oxide semiconductor ([Ga] / ([Ga] + [all metal elements other than Ga]) × 100) is 3.0 to 10 at%.

12. The transistor according to any one of claims 1 to 11, wherein the number of grain boundaries in the oxide semiconductor is 0 to 5.

13. The transistor according to any one of claims 1 to 12, wherein the number of grain boundaries in the oxide semiconductor is zero.

14. The transistor according to any one of claims 1 to 12, wherein the number of grain boundaries in the oxide semiconductor is 1 to 5.

15. The transistor according to any one of claims 1 to 14, wherein the ratio of indium atoms to all metal atoms contained in the oxide semiconductor is 80 atomic percent or more.

16. The transistor according to any one of claims 1 to 15, wherein the indium oxide content in the oxide semiconductor is 55% by mass or more.

17. The transistor according to any one of claims 1 to 16, wherein at least one of the first electrode and the second electrode is at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), aluminum (Al), silicon (Si), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), germanium (Ge), molybdenum (Mo), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), tantalum (Ta), iridium (Ir), platinum (Pt), tungsten (W), titanium (Ti), titanium nitride (TiN), aluminum nitride (AlN), manganese nitride (MnN), molybdenum nitride (MoN), and nickel nitride (Ni3N).

18. The transistor according to any one of claims 1 to 17, wherein the oxide semiconductor is a crystalline oxide semiconductor formed by atomic layer deposition.

19. A semiconductor device comprising a transistor according to any one of claims 1 to 18.

20. The semiconductor device according to claim 19, comprising four or more transistors, wherein the coefficient of variation of the number of crystal grain boundaries in the oxide semiconductor contained in each of the four adjacent transistors is 0.0 or more and 1.0 or less.

21. A semiconductor device according to claim 19 or 20, which is a semiconductor memory device.

22. A transistor comprising: a first electrode and a second electrode; an oxide semiconductor connecting the first electrode and the second electrode; and a third electrode adjacent to the oxide semiconductor without contact with the oxide semiconductor, wherein the first electrode and the second electrode are stacked with at least a first insulating film in between; the oxide semiconductor is a single-crystal oxide semiconductor or polycrystalline oxide semiconductor having a bix-byte structure and mainly composed of indium oxide; the channel length of the oxide semiconductor is 1 to 1000 nm; the oxide semiconductor contains Ga; the atomic ratio of Ga to all metal elements contained in the oxide semiconductor ([Ga] / ([Ga] + [all metal elements other than Ga]) × 100) is 0.5 to 20 at%; and the number of grain boundaries in the oxide semiconductor is 0 to 5.

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