Transmission device and reset method for input interface

Abstract

A transmission device (100) comprises: a plurality of input interface units (3); and a control circuit (1) that controls each input interface unit (3). Each input interface unit (3) comprises an FPGA (34) that processes main signals input from a plurality of ports (p), a CPU (31) that controls the FPGA (34), and a reset circuit (32) that resets the input interface unit (3). The control circuit (1) comprises a monitoring unit (11) that monitors another error such as a multibit error which occurs in the CPU (31); and a reset unit (12) that transmits a reset command to the reset circuit (32) when the occurrence of the other error has been detected in the monitoring unit (11). The reset circuit (32) resets the input interface unit (3) when the reset command has been transmitted.

Description

Reset Method for Transmission Device and Input Interface

[0001] The present disclosure relates to a transmission device and a method for resetting a redundant input interface mounted on the transmission device.

[0002] A transmission device used in a network system includes an input interface (hereinafter abbreviated as "input IF unit") that inputs a main signal output from a plurality of hosts. To ensure stable operation, the transmission device has made the input IF unit redundant.

[0003] For example, two input IF units each having a plurality of ports are installed. The ports of one input IF unit are set as active (ACT), and the ports of the other input IF unit are set as standby (SBY) to conduct the main signal output from the host. By having such a redundant configuration, even if the CPU of one input IF unit stacks due to a soft error, communication can be prevented from being interrupted by switching the ports of the other input IF unit to ACT.

[0004] Japanese Patent Application Laid-Open No. 2015-165609

[0005] Operation of the Alarm System and Switching System of the "JT-G783" SDH Multiplexing Device, [Searched on January 16, 2025], Internet <URL: https: / / www.ttc.or.jp / application / files / 2515 / 5425 / 3967 / JT-G783v3.pdf> NTT Technical Journal 2015.4, [Searched on January 16, 2025], Internet <URL: https: / / journal.ntt.co.jp / backnumber2 / 1504 / files / jn201504067.pdf>

[0006] In conventional transmission devices, if a single-bit soft error occurs in the CPU of one of the two input IF sections, it can autonomously recover and continue communication. However, if a multi-bit error occurs in the CPU of the other input IF section, the CPU will stack, and the keep-alive function will be disabled, making it impossible to autonomously recover that input IF section. Therefore, manual repair work on the input IF section is required by the operator.

[0007] Furthermore, Non-Patent Document 1 discloses the operation of the alarm and switching systems of an SDH multiplexer. Non-Patent Document 2 discloses a cross-connect device that applies packet transport technology. Patent Document 1 discloses a communication system with a redundant configuration.

[0008] However, Non-Patent Document 1 has a problem in that the switching cannot be completed unless the signals within the frame are updated, regardless of the protocol, commands, or operation for automatic switching (APS) and backup switching (1+1). In Non-Patent Document 2, although the input IF unit is controlled by the control monitoring unit, if the input IF unit gets stuck, the path cannot be switched properly. Furthermore, no measures are disclosed for when the input IF unit does not recover through autonomous recovery in the event of a soft error. In Patent Document 1, there is a problem in that if a device controlled by the management device is in a stuck state, it is not possible to switch to a redundant path.

[0009] This disclosure has been made in view of the above circumstances, and its purpose is to provide a transmission device and an input interface reset method that can reset the input IF unit even when an error other than a single-bit error, such as a multi-bit error, occurs in the control circuit mounted on the input IF unit.

[0010] A transmission device according to one aspect of the present disclosure is a transmission device comprising a plurality of input interfaces and a control device for controlling each input interface, wherein each input interface comprises a signal processing circuit for processing main signals input from a plurality of ports, a control circuit for controlling the signal processing circuit, and a reset circuit for resetting the input interface, the control device comprising a monitoring unit for monitoring errors other than 1-bit errors occurring in the control circuit, and a reset unit that transmits a reset command to the reset circuit when the monitoring unit detects the occurrence of the other error, and the reset circuit resets the input interface when the reset command is transmitted.

[0011] A method for resetting an input interface in one aspect of the present disclosure is a method for resetting a plurality of input interfaces mounted on a transmission device, wherein the input interface comprises a control circuit for controlling a signal processing circuit and a reset circuit for resetting the input interface, and a monitoring unit monitors whether an error other than a 1-bit error has occurred in the control circuit, and when such an error is detected, the reset unit transmits a reset command to the reset circuit, and the reset circuit receives the reset command and resets the input interface.

[0012] According to this disclosure, it becomes possible to reset the input interface even if an error other than a 1-bit error occurs in the control circuit installed in the input interface.

[0013] Figure 1 is a block diagram showing the configuration of the transmission device according to the embodiment. Figure 2 is an explanatory diagram showing the connection status between each port of the first and second input IF units and each host, where (a) shows the state before a soft error occurs and (b) shows the state after a soft error occurs. Figure 3 is an explanatory diagram showing the connection status between each port of the first and second input IF units and each host, where (a) shows the state before a soft error occurs, (b) shows the state when monitoring by the monitoring unit is turned off, and (c) shows the state when the first input IF unit is turned off. Figure 4A is the first subdivision of a flowchart showing the procedure for resetting or turning off an input IF unit where a soft error has occurred using the transmission device according to the embodiment. Figure 4B is the second subdivision of a flowchart showing the procedure for resetting or turning off an input IF unit where a soft error has occurred using the transmission device according to the embodiment. Figure 5 is a block diagram showing the hardware configuration of this embodiment.

[0014] The embodiments will now be described with reference to the drawings. Figure 1 is a block diagram showing the configuration of the transmission device 100 according to the embodiment. As shown in Figure 1, the transmission device 100 comprises a control device 1, a first input IF unit 3A (input interface), a second input IF unit 3B (input interface), and a switch unit 5 (indicated as "SW unit" in the figure). That is, the transmission device 100 comprises a plurality of input IF units and a control device 1 that controls each input IF unit. The first input IF unit 3A and the second input IF unit 3B are connected to a plurality of hosts 2 (2-1 to 2-4) (indicated as NE; Network Element in the figure).

[0015] The control device 1 includes a monitoring unit 11, a reset unit 12, and a cutoff unit 13.

[0016] The first input IF section 3A includes a CPU 31A (control circuit), a reset circuit 32A, a cutoff circuit 33A, and an FPGA (Field Programmable Gate Array) 34A. Similarly, the second input IF section 3B includes a CPU 31B (control circuit), a reset circuit 32B, a cutoff circuit 33B, and an FPGA 34B. In other words, the input IF section is made redundant by providing the first input IF section 3A and the second input IF section 3B, which have the same configuration. FPGAs 34A and 34B are examples of signal processing circuits that process main signals input from multiple ports. CPUs 31A and 31B are examples of control circuits that control the FPGAs (signal processing circuits).

[0017] Hereafter, when the first input IF section and the second input IF section are specifically referred to, they will be indicated with the suffixes "first input IF section 3A" and "second input IF section 3B," respectively. When they are not specifically referred to or are used collectively, they will be indicated as "input IF section 3" without the suffix. Similarly, when one of the two CPUs is specifically referred to, it will be indicated with the suffixes "CPU 31A" and "CPU 31B." When they are not specifically referred to or are used collectively, they will be indicated as "CPU 31" without the suffix. The same applies to the reset circuit, the cutoff circuit, and other symbols.

[0018] The first input IF unit 3A has four ports p11, p12, p13, and p14. Similarly, the second input IF unit 3B also has four ports p21, p22, p23, and p24. Each input IF unit 3A and 3B can hold multiple ports p and operate independently. Ports p11 and p21 are connected to host 2-1, with one being ACT (active) and the other SBY (standby). Ports p12 and p22 are connected to host 2-2, with one being ACT and the other SBY. Ports p13 and p23 are connected to host 2-3, with one being ACT and the other SBY. Ports p14 and p24 are connected to host 2-4, with one being ACT and the other SBY.

[0019] In Figure 1, ports p designated as ACT are shown with white circles, and ports p designated as SBY are shown with black circles. For example, port p11 is designated as ACT with host 2-1, and port p21 is designated as SBY with host 2-1.

[0020] The monitoring unit 11 transmits a monitoring signal to check whether or not an abnormality has occurred in the CPUs 31A and 31B of each input IF unit 3A and 3B. The monitoring unit 11 receives abnormality detection signals transmitted from each CPU 31A and 31B. When an abnormality detection signal is received, the monitoring unit 11 determines whether the abnormality occurring in the input IF unit 3 is a hardware failure, a 1-bit error (1-bit soft error), or some other type of error. If the monitoring unit 11 determines that the abnormality in the input IF unit 3 is due to a hardware failure, it transmits a switching command to the input IF unit 3 to switch the ACT / SBY of port p.

[0021] The monitoring unit 11, when an abnormality occurs in the input IF unit 3 and the abnormality is not a hardware error, determines whether the error is a single-bit error or another type of error. "Other types of errors" refers to errors of unknown cause, including multi-bit errors (multi-bit soft errors). If a single-bit error occurs in the input IF unit 3, the monitoring unit 11 sends an autonomous reset command to the input IF unit 3. In other words, the monitoring unit 11 monitors single-bit errors and multi-bit errors occurring in the CPU 31 (control circuit).

[0022] The reset unit 12 transmits a reset command to the reset circuit 32 if an abnormality occurs in the input IF unit 3 and this abnormality is another type of error. For example, if an abnormality occurs in the first input IF unit 3A and this abnormality is another type of error such as a multi-bit error in the CPU 31A, the reset unit 12 transmits a reset command to the reset circuit 32A. In other words, the reset unit 12 transmits a reset command to the reset circuit 32 when the monitoring unit 11 detects the occurrence of a multi-bit error.

[0023] The cutoff unit 13 transmits a cutoff command to the input IF unit 3 if an abnormality occurs in the input IF unit 3, this abnormality is another type of error, and the reset circuit 32 attempts to reset the unit up to a predetermined upper limit number of times, but the reset is not completed. For example, if an abnormality occurs in the first input IF unit 3A, this abnormality is a multi-bit error (another type of error) in the CPU 31A, and the reset circuit 32 attempts to reset the first input IF unit 3A up to a predetermined upper limit number of times, but the reset is not completed, the cutoff unit 13 transmits a cutoff command to the cutoff circuit 33A of the first input IF unit 3A. In other words, the cutoff unit 13 transmits a cutoff command to the cutoff circuit 33 if the reset of the input IF unit 3 is not completed after one or more reset attempts by the reset circuit 32.

[0024] The CPU 31 mounted on the input IF unit 3 manages the operation of the FPGA 34. When a monitoring signal is transmitted from the monitoring unit 11, the CPU 31 transmits abnormal detection signals to the monitoring unit 11 indicating hardware failures (HW failures) occurring in the input IF unit 3, soft errors occurring in the CPU 31, and other errors. As a countermeasure against soft errors, the CPU 31 has a function to reset the input IF unit 3 and autonomously recover the input IF unit 3 when a 1-bit error occurs. The autonomous recovery function includes a function to update the ACT / SBY of each port p.

[0025] The CPU 31 autonomously resets the input IF unit 3 when an autonomous reset command is transmitted from the monitoring unit 11. "Autonomous reset" refers to the CPU 31 resetting the input IF unit 3 when a soft error occurs in the CPU 31. Specifically, the CPU 31 executes a process to update the ACT / SBY status of each port p. For example, as shown in Figures 1 and 2(a), when ports p11 and p14 are set to ACT, and the CPU 31A receives an autonomous reset command, it executes a process to switch ports p11 and p14 from ACT to SBY, as shown in Figure 2(b). In other words, when the input IF unit 3 is reset by the reset circuit 32, the CPU 31 (control circuit) performs a process to switch all ports of the input IF unit 3 to standby (SBY). The input IF unit 3 may also be configured to include a forced reset function by manual operation by the operator and a function to block external instructions.

[0026] The reset circuit 32 shown in Figure 1 receives a reset command from the reset unit 12 and resets the input IF unit 3. For example, when the reset circuit 32A of the first input IF unit 3A receives a reset command, it attempts to reset the first input IF unit 3A. Once the reset is complete, the reset circuit 32A sends a reset completion signal to the reset unit 12.

[0027] The reset circuit 32 attempts to reset the input IF unit 3, and if the reset is not completed, it repeats the reset attempt multiple times. If the reset is not completed even after the number of reset attempts reaches a predetermined upper limit (for example, 6 times), the reset circuit 32 sends a reset incomplete signal to the reset unit 12.

[0028] The blocking circuit 33 blocks the input IF unit 3 when a blocking command is transmitted from the blocking unit 13. For example, when a blocking command for the first input IF unit 3A is transmitted from the blocking unit 13, this blocking command is input to the blocking circuit 33A. The blocking circuit 33A blocks the first input IF unit 3A. "Blocking" refers to blocking the function of the input IF unit 3. When the first input IF unit 3A is blocked, each port p11 to p14 is set to SBY, and each port p21 to p24 of the second input IF unit 3B is switched to ACT.

[0029] The FPGA34 processes the main signals output from each host 2 according to the desired program. "Main signals" refer to the signals that are the main focus of data communication.

[0030] The switch unit 5 is equipped with two ports r1 and r2, and receives signals output from port q1 on the output side of the first input IF unit 3A and port q2 on the output side of the second input IF unit 3B, and performs switching processing.

[0031] Next, the procedure for resetting the input IF unit 3 using the transmission device 100 according to this embodiment will be explained with reference to the flowcharts shown in Figures 4A and 4B.

[0032] First, in step S11 of Figure 4A, the monitoring unit 11 transmits an abnormality monitoring signal to each input IF unit 3.

[0033] In step S12, the monitoring unit 11 determines whether or not an abnormality has occurred in the first input IF unit 3A and the second input IF unit 3B. Specifically, when the monitoring unit 11 receives the aforementioned abnormality detection signal, it determines that an abnormality has occurred. If an abnormality has occurred (S12; YES), the process proceeds to step S13; otherwise (S12; NO), the process returns to step S11.

[0034] In step S13, the monitoring unit 11 determines whether the abnormality that occurred in each input IF unit 3A, 3B is a hardware failure. If it is a hardware failure (S13; YES), the process proceeds to step S14; otherwise, it proceeds to step S17.

[0035] In step S14, the CPU 31 switches port p, which is set to ACT with respect to the host 2, to SBY. For example, if a hardware failure occurs in the first input IF unit 3A, the CPU 31A mounted on the first input IF unit 3A sets ports p11 to p14 to SBY. In the example shown in Figure 1, ports p11 and p14, which are set to ACT, are switched to SBY.

[0036] In step S15, the CPU 31 stops the operation of the input IF unit 3 where a hardware failure has occurred. For example, if a hardware failure occurs in the first input IF unit 3A, the CPU 31A stops the operation of the first input IF unit 3A. In other words, only the second input IF unit 3B is in operation.

[0037] In step S16, the monitoring unit 11 notifies the operator that the input IF unit 3 that has failed needs to be replaced. Upon receiving this notification, the operator recognizes that a hardware failure has occurred in the first input IF unit 3A and performs the replacement work. This enables the rapid replacement of the first input IF unit 3A that has experienced a hardware failure. After this, the process ends.

[0038] In step S17, the monitoring unit 11 determines whether the abnormality that occurred in the input IF unit 3 is a 1-bit error or not. If it is a 1-bit error (S17; YES), the process proceeds to step S18. If it is a multi-bit error or other type of error (hereinafter referred to as "other error") (S17; NO), the process proceeds to step S20.

[0039] In step S18, the CPU 31 autonomously resets the input IF unit 3. For example, if a 1-bit error occurs in the first input IF unit 3A, the monitoring unit 11 sends an autonomous reset command to the first input IF unit 3A, and the CPU 31A receives this autonomous reset command and autonomously resets the first input IF unit 3A.

[0040] In step S19, the CPU 31 switches the input IF unit 3. For example, in the state shown in Figure 2(a), if a 1-bit error occurs in the CPU 31A of the first input IF unit 3A, the CPU 31A switches ports p11 to p14 to SBY as shown in Figure 2(b). Also, the CPU 31B of the second input IF unit 3B switches ports p21 to p24 to ACT. Therefore, if a 1-bit error occurs in the CPU 31A, the first input IF unit 3A is autonomously reset, and the ports p that are in conductivity with each host 2 are switched to ports p21 to p24 of the second input IF unit 3B, allowing the processing of the main signal to continue and the operation of the transmission device 100 to continue. After that, this process is terminated.

[0041] In step S20, the monitoring unit 11 counts the number of errors other than 1-bit errors that occur in the CPU 31 and determines whether this count exceeds a predetermined monitoring anomaly threshold. If the number of other errors exceeds the monitoring anomaly threshold (S20; YES), the process proceeds to step S21 in Figure 4B; otherwise (S20; NO), the process returns to step S11.

[0042] In step S21, the reset unit 12 sends a reset command to the reset circuit 32 of the input IF unit 3 where the abnormality occurred. For example, if a multi-bit error (another error) is detected in the CPU 31A of the first input IF unit 3A, and this multi-bit error exceeds the monitoring abnormality threshold, a reset command is sent to the reset circuit 32A. The reset circuit 32A attempts to reset the input IF unit 3A.

[0043] In step S22, the reset unit 12 determines whether the reset of the first input IF unit 3A is complete by attempting to reset the reset circuit 32A. The reset unit 12 receives the reset completion signal or reset incomplete signal mentioned above and determines whether the reset is complete. If the reset is complete (S22; YES), the process proceeds to step S23; otherwise (S22; NO), the process proceeds to step S24.

[0044] In step S23, the CPU 31 switches the input IF unit 3. Specifically, the CPU 31A switches each port p11 to p14 of the first input IF unit 3A to SBY. The CPU 31B switches each port p21 to p24 of the second input IF unit 3B to ACT. For this reason, when another error (for example, a multi-bit error) occurs in the CPU 31A of the first input IF unit 3A and the reset of the first input IF unit 3A is completed by the reset circuit 32A, each port p21 to p24 of the second input IF unit 3B can be switched to ACT to continue the operation as the transmission device 100.

[0045] For example, as shown in FIG. 2(a), when ports p11 and p14 of each port p of the first input IF unit 3A are set to ACT and ports p12 and p13 are set to SBY, if a multi-bit error occurs in the CPU 31A and the reset by the reset circuit 32A is completed, as shown in FIG. 2(b), all ports p11 to p14 are switched to SBY. Further, by switching all ports p21 to p24 of the second input IF unit 3B to ACT, the operation as the transmission device 100 can be continued. That is, it is possible to cope with the stack of the CPU 31 caused by the occurrence of other errors such as multi-bit errors. Then, this process ends.

[0046] In step S24, the reset unit 12 counts the number of resets by the reset circuit 32. For example, a threshold number of resets (for example, 6 times) that is the upper limit of the number of resets is set, and when the number of resets reaches the threshold number of resets but the reset is not completed, it is determined that the threshold number of resets has been exceeded. When the threshold number of resets is exceeded (S24; YES), the process proceeds to step S25, and otherwise (S24; NO), the process returns to step S21.

[0047] In step S25, the blocking unit 13 transmits a blocking command to the input IF unit 3 in which another error has occurred. The blocking circuit 33 of the input IF unit 3 attempts to block the input IF unit 3. For example, when a multi-bit error occurs in the CPU 31A of the first input IF unit 3A and the number of reset times exceeds the threshold number of times, the blocking circuit 33A of the first input IF unit 3A attempts to block the first input IF unit 3A.

[0048] In step S26, the blocking unit 13 determines whether or not the blocking of the input IF unit 3 by the blocking circuit 33 has been completed. If the blocking has been completed (S26; YES), the process proceeds to step S27, and if not (S26; NO), the process proceeds to step S29.

[0049] In step S27, the blocking unit 13 notifies the operator that the input IF unit 3 in which an abnormality has occurred has been blocked. FIG. 3 is an explanatory diagram showing the ACT / SBY states of the port p in the first and second input IF units 3A and 3B. FIG. 3(a) shows the state before a multi-bit error occurs, FIG. 3(b) shows the state after a multi-bit error occurs, and FIG. 3(c) shows the state when the first input IF unit 3A is blocked.

[0050] As shown in FIG. 3(a), when a multi-bit error occurs in the first input IF unit 3A, as shown in FIG. 3(b), the monitoring of the CPU 31A by the monitoring unit 11 is blocked. For this reason, the switching of each port p11 to p14 by the CPU 31A becomes impossible , and the state where the ports p11 and p14 are ACT and the ports p12 and p13 are SBY is maintained.

[0051] That is, although it is desirable to switch each port p21 to p24 of the second input IF unit 3B to ACT, since the signal transmitted from the host 2 (for example, APS (Automatic Protection Switch) switching) also communicates with the first input IF unit 3A, it is necessary to switch to SBY between each port p of the first input IF unit 3A. However, since this switching is not completed, the host 2 cannot select which input IF unit 3 to communicate with. For this reason, the main signal from the host 2 becomes non-conductive.

[0052] In this embodiment, by blocking the first input IF section 3A with the blocking circuit 33A, the first input IF section 3A becomes blocked as shown in Figure 3(c), and all ports p11 to p14 become SBY. Consequently, the CPU 31B of the second input IF section 3B switches all ports p21 to p24 of the second input IF section 3B to ACT, enabling the main signal to be transmitted to the host 2.

[0053] In step S28, the interruption unit 13 notifies the operator to restore the interrupted input IF unit 3. That is, for example, if the first input IF unit 3A is interrupted, as shown in Figure 3(c), the first input IF unit 3A is blocked and requires restoration by the operator, so the unit notifies the operator to restore the interrupted input. After that, this process is terminated.

[0054] In step S29, the shut-off unit 13 notifies the operator that it has failed to shut off the input IF unit 3 where an abnormality occurred.

[0055] In step S30, the shutdown unit 13 notifies the operator to restore service to the shutdown input IF unit 3. After that, the process ends.

[0056] As described above, the transmission device 100 according to this embodiment is a transmission device 100 comprising a plurality of input IF units 3 (input interfaces) and a control device 1 that controls each input IF unit 3, wherein each input IF unit 3 comprises an FPGA 34 (signal processing circuit) that processes main signals input from a plurality of ports p, a CPU 31 (control circuit) that controls the FPGA 34, and a reset circuit 32 that resets the input IF unit 3, wherein the control device 1 comprises a monitoring unit 11 that monitors for errors other than 1-bit errors that occur in the CPU 31, and a reset unit 12 that transmits a reset command to the reset circuit 32 when the monitoring unit 11 detects the occurrence of another error, and the reset circuit 32 resets the input IF unit 3 when a reset command is transmitted.

[0057] In the transmission device 100 according to this embodiment, each input IF unit 3 is equipped with a reset circuit 32 that resets the input IF unit 3 independently of the CPU 31. Therefore, even if an error other than a single-bit error, such as a multi-bit error, occurs in one of the input IF units 3, resetting this input IF unit 3 allows switching to the other input IF unit 3, enabling the main signal to be transmitted between each host 2.

[0058] In the transmission device 100 according to this embodiment, each input IF unit 3 is equipped with a blocking circuit 33 that blocks the input IF unit 3. Therefore, even if a multi-bit error occurs in one input IF unit 3 and the reset is not completed, by blocking and closing this input IF unit 3, only the other input IF unit 3 can be operated, making it possible to conduct the main signal to each host 2. For this reason, even if an error other than a single-bit error, such as a multi-bit error, occurs in the CPU 31, the operation of the transmission device 100 can be continued without requiring human intervention such as recovery work by the operator.

[0059] Therefore, even if the input IF unit 3 becomes stuck due to a multi-bit error occurring in the CPU 31, the control device 1 can recover or block the input IF unit 3, thereby reducing the time during which communication with the host 2 is interrupted. This reduces the impact on the conduction of the main signal. Furthermore, it reduces the effort required for recovery work by operators.

[0060] Furthermore, since this can be addressed by equipping each input IF section 3 with a reset circuit 32 and a cutoff circuit 33, hardware modifications can be kept to a minimum.

[0061] As shown in Figure 5, the control device 1 of this embodiment described above can be a general-purpose computer system comprising, for example, a CPU (Central Processing Unit, processor) 901, memory 902, storage 903 (HDD: Hard Disk Drive, SSD: Solid State Drive), communication device 904, input device 905, and output device 906. The memory 902 and storage 903 are storage devices. In this computer system, each function of the control device 1 is realized when the CPU 901 executes a predetermined program loaded onto the memory 902.

[0062] The control device 1 may be implemented on a single computer, or on multiple computers. Furthermore, the control device 1 may be a virtual machine implemented on a computer.

[0063] The program for the control device 1 can be stored on a computer-readable recording medium such as an HDD, SSD, USB (Universal Serial Bus) memory, CD (Compact Disc), or DVD (Digital Versatile Disc), or it can be distributed via a network. A computer-readable recording medium is, for example, a non-transitory recording medium.

[0064] This disclosure is not limited to the embodiments described above, and numerous modifications are possible within the scope of its essence.

[0065] 1 Control device 2 (2-1 to 2-4) Host 3A First input IF unit (input interface) 3B Second input IF unit (input interface) 5 Switch unit 11 Monitoring unit 12 Reset unit 13 Cutoff unit 31 (31A, 31B) CPU (control circuit) 32 (32A, 32B) Reset circuit 33 (33A, 33B) Cutoff circuit 100 Transmission device

Claims

1. A transmission device comprising a plurality of input interfaces and a control device for controlling each input interface, wherein each input interface comprises a signal processing circuit for processing main signals input from a plurality of ports, a control circuit for controlling the signal processing circuit, and a reset circuit for resetting the input interface, the control device comprising a monitoring unit for monitoring errors other than 1-bit errors occurring in the control circuit, and a reset unit for transmitting a reset command to the reset circuit when the monitoring unit detects the occurrence of the other error, and the reset circuit for resetting the input interface when the reset command is transmitted.

2. The transmission device according to claim 1, wherein each of the input interfaces further comprises a blocking circuit for blocking the input interface, and the control device further comprises a blocking unit that transmits a blocking command to the blocking circuit if the reset of the input interface is not completed by one or more reset attempts by the reset circuit.

3. The transmission device according to claim 1 or 2, wherein the control circuit of each input interface switches all ports of the input interface to standby when the input interface is reset by the reset circuit.

4. A method for resetting an input interface, wherein the input interface comprises a control circuit for controlling a signal processing circuit and a reset circuit for resetting the input interface, the monitoring unit monitors whether an error other than a 1-bit error has occurred in the control circuit, and when such an error is detected, the reset unit transmits a reset command to the reset circuit, and the reset circuit receives the reset command and resets the input interface.

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