Silicon carbide semiconductor device
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- HITACHI LTD
- Filing Date
- 2025-10-24
- Publication Date
- 2026-07-30
Smart Images
Figure JP2025037444_30072026_PF_FP_ABST
Abstract
Description
Silicon Carbide Semiconductor Device
[0001] The present invention relates to a silicon carbide semiconductor device.
[0002] A silicon carbide semiconductor device using silicon carbide (SiC) for a semiconductor substrate is known. For example, Patent Document 1 describes a semiconductor device for power in which a power MOSFET is formed on a silicon carbide substrate. Silicon carbide semiconductor devices have many excellent electrical characteristics compared to semiconductor devices using silicon substrates, which are the mainstream at present.
[0003] International Publication No. 2002 / 097888
[0004] However, manufacturing a silicon carbide semiconductor device requires sophisticated and advanced manufacturing techniques, and at present, the yield tends to be poor. That is, there is room for further improving the practicality of silicon carbide semiconductor devices.
[0005] An object of the present invention is to further improve the practicality of a silicon carbide semiconductor device.
[0006] According to one embodiment, a silicon carbide semiconductor device includes a silicon carbide substrate, a plurality of unit cells, and N gate pads. The plurality of unit cells are formed on the silicon carbide substrate and each has a MOSFET structure. The N gate pads are formed on the silicon carbide substrate, each corresponding to one of N partial cell regions obtained by dividing a region including the plurality of unit cells, and are connected to the gates of the MOSFETs of the unit cells within the partial cell regions. The termination structures of the MOSFETs of the unit cells within the N partial cell regions are common.
[0007] According to one embodiment, the practicality of a silicon carbide semiconductor device can be further improved.
[0008] This is a diagram showing the configuration of a semiconductor device according to the first embodiment. This is a plan view showing a chip according to the first embodiment. This is a plan view showing a chip according to the first embodiment. This is a cross-sectional view showing the cell region and termination region in the first embodiment. This is an enlarged cross-sectional view showing the area around the MOSFET in the cell region in the first embodiment. This is a diagram showing an example of the relationship between device characteristics and the MOSFET control method in the second embodiment. This is a tree diagram showing some examples of the control method for the MOSFET of a unit cell in the second embodiment. This is a diagram showing the structure of a general shield trench gate power MOSFET. This is a diagram showing an example of the structure of a chip of a semiconductor device according to the second embodiment. This is a diagram showing an example of a gate drive circuit configured with a totem pole circuit. This is a diagram showing an example of a chip and peripheral circuits mounted on a planar substrate. This is a diagram showing a first example of a semiconductor device in which an IC circuit is stacked on a chip according to the third embodiment. This is a diagram showing a second example of a semiconductor device in which an IC circuit is stacked on a chip according to the third embodiment. This is a side view showing an example of the structure of a semiconductor device in which a chip and an IC circuit are stacked according to the third embodiment.
[0009] (Background of the inventors' research) The embodiments of the present invention will be described below, but before that, the background of the inventors' research will be explained.
[0010] Semiconductor power devices require high voltage resistance, low on-resistance, and low switching losses. However, silicon (Si) power devices, which are currently the mainstream, are approaching their theoretical performance limits. On the other hand, silicon carbide (SiC) has a dielectric breakdown field strength that is about an order of magnitude greater than that of Si. Therefore, compared to Si devices, SiC devices can theoretically reduce the resistance of the device by more than three orders of magnitude by making the drift layer that maintains the voltage resistance about 1 / 10th thinner and increasing the impurity concentration by about 100 times. In addition, SiC has a band gap that is about three times larger than that of Si. For these reasons, SiC devices can operate at high temperatures and are expected to have performance that surpasses that of Si devices, and the development of SiC power devices is progressing.
[0011] Unlike low-power Si devices used in integrated circuits (ICs), SiC power devices require operation at high temperatures, high voltages, or high currents. Furthermore, their recent application in electric vehicles and railways necessitates high reliability, such as sufficient short-circuit withstand capability, voltage resistance, and gate reliability. Moreover, the increasing demand for energy conservation has led to a growing need for improved SiC device performance, such as reduced on-resistance.
[0012] However, generally speaking, there is a trade-off between performance and reliability, such as on-resistance and short-circuit withstand capability / voltage withstand capability. In the case of a power device with a JFET structure, narrowing the JFET width increases short-circuit withstand capability and voltage withstand capability, but also increases resistance. In this case, JFET design, and by extension the dimensional control of JFET design, becomes extremely important. Furthermore, while SiC has a wider bandgap and higher dielectric breakdown strength compared to Si, the electric field applied to the insulating film is also larger, so techniques to mitigate the electric field of the insulating film are extremely important.
[0013] A strong electric field in the insulating film can cause leakage current in the gate insulating film, leading to device malfunctions such as reduced gate insulating film life and dielectric breakdown. Therefore, research is being conducted on technologies to improve the breakdown voltage of the gate insulating film through improvements in the film deposition process, and on design technologies to mitigate the electric field acting on the gate insulating film. In the case of devices with trenches, there is a trade-off relationship between mitigating the gate electric field and performance, making precise manufacturing technology in the trenching process essential.
[0014] Thus, extremely stringent design is required for SiC power devices. On the other hand, power devices generally require high-energy impurity implantation, which necessitates forming a thick resist for the mask, making dimensional control during the photoprocessing process very strict for the design. Furthermore, if the device has trenches, etching of the SiC is necessary, but since SiC is harder than Si, dimensional control during etching also becomes very strict.
[0015] Furthermore, power device chips have termination regions to mitigate the electric field at the corners of the chip. Common termination structures for these regions include JTE and FFR structures, but the voltage that needs to be mitigated increases with higher voltage ratings. As a result, the area of the termination region within the chip becomes larger compared to the main cell area.
[0016] Recent power device chips require small size and high output. Therefore, it is desirable to increase the chip size and the main cell area.
[0017] However, as mentioned earlier, increasing the chip size reduces the yield due to process variations and crystal defects within the wafer. SiC, in particular, has many crystal defects, which affects its reliability.
[0018] The inventors, after diligent study to address the above-mentioned problems, have devised the proposed technology. This proposed technology divides the cell region of a large-area chip into multiple sub-cell regions, enabling separate control for each sub-cell region. This suppresses the effects of manufacturing variations in unit cells within the cell region, achieving high reliability and performance even in SiC manufacturing processes where mass production technology is not yet mature.
[0019] Furthermore, while currently strict process control necessitates developing design and manufacturing technologies for each application, unifying the design and changing the chip control method will enable application-specific applications. This will be an essential technology when SiC wafer costs decrease in the future.
[0020] Furthermore, in this proposed technology, the current, temperature, etc. of the unit cell are sensed on the chip mounting substrate, immediately adjacent to the chip, and the chip is water-cooled or oil-cooled. Control of each cell is performed by a control chip within the cell. This enables feedback control with low delay and achieves high reliability.
[0021] The embodiments will now be described with reference to the figures. In each embodiment, the same components or components having the same function will be denoted by the same reference numeral, and repeated descriptions will be omitted unless necessary.
[0022] (First Embodiment) The first embodiment will be described. The first embodiment focuses on a case where there is variation in the finished dimensions of multiple unit cells within the same chip, causing an imbalance in performance or characteristics. The technology for resolving or addressing this imbalance will be described.
[0023] <Overview of Semiconductor Device> Figure 1 is a diagram showing the configuration of a semiconductor device according to the first embodiment. In the following structural diagrams, the direction of the substrate surface of the chip constituting the semiconductor device 100 according to the first embodiment is defined as the XY plane direction, and the direction perpendicular to the XY plane is defined as the Z direction.
[0024] The semiconductor device 100 comprises a power device chip 1 and an IC circuit 9 including a gate driver 7. The chip 1 includes a cell region 3 formed on the upper surface of a SiC substrate 2 by arranging a large number of unit cells. Each unit cell has a MOSFET structure. The cell region 3 is divided into N sub-cell regions 3P. The chip 1 also has N gate pads 4 formed on it. Each gate pad 4 corresponds to one sub-cell region 3P and is connected to the gate of the MOSFET of each unit cell within one sub-cell region 3P. The termination structure of the MOSFET termination region 50 in multiple sub-cell regions 3P is common. With this configuration, even though it is a power device chip, it is possible to control the gate voltage of the unit cell MOSFET for each sub-cell region 3P within the same chip 1.
[0025] The semiconductor device 100 shown in Figure 1 is an example where the number of cell region divisions N = 4. That is, the semiconductor device 100 is an example in which four partial cell regions 3P are formed within a chip 1 using a SiC substrate 2 as the semiconductor substrate, and four gate pads 4 are provided. Note that although Figure 1 illustrates the case where N = 4, it is not limited to N ≥ 2, i.e., as long as N is an integer of 2 or more. Also, the size, shape, and arrangement method of the gate pads 4 are not limited to this. In particular, in chips for high-voltage applications, the termination region that mitigates the electric field at the end of the chip is often very large in relation to the active size. In this embodiment, it is possible to make the size of one chip relatively large and increase the ratio of active area.
[0026] Larger chip sizes tend to have greater dimensional variations within the same chip and a higher probability of containing defects, resulting in lower yield. This proposed technology allows for the isolation of defective areas from the control target, enabling control only of defect-free areas. As a result, chips that would otherwise be unusable due to some defects become usable, leading to improved chip yield.
[0027] Regarding the chip control method, for example, the choice of control method can be determined based on the device characteristics obtained from electrical characteristic evaluations performed in general product inspections. The control method is used in the IC circuit 9 that controls the chip 1. Details of the characteristic evaluation and IC circuit will be described later.
[0028] In the example shown in Figure 1, four control CMOS circuits 5 are formed within the same chip 1, and each gate pad 4 and control CMOS circuit 5 is connected by a wiring 6. The wiring 6 may be one or more conductive wires, conductive plates, conductive patterns, etc. The gate driver 7 controls the MOSFETs of each cell unit in each subcell region 3P by controlling the control CMOS circuits 5.
[0029] As a method for controlling the MOSFETs of the cell unit for each sub-cell region 3P, for example, the following method may be adopted: N commercially available CMOS circuits are mounted on the mounting board, and each mounted CMOS circuit is connected to the gate pad 4. Alternatively, N CMOS / MOS circuits are prepared in the gate driver 7, and each CMOS / MOS circuit is connected to the gate pad 4. Then, the IC circuit 9 controls the mounted or prepared CMOS or MOS circuits via the gate driver 7, thereby independently controlling the MOSFETs of the unit cell for each sub-cell region 3P.
[0030] Furthermore, chip 1, or semiconductor device 100, is an example of a silicon carbide semiconductor device in this application. Also, the control CMOS circuit 5, gate driver 7, or IC circuit 9 is an example of a control circuit in this application.
[0031] <Details of the chip structure> Here, the structure of the chip 1 according to the first embodiment will be described in detail using Figures 2 to 5.
[0032] Figures 2 and 3 are plan views showing a chip according to the first embodiment. Figure 4 is a cross-sectional view showing the cell region and termination region in the first embodiment. Figure 5 is an enlarged cross-sectional view of the area around the MOSFET in the cell region in the first embodiment.
[0033] As shown in Figure 2, the chip 1 comprises a cell region CA in which a plurality of unit cells are formed, and a terminal region TA surrounding the cell region CA in a plan view. In the first embodiment, the unit cells have a MOSFET structure.
[0034] As shown in Figure 2, the chip 1 is provided with multiple wirings. A source electrode SE is formed as wiring in the cell region CA. Multiple MOSFETs are formed below the source electrode SE. In the termination region TA, gate wirings GW1, GW2, GW3, GW4, source wiring SW, and guard ring wiring GR are formed as wirings, respectively.
[0035] The gate wiring GW surrounds the source electrode SE in a plan view. The source wiring SW is drawn out from the source electrode SE and is formed in a ring shape so as to surround the gate wiring GW in a plan view. The guard ring wiring GR is formed in a ring shape so as to surround the source wiring SW in a plan view.
[0036] Furthermore, as shown in Figure 4, the source electrode SE, gate wiring GW, source wiring SW, and guard ring wiring GR are covered with a protective film PIQ. An opening is provided in a part of the protective film PIQ. The protective film PIQ is a resin film, for example, a polyimide film.
[0037] Figures 2 and 3 show the resurf region RS formed in the semiconductor substrate SUB of the terminal region TA. The hatched area in Figure 3 is the resurf region RS. The location of the resurf region RS shown in Figure 3 coincides with the location of the resurf region RS shown by the dashed line in Figure 2.
[0038] Each resurf region RS is formed in a ring shape within the terminal region TA, surrounding the cell region CA in a plan view.
[0039] As shown in Figure 3, the cell region CA is composed of multiple divided sub-cell regions. In this example, the cell region CA is divided into four parts, consisting of sub-cell regions CA1, CA2, CA3, and CA4. The gate wirings GW1, GW2, GW3, and GW4 correspond to the sub-cell regions CA1, CA2, CA3, and CA4, respectively. That is, the gate of the MOSFET of the unit cell in sub-cell region CA1 is connected to gate wiring GW1. The gate of the MOSFET of the unit cell in sub-cell region CA2 is connected to gate wiring GW2. The gate of the MOSFET of the unit cell in sub-cell region CA3 is connected to gate wiring GW3. Also, the gate of the MOSFET of the unit cell in sub-cell region CA4 is connected to gate wiring GW4.
[0040] The cross-sectional structure of the MOSFET 1Q formed in the cell region CA and the cross-sectional structure of the terminal region TA will be described below with reference to Figures 4 and 5. Note that the cell region CA in Figure 5 is an enlarged view of a portion of Figure 4.
[0041] <Structure of MOSFET 1Q in Cell Region CA> As shown in Figures 4 and 5, the semiconductor substrate SUB has an upper surface TS and a lower surface BS and is composed of n-type silicon carbide (SiC). The semiconductor substrate SUB has an n-type drift region NV and an n-type drain region ND. The drain region ND is formed in the semiconductor substrate SUB so as to have a predetermined thickness from the lower surface BS of the semiconductor substrate SUB toward the upper surface TS of the semiconductor substrate SUB. The impurity concentration in the drain region ND is higher than the impurity concentration in the drift region NV.
[0042] The semiconductor substrate SUB may be, for example, a laminate of an n-type SiC substrate and an n-type SiC layer formed on the n-type SiC substrate by an epitaxial growth method. In this case, the n-type silicon substrate constitutes the drain region ND, and the n-type SiC layer constitutes the drift region NV. The drift region NV includes the JFET region. Within the drift region NV, a protective region PP is formed so as to cover the area around the bottom of the gate insulating film GI that covers the gate electrode GE.
[0043] A drain electrode DE is formed beneath the lower surface BS of the semiconductor substrate SUB. The drain electrode DE is composed of a single layer of metal film, such as an aluminum film, titanium film, nickel film, gold film, or silver film, or a laminated film formed by appropriately stacking these metal films. The drain region ND and the drain electrode DE are formed over the entire lower surface BS of the semiconductor substrate SUB. Drain potential is supplied to the semiconductor substrate SUB (drain region ND, drift region NV) from the drain electrode DE.
[0044] On the upper surface TS of the semiconductor substrate SUB in the cell region CA, a gate electrode GE is formed via a gate insulating film GI. The gate electrode GE is located inside the formed trench TR. The gate insulating film GI is made of, for example, a silicon oxide film. The gate electrode GE is made of, for example, a polycrystalline silicon film into which n-type impurities are introduced.
[0045] In the semiconductor substrate SUB in the cell region CA, a p-type body region PB reaching a predetermined depth from the upper surface TS of the semiconductor substrate SUB is formed. In the body region PB, an n-type source region NS and a p-type high-concentration diffusion region PR are formed. The impurity concentration of the source region NS is higher than that of the drift region NV. The impurity concentration of the high-concentration diffusion region PR is higher than that of the body region PB.
[0046] Note that the body region PB and the high-concentration diffusion region PR contain, for example, aluminum (Al) as an impurity. The source region NS contains, for example, nitrogen (N) as an impurity.
[0047] The gate electrode GE is formed so as to straddle a part of each of two adjacent body regions PB and a drift region NV located between the two adjacent body regions PB. Among the body regions PB, the portion located below the gate electrode GE via the gate insulating film GI and located between the source region NS and the drift region NV in a plan view constitutes the channel region of the MOSFET1Q.
[0048] On the upper surface TS of the semiconductor substrate SUB, an interlayer insulating film IL is formed so as to cover the MOSFET1Q. The interlayer insulating film IL is, for example, a silicon oxide film. In the interlayer insulating film IL, holes CH are formed so as to reach the source region NS and the high-concentration diffusion region PR.
[0049] On the interlayer insulating film IL in the cell region CA, a source electrode SE is formed. The source electrode SE is also formed inside the holes CH, is electrically connected to the source region NS, the high-concentration diffusion region PR, and the body region PB, and supplies a source potential to these impurity regions.
[0050] As shown in Figure 4, in the terminal region TA, holes CH are formed in the interlayer insulating film IL. Guard ring wiring GR is formed on the interlayer insulating film IL and inside the holes CH. In addition, in the terminal region TA, holes CH that reach the semiconductor substrate SUB are also formed in the interlayer insulating film IL.
[0051] <Structure of the Termination Region TA> As shown in Figure 4, a field insulating film IF0 is formed on the upper surface TS of the semiconductor substrate SUB in the termination region TA. The field insulating film IF0 is, for example, a silicon oxide film and has a greater thickness than the gate insulating film GI. An interlayer insulating film IL is formed on the upper surface TS of the semiconductor substrate SUB so as to cover the field insulating film IF0. Gate wiring GW, source wiring SW, and guard ring wiring GR are formed on the interlayer insulating film IL of the termination region TA.
[0052] The source electrode SE, gate wiring GW, source wiring SW, and guard ring wiring GR are composed of, for example, a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a titanium-tungsten film. The conductive film is, for example, an aluminum alloy film with copper or silicon added.
[0053] As shown in Figures 4 and 5, a resurf region RS and an impurity region NGR are formed in the semiconductor substrate SUB of the termination region TA, extending to a predetermined depth from the upper surface TS of the semiconductor substrate SUB. The impurity concentration in the impurity region NGR is higher than that in the drift region NV.
[0054] As shown in Figure 4, a pore CH is formed in the interlayer insulating film IL of the terminal region TA, reaching the resurf region RS, and the source wiring SW is also formed inside this pore CH. The source wiring SW is electrically connected to the resurf region RS and supplies a source potential to these impurity regions.
[0055] Furthermore, a pore CH is formed in the interlayer insulating film IL of the terminal region TA, reaching the impurity region NGR, and the guard ring wiring GR is also formed inside this pore CH. The guard ring wiring GR and the impurity region NGR are electrically connected to the drain electrode DE via the drift region NV and the drain region ND. Therefore, the drain electrode DE supplies the drain potential to the guard ring wiring GR and the impurity region NGR.
[0056] Although not shown in the diagram, a silicide film may be formed on the upper surface of each of the impurity region NGR, resurf region RS, source region NS, and high-concentration diffusion region PR located at the bottom of the pore CH. Such a silicide film may be, for example, nickel silicide or titanium silicide.
[0057] <Electrical Characteristics Evaluation and Obtained Device Characteristics> Next, we will explain the electrical characteristics evaluation of MOSFETs and the device characteristics obtained from that evaluation. We will also explain how a gate driver controls the MOSFETs in a unit cell based on the electrical characteristics evaluation of the MOSFETs, i.e., the device characteristics.
[0058] Generally, for MOSFETs, the combinations of electrical characteristic evaluation and the device characteristics obtained from that evaluation are as follows:
[0059] (1) The threshold voltage Vth can be determined from the drain current Id-gate voltage Vg characteristic. (2) The drain-induced barrier drop DIBL can be determined from the drain voltage Vd dependence. (3) The gate breakdown voltage (immediate dielectric breakdown voltage) TZDB can be determined from the gate current Ig-gate voltage Vg characteristic. (4) The on-resistance RonA can be determined from the drain current Id-drain voltage Vd characteristic. In particular, if the drive Vg dependence is obtained, the channel resistance Rch can be estimated. (5) The breakdown voltage BV can be determined from the BV characteristic. Also, the amount of Ig leakage is related to the gate electric field. (6) The input capacitance Ciss, output capacitance Coss, and feedback capacitance Crss can be determined from the capacitance characteristics. (7) Switching characteristics, short-circuit characteristics, etc. can be determined from the on-resistance RonA, threshold voltage Vth, various capacitances Ciss, Coss, Crss, and breakdown voltage BV.
[0060] <MOSFET Control Method> Figure 6 is a diagram showing an example of the relationship between device characteristics and the MOSFET control (driving) method in the second embodiment. Figure 7 is a tree diagram showing a part of the control (driving) method of the unit cell MOSFET in the second embodiment. Control circuits such as the control CMOS circuit 5, gate driver 7, and IC circuit 9 control the unit cell MOSFET using these control methods.
[0061] Information representing the electrical characteristics evaluation may be input into the IC circuit 9 by the user or application software, or the IC circuit 9 itself may perform the electrical characteristics evaluation based on a predetermined algorithm and obtain the information. Furthermore, the selection and setting of the control method used by the IC circuit 9 may be done by the user by inputting information into the IC circuit 9, or the IC circuit 9 itself may do so based on the electrical characteristics evaluation information by performing a predetermined algorithm.
[0062] In the control method described below, when comparing a physical quantity related to a MOSFET within a sub-cell region with a certain value, the physical quantity used is generally a representative value of the physical quantities related to multiple MOSFETs within the cell region, such as the mean or median.
[0063] Control method M (1-1) (a): With respect to the MOSFET in the target subcell region, if the channel resistance Rch is higher (lower) or the threshold voltage Vth is higher (lower) compared to MOSFETs in other subcell regions, then the on-resistance RonA is inevitably higher (lower). In this case, driving with a gate voltage Vg higher than a predetermined reference value is required (driving with a lower Vg is possible). Therefore, the gate voltage Vg is set higher (lower) than that of MOSFETs in other subcell regions for driving.
[0064] This control eliminates the imbalance in the on-resistance RonA of MOSFETs between multiple subcell regions contained within the same chip, thereby improving reliability. However, when driving with a high gate voltage Vg, Vg should be adjusted while also considering the reliability of the following control method M(1-2).
[0065] (b) If the gate breakdown voltage TZDB of a MOSFET in the target sub-cell region is smaller than that of a MOSFET in other cell regions, or if the drain-source voltage BVdss at which gate current Ig leakage occurs during avalanche fall is smaller, it is possible to drive it with a gate voltage Vg lower than a predetermined reference value. Therefore, it is driven with a lower gate voltage Vg than the MOSFETs in other cell regions.
[0066] This control method makes it possible to improve reliability by using chips with low gate reliability at low drive voltages. In other words, reliability can be improved by actively using MOSFETs in unit cells with high gate reliability. However, since degradation other than the gate may occur, monitoring by sensing is necessary each time. Consider this in combination with the above M(1-1).
[0067] (c): If the on-resistance RonA of a MOSFET in a target subcell region is higher (lower) than that of a MOSFET in another subcell region, it is necessary to drive it with a drain-source voltage Vdss higher than a predetermined reference value (driving with a lower Vdss is possible). Therefore, it is driven with a higher (lower) drain-source voltage Vdss than the MOSFET in another subcell region.
[0068] (d): If the breakdown voltage BV of a MOSFET in a target subcell region is higher (lower) than that of a MOSFET in another subcell region, it is necessary to drive it at a drain-source voltage Vdss higher than a predetermined reference value (or it is possible to drive it at a lower Vdss). Therefore, it is driven at a higher (lower) drain-source voltage Vdss than the MOSFET in another subcell region.
[0069] Numerous methods are possible for controlling (driving) the MOSFETs in a unit cell. Here, we will explain some examples of how to control the MOSFETs in a unit cell.
[0070] <<Limiting the usable area based on inspection information>> Control method M(1-2): In a power device (chip) to which control method M(1-1) is applied, the control method is changed for cell areas that are presumed to have poor characteristics based on inspection information before or during the manufacturing process (due to defects or yield).
[0071] Control method M(1-3): In control method M(1-2), a negative voltage is applied as the gate voltage Vg, and the information of the MOS characteristics is not used, only the characteristics of the body diode are used.
[0072] Control method M(1-4): In control method M(1-2), if there is a defect in a unit cell within a sub-cell region, the MOSFET of that unit cell within that sub-cell region is used only in a low-speed operation mode.
[0073] <<Status and Degradation Detection>> Control Method M(1-5): In a power device to which Control Method M(1-1) is applied, the on-resistance in each cell is estimated from the current in each active region. When the on-resistance is low, the drain voltage of the MOSFET in the unit cell within the target sub-cell region is lowered and the device is operated. By eliminating the imbalance between cell regions, the current is suppressed from flowing concentratedly to the MOSFET in the unit cell within the target sub-cell region, which would accelerate degradation.
[0074] Control method M(1-6): In a power device to which control method M(1-1) is applied, the on-resistance or breakdown voltage of the MOSFETs in each cell region is estimated from the current in each active region. When the on-resistance is high and the breakdown voltage is also sufficiently high, the drain-induced barrier drop DIBL is measured from the IdVg measurement sensing. Once it is confirmed that the reliability is sufficient with respect to the voltage rise, the MOSFETs in the target cell region are operated at a high drain voltage Vd to improve performance.
[0075] Control method M(1-7): In a power device to which control method M(1-1) is applied, the threshold voltage and channel resistance of the MOSFETs in each cell region are estimated from the current in each active region. When the channel resistance is low and the threshold voltage is also low, the MOSFETs in the target cell region are driven with a low gate voltage Vg to improve reliability.
[0076] Control method M(1-8): In a power device to which control method M(1-1) is applied, the threshold voltage and channel resistance of the MOSFETs in each cell region are estimated from the current in each active region. When the channel resistance is high, the threshold voltage is high, and furthermore, the gate breakdown voltage TZDB and the voltage through which the leakage current flows at high voltages are high, the MOSFETs in the target cell region are driven with a high gate voltage Vg to improve performance.
[0077] Control method M(1-9): In a power device to which control method M(1-1) is applied, the gate breakdown voltage TZDB and Ig leakage current at high voltage of the MOSFETs in each cell region are estimated from the current in each active region. When the voltage through which the gate breakdown voltage TZDB and Ig leakage current at high voltage flow is low, the MOSFETs in the target cell region are driven with a low gate voltage Vg to improve reliability.
[0078] <<Anomaly Detection>> Control Method M(1-10): In a power device to which control method M(1-1) is applied, a MOSFET or diode for interruption is arranged in parallel in the active region of each unit cell, and an overcurrent detection unit is connected to the source. When an overcurrent is detected by the overcurrent detection unit, the resistance of the interruption MOSFET (or diode) suppresses the overcurrent, thereby suppressing a short circuit.
[0079] Control method M(1-11): In a power device to which control method M(1-1) is applied, a MOSFET or diode for interruption is arranged within the same chip, and an overcurrent detection unit is connected to the source portion of the active region. When an overcurrent is detected by the overcurrent detection unit, the resistance of the interruption MOSFET (or diode) suppresses the overcurrent, thereby suppressing the short circuit.
[0080] Furthermore, the above-described control methods M(1-10) and M(1-11) can be implemented, for example, in the second embodiment described later.
[0081] <MOSFET Structure and Variation> Figure 8 shows the structure of a typical shielded trench gate power MOSFET. As shown in Figure 8, a drain region 22 is formed on the bottom side of the semiconductor substrate 21. A metal silicide layer 23 is formed on the bottom side of the drain region 22. Furthermore, a drain electrode 24 is formed on the bottom side of the metal silicide layer 23. A drift layer 25 is formed on the top side of the semiconductor substrate 21. A JFET region 27 is formed on the top side of the drift layer 25. A body 28 is formed on the top side of the JFET region 27. A source 29 is formed on the top side of the body 28. An insulating film 30 is formed on the top side of the source 29.
[0082] In the stacked region of the insulating film 30, source 29, body 28, and JFET region 27, a trench 31 is formed in the vertical direction. A gate insulating film 35 is formed on the surface of the trench 31. A gate electrode 36 is formed on the upper surface of the gate insulating film 35. Above the gate insulating film 35, an interlayer insulating film 37 is formed so as to cover the gate electrode 36. A source electrode 38 is also formed so as to cover the insulating film 30, the gate insulating film 35, and the interlayer insulating film 37. In the JFET region 27, a trench protection region 26 is formed so as to cover the gate insulating film 35 that forms the trench bottom surface 33 and a part of the trench side wall surface 32 connected to the trench bottom surface 33. A potential fixed region 34 is also formed between the body 28 and the source electrode 38.
[0083] In typical shielded trench gate power MOSFETs, variations in trench etching accuracy occur. When variations in trench etching accuracy occur, the trenches 31 may become deeper or wider in some MOSFETs. This can lead to a narrowing of the distance between the trench 31 and the trench protection region 26, potentially resulting in insufficient electric field relaxation of the oxide film. In such cases, it is preferable to use a control method such as M(1-10) shown in Figure 7.
[0084] Furthermore, variations in the precision of the photoresist can cause the depth of the body 28 to increase, and variations in the oxide film thickness can cause the film thickness of the insulating film 30 or the interlayer insulating film 37 to increase. In such cases, the threshold voltage Vth and the channel resistance Rch will increase, so it is preferable to use a control method such as M(1-9) shown in Figure 7.
[0085] Furthermore, variations in the precision of the photoresist can narrow the width of the JFET region 27. This increases the on-resistivity RonA, so it is preferable to use a control method such as M(1-6) shown in Figure 7.
[0086] Furthermore, variations in the precision of the photoresist can cause the width of the JFET region 27 to widen, resulting in a lower breakdown voltage BV. In this case, it is preferable to use the control method M(1-7) shown in Figure 7.
[0087] It should be noted that there are various variations in the structure of MOSFETs, and the control method shown here is just one example. Other control methods could include, for example, not using the gate-source short region if there is a manufacturing defect in the gate electrode 36.
[0088] According to the semiconductor device 100 of this first embodiment, when multiple unit cells are included within the same chip 1, the cell region 3 of the chip 1 is divided into N (N≧2) partial cell regions 3P, and a gate pad 4 is provided for each partial cell region 3P. The gates of the multiple unit cells, i.e., multiple MOSFETs, within the partial cell region 3P are all connected to one gate pad 4 corresponding to that partial cell region 3P.
[0089] With this configuration, it becomes possible to control the MOSFETs of the unit cells separately for each subcell region 3P based on the results of characteristic evaluation and test results of the MOSFETs in the unit cells in each subcell region 3P. Even if there are defects in some of the subcell regions 3P, it is possible to avoid rendering the chip 1 itself unusable by limiting the use of the subcell regions to other good subcell regions 3P. Therefore, the yield in the manufacturing of the semiconductor device 100 can be improved, and the practicality of the silicon carbide semiconductor device can be enhanced.
[0090] Furthermore, according to the semiconductor device 100 of the first embodiment, a gate driver 7 or IC circuit 9 is provided as a control circuit that independently controls the voltage applied to N gate pads. This makes it possible to control the MOSFETs of the unit cells in each subcell region 3P in an appropriate manner that takes into account their characteristics, enabling efficient use of the MOSFETs.
[0091] Furthermore, according to the semiconductor device 100 of the first embodiment, the IC circuit 9 as a control circuit can change the operating conditions of the MOSFETs of the unit cells for each of the N subcell regions 3P based on characteristic evaluation information of the unit cells within each subcell region 3P. This makes it possible to operate the MOSFETs of the unit cells in each subcell region 3P under operating conditions suitable for their characteristics.
[0092] The characteristic evaluation information includes at least one of the MOSFET's on-resistance, channel resistance, and threshold voltage. This proposes a concrete example of characteristic evaluation information that forms the basis for determining the operating conditions of the MOSFET in a unit cell.
[0093] Furthermore, the operating conditions include at least one of the MOSFET's drain voltage and gate voltage. This allows for the proposal of specific examples of MOSFET operating conditions.
[0094] In the above embodiment, the number of cell units contained within one divided sub-cell region is not specifically defined, but it can be any number, as long as it is basically one or more.
[0095] (Second Embodiment) A second embodiment will now be described. In the second embodiment, it is assumed that there are multiple types of unit cells within the same chip. For the MOSFETs of each of the multiple types of unit cells, control is performed to change the connection method of the MOSFETs depending on the control application and the state of each unit cell.
[0096] Figure 9 shows an example of the structure of a semiconductor device chip according to the second embodiment. In the example in Figure 9, numerous unit cells composed of seven types of unit cells, A through G, are formed within chip 1A. In addition, chip 1A has a total of 49 partial cell regions, with seven of each of the partial cell regions 3A, 3B, 3C, 3D, 3E, 3F, and 3G. In other words, the entire cell region of chip 1A is divided into 49 parts. Partial cell region 3A contains multiple A-type unit cells. Partial cell region 3B contains multiple B-type unit cells. The same applies to each of the partial cell regions from partial cell region 3C to partial cell region 3G.
[0097] Furthermore, in the region of chip 1A, one gate pad is assigned and formed for each subcell region. That is, one gate pad 4A is formed for each subcell region 3A. Similarly, one gate pad 4B is formed for each subcell region 3B. The same applies to each subcell region from subcell region 3C to subcell region 3G. Therefore, a total of 49 gate pads are formed. Note that in Figure 9, the gate drivers connected to the gate pads, their connection lines, etc., are not shown.
[0098] In the case of such a chip 1A, it is easy to connect different types of chips in parallel, or to connect detection devices to the chip in series or parallel, which makes it possible to reduce the noise generated and improve operating accuracy.
[0099] If using chips of the same type, the design should prioritize on-resistance, and in the event of blocking or a short circuit, the current path should be switched to direct current to the chip with guaranteed reliability. Alternatively, MOSFETs in unit cells within a defective sub-cell region should only operate with their built-in diodes. Or, for MOSFETs in unit cells with different threshold voltages, parallel operation can be considered by, for example, changing the drive voltage for each MOSFET.
[0100] These controls may also be programmable using AI (artificial intelligence) via gate drivers 7 connected to gate pads 4 of each subcell region 3P.
[0101] When multiple subcell regions containing different types of unit cells exist within the same chip, arranging various sensors, drive circuits, etc., near the chip enables sensing or high-speed control of the MOSFETs of the unit cells within each subcell region. Examples of various sensors and drive circuits include current sensors, temperature sensors, MEMS (Micro Electro Mechanical Systems) sensors, electromagnetic field sensors, and drive SiCICs (SiC semiconductor integrated circuits).
[0102] Regarding the SiCIC used for driving, various gate drive circuits are possible, but one example is a totem-pole circuit (also called a push-pull circuit).
[0103] Figure 10 shows an example of a gate drive circuit configured as a totem pole circuit. The gate drive circuit shown in Figure 10 includes a P-type MOSFET 41 and an N-type MOSFET 42. The source-drain path of the P-type MOSFET 41 and the drain-source path of the N-type MOSFET 42 are connected in series. The gate of the P-type MOSFET 41 and the gate of the N-type MOSFET 42 are connected, and a control signal is input to this connection point. The connection point between the drain of the P-type MOSFET 41 and the drain of the N-type MOSFET 42 is connected to the gate of the main MOSFET 43 to be driven, as the output node of the totem pole circuit. The source of the P-type MOSFET 41 and the drain of the main MOSFET 43 are connected, for example, to a high-potential line VDD of a predetermined power supply. The source of the N-type MOSFET 42 and the source of the main MOSFET 43 are connected, for example, to a low-potential line VSS of a predetermined power supply. VSS is connected, for example, to a ground terminal.
[0104] By using a gate drive circuit configured with such a totem pole circuit, the gate of the main MOSFET 43 can be quickly charged and discharged, enabling high-speed gate control.
[0105] Furthermore, regarding the design of the IC circuit that controls chip 1A, it is possible to freely control the MOSFETs of the unit cell, such as by changing the control for each sub-cell region. In addition, CMOS can be used to sense the degradation state of the unit cell.
[0106] According to the semiconductor device of this second embodiment, the plurality (N) of partial cell regions include a partial cell region 3A containing a unit cell A of a first type, and a partial cell region 3B containing a unit cell B of a second type different from the first type. With this configuration, it is possible to connect multiple semiconductor devices to each other, or to connect a semiconductor device to other detection devices, thereby realizing a highly flexible circuit design.
[0107] (Third Embodiment) A third embodiment will now be described. In the third embodiment, a technology will be described in which a chip and its surrounding parts, which would normally be mounted on the surface of a flat substrate, are mounted three-dimensionally to improve operational accuracy, save space, etc.
[0108] The semiconductor device according to the third embodiment can be realized, for example, by applying the semiconductor devices according to the first and second embodiments and stacking chips together, or chips and peripheral circuits in a three-dimensional manner. The advantages of stacking chips, peripheral circuits, etc., in a three-dimensional manner include, for example, when using a temperature sensor, the temperature of the chip can be directly measured, and in the semiconductor device according to the first or second embodiment, only the high-temperature region can be sensed, and the control can be changed in the CMOS circuit within the same chip, for example, implemented using the method of the semiconductor device according to the second embodiment. Furthermore, by mounting small inductors in a three-dimensional manner and sensing the magnetic field, it becomes possible to sense the current value of the current flowing through the MOSFET of the unit cell in real time. In addition, by directly cooling the mounting substrate and combining it with the temperature sensing described above, it is also possible to control the water passages, oil passages, or flow rate of water cooling or oil cooling.
[0109] Figure 11 shows an example of a chip and peripheral circuits mounted on a planar substrate. In the example shown in Figure 11, a chip 1B manufactured using a silicon carbide semiconductor substrate, multiple control CMOS circuits 5, multiple sensors 8, and an IC circuit 9 including a gate driver 7 are mounted on the surface of the substrate 10. The chip 1B includes multiple divided sub-cell regions 3P, and each sub-cell region 3P has multiple gate pads 4 formed on it corresponding to each sub-cell region 3P. The gate pads 4 and the control CMOS circuits 5 are connected by wiring 6 such as wires. Similarly, the sub-cell regions 3P and the sensors 8 are connected by wiring 6. Furthermore, the multiple control CMOS circuits 5 and the multiple sensors 8 and the IC circuit 9 are connected by wiring 6. Note that in Figure 11, the wiring 6 connected to the IC circuit 9 is not shown.
[0110] IC circuit 9 is a circuit that controls chip 1B. Based on the output of sensor 8, etc., IC circuit 9 evaluates the electrical characteristics of each unit cell MOSFET within the sub-cell region 3P. Based on the evaluation results and the designed control operation, IC circuit 9 controls the gate driver 7 and controls each unit cell MOSFET within each sub-cell region 3P in a manner suitable for its electrical characteristics.
[0111] As shown in Figure 11, when the chip 1B and its peripheral circuits are mounted on the substrate 10L, the area occupied by the chip and peripheral circuits on the planar substrate increases, and the wiring connecting the chip and peripheral circuits tends to become longer. In this case, the accuracy of the physical quantity detected by the sensor 8 decreases, and the operating accuracy and operating speed limits of the MOSFETs of each unit cell within the partial cell region 3P decrease, as does the noise immunity. Below, an example of a semiconductor device that can solve the above-mentioned problems will be described.
[0112] Figure 12 shows a first example of a semiconductor device in which IC circuits are stacked on a chip according to a third embodiment. In the example shown in Figure 12, an IC circuit 9 that controls the chip 1, including a gate driver 7, is stacked on the upper side of the chip 1 shown in Figure 1. The control CMOS circuit 5 of the chip 1 and the IC circuit 9 are connected via wiring 6 or via a conductive mechanism (not shown).
[0113] Figure 13 shows a second example of a semiconductor device in which an IC circuit is stacked on a chip according to a third embodiment. In the example shown in Figure 13, an IC circuit 9, which includes a gate driver 7 and controls the chip 1A, is stacked on the upper side of the chip 1A shown in Figure 9. The MOSFET of the unit cell of the chip 1A and the IC circuit 9 are connected via wiring 6 or via a conductive mechanism (not shown).
[0114] Figure 14 is a side view showing an example of the structure of a semiconductor device in which a chip and an IC circuit are stacked according to a third embodiment. In the example shown in Figure 14, a bonding layer 11L is formed on the upper side of the substrate 10L, and a silicon carbide chip layer 1L is arranged on the upper side of the bonding layer 11L. A sensor layer 8L is arranged on the upper side of the chip layer 1L, and an IC circuit 9 is arranged on the upper side of the sensor layer 8L. Multiple gate pads 4 are formed on the substrate 10L. The multiple gate pads 4, the chip layer 1L, and the IC circuit 9 are connected via a wiring network 6L.
[0115] Each MOSFET in the cell unit contained in the chip layer 1L is sensed by various sensors contained in the sensor layer 8L. The sensor layer 8L includes MEMS sensors, temperature sensors, current sensors, magnetic field sensors, etc. The chip layer 1L and the sensor layer 8L are stacked in close proximity or in close contact with each other. The sensors contained in the sensor layer 8L sense the state of the MOSFETs in close proximity or in close contact with them. In this configuration, the noise immunity of the sensor operation and output is increased, and the accuracy of sensing is improved. In particular, temperature sensors and magnetic field sensors can directly sense the temperature and magnetic field of the MOSFETs, and high accuracy of detected temperature and magnetic field is expected.
[0116] Information obtained by sensing in the sensor layer 8L is sent to the IC circuit 9. Based on the information obtained by sensing, the IC circuit 9 controls the gate voltage input to the gate pad 4, thereby controlling the MOSFETs of the cell units within each cell region included in the chip layer 1L. The IC circuit 9 provides feedback control to the MOSFETs of each cell unit as needed. Furthermore, by stacking a cooling mechanism directly or indirectly on the upper or lower side of the chip layer 1L, the chip layer 1L can be cooled efficiently. In addition, the IC circuit 9 can also perform processing related to life diagnosis of the chip layer 1L, cell regions, or unit cells by accumulating the information obtained by sensing in the sensor layer 8L.
[0117] As described above, the semiconductor device according to the third embodiment includes one or more sensors that detect a physical quantity relating to at least one of the multiple unit cells. The IC circuit 9 controls the operating conditions of the MOSFETs of the unit cells based on the physical quantities detected by the one or more sensors. This makes it possible to directly and accurately determine the state of the unit cells using the sensors and to control the operating conditions of the MOSFETs with high precision.
[0118] Furthermore, the one or more sensors described above include at least one of a temperature sensor, a current sensor, and a magnetic field sensor. This allows for the proposal of specific examples of usable sensors.
[0119] Furthermore, according to the semiconductor device of the third embodiment, control circuits such as the IC circuit 9 are laminated on the chip layer 1L, that is, the silicon carbide substrate layer. This laminated structure reduces the occupied area and saves space. In addition, wiring can be shortened and noise immunity can be improved.
[0120] Furthermore, according to the semiconductor device of the third embodiment, the sensor layer 8L, which includes one or more of the above-mentioned sensors, is laminated on the chip layer 1L, i.e., the silicon carbide substrate. With such a laminated structure, the sensors can be arranged in close proximity to or in close contact with the unit cell, and physical quantities can be detected with high accuracy.
[0121] Although the present invention has been specifically described above based on embodiments, it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence.
[0122] 1, 1A, 1B... Chip, 2... SiC substrate, 3... Cell region, 3P, 3A, 3B, 3C, 3D, 3E, 3F, 3G... Partial cell region, 4, 4A, 4B, 4C, 4D, 4E, 4F, 4G... Gate pad, 5... Control CMOS circuit, 6... Wiring, 6L... Wiring network, 7... Gate driver, 8... Sensor, 8L... Sensor layer, 9... IC circuit, 10... Substrate, 10L... Substrate, 11L... Bonding layer, 21... Semiconductor substrate 22...Drain region, 23...Metal silicide layer, 24...Drain electrode, 25...Drift layer, 26...Trench protection region, 27...JFET region, 28...Body, 29...Source, 30...Insulating film, 31...Trench, 32...Trench sidewall, 33...Trench bottom, 34...Potential fixed region, 35...Gate insulating film, 36...Gate electrode, 37...Interlayer insulating film, 38...Source electrode, 50...Termination region, 100...Semiconductor device.
Claims
1. A silicon carbide semiconductor device comprising: a silicon carbide substrate; a plurality of unit cells formed on the silicon carbide substrate, each having a MOSFET structure; and N gate pads formed on the silicon carbide substrate, each corresponding to one of N subcell regions obtained by dividing a region containing the plurality of unit cells, and connected to the gates of the MOSFETs of the unit cells within the subcell regions, wherein the termination structure of the MOSFETs of the unit cells within the N subcell regions is common.
2. A silicon carbide semiconductor device according to claim 1, comprising a control circuit for independently controlling the voltage applied to the N gate pads.
3. A silicon carbide semiconductor device according to claim 2, wherein the control circuit limits the partial cell regions to be used based on characteristic evaluation information of the unit cells within the N partial cell regions.
4. A silicon carbide semiconductor device according to claim 2, wherein the control circuit changes the operating conditions of the MOSFETs of the unit cells for each of the N subcell regions based on characteristic evaluation information of the unit cells within the N subcell regions.
5. A silicon carbide semiconductor device according to claim 4, wherein the characteristic evaluation information includes at least one of the on-resistance, channel resistance, and threshold voltage of the MOSFET.
6. A silicon carbide semiconductor device according to claim 4, wherein the operating condition includes at least one of the drain voltage and gate voltage of the MOSFET.
7. A silicon carbide semiconductor device according to claim 2, comprising one or more sensors for detecting a physical quantity relating to at least one of the plurality of unit cells, wherein the control circuit controls the operating conditions of the MOSFET of the unit cell based on the physical quantity detected by the one or more sensors.
8. A silicon carbide semiconductor device according to claim 7, wherein the one or more sensors include at least one of a temperature sensor, a current sensor, and a magnetic field sensor.
9. A silicon carbide semiconductor device according to claim 2, wherein the control circuit is laminated on the silicon carbide substrate.
10. A silicon carbide semiconductor device according to claim 7, wherein the layer containing one or more sensors is laminated on the silicon carbide substrate.
11. A silicon carbide semiconductor device according to claim 1, wherein the N subcell regions include a subcell region containing a first type of unit cell and a subcell region containing a second type of unit cell different from the first type.