Imaging element and imaging device
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- NIKON CORP
- Filing Date
- 2025-12-26
- Publication Date
- 2026-07-30
Smart Images
Figure JP2025046008_30072026_PF_FP_ABST
Abstract
Description
Image sensor and imaging device
[0001] The present invention relates to an image sensor and an imaging device. This application claims priority under Japanese Patent Application No. 2025-010659, filed on 24 January 2025, the contents of which are incorporated herein by reference.
[0002] The invention describes an image sensor in which multiple pixels are arranged in a two-dimensional array. Improvements in image quality have been desired for some time (for example, Patent Document 1).
[0003] Japanese Patent Publication No. 2008-186894
[0004] An image sensor according to one aspect of the present invention includes a first photoelectric conversion unit that converts light into electric charge, a first pixel block that includes a first photoelectric conversion unit that converts light into electric charge and a second photoelectric conversion unit that converts light into electric charge and is arranged in the column direction alongside the first photoelectric conversion unit, and outputs a first signal based on the charge converted by the first photoelectric conversion unit and a second signal based on the charge converted by the second photoelectric conversion unit, and a second pixel block that includes a third photoelectric conversion unit that converts light into electric charge and is arranged in the column direction alongside the first photoelectric conversion unit, and outputs a third signal based on the charge converted by the third photoelectric conversion unit, and a first substrate laminated together with the first substrate, arranged at a position opposite to the first pixel block, and a signal processing unit that processes at least one of the first signal and the second signal. The second substrate includes a first signal processing block including a first signal processing unit that performs signal processing, and a second signal processing block positioned opposite the second pixel block and including a second signal processing unit that performs signal processing on the third signal. The control unit controls the first timing at which the first signal is output from the first pixel block, the second timing at which the second signal is output from the first pixel block, and the third timing at which the third signal is output from the second pixel block, so that they occur in the order of the first timing, the second timing, and the third timing, respectively. The second photoelectric conversion unit is positioned between the first photoelectric conversion unit and the third photoelectric conversion unit in the column direction, and is positioned such that the distance to the third photoelectric conversion unit is shorter than the distance to the first photoelectric conversion unit.Also, an image sensor according to one aspect of the present invention includes a first pixel block including a plurality of first photoelectric conversion units that convert light into charge, and a pixel block including a plurality of second photoelectric conversion units that convert light into charge, the second pixel block being arranged side by side with the first pixel block in the column direction, a first substrate having the second pixel block, a substrate laminated together with the first substrate, the first signal processing block being arranged at a position facing the first pixel block and including a first circuit portion electrically connected to the first pixel block, a second signal processing block being arranged at a position facing the second pixel block and including a second circuit portion electrically connected to the second pixel block, a control unit that controls so that a first period in which signals based on charges respectively converted by the plurality of first photoelectric conversion units are output from the first pixel block and a second period in which signals based on charges respectively converted by the plurality of second photoelectric conversion units are output from the second pixel block are in the order of the first period and the second period.
[0005] An imaging device according to one aspect of the present invention includes the above-described image sensor.
[0006] This figure shows a schematic configuration example of an image sensor according to an embodiment. This figure shows an example of the configuration of a pixel section according to an embodiment. This figure shows an example of the configuration of an image sensor according to an embodiment. This figure is for explaining the processing overview of the image sensor according to the first embodiment. This figure shows a schematic configuration example of the circuit of the image sensor according to the first embodiment. This figure shows an example of the timing budget for processing according to the first embodiment. This figure shows an example of the circuit configuration of the image sensor according to the first embodiment. This is an image diagram illustrating the readout timing when a pixel signal is read out using the method of the first embodiment. This figure shows an example of an image resulting from reading out a pixel signal using the method of the first embodiment. This figure shows the readout timing when a moving object is photographed with an image sensor equipped with an AD converter for each pixel block of a comparative example. This figure shows an example of an image when a moving object is photographed with an image sensor equipped with an AD converter for each pixel block of a comparative example. This figure is for explaining the processing overview of an image sensor according to the second embodiment. This figure shows an example of the timing budget for processing according to the second embodiment. This figure shows an example of the circuit configuration of an image sensor according to the second embodiment. This figure is for explaining an example of a method for realizing readout with the first gain and second gain according to the second embodiment. This figure shows an example of a circuit when the capacity of the FD is switched for each pixel according to the second embodiment to switch the gain. This figure shows an example of a circuit when the FD connected to a pixel not used for readout according to the second embodiment is connected to the FD being read out to switch the gain. This figure illustrates an example of processing when the gain is switched by controlling the accumulation time according to the second embodiment. This figure shows an example of the configuration of the imaging device according to the embodiment.
[0007] Embodiments of the present invention will be described below with reference to the drawings. Note that in the drawings used in the following description, the scale of each component has been appropriately changed to ensure that each component is recognizable.
[0008] <Example of Schematic Configuration of Image Sensor and Example of Pixel Configuration> First, an example of the schematic configuration of the image sensor and an example of the configuration of the pixel section will be explained using Figures 1 and 2. Figure 1 is a diagram showing an example of the schematic configuration of an image sensor according to an embodiment. Image sensor 1 captures an image of a subject. Image sensor 1 generates image data of the captured subject. In Figure 1, the X axis and Y axis are orthogonal to each other, and the Z axis is orthogonal to the XY plane. The XYZ axes constitute a right-handed system. The direction parallel to the Z axis is sometimes referred to as the stacking direction of image sensor 1. In the following explanation, the terms "up" and "down" are not limited to the up and down directions in the direction of gravity. These terms merely refer to relative directions in the Z axis direction. In the following explanation, the arrangement in the X axis direction is described as a "row," and the arrangement in the Y axis direction is described as a "column," but the matrix direction is not limited to these.
[0009] The image sensor 1 comprises a first semiconductor substrate 10 and a second semiconductor substrate 20. The first semiconductor substrate 10 is stacked on the second semiconductor substrate 20. The first semiconductor substrate 10 includes a pixel section 11. The pixel section 11 comprises a plurality of pixel blocks 15. The pixel section 11 outputs a pixel signal based on incident light. The pixel blocks 15 comprise a plurality of pixels 121.
[0010] The second semiconductor substrate 20 includes a control circuit unit 21 and a peripheral circuit unit 23. The control circuit unit 21 includes a plurality of AD converters (hereinafter also referred to as "ADCs") 25. Pixel signals output from the first semiconductor substrate 10 are input to the control circuit unit 21. The control circuit unit 21 processes the input pixel signals. The control circuit unit 21 is positioned on the second semiconductor substrate 20, for example, opposite the pixel unit 11. The control circuit unit 21 may output control signals to the pixel unit 11 for controlling the driving of the pixel unit 11.
[0011] The peripheral circuit section 23 controls the driving of the control circuit section 21. The peripheral circuit section 23 controls, for example, the signal readout of the pixels 121 included in the pixel section 11. The peripheral circuit section 23 is arranged on the second semiconductor substrate 20, for example, around the control circuit section 21. Alternatively, the peripheral circuit section 23 may be electrically connected to the first semiconductor substrate 10 and control the driving of the pixel section 11. In Figure 1, the peripheral circuit section 23 is arranged along two sides of the second semiconductor substrate 20, but the arrangement of the peripheral circuit section 23 is not limited to this.
[0012] Furthermore, the image sensor 1 may have a memory chip stacked on the second semiconductor substrate 20, in addition to the first semiconductor substrate 10 and the second semiconductor substrate 20. The memory chip performs image processing, for example, in response to the signal output by the second semiconductor substrate 20. Also, the structure of the image sensor 1 may be back-illuminated or front-illuminated.
[0013] Figure 2 shows an example of the configuration of a pixel section according to an embodiment. Figure 2 shows an enlarged view of the pixel section 11 and the pixel blocks 15 provided by the pixel section 11. The pixel section 11 comprises M × N pixel blocks 15 (where M and N are natural numbers) arranged in rows and columns. Although Figure 2 shows the case where M is equal to N, M and N may be different.
[0014] Pixel block 15 comprises m × n pixels 121 (where m and n are natural numbers). For example, pixel block 15 comprises 16 × 16 pixels 121. Note that the number of pixels 121 in pixel block 15 is not limited to this and can be one or more. Also, although Figure 2 illustrates the case where m is equal to n, m may be different from n.
[0015] The pixel block 15 has a plurality of pixels 121 connected to a common control line in the row direction.
[0016] As shown in Figure 2, the pixel block group 12 comprises two pixel blocks 15. In the example in Figure 2, the pixel block group 12 comprises two pixel blocks 15 arranged side by side along the column direction. The pixel block group 12 may consist of one pixel block 15 or three or more.
[0017] If the pixel block group 12 comprises multiple pixel blocks 15, each pixel block 15 may be set to a different exposure time. The pixel block group 12 has 2m × n pixels 121. For example, the pixel block group 12 may have, for example, 32 × 16 pixels 121. However, the number of pixels 121 in the pixel block group 12 is not limited to this.
[0018] Each pixel 121 includes a photoelectric conversion unit that converts light into electric charge, and a readout circuit for reading a signal based on the charge converted by the photoelectric conversion unit. The photoelectric conversion unit stores the photoelectrically converted charge. The readout circuit is composed of, for example, multiple transistors. Two m pixels 121 are arranged in n rows in the row direction within the pixel block group 12.
[0019] <Example of Image Sensor Configuration> Next, an example of the configuration of an image sensor will be described. Figure 3 is a diagram showing an example of the configuration of an image sensor according to the embodiment. As shown in Figure 3, the image sensor 1 comprises m pixel blocks 15-1, ..., 15-m, m readout units 26-1, ..., 26-m, and a readout control unit 31. In the following description, if one of the pixel blocks 15-1, ..., 15-m is not specified, it will be referred to as "pixel block 15", and if one of the readout units 26-1, ..., 3-m is not specified, it will be referred to as "readout unit 26".
[0020] Pixel block 15 comprises n pixels 121 (where n is an integer greater than or equal to 2). For example, pixel block 15-1 comprises n pixels 121-1-1 to 121-1-n. The reading unit 26 comprises, for example, a pixel current source 27, an AD converter 25, and a memory / control circuit 28. For example, the reading unit 26-1 comprises a pixel current source 27-1, an AD converter 25-1, and a memory / control circuit 28-1. In the following description, "AD converter" will also be referred to as "ADC".
[0021] The AD converter 25 is a converter that converts analog signals into digital signals, and is, for example, a single-slope type AD converter. The memory and control circuit 28 includes, for example, SRAM and a control circuit, and stores the digital signal value converted by the AD converter 25.
[0022] The readout control unit 31 sequentially reads out the pixel signals of each of the multiple pixel blocks 15 in the order of the pixel block 15 arrangement by the readout unit. The readout control unit 31 may also be provided in the imaging device 700 (Figure 19).
[0023] [First Embodiment] Figure 4 is a diagram illustrating the processing overview of the image sensor according to this embodiment. In Figure 4, the horizontal axis represents time, and the vertical axis represents the position of the read row in one block row (hereinafter referred to as "block row"). A block row is a plurality of pixel blocks 15 in the row direction. As shown in Figure 4, in this embodiment, at time t1, the image sensor 1 starts reading out the pixel signal of the uppermost block row g111 of the pixel section 11 with a predetermined gain. Subsequently, at time t2, the image sensor 1 starts reading out the pixel signal of the second uppermost block row g121 of the pixel section 11 with a predetermined gain, at time t3, the pixel signal of the third uppermost block row g131 of the pixel section 11 with a predetermined gain, and at time t4, the pixel signal of the fourth uppermost block row g141 of the pixel section 11 with a predetermined gain. Block rows g111, g121, g123, and g141 are composed of a plurality of pixel blocks 15.
[0024] As shown in the image indicated by code g151, the image sensor 1 reads out each row of pixels 121 from top to bottom for each pixel block 15. One pixel block 15 is, for example, 128 pixels (= 16 pixels × 8 units), with a vertical dimension of 16 pixels. As shown in graph g161, the image sensor 1 reads out the top row of the fourth uppermost block row g141 in the pixel section 11 at time t401 (= t4), the second uppermost row of the fourth uppermost block row g141 in the pixel section 11 at time t402, ..., and reads out the sixteenth uppermost row of the fourth uppermost block row g141 in the pixel section 11 at time t416. The time difference between times t401 and t416 is, for example, 8.3 (msec). The image sensor 1 reads out the pixel signal of the bottom row of the previous block row, and then starts reading out the pixel signal of the top row of the next block row.
[0025] Next, a schematic example of the circuit configuration of the image sensor 1 of this embodiment will be described. Figure 5 is a diagram showing a schematic example of the circuit configuration of the image sensor of this embodiment. Image g210 is an example of the overall configuration, and image g220 is an enlarged view. As shown in Figure 5, in this embodiment, for example, every 16 pixels there is a pixel current source 27 (labeled CS in the figure), an AD converter 25 (labeled ADC in the figure), and a memory / control circuit 28 (labeled SRAM etc. in the figure). Also, as shown in image g220, the vertical signal lines 155 are divided into, for example, every 128 pixels. In this embodiment, eight vertical signal lines 155 are connected to each pixel.
[0026] Figure 6 shows an example of a timing budget for the processing according to this embodiment. In Figure 6, "8 rows" refers to eight 16-pixel block rows as shown in Figure 4. The time required to read the 8 rows is, for example, RST (reset), setting time, RST ADC time, TX time, setting time, and SIG (signal) ADC time. RST ADC time is the time required to read the RST data and perform AD conversion. TX time is the time required for transfer. SIG ADC time is the time required to read the signal data and perform AD conversion.
[0027] The transfer timing for RST data (reset data) is, for example, after the RST ADC time. Similarly, the transfer timing for SIG data is, for example, after the SIG ADC time. Note that the example shown in Figure 6 is just one example and is not limited to this.
[0028] Next, an example of the circuit configuration of the image sensor 1 will be described. Figure 7 shows an example of the circuit configuration of the image sensor according to this embodiment. The image sensor 1 is equipped with an SRAM and a MUX (multiplexer) for each pixel (row), such as g401, 402, ... The SRAM and MUX correspond to the memory / control circuit 28. There is one data read line 161 for each pixel.
[0029] Multiple data read lines 161 are connected to the integrated read unit 50. The integrated read unit 50 includes, for example, a G2B 51, a memory 52, a D-CDS 53, a memory 55, and a read circuit 56. The G2B 51 is a converter that converts Gray code values into binary code. The memory 52 is a memory for storing RST (reset voltage) and SIG (signal) for 8 lines. The D-CDS 53 is a circuit that performs CDS (correlated double sampling) by subtracting the reset value and the signal value. The memory 55 is a memory for storing the data after D-CDS again. The read circuit 56 is a circuit that outputs data based on the read pixel signals as an electric current. Note that the configuration example shown in Figure 7 is just one example and is not limited to this.
[0030] Figure 8 is an illustrative diagram of the reading timing when pixel signals are read using the method of this embodiment. Note that Figure 8 is an example where an object moves from right to left. As shown in Figure 8, in this embodiment, the pixel signal of pixel g301 is read at time t301, the pixel signal of pixel g302 is read at time t302, and the pixel signal of pixel g303 is read at time t303.
[0031] The read-out image will be, for example, an image like Figure 9. Figure 9 is a diagram showing an example image resulting from reading out pixel signals using the method of this embodiment. Note that the example in Figure 9 is an example image when an object is moving from left to right. When pixel signals are read out using the method of this embodiment, as shown in Figure 9, when a part of the overall image g351 is enlarged, the image becomes diagonally distorted, as shown in the enlarged image g352. This distortion is similar to that of an image taken with a rolling shutter.
[0032] <Comparative Example> Here, as a comparative example, we will explain the readout and image example when a moving object is photographed using an image sensor equipped with an AD converter for each pixel block. Figure 10 is a diagram showing the readout timing when a moving object is photographed using an image sensor equipped with an AD converter for each pixel block, as in the comparative example. In images g920 and g930, the longitudinal direction is the x-axis direction and the transverse direction is the y-axis direction. Image g920 shows the state in which the image g921 of the object to be photographed is stationary. Image g930 shows the state in which the image g921 of the object to be photographed has moved from right to left in the x-axis direction. In images g920 and g930, it is assumed that the pixel block g910 has, for example, 16 x 16 pixels. In an image sensor equipped with an AD converter for each pixel block, the image signal of each pixel block is read out from top to bottom in the y-axis direction. Therefore, at time t901, the pixel signals of pixels g931, g932, and g933 are read out, and at time t902, the pixel signals of pixels g934, g935, and g936 are read out. In this way, when an image sensor equipped with an AD converter for each pixel block captures a moving object, multiple pixel signals are read out simultaneously, and the timing of reading out other pixel signals in the same pixel block differs, resulting in diagonal distortion of the image row by row.
[0033] Figure 11 shows an example image when a moving object is captured using an image sensor equipped with an AD converter for each pixel block, as in the comparative example. Note that the example in Figure 11 is an image when the object is moving from left to right. With an image sensor equipped with an AD converter for each pixel block, when a portion of the overall image g901 of a moving object is magnified, the diagonally distorted parts are adjacent to each other, making the outline appear jagged, as shown in the magnified image g902.
[0034] In contrast, according to this embodiment, as shown in Figure 3, an AD converter 25 is provided for each pixel block 15, and the pixel signals of the block row are read out sequentially like a rolling shutter. With this configuration and reading timing, according to this embodiment, the reading timing can be made different for each block row. As a result, according to this embodiment, the phenomenon in which the outline of a moving object appears jagged, as seen in the magnified image g352 of a photographed moving object and the magnified image g902 of the comparative example, can be eliminated. Furthermore, according to this embodiment, by using the AD converters 25 arranged in a block shape to perform pipeline operation, pixel signals can be read out without reducing the frame rate.
[0035] <Second Embodiment> The configuration of the image sensor 1 is the same as in Figure 3 of the first embodiment. Figure 12 is a diagram illustrating the processing overview of the image sensor according to this embodiment. In Figure 12, the horizontal axis represents time, and the vertical axis represents the position of the row being read out in one block row. In this embodiment, the pixel signal is read out with two different gains (first gain and second gain). In the following description, the first gain will also be referred to as LCG, and the second gain will also be referred to as HCG. The ratio of the first gain to the second gain is, for example, 10 times.
[0036] As shown in Figure 12, in this embodiment, at time t1, the image sensor 1 starts reading out the pixel signal of the uppermost block row g421 of the pixel section 11 with a first gain (g420). At time t2, the image sensor 1 starts reading out the pixel signal of the uppermost block row g421 of the pixel section 11 with a second gain, and starts reading out the pixel signal of the second uppermost block row g422 of the pixel section 11 with a first gain (g430). The second gain is a different gain from the first gain, for example, a lower gain than the first gain. At time t3, the image sensor 1 starts reading out the pixel signal of the second uppermost block row g422 of the pixel section 11 with a second gain, and starts reading out the pixel signal of the third uppermost block row g423 of the pixel section 11 with a first gain (g440). At time t4, the image sensor 1 starts reading out the pixel signal of the third uppermost block row g423 of the pixel section 11 with a second gain, and starts reading out the pixel signal of the fourth uppermost block row g424 of the pixel section 11 with a first gain (g450). Note that block rows g421, g422, g423, and g424 are composed of multiple pixel blocks 15.
[0037] Thus, in this embodiment, from time t2 onward, the pixel signals of two rows are read out with two different gains. As shown in the image indicated by code g451, the image sensor 1 reads out each row of pixels 121 from top to bottom with a first gain for one pixel block 15. One pixel block 15 is, for example, 128 pixels (= 16 pixels × 8 units), with 16 pixels in the vertical direction. Furthermore, as shown in the image indicated by code g461, the image sensor 1 reads out each row of pixels 121 from top to bottom with a second gain for one pixel block 15.
[0038] Furthermore, as shown in graph g471, the image sensor 1 reads out the top row of the fourth uppermost block row g414 of the sensor 7 at time t401 (=t4), reads out the second uppermost row of the fourth uppermost block row g414 of the sensor 7 with the second gain at time t402, ..., and reads out the sixteenth uppermost row of the fourth uppermost block row g414 of the sensor 7 at time t416. The time difference between t401 and t416 is, for example, 8.3 (msec).
[0039] Note that the readout timing g473 for the first gain and the readout timing g472 for the second gain may be the same, even if there is a time difference. The time difference is, for example, 240 μs. Also, the image sensor 1 reads out the pixel signal of the bottom row of the previous block row, and then starts reading out the pixel signal of the top row of the next block row. In this embodiment, the time required to read out the pixel signal can be read out in the time of the number of vertical block row readouts + 1.
[0040] The schematic configuration example of the circuit of the image sensor 1 in this embodiment is the same as that shown in Figure 5 of the first embodiment.
[0041] Figure 13 shows an example of a timing budget for the processing according to this embodiment. In Figure 13, "8 rows" refers to eight 16-pixel block rows as shown in Figure 6. The time required to read the 8 rows is, for example, RST (reset), setting time, RST ADC time, TX time, setting time, and SIG (signal) ADC time. RST ADC time is the time required to read the RST data and perform AD conversion. TX time is the time required for transfer. SIG ADC time is the time required to read the signal data and perform AD conversion.
[0042] As shown in Figure 13, the RST data transferred in this embodiment includes eight lines read by the first gain (LCG) and eight lines read by the second gain (HCG). Similarly, the SIG data transferred also includes eight lines read by the first gain (LCG) and eight lines read by the second gain (HCG).
[0043] Also, the transfer timing of the RST data is, for example, after the RST ADC time. Also, the transfer timing of the SIG data is, for example, after the SIG ADC time. Note that the example shown in FIG. 13 is just an example and is not limited to it.
[0044] Next, a circuit configuration example of the imaging device 1 will be described. FIG. 14 is a diagram showing a circuit configuration example of the imaging device according to the present embodiment. The imaging device 1 includes an SRAM and a MUX (multiplexer) for each pixel (one column) such as reference numerals g401, 402,.... The SRAM and the MUX correspond to the memory control circuit 28. The data readout line 161 is one for each pixel.
[0045] A plurality of these data readout lines 161 are connected to the integrated readout unit 50A. The integrated readout unit 50A includes, for example, a G2B51, a memory 52A, a D-CDS53, a memory 54, a memory 55, and a readout circuit 56A.
[0046] The G2B51 is a converter that converts a gray code value into a binary code. The memory 52A is a memory for storing the RST (reset voltage) of the first gain for 8 rows, the RST of the second gain for 8 rows, the SIG (signal) of the first gain for 8 rows, and the SIG (signal) of the second gain for 8 rows. The D-CDS53 is a circuit that performs CDS (correlated double sampling) by subtracting the reset value and the signal value.
[0047] The memory 54 is a memory for storing the data of the first gain after D-CDS again. The memory 55A is a memory for storing the data of the second gain after D-CDS again.
[0048] The readout circuit 56A is a circuit that outputs data based on the read pixel signals as current. The readout circuit 56A checks whether the data read and stored with the second gain is saturated or exceeds the threshold value, and outputs one of the data read with the first gain and the data read with the second gain based on the result of the check. For example, when it is determined that the data is not saturated, the readout circuit 56A outputs the data read with the second gain, and when it is within a predetermined value with respect to saturation, the readout circuit 56A outputs the data read with the first gain. Note that the configuration example shown in FIG. 14 is merely an example and is not limited thereto.
[0049] (Example of method for realizing readout with first and second gains) Here, an example of a method for realizing readout with the first and second gains will be described.
[0050] (1) Varying the voltage of the ramp signal of the AD converter 25 FIG. 15 is a diagram for explaining an example of a method for realizing readout with the first and second gains according to the present embodiment. The AD converter 25 of the image pickup device 1 is a single-slope type AD converter as described above. In a single-slope type AD converter, a ramp voltage is used as a comparison signal.
[0051] In the image g500, two buffers 505 and 506 are connected to each of the block rows g501 and g502. A first ramp voltage generation circuit 503 is connected to the buffer 505, and a second ramp voltage generation circuit 504 is connected to the buffer 506. The waveform g511 is an example of a ramp voltage waveform output by the first ramp voltage generation circuit 503. The waveform g512 is an example of a ramp voltage waveform output by the second ramp voltage generation circuit 504.
[0052] In the present embodiment, as described using FIG. 12, the block rows are read from top to bottom like a rolling shutter. Therefore, the AD converter 25 and the like used at the time of reading are connected to the block row being read, and the AD converter 25 and the like of other rows are not used. In the present embodiment, by enabling the ramp voltage generation circuit of the block row used for reading, the load seen from the ramp voltage generation circuit side is reduced.
[0053] Switching between the first ramp voltage generation circuit 503 and the second ramp voltage generation circuit 504 can be achieved, for example, by alternately switching two switches 522 and 523 connected to the output of buffer 506, as in circuit 520. With this circuit configuration, the influence of the switch's on-resistance can be reduced. With this circuit configuration, by varying the magnitude of the ramp signal at the root of the block row, it is also possible to perform reading using the first gain and the second gain simultaneously.
[0054] In other words, the readout control unit 31 may control the first readout unit 26-1 to sequentially read out the pixel signals of a pixel block with a first gain, and the second readout unit 26-2 to sequentially read out the pixel signals of a pixel block different from the pixel block being read out by the first readout unit 26-1 at the same timing as the first readout unit 26-1, and with a second gain. Alternatively, the readout control unit 31 may control the second readout unit 26-2 to read out the pixel block read out by the first readout unit 26-1 with a first gain after a predetermined time, with a second gain.
[0055] Furthermore, in a configuration like circuit g530, where a single switch g532 is connected to the output of buffer g506 to switch it on and off, the effect of the switch's on-resistance is greater than in circuit g520.
[0056] (2) Switching the slope of the lamp signal As a variation of method (1), the image sensor 1 may be provided with an attenuator ATT (g541) at the input of the AD converter 25, as shown in the circuit g540 of Figure 15, and the slope of the lamp signal may be changed by switching the attenuation amount of the attenuator.
[0057] (3) Switching the capacitance of the FD Figure 16 shows an example of a circuit in which the gain is switched by switching the capacitance of the FD for each pixel according to this embodiment, as shown in Figure 6. The pixel 121 includes, for example, a PD-1 that performs photoelectric conversion, a transfer transistor TR-1 that transfers the charge stored in the PD, and FD (floating diffusion)-1(1) and FD-2 that store the transferred charge. The switching circuit 41A can realize a first gain and a second gain by switching the capacitance of the FD. That is, the first gain and the second gain are realized by varying the capacitance of the pixel block that stores the charge of the pixel. In the example of Figure 16, two FDs (FD-1(1) and FD-1(2)) are connected to PD-1. The switching circuit 41A may switch the gain by switching whether or not to connect FD-1(2) to FD-1(1), for example, in parallel. Note that the connection of FD-1(1) and FD-1(2) may be in series. In Figure 16, the comparator COMP, which performs analog-to-digital conversion by outputting the result of comparing the lamp voltage and the pixel signal, the control circuit 45 that controls the readout, and the memory 46 that stores the readout data all correspond to the readout unit 26. Furthermore, the on and off states of transistors RST and FDRST are controlled by the control circuit 45 to reset the charge accumulated in FD.
[0058] Alternatively, as shown in Figure 17, the capacitance may be switched by connecting the FD connected to the pixel 121 that is not being read to the FD that is being read. Figure 17 is a diagram showing an example of a circuit in which the gain is switched by connecting the FD connected to the pixel that is not being read to the FD that is being read according to this embodiment. In the example in Figure 17, it is assumed that PD-1 is being read and PD-n is not being read. In this case, the switching circuit 41B may switch the gain by switching whether or not to connect FD-n to FD-1, for example, in parallel. Note that the connection between FD-1 and FD-n may be in series. Also, in Figure 17, the control circuit etc. corresponds to the read unit 26.
[0059] (4) Controlling the storage time For example, the image sensor 1 may switch the storage time to achieve the first gain and the second gain by switching the reset period for each gain. The reset period is the RST ADC period in Figure 13. Figure 18 is a diagram illustrating an example of processing when the gain is switched by controlling the storage time according to this embodiment. In Figure 18, the horizontal axis is time, and the vertical axis is the position of the row being read in one block row. Line g601 is the readout with the first gain, and line g602 is the readout with the second gain.
[0060] It takes, for example, 8.04 ms to read one block row from top to bottom. The time difference between the second gain and the first gain is, for example, 240 μs. The total time of 8.04 ms and 240 μs is approximately 8.3 ms. In contrast, the exposure time is, for example, 240 μs. The ratio of 8.04 ms to 240 μs is approximately 30 dB (approximately 30 times). Focusing on this point, the image sensor 1 may change the gain without changing the capacitance of the FD or the slope of the lamp voltage by controlling the storage time. That is, the image sensor 1 may realize the first and second gains by varying the storage time to the capacitance that stores the charge of the pixels in the pixel block.
[0061] The four gain switching methods described above are just examples and are not limited to these.
[0062] As described above, in this embodiment, similar to the first embodiment, block rows are read out sequentially from top to bottom like a rolling shutter. Furthermore, in this embodiment, the pixel signals of the same block row are read out with two different gains. As a result, according to this embodiment, the phenomenon of jagged outlines of moving objects can be eliminated, similar to the first embodiment, and the dynamic range can be expanded by reading with two gains. In addition, in this embodiment as well, by using a block-shaped arrangement of AD converters 25 to perform pipeline operation, it is possible to read out pixel signals with multiple gains without reducing the frame rate. Furthermore, according to this embodiment, the readout speed of the present invention can be approximately twice as fast as the conventional method of reading out one pixel twice with a first gain and a second gain.
[0063] (Variations) In the example described above, an example using two gains was explained, but there may be three or more gains used for readout. The gains used by the image sensor 1 for readout may be, for example, a first gain, a second gain that is higher than the first gain, and a third gain that is intermediate between the first and second gains.
[0064] When reading with three gains in this way, for example, at time t2 in Figure 12, the image sensor 1 may start reading the pixel signal of the uppermost block row g421 of the pixel section 11 with the second gain, start reading the pixel signal of the second uppermost block row g422 of the pixel section 11 with the third gain, and start reading the pixel signal of the third uppermost block row g423 of the pixel section 11 with the first gain. In this embodiment, the time required to read out the pixel signal can be measured in the time of the number of vertical block row readouts + 2. That is, according to this embodiment, the time required to read out the pixel signal can be measured in the time of the number of vertical block row readouts + (type of gain - 1).
[0065] In this way, by reading out with three or more gains, the effect of quantization noise when switching between the first and second gains can be reduced.
[0066] <Example Configuration of Imaging Device> Here, an example configuration of an imaging device 700 equipped with the image sensor 1 of each embodiment will be described. Figure 19 is a diagram showing an example configuration of an imaging device according to an embodiment. As shown in Figure 19, the imaging device 700 includes, for example, an image sensor 1, an imaging optical system 701, an image processing unit 703, a work memory 704, an operation unit 705, a display unit 706, a control device 707, and a storage unit 708. Note that the configuration of the imaging device shown in Figure 19 is just an example and is not limited thereto.
[0067] The imaging optical system 701 is composed of multiple lenses and guides the light beam from the field of view to the image sensor 1. The imaging optical system 701 may be integrated with the imaging device 700, or it may be configured to be interchangeable with the imaging device 700. The imaging optical system 701 may also have a built-in focus lens or a built-in zoom lens.
[0068] The image processing unit 703 works in cooperation with the work memory 704 to perform image processing on the image data captured by the image sensor 1.
[0069] The work memory 704 temporarily stores, for example, image data before and after image compression, and is also used as a buffer memory for images captured by the image sensor 1.
[0070] The operation unit 705 detects the user's operation result and outputs it to the control device 707. The operation unit 705 is, for example, a touch panel sensor or mechanical switch provided on the display unit 706.
[0071] The display unit 706 is composed of, for example, a liquid crystal display panel, and displays images (still images, videos) and various information captured by the image sensor 1, as well as displaying an operation input screen.
[0072] The control device 707 is, for example, a CPU (Central Processing Unit) and controls each part. The control device 707 may also include a read control unit 31.
[0073] The memory unit 708 stores various data, such as image data acquired in response to an imaging instruction, on a storage medium such as a memory card.
[0074] Although embodiments for carrying out the present invention have been described above using examples, the present invention is not limited in any way to these embodiments, and various modifications and substitutions can be made without departing from the spirit of the present invention.
[0075] 1...Image sensor, 10...First semiconductor substrate, 20...Second semiconductor substrate, 11...Pixel section, 12...Pixel block group, 15, 15-1, ..., 15-m...Pixel block, 21...Control circuit section, 23...Peripheral circuit section, 25, 25-1, ..., 25-m...AD converter, 26, 26-1, ..., 26-m...Reading section, 27, 27-1, ..., 27-m...Memory / control circuit, 31...Reading control section, 121...Pixel, 700...Imaging device, 701...Imaging optical system, 703...Image processing section, 704...Work memory, 705...Operation section, 706...Display section, 707...Control device, 708...Storage section
Claims
1. A first substrate having a first photoelectric conversion unit that converts light into electric charge, a second photoelectric conversion unit that converts light into electric charge and is arranged in the column direction alongside the first photoelectric conversion unit, and a first pixel block that outputs a first signal based on the charge converted by the first photoelectric conversion unit and a second signal based on the charge converted by the second photoelectric conversion unit, and a second pixel block that has a third photoelectric conversion unit that converts light into electric charge and is arranged in the column direction alongside the first photoelectric conversion unit, and outputs a third signal based on the charge converted by the third photoelectric conversion unit; a second substrate that is laminated together with the first substrate and has a first signal processing block that is arranged opposite to the first pixel block and includes a first signal processing unit that performs signal processing on at least one of the first signal and the second signal, and a second signal processing block that is arranged opposite to the second pixel block and includes a second signal processing unit that performs signal processing on the third signal, An image sensor comprising: a control unit that controls the first timing at which the first signal is output from the first pixel block, the second timing at which the second signal is output from the first pixel block, and the third timing at which the third signal is output from the second pixel block, so that they occur in the order of the first timing, the second timing, and the third timing, wherein the second photoelectric conversion unit is positioned between the first photoelectric conversion unit and the third photoelectric conversion unit in the column direction, and is positioned such that the distance to the third photoelectric conversion unit is shorter than the distance to the first photoelectric conversion unit.
2. The image sensor according to claim 1, wherein the second pixel block includes a photoelectric conversion unit that converts light into electric charge and is arranged in the column direction alongside the first photoelectric conversion unit, and outputs a fourth signal based on the charge converted by the fourth photoelectric conversion unit, the second signal processing unit performs signal processing on at least one of the third signal and the fourth signal, the control unit controls the fourth timing at which the fourth signal is output from the second pixel block to be later than the first timing, and the fourth photoelectric conversion unit is arranged in the column direction between the second photoelectric conversion unit and the third photoelectric conversion unit, and is positioned such that the distance to the second photoelectric conversion unit is shorter than the distance to the third photoelectric conversion unit.
3. The image sensor according to claim 2, wherein the second photoelectric conversion unit is arranged adjacent to the fourth photoelectric conversion unit in the row direction.
4. The image sensor according to claim 1, wherein the control unit controls the first pixel block and the second pixel block such that the first timing, the second timing, and the third timing occur in the order of the first timing, the second timing, and the third timing during one frame period.
5. The image sensor according to claim 1, wherein the first signal processing block has a first conversion circuit that converts at least one of the first signal and the second signal into a digital signal, and the second signal processing block has a second conversion circuit that converts the third signal into a digital signal.
6. The image sensor according to claim 1, wherein the first signal processing block is positioned opposite to the first pixel block in the stacking direction in which the first substrate and the second substrate are stacked, and the second signal processing block is positioned opposite to the second pixel block in the stacking direction.
7. The image sensor according to claim 6, wherein the first signal processing block is positioned opposite to the first photoelectric conversion unit in the stacking direction, and the second signal processing block is positioned opposite to the third photoelectric conversion unit in the stacking direction.
8. The image sensor according to claim 1, comprising a first signal line on which at least one of the first signal and the second signal is output, and a second signal line on which the third signal is output.
9. The control unit is disposed on the second substrate, as described in claim 1.
10. The image sensor according to claim 1, wherein the control unit controls the first signal of the first photoelectric conversion unit to be read out two or more times within a frame period.
11. The image sensor according to claim 10, wherein the control unit controls the first signal of the first photoelectric conversion unit to be read out with a first gain and then read out with a second gain.
12. The image sensor according to claim 11, wherein the control unit controls the reading of the first signal from the first photoelectric conversion unit with the second gain, and then reading the second signal from the second photoelectric conversion unit with the first gain.
13. The image sensor according to claim 1, wherein the first pixel block has a first floating diffusion to which the charge converted by the first photoelectric conversion unit is transferred, and a second floating diffusion to which the charge converted by the first photoelectric conversion unit is transferred, and the control unit controls to output a signal based on the charge transferred to the first floating diffusion and a signal based on the charge transferred to the first floating diffusion and the second floating diffusion.
14. The image sensor according to claim 13, wherein the first pixel block includes a second floating diffusion to which the charge converted by the first photoelectric conversion unit is transferred, and a connection circuit that switches the connection between the first floating diffusion and the second floating diffusion.
15. The image sensor according to claim 14, wherein the control unit outputs the first signal in a state in which the first floating diffusion and the second floating diffusion are not connected, and in a state in which the first floating diffusion and the second floating diffusion are connected, during a one-frame period.
16. The image sensor according to claim 1, wherein the first signal processing block has a first conversion circuit that converts at least one of the first signal and the second signal into a digital signal, and the first conversion circuit is a single-slope type analog-to-digital converter.
17. The image sensor according to claim 16, wherein the first signal processing block comprises a first lamp circuit that supplies a first lamp signal whose voltage changes over time to the first conversion circuit, a second lamp circuit that supplies a second lamp signal whose voltage changes over time to the first conversion circuit, and a connection circuit that switches the connection between the first conversion circuit, the first lamp circuit, and the second lamp circuit.
18. The image sensor according to claim 17, wherein the control unit reads out the first signal in a state in which the first conversion circuit and the first lamp circuit are connected by the connection circuit, and in a state in which the first conversion circuit and the second lamp circuit are connected by the connection circuit, during a frame period.
19. The image sensor according to claim 1, wherein the first signal processing block includes a first conversion circuit that converts at least one of the first signal and the second signal into a digital signal, and an adjustment circuit that controls the amount of change in voltage with respect to time of a time-varying ramp signal received by the first conversion circuit.
20. The image sensor according to claim 19, wherein the control unit controls an adjustment circuit during a frame period to read out the first signal of the first photoelectric conversion unit with a first gain and a second gain.
21. The image sensor according to claim 1, wherein the control unit controls the output of a signal based on the charge converted by the first photoelectric conversion unit in a first period within a frame period and a signal based on the charge converted in a second period within a frame period.
22. An image sensor comprising: a first substrate having a first pixel block including a plurality of first photoelectric conversion units that convert light into electric charge, and a second pixel block including a plurality of second photoelectric conversion units that convert light into electric charge, and arranged in the column direction alongside the first pixel block; a second substrate laminated together with the first substrate, having a first signal processing block arranged at a position opposite to the first pixel block and including a first circuit unit electrically connected to the first pixel block, and a second signal processing block arranged at a position opposite to the second pixel block and including a second circuit unit electrically connected to the second pixel block; and a control unit that controls the sequence of the first period and the second period so that the first period and the second period are output from the first pixel block, respectively, for a first period in which signals based on the charges converted by the plurality of first photoelectric conversion units are output from the first pixel block.
23. The image sensor according to claim 22, wherein the first pixel block is arranged adjacent to the second pixel block in the column direction.
24. The image sensor according to claim 22, wherein the control unit controls the first pixel block and the second pixel block so that the first period and the second period occur in the order of the first period and the second period within one frame period.
25. The image sensor according to claim 22, wherein the first circuit unit converts signals based on the charges converted by each of the plurality of first photoelectric conversion units into digital signals, and the second circuit unit converts signals based on the charges converted by each of the plurality of second photoelectric conversion units into digital signals.
26. The image sensor according to claim 22, comprising: a first signal line on which signals based on charges converted by each of the plurality of first photoelectric conversion units are output; and a second signal line on which signals based on charges converted by each of the plurality of second photoelectric conversion units are output.
27. The image sensor according to claim 22, wherein the control unit controls the reading out of the signals based on the charge converted by each of the plurality of first photoelectric conversion units two or more times within a frame period.
28. The image sensor according to claim 27, wherein the control unit controls the signal based on the charge converted by each of the plurality of first photoelectric conversion units to be read out with a first gain and then read out with a second gain.
29. The image sensor according to claim 28, wherein the control unit reads out the signals based on the charges converted by each of the plurality of first photoelectric conversion units with the second gain, and then controls the control unit to read out the signals based on the charges converted by each of the plurality of second photoelectric conversion units with the first gain.
30. The image sensor according to claim 22, wherein the control unit controls the second signal processing block to perform signal processing on the signals based on the charges converted by the plurality of second photoelectric conversion units at the same timing as the first signal processing block performs signal processing on the signals based on the charges converted by the plurality of first photoelectric conversion units.
31. An imaging device comprising an image sensor according to any one of claims 1 to 30.
32. The imaging apparatus according to claim 31, further comprising a display unit that displays an image based on a signal output by the image sensor.