Overvoltage protection element

Abstract

An overvoltage protection element of the present invention comprises a semiconductor substrate having: a first groove and a second groove formed on a first main surface; a first well region that is of a first conductivity type and is embedded so as to surround the first groove; and a second well region that is of a second conductivity type and is embedded so as to surround the second groove. The overvoltage protection element further comprises: a first diffusion region that is of the second conductivity type and is embedded in an upper part of the first well region while contacting a side surface of the first groove; a second diffusion region that is of the first conductivity type and is embedded in an upper surface, of the first well region, located at a bottom surface of the first groove; a third diffusion region that is of the first conductivity type and is embedded in an upper part of the second well region while contacting a side surface of the second groove; and a fourth diffusion region that is of the second conductivity type and is embedded in an upper surface, of the second well region, located at a bottom surface of the second groove.

Description

Overvoltage protection element

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[0001] The present disclosure relates to an overvoltage protection element.

[0002] Conventionally, overvoltage protection elements have been used to protect subsequent ICs from unexpected surges caused by static electricity and power supply variations in semiconductor devices such as ICs (Integrated Circuits) and LSIs (Large Scale Integration). The overvoltage protection element includes an ESD (Electro-Static Discharge) protection element. The overvoltage protection element becomes a low-resistance state only when a surge voltage is applied and can safely pass (release) the surge current.

[0003] Examples of the types of overvoltage protection elements include diodes or thyristors such as transient voltage suppressors (TVS) diodes, and npn-type or pnp-type bipolar transistors.

[0004] Japanese Patent Application Laid-Open No. 2021-190531

[0005] [Summary] There is an increasing demand for an overvoltage protection element with a small area and high ESD tolerance. On the other hand, the overvoltage protection element using a thyristor had a configuration in which current flowed unidirectionally along the pnpn junction at breakdown.

[0006] An object of the present disclosure is to provide an overvoltage protection element that uses a thyristor, has a small area, and has a high ESD tolerance.

[0007] To solve the above-mentioned problems, an overvoltage protection element according to one aspect of the present disclosure comprises a semiconductor substrate having a first main surface extending in a first direction and a second direction intersecting the first direction, and a first groove and a second groove formed on the first main surface at a distance from each other. The overvoltage protection element further comprises a first well region of a first conductivity type embedded so as to surround the first groove in the first and second directions on the first main surface and in the depth direction of the semiconductor substrate perpendicular to the first main surface. The overvoltage protection element further comprises a first diffusion region of a second conductivity type embedded in the upper part of the first well region located on both sides of the first groove in the first direction, in contact with the side surface of the first groove. The overvoltage protection element further comprises a second diffusion region of a first conductivity type embedded on the upper surface of the first well region located at the bottom surface of the first groove, at a distance from the first diffusion region in the depth direction of the semiconductor substrate.

[0008] The overvoltage protection element further comprises a second well region of a second conductivity type, embedded in a manner that surrounds the second groove and is separated from the first well region in a first and second direction on the first main surface and in the depth direction of the semiconductor substrate. The overvoltage protection element further comprises a third diffusion region of a first conductivity type, embedded in the upper part of the second well region located on both sides of the second groove in the first direction, in contact with the side surface of the second groove. The overvoltage protection element further comprises a fourth diffusion region of a second conductivity type, embedded on the upper surface of the second well region located at the bottom surface of the second groove, separated from the third diffusion region in the depth direction of the semiconductor substrate.

[0009] The overvoltage protection element is arranged in contact with the side surfaces and bottom surface on both sides in the first direction of the first groove and further comprises a first contact electrically connected to the first diffusion region and the second diffusion region. The overvoltage protection element is arranged in contact with the side surfaces and bottom surface on both sides in the first direction of the second groove and further comprises a second contact electrically connected to the third diffusion region and the fourth diffusion region. The overvoltage protection element further comprises a first electrode electrically connected to the first contact and a second electrode electrically connected to the second contact. A first pnpn junction is formed by the arrangement of the first diffusion region, the first well region, the second well region and the third diffusion region, and a first pn junction is formed by the arrangement of the second well region and the first well region.

[0010] Figure 1A is a cross-sectional view of the main part of the overvoltage protection element according to the first embodiment. Figure 1B is a cross-sectional view of the main part of the overvoltage protection element according to the first embodiment. Figure 2 is a plan view of the main part of the overvoltage protection element according to the first embodiment. Figure 3 is a diagram showing the cross-section and current path of the overvoltage protection element according to the first embodiment. Figure 4 is a plan view of the overvoltage protection element according to the first embodiment. Figure 5 is a cross-sectional view of the main part of the overvoltage protection element according to the second embodiment. Figure 6A is a diagram showing the cross-section and current path of the overvoltage protection element according to the third embodiment. Figure 6B is a diagram showing the cross-section and current path of the overvoltage protection element according to the third embodiment. Figure 7 is a plan view of the overvoltage protection element according to the third embodiment. Figure 8 is a cross-sectional view of the main part of the overvoltage protection element according to the fourth embodiment. Figure 9A is a diagram showing the cross-section and current path of the overvoltage protection element according to the fourth embodiment. Figure 9B is a diagram showing the cross-section and current path of the overvoltage protection element according to the fourth embodiment. Figure 10 is a plan view of the overvoltage protection element according to the fourth embodiment. Figure 11A is a diagram showing the cross-section and current path of the overvoltage protection element according to the fifth embodiment. Figure 11B is a diagram showing the cross-section and current path of the overvoltage protection element according to the fifth embodiment. Figure 12 is a plan view of the overvoltage protection element according to the fifth embodiment.

[0011] [Detailed Description] The overvoltage protection elements relating to multiple embodiments will be described in detail below with reference to the drawings. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each part, etc., may differ from those in reality. Furthermore, it is also true that there are parts where the dimensional relationships or ratios differ between drawings.

[0012] The embodiments described below are general or specific examples. The numerical values, shapes, materials, components, installation locations, and connection configurations shown in the embodiments below are examples and are not intended to limit the scope of this disclosure. Furthermore, among the components in the embodiments below, those not described in the independent claim representing the highest-level concept will be described as optional components. In addition, the dimensional ratios in the drawings are exaggerated for illustrative purposes and may differ from actual ratios. Furthermore, the embodiments and their modifications below may include similar components, and similar components will be given the same reference numerals, and redundant descriptions will be omitted.

[0013] [First Embodiment] (Configuration of Overvoltage Protection Element) Figures 1A and 1B are cross-sectional views of the main part 100a of the overvoltage protection element 100 according to the first embodiment. Figure 1A is a cross-sectional view along the line IA-IA in the plan view of Figure 2, which will be described later, and Figure 1B is a cross-sectional view along the line IB-IB in Figure 2.

[0014] In the following explanation, we will use the XYZ coordinate system, which is an example of a Cartesian coordinate system. Specifically, the plane parallel to the first main surface 3a, which is the main surface of the semiconductor substrate 3 constituting the overvoltage protection element 100, will be defined as the XY plane, and the normal direction perpendicular to the XY plane, i.e., the direction perpendicular to the first main surface 3a, will be defined as the Z direction. Furthermore, the depth direction of the paper in Figure 1A will be defined as the second direction, the Y direction, and the direction perpendicular to the Y direction in the XY plane will be defined as the first direction, the X direction.

[0015] First, let's describe the cross-sectional view shown in Figure 1A. The overvoltage protection element 100 is configured on the upper surface of the semiconductor substrate 3. In the first embodiment, the semiconductor substrate 3 is a p-type semiconductor. However, the semiconductor substrate 3 may also be an intrinsic (i-type) semiconductor. When an i-type semiconductor is used, parasitic capacitance caused by junction capacitance can be reduced. Furthermore, the semiconductor substrate 3 may be silicon (Si), or it may be a semiconductor other than Si.

[0016] A first well region 11 of a first conductivity type and a second well region 12 of a second conductivity type are embedded on the upper surface of the semiconductor substrate 3, spaced apart from each other in the first direction, the X direction. The first and second conductivity types are opposite conductivity types. In the first embodiment, the first conductivity type is n type and the second conductivity type is p type. A first groove 21 is formed on a part of the upper surface of the first well region 11. In other words, the first well region 11 is arranged to surround the first groove 21 in the X and Y directions on the first main surface 3a and in the depth direction of the semiconductor substrate 3 perpendicular to the first main surface 3a. A second groove 22 is formed on a part of the upper surface of the second well region 12. In other words, the second well region 12 is arranged to surround the second groove 22 in the X and Y directions on the first main surface 3a and in the depth direction of the semiconductor substrate 3 perpendicular to the first main surface 3a.

[0017] On the upper part of the first well region 11 located on both sides of the first groove 21 in the X direction, the first diffusion regions 11b1 and 11b2 of the second conductivity type, which are p-type, are embedded in contact with the sides 21a1 and 21a2 of the first groove 21. On the upper surface of the first well region 11 located on the bottom surface 21b of the first groove 21, the second diffusion region 11a of the first conductivity type, which are n-type, are embedded, separated from the first diffusion regions 11b1 and 11b2 in the depth direction of the semiconductor substrate 3.

[0018] Third diffusion regions 12a1 and 12a2 of the first conductivity type are embedded in the upper part of the second well region 12 located on both sides of the second groove 22 in the X direction, in contact with the sides 22a1 and 22a2 of the second groove 22. Fourth diffusion region 12b of the second conductivity type is embedded on the upper surface of the second well region 12 located on the bottom surface 22b of the second groove 22, separated from the third diffusion regions 12a1 and 12a2 in the depth direction of the semiconductor substrate 3.

[0019] In Figure 1A, the side where the first well region 11 is located is referred to as the positive side in the X direction, and the side where the second well region 12 is located is referred to as the negative side in the X direction, with the midpoint between the first well region 11 and the second well region 12 in the X direction as the reference point. Hereafter, the same terminology will be used for different reference points in the X and Y directions.

[0020] A first contact 31 is positioned in the first groove 21 so as to be in contact with the side surfaces 21a1, 21a2 and the bottom surface 21b of the first groove 21. The first contact 31 is conductive and is electrically connected to the first diffusion regions 11b1, 11b2 and the second diffusion region 11a. A second contact 32 is positioned in the second groove 22 so as to be in contact with the side surfaces 22a1, 22a2 and the bottom surface 22b of the second groove 22. The second contact 32 is conductive and is electrically connected to the third diffusion regions 12a1, 12a2 and the fourth diffusion region 12b.

[0021] In Figure 1A, the first contact 31 and the second contact 32 each have a portion located inside the first groove 21 and the second groove 22, i.e., a portion located at a height less than or equal to the surface height of the first main surface 3a, and a portion located on the first main surface 3a. The portions located inside the first groove 21 and the second groove 22 are sometimes referred to as trench contacts, and the portions located on the first main surface 3a are sometimes referred to as contacts. Unlike in Figure 1A, the first contact 31 and the second contact 32 may each include only the trench contact portions located inside the first groove 21 and the second groove 22, and the contact portions located on the first main surface 3a may be included in the wiring layers 41 and 42 described below.

[0022] A wiring layer 41 is positioned above the first contact 31 in the Z direction, in contact with the upper surface of the first contact 31, and a wiring layer 42 is positioned above the second contact 32, in contact with the upper surface of the first contact 31. The wiring layers 41 and 42 each include a first layer of metal wiring, M1 wiring, a second layer of metal wiring, M2 wiring, and contacts connecting the M1 and M2 wirings, and are conductive.

[0023] In Figure 1A, an insulating film 71 is placed in the region from the first main surface 3a of the semiconductor substrate 3 up to the height of the upper surfaces of the wiring layers 41 and 42, where the first contact 31, the second contact 32, and the wiring layers 41 and 42 are not present. The insulating film 71 is an interlayer insulating film and plays a role in insulating the wirings in the multilayer wiring structure of the overvoltage protection element 100. In addition, an insulating film 72 is placed on the upper surfaces of the wiring layers 41 and 42 and the insulating film 71. The insulating film 72 coats the surface of the overvoltage protection element 100 and acts as a protective film to prevent influence from the external environment and adhesion of contaminants.

[0024] The first contact 31 and the wiring layer 41 are electrically connected to form the first electrode T1. The first electrode T1 is electrically connected to the first diffusion regions 11b1, 11b2 and the second diffusion region 11a. The second contact 32 and the wiring layer 42 are electrically connected to form the second electrode T2. The second electrode T2 is electrically connected to the third diffusion regions 12a1, 12a2 and the fourth diffusion region 12b. Although not shown in Figure 1A, an opening region is provided on the upper surface of each of the wiring layers 41 and 42 where the insulating film 72 is not placed, at a position different from the cross-sectional position shown in Figure 1A. In the opening region provided on the upper surface of the wiring layers 41 and 42, the first electrode T1 and the second electrode T2 can be electrically connected to a terminal provided outside the overvoltage protection element 100.

[0025] In the cross-sectional structure described above, the first pnpn junction 1, which is a thyristor, is formed by the arrangement of the first diffusion regions 11b1, 11b2, the first well region 11, the second well region 12, and the third diffusion regions 12a1, 12a2. Here, an i-type semiconductor may be used as the semiconductor substrate 3, and the first pnpn junction 1 may include a p-n-i-p-n junction. Furthermore, the first pn junction 2, which is a diode, is formed by the arrangement of the second well region 12 and the first well region 11. Here, an i-type semiconductor may be used as the semiconductor substrate 3, and the first pn junction 2 may constitute a PIN diode.

[0026] Next, we will describe the cross-sectional view shown in Figure 1B. Parts identical to those in Figure 1A are denoted by the same reference numerals, and their descriptions are omitted.

[0027] Compared to Figure 1A, Figure 1B differs in the following respects. In Figure 1B, a connection region 132 is positioned between the first well region 11 and the second well region 12, connecting the first well region 11 and the second well region 12. In this embodiment, the connection region 132 is a second conductivity type, which is p-type, and the resistivity of the connection region 132 is set lower than the resistivity of the semiconductor substrate 3. A structure in which a low-resistivity connection region 132 is positioned on the first pnpn junction 1, which is a thyristor, will be referred to as a trigger diode. Also, in Figure 1B, the width of the first well region 11 in the X direction is wider than in Figure 1A on the side connected to the connection region 132.

[0028] Figure 2 is a plan view of the main part 100a of the overvoltage protection element 100 according to the first embodiment, viewed from the direction normal to the first main surface 3a. Figure 1A, mentioned above, is a cross-sectional view along the line IA-IA in Figure 2, and Figure 1B, mentioned above, is a cross-sectional view along the line IB-IB in Figure 2. In Figure 2, for the sake of understanding, the first contact 31, the second contact 32, the wiring layers 41, 42, and the insulating films 71, 72 are omitted from the illustration, and the first groove 21, the second groove 22, the well region and the diffusion region arranged on the upper surface of the semiconductor substrate 3 are shown.

[0029] In Figure 2, a first well region 11 and a second well region 12 are arranged on the first main surface 3a of the semiconductor substrate 3, extending along the Y direction. A first groove 21 is formed on the upper surface of the first well region 11, and a second groove 22 is formed on the upper surface of the second well region 12, both extending along the Y direction.

[0030] First diffusion regions 11b1 and 11b2 are arranged on the upper surfaces of the first well regions 11 on both sides in the X direction of the first groove 21, extending along the Y direction. The first diffusion region 11b1 is in contact with the side surface 21a1 of the first groove 21, and the first diffusion region 11b2 is in contact with the side surface 21a2. A second diffusion region 11a is arranged on the upper surface of the first well region 11 located at the bottom of the first groove 21, extending along the Y direction. Third diffusion regions 12a1 and 12a2 are arranged on the upper surfaces of the second well regions 12 on both sides in the X direction of the second groove 22, extending along the Y direction. The third diffusion region 12a1 is in contact with the side surface 22a1 of the second groove 22, and the third diffusion region 12a2 is in contact with the side surface 22a2. A fourth diffusion region 12b is arranged on the upper surface of the second well region 12 located at the bottom of the second groove 22, extending along the Y direction.

[0031] As described above with reference to Figure 1A, the first diffusion regions 11b1, 11b2 and the second diffusion region 11a are spaced apart in the depth direction of the semiconductor substrate 3. Therefore, when viewed from the direction normal to the first main surface 3a, the spacing in the X direction between the first diffusion regions 11b1, 11b2 and the second diffusion region 11a, and the spacing in the X direction between the third diffusion regions 12a1, 12a2 and the fourth diffusion region 12b are unnecessary. This makes it possible to reduce the length in the X direction of the first well region 11, the second well region 12, and the semiconductor substrate 3, and to reduce the area of ​​each junction and the parasitic capacitance.

[0032] As described above with reference to Figure 1B, the overvoltage protection element 100 includes a connection region 132 of the second conductivity type at the position of the IB-IB line, and further includes connection regions 131 and 133 at different positions in the Y direction from the IB-IB line. As shown in Figure 2, by providing a connection region in a part of the semiconductor substrate 3 between the first well region 11 and the second well region 12, parasitic capacitance can be suppressed while lowering the breakdown voltage of the overvoltage protection element 100, which will be described later with reference to Figure 3, to an appropriate value.

[0033] As shown in Figure 2, the positions of the connection regions 131, 132, and 133 in the Y direction are different for each adjacent pair of first and second well regions, and are arranged so that they are the same every other well region. By arranging the connection regions in this manner, the positions of the current paths in the Y direction can be distributed, thereby improving the withstand voltage.

[0034] Furthermore, the width of the first well region 11 in the X direction is such that the side connecting to the connection regions 132 and 133 is relatively wider near the point of connection with the connection regions 132 and 133, and relatively narrower in the portion further away from the point of connection with the connection regions 132 and 133.

[0035] By arranging the connection region, the current that dissipates overvoltage surges mainly flows through the connection region with low resistivity. The current flowing through the portion of the first well region 11 that is far from the vicinity of the portion in contact with the connection regions 132 and 133 is relatively small. Therefore, even if the width of the first well region 11 in the X direction is made relatively narrower in the portion far from the vicinity of the portion in contact with the connection regions 132 and 133, the current dissipation capacity and withstand voltage do not decrease significantly. On the other hand, by making the width of the first well region 11 in the X direction relatively narrower in the portion far from the vicinity of the portion in contact with the connection regions 132 and 133, the area of ​​the first well region 11 can be reduced, and parasitic capacitance caused by junction capacitance can be reduced.

[0036] Figure 3 shows a cross-section and current path of the overvoltage protection element 100 according to the first embodiment. The overvoltage protection element 100 in Figure 3 is constructed by arranging two of the main parts 100a of the overvoltage protection element 100 described with reference to Figures 1A and 2 on the same semiconductor substrate 3 and connecting their second electrodes T2 together.

[0037] In Figure 3, one of the main components 100a from Figure 1A is positioned on the positive side with reference to the center in the X direction of Figure 3. Additionally, one of the main components 100a from Figure 1A is positioned on the negative side in the X direction of Figure 3, by reversing the axis of symmetry with the end on the side where the second well region 12 is located in the X direction of Figure 1A. The main component 100a positioned on the positive side in the X direction of Figure 3 is referred to as the first overvoltage protection element 100aU, and the main component 100a positioned on the negative side in the X direction is referred to as the second overvoltage protection element 100aL. For ease of understanding, the M2 wiring among the wiring layers 41 and 42, the contacts connecting the M1 wiring and the M2 wiring, and the insulating films 71 and 72 positioned at a height greater than or equal to the height of the upper surface of the M1 wiring are omitted from the illustration.

[0038] The components of the first overvoltage protection element 100aU are denoted with the letter "U," and the components of the second overvoltage protection element 100aL are denoted with the letter "L," thereby distinguishing the components of the first overvoltage protection element 100aU from those of the second overvoltage protection element 100aL. However, the actual configuration of each is the same as that of Figure 1A. The points that are the same as those in Figure 1A will not be explained.

[0039] In the overvoltage protection element 100 shown in Figure 3, the second electrode T2U of the first overvoltage protection element 100aU and the second electrode T2L of the second overvoltage protection element 100aL are connected by a connecting electrode made of metal wiring (not shown). A first voltage V1 is input to the first electrode T1U of the first overvoltage protection element 100aU, and a second voltage V2 is input to the first electrode T1L of the second overvoltage protection element 100aL. Each of the first overvoltage protection element 100aU and the second overvoltage protection element 100aL has unidirectional polarity, meaning that the direction of the voltage of the overvoltage surge that can be protected is unidirectional. In Figure 3, bidirectional polarity is achieved by connecting the second electrodes T2 of each element and inputting voltage to the first electrodes T1 of each element.

[0040] When the first voltage V1 is lower than the second differential voltage relative to the second voltage V2, and the second voltage V2 is lower than the second differential voltage relative to the first voltage V1, no current flows between the first electrode T1U and the first electrode T1L of the overvoltage protection element 100. Here, the second differential voltage may be in the range of 5V to 120V, for example. Furthermore, the second differential voltage may be in the range of 8V to 12V.

[0041] When the first voltage V1 becomes higher than the second differential voltage relative to the second voltage V2, the voltage at the first electrode T1U becomes higher than the voltage at the second electrode T2U relative to the first differential voltage, and a voltage equal to the second differential voltage minus the first differential voltage is applied between the second electrode T2L and the first electrode T1L. As will be described later, the voltage between the second electrode T2L and the first electrode T1L is the forward voltage of the diode and is small compared to the second differential voltage, so the first differential voltage accounts for a large proportion of the second differential voltage. The first differential voltage may be in the range of 5V to 120V, for example, or in the range of 8V to 12V.

[0042] When the voltage at the first electrode T1U becomes higher than the voltage at the second electrode T2U by a first differential voltage, a voltage equal to or greater than the breakdown voltage or breakover voltage is applied to the first pnpn junction 1U, which is a thyristor of the first overvoltage protection element 100aU. As a result, current flows from the first electrode T1U to the second electrodes T2U and T2L along the path indicated by the solid arrow in Figure 3. Hereafter, the breakdown voltage and breakover voltage will be collectively referred to as the breakdown voltage.

[0043] In this case, although not shown in Figure 3, a fourth well region 16U of the second conductivity type may be located on the positive side in the X direction of the first well region 11U, in which case current can flow from the first well region 11U to the fourth well region 16U. Also, although not shown in Figure 3, a third well region 13U of the first conductivity type may be located on the negative side in the X direction of the second well region 12U, in which case current can flow from the third well region 13U to the second well region 12U. In other words, the current flowing through each well region can flow in both the positive and negative directions in the X direction.

[0044] A voltage substantially equal to the voltage obtained by subtracting the first differential voltage from the second differential voltage described above is applied to the first pn junction 2L, which is a diode of the second overvoltage protection element 100aL, and a forward voltage equal to or higher than the voltage at which the first pn junction 2L turns on is applied. Therefore, the current flowing from the first electrode T1U of the first overvoltage protection element 100aU through the first pnpn junction 1U to the second electrodes T2U and T2L flows through the first pn junction 2L of the second overvoltage protection element 100aL and then to the first electrode T1L.

[0045] At this time, although not shown in FIG. 3, a third well region 13L of the first conductivity type may be disposed on the positive side in the X direction of the second well region 12L of the second overvoltage protection element 100aL. In that case, current can also flow from the second well region 12L to the third well region 13L. Also, although not shown in FIG. 3, a fourth well region 16L of the second conductivity type may be disposed on the negative side in the X direction of the first well region 11L. In that case, current can also flow from the fourth well region 16L to the first well region 11L. That is, the current flowing through each well region can flow in both the positive and negative directions in the X direction.

[0046] As described above, when the first voltage V1 becomes higher than the second voltage V2 by the second differential voltage or more, current flows from the first electrode T1U of the first overvoltage protection element 100aU to the first electrode T1L of the second overvoltage protection element 100aL along the path indicated by the solid arrow in FIG. 3.

[0047] On the other hand, when the second voltage V2 becomes higher than the first voltage V1 by a second differential voltage or more, current flows from the first electrode T1L of the second overvoltage protection element 100aL to the first electrode T1U of the first overvoltage protection element 100aU through the path indicated by the dashed arrow in FIG. 3. Specifically, when the second voltage V2 becomes higher than the first voltage V1 by a second differential voltage or more, the voltage of the first electrode T1L becomes higher than the voltage of the second electrode T2L by a first differential voltage or more. Then, a voltage equal to or higher than the breakdown voltage is applied to the first pnpn junction 1L of the second overvoltage protection element 100aL, and current flows from the first electrode T1L to the second electrodes T2L and T2U through the path indicated by the dashed arrow in FIG. 3. Since it is the same as the case where the first voltage V1 becomes higher than the second voltage V2 by a second differential voltage or more, detailed description is omitted, but the current flowing through each well region can flow in both the positive and negative directions in the X direction.

[0048] A forward voltage equal to or higher than the voltage at which the first pn junction 2U of the first overvoltage protection element 100aU turns on is applied to the first pn junction 2U. Therefore, the current flowing from the first electrode T1L of the second overvoltage protection element 100aL to the second electrodes T2L and T2U through the first pnpn junction 1L flows through the first pn junction 2U of the first overvoltage protection element 100aU and then to the first electrode T1U.

[0049] As described above, when the first voltage V1 input to the first electrode T1U becomes higher than the second voltage V2 input to the first electrode T1L by a second differential voltage or more, the overvoltage protection element 100 discharges the overvoltage input to the first electrode T1U to the first electrode T1L. Further, when the second voltage V2 input to the first electrode T1L becomes higher than the first voltage V1 input to the first electrode T1U by a second differential voltage or more, the overvoltage protection element 100 discharges the overvoltage input to the first electrode T1L to the first electrode T1U. Thus, the overvoltage protection element 100 protects the input terminal of the IC or LSI connected to the subsequent stage of the overvoltage protection element 100 from overvoltage.

[0050] As mentioned above, the current that dissipates the overvoltage in the overvoltage protection element 100 flows in both the positive and negative directions in the X direction of the well region. Therefore, compared to the case where the current that dissipates the overvoltage flows in one direction, the overvoltage can be dissipated in a shorter time, and the ESD withstand capability can be improved.

[0051] Furthermore, in the first pnpn junctions 1U and 1L, which are thyristors of the overvoltage protection element 100, current flows in a direction parallel to the first main surface 3a at the depth of the diffusion region located on the side surface of the trench contacts of the first contact 31U and the second contact 32U. In the first pn junctions 2U and 2L, which are diodes, current flows in a direction parallel to the first main surface 3a at the depth of the diffusion region located on the bottom surface of the trench contacts of the first contact 31U and the second contact 32U. In other words, the thyristor and diode can be formed at the same position in the X direction but at different depths. Therefore, compared to forming the thyristor and diode at different positions in the X direction of the first main surface 3a, the volume occupied by the overvoltage protection element can be reduced, and the parasitic capacitance connected to the signal line and manufacturing costs can be reduced. In addition, the current path can be shortened to reduce the overall resistance and improve the forward characteristics.

[0052] Figure 4 is a plan view of the overvoltage protection element 100 according to the first embodiment. In Figure 4, for ease of understanding, the first contact 31, the second contact 32, the wiring layers 41, 42, and the insulating films 71, 72 are omitted from the illustration. Figure 4 shows the first groove 21, the second groove 22, the well region and the diffusion region, and the power supply wiring that supplies power to them, which are arranged on the upper surface of the semiconductor substrate 3. The power supply wiring 81 and 82 are composed of M2 wiring. Although not shown in Figure 4, the power supply wiring 81 is connected to the wiring layer 41U of the first electrode T1U in Figure 3, and the power supply wiring 82 is connected to the wiring layer 42U of the second electrode T2U in Figure 3.

[0053] Figure 2, mentioned above, shows the region indicated by the main part 100a in Figure 4. Also, the first overvoltage protection element 100aU in Figure 3 is located in the region sandwiched between the power supply wirings 81 and 82 in Figure 4. In Figure 4, the second overvoltage protection element 100aL in Figure 3 is located in the region opposite to the first overvoltage protection element 100aU with respect to the power supply wiring 82, with the first overvoltage protection element 100aU inverted in the Y direction with respect to the power supply wiring 82 as the axis of symmetry. However, the arrangement shown in Figure 4 is just one example, and the second overvoltage protection element 100aL may be located in the same Y direction as the first overvoltage protection element 100aU, but with a different position in the X direction, without being inverted in the Y direction.

[0054] As shown in Figure 4, the first overvoltage protection element 100aU has a fourth well region 16U on the positive side in the X direction of the first well region 11U, and a third well region 13U on the negative side in the X direction of the second well region 12U. The first well region 11U and the third well region 13U are connected to a common well region 11cU on the side of the power supply wiring 81, and although not shown in Figure 4, the well region 11cU is connected to the power supply wiring 81. The second well region 12U and the fourth well region 16U are connected to a common well region 12cU on the side of the power supply wiring 82, and although not shown in Figure 4, the well region 12cU is connected to the power supply wiring 82.

[0055] The second overvoltage protection element 100aL includes a fourth well region 16L on the positive side in the X direction of the first well region 11L, and a third well region 13L on the negative side in the X direction of the second well region 12L. The second well region 12L and the fourth well region 16L are connected to a common well region 12cL on the side of the power supply wiring 82, and although not shown in Figure 4, the well region 12cL is connected to the power supply wiring 82. Although not shown in Figure 4, the first well region 11L and the third well region 13L are connected to a common well region 11cL.

[0056] As described above with reference to Figures 3 and 4, the overvoltage protection element 100 according to the first embodiment allows for a reduction in the area of ​​the first well region 11 by, for example, 50% compared to the case where both the first pnpn junction 1 and the first pn junction 2 are formed on the upper surface of the semiconductor substrate 3. This reduces the volume occupied by the overvoltage protection element, thereby reducing parasitic capacitance connected to the signal line and manufacturing costs. Furthermore, the length of the current path of the first pn junction 2 can be reduced by, for example, 35%. This reduces the overall resistance and improves the forward characteristics.

[0057] (Effects of the first embodiment) With the overvoltage protection element 100, since the diffusion regions of different conductivity types are spaced apart in the depth direction, spacing in the X direction is unnecessary, and the width of the first well region 11 and the second well region 12 in the X direction can be reduced. In addition, the thyristor and diode can be placed in locations that are at the same position in the X direction but at different depths. As a result, the volume occupied by the overvoltage protection element can be reduced, parasitic capacitance connected to the signal line and manufacturing costs can be reduced, and the current path can be shortened to reduce the overall resistance and improve the forward characteristics. Furthermore, with the overvoltage protection element 100, since the current that dissipates the overvoltage flows in both directions in the X direction of the well region, the overvoltage can be dissipated in a shorter time and the ESD withstand capability can be improved.

[0058] The overvoltage protection element 100 allows the breakdown voltage to be set to an appropriate value while suppressing parasitic capacitance by providing a connection region 132 in a part of the semiconductor substrate 3 between the first well region 11 and the second well region 12. In the overvoltage protection element 100, the connection regions 131, 132, and 133 are arranged such that their positions in the Y direction differ from each other between adjacent pairs of well regions, and are the same every other time. The overvoltage protection element 100 allows the breakdown voltage to be improved by distributing the positions of the current paths in the Y direction. The overvoltage protection element 100 allows the width of the first well region 11 in the X direction to be made relatively narrower in the parts away from the vicinity of the parts in contact with the connection regions 132 and 133, thereby reducing parasitic capacitance caused by junction capacitance.

[0059] [Second Embodiment] (Configuration of Overvoltage Protection Element) Figure 5 is a cross-sectional view of the main part 101a of the overvoltage protection element 101 according to the second embodiment. The same reference numerals are used for the same parts as the main part 100a of the overvoltage protection element 100 according to the first embodiment shown in Figure 1A, and their descriptions are omitted.

[0060] Compared to Figure 1A, Figure 5 differs in the following respects. In Figure 5, third diffusion regions 12b1 and 12b2 of the second conductivity type, which are p-type, are embedded in the upper part of the second well region 12 located on both sides of the second groove 22 in the X direction, while in contact with the sides 22a1 and 22a2 of the second groove 22. In addition, a fourth diffusion region 12a of the first conductivity type, which are n-type, are embedded on the upper surface of the second well region 12 located on the bottom surface 22b of the second groove 22, separated from the third diffusion regions 12b1 and 12b2 in the depth direction of the semiconductor substrate 3.

[0061] In Figure 5, the first pnpn junction 1, which is a thyristor, is formed by the arrangement of the first diffusion regions 11b1, 11b2, the first well region 11, the second well region 12, and the fourth diffusion region 12a. In addition, the first pn junction 2, which is a diode, is formed by the arrangement of the second well region 12 and the first well region 11.

[0062] In the cross-sectional view shown in Figure 1A, the depths in the Z direction from the first main surface 3a are different for the first diffusion regions 11b1 and 11b2 and the fourth diffusion region 12b of the second conductivity type, which is p-type, and the depths in the Z direction are different for the second diffusion region 11a and the third diffusion regions 12a1 and 12a2 of the first conductivity type, which is n-type. Therefore, the first diffusion regions 11b1 and 11b2 and the fourth diffusion region 12b of the second conductivity type are formed by separate impurity injection processes, and the second diffusion region 11a and the third diffusion regions 12a1 and 12a2 of the first conductivity type are formed by separate impurity injection processes.

[0063] On the other hand, in the cross-sectional view shown in Figure 5, the first diffusion regions 11b1 and 11b2 and the third diffusion regions 12b1 and 12b2 of the second conductivity type, which are p-type, are both embedded in the upper surface of the semiconductor substrate 3, and their depth in the Z direction from the first main surface 3a is the same. Also, the second diffusion region 11a and the fourth diffusion region 12a of the first conductivity type, which are n-type, are both embedded in the upper surface of the well region located at the bottom of the first contact 31 and the second contact 32, and their depth in the Z direction from the first main surface 3a is the same.

[0064] Therefore, the first diffusion regions 11b1, 11b2 and the third diffusion regions 12b1, 12b2 of the second conductivity type can be formed by the same impurity implantation process, and the second diffusion region 11a and the fourth diffusion region 12a of the first conductivity type can be formed by the same impurity implantation process. Compared with Figure 1A, the overvoltage protection element 101 equipped with the main part 101a shown in Figure 5 can reduce the number of layers for forming the diffusion regions by two, and the manufacturing process can be reduced by two steps. This reduces manufacturing costs.

[0065] In the cross-sectional view shown in Figure 5, the depth in the Z direction from the first main surface 3a of the bottom surfaces of the second diffusion region 11a and the fourth diffusion region 12a of the first conductivity type may be about 1.0 μm to 1.5 μm. On the other hand, the distance in the X direction between the first diffusion region 11b2 and the third diffusion region 12b1 of the second conductivity type may be about 15 μm. Compared with Figure 1A, in Figure 5, the depth direction distance between the first diffusion regions 11b1, 11b2 and the fourth diffusion region 12a is added to the current path of the first pn junction 1, which is a thyristor. Also, the depth direction distance between the second diffusion region 11a and the third diffusion regions 12b1, 12b2 is added to the current path of the first pn junction 2, which is a diode. However, as mentioned above, the depth direction distance is sufficiently small compared to the distance in the X direction, and the current path is still short, so the overall resistance can be reduced and the forward characteristics can be improved.

[0066] (Effects of the second embodiment) The overvoltage protection element 101 reduces the volume occupied by the overvoltage protection element, reduces parasitic capacitance connected to the signal line and manufacturing costs, shortens the current path to reduce the overall resistance and improves forward characteristics. Furthermore, the overvoltage protection element 101 allows the current that escapes overcurrent to flow in both directions in the X direction of the well region, thereby improving ESD withstand capability. The overvoltage protection element 101 reduces the number of layers and manufacturing processes required to form the diffusion region, thereby reducing manufacturing costs.

[0067] [Third Embodiment] (Configuration of Overvoltage Protection Element) Figures 6A and 6B show the cross-section and current path of the overvoltage protection element 102 according to the third embodiment. Although Figures 6A and 6B are separated for the sake of space, they are arranged on the same semiconductor substrate 3 and connected at connection point A. Figure 6A is a cross-sectional view along the line VI1-VI2 in the plan view of Figure 7, which will be described later, and Figure 6B is a cross-sectional view along the line VI4-VI3 in Figure 7. The overvoltage protection element in Figure 6A will be referred to as the first overvoltage protection element 102aU, and the overvoltage protection element in Figure 6B will be referred to as the second overvoltage protection element 102aL. The same reference numerals are used for parts that are the same as those in the cross-section of the overvoltage protection element 100 according to the first embodiment shown in Figure 3, and their explanation is omitted.

[0068] Compared to the first overvoltage protection element 100aU in Figure 3, the first overvoltage protection element 102aU in Figure 6A differs in the following respects. In Figure 6A, a third well region 14U of p-type, second conductivity is embedded on the positive side in the X direction of the first well region 11U, separated from the first well region 11U and the second well region 12U. A fifth diffusion region 14bU of second conductivity is embedded in a part of the upper surface of the third well region 14U. Also, a fourth well region 15U of n-type, first conductivity is embedded on the positive side in the X direction of the third well region 14U, separated from the first well region 11U, the second well region 12U, and the third well region 14U. A sixth diffusion region 15aU of first conductivity is embedded in a part of the upper surface of the fourth well region 15U.

[0069] The fifth diffusion region 14bU is electrically connected to the second electrode T2U, and the sixth diffusion region 15aU is electrically connected to the first electrode T1U. The arrangement of the third well region 14U and the fourth well region 15U constitutes the second pn junction 5U.

[0070] Figure 6B is obtained by inverting Figure 6A in the X direction, using the negative end in the X direction where connection point A is located as the axis of symmetry, and changing the letter added to the end of the reference numerals of the constituent members from "U" to "L". The substantial configuration of Figure 6B is the same as that of Figure 6A, and the points that are the same as those of Figure 6A will not be explained. Similar to Figure 6A, in Figure 6B, the second pn joint 5L is formed by the arrangement of the third well region 14L and the fourth well region 15L.

[0071] In the overvoltage protection elements 102 shown in Figures 6A and 6B, the second electrode T2U of the first overvoltage protection element 102aU and the second electrode T2L of the second overvoltage protection element 102aL are connected by metal wiring (not shown). A first voltage V1 is input to the first electrode T1U of the first overvoltage protection element 102aU, and a second voltage V2 is input to the first electrode T1L of the second overvoltage protection element 102aL. Although the first overvoltage protection element 102aU and the second overvoltage protection element 102aL each have unidirectional polarity, bidirectional polarity is achieved by connecting their respective second electrodes T2 and inputting voltage to their respective first electrodes T1.

[0072] When the first voltage V1 is lower than the second differential voltage relative to the second voltage V2, and the second voltage V2 is lower than the second differential voltage relative to the first voltage V1, no current flows between the first electrode T1U and the first electrode T1L of the overvoltage protection element 102.

[0073] When the first voltage V1 becomes higher than or equal to the second differential voltage V2, current flows from the first electrode T1U of the first overvoltage protection element 102aU to the first electrode T1L of the second overvoltage protection element 100aL, along the path indicated by the solid arrows in Figures 6A and 6B.

[0074] Specifically, when the first voltage V1 becomes higher than the second differential voltage relative to the second voltage V2, the voltage at the first electrode T1U becomes higher than the first differential voltage relative to the voltage at the second electrode T2U. Here, the first and second differential voltages may be in the range of 5V to 120V, for example, or in the range of 8V to 12V. Then, a voltage of equal to or greater than the breakdown voltage is applied to the first pnpn junction 1U, which is a thyristor, and current flows from the first electrode T1U to the second electrodes T2U and T2L in the paths shown by the solid arrows in Figures 6A and 6B. As explained with reference to Figure 3, the current can flow in both the positive and negative directions in the X direction of the second well regions 12U and 12L, respectively.

[0075] In Figure 6B, a first pn junction 2L and a second pn junction 5L, which are diodes, are connected in parallel between the second electrode T2L and the first electrode T1L. Similar to Figure 3, a forward voltage greater than or equal to the voltage at which the first pn junction 2L turns on is applied to the first pn junction 2L in Figure 6B. Also in Figure 6B, a forward voltage greater than or equal to the voltage at which the second pn junction 5L turns on is applied to the second pn junction 5L. Therefore, the current that flows from the first electrode T1U of the first overvoltage protection element 102aU through the first pnpn junction 1U to the second electrode T2L flows through the first pn junction 2L and the second pn junction 5L of the second overvoltage protection element 102aL to the first electrode T1L. Since a forward current can flow in parallel between the first pn junction 2L and the second pn junction 5L, the forward characteristics can be improved.

[0076] On the other hand, when the second voltage V2 becomes higher than the second differential voltage relative to the first voltage V1, current flows from the first electrode T1L of the second overvoltage protection element 102aL to the first electrode T1U of the first overvoltage protection element 102aU, along the path indicated by the dashed arrows in Figures 6A and 6B. A detailed explanation is omitted as this is the same as when the first voltage V1 becomes higher than the second differential voltage relative to the second voltage V2, but since a forward current can be passed in parallel between the first pn junction 2U and the second pn junction 5U, the forward characteristics can be improved.

[0077] Figure 7 is a plan view of the overvoltage protection element 102 according to the third embodiment. The same reference numerals are used for parts identical to those in the plan view of the overvoltage protection element 100 according to the first embodiment shown in Figure 4, and their descriptions are omitted.

[0078] Figure 6A, mentioned above, shows a cross-section along the line VI1-VI2 in Figure 7, and Figure 6B, mentioned above, shows a cross-section along the line VI4-VI3 in Figure 7. Compared with Figure 4, Figure 7 differs in the following respects. In Figure 7, a second pn junction 5U, including a third well region 14U and a fourth well region 15U, is located on the positive X-side of a first pnpn junction 1U, including a first well region 11U. Also, a second pn junction 5L, including a third well region 14L and a fourth well region 15L, is located on the positive X-side of a first pnpn junction 1L, including a first well region 11L.

[0079] Similar to Figure 4, in Figure 7, the first well region 11U is connected to the well region 11cU that extends in the X direction on the side of the power supply wiring 81, and is connected to the power supply wiring 81, although it is not shown in Figure 7. Also, the fourth well region 15U is connected to the well region 11dU that extends in the X direction on the side of the power supply wiring 81, and is connected to the power supply wiring 81, although it is not shown in Figure 7. In other words, the well region 11cU of the first pnpn junction 1U and the well region 11dU of the second pn junction 5U are electrically connected by the power supply wiring 81. The well region 11cU and the well region 11dU may be directly connected without being separated in the X direction.

[0080] The second well region 12U is connected to the well region 12cU that extends in the X direction on the side of the power supply wiring 82, and is connected to the power supply wiring 82, although it is not shown in Figure 4. Similarly, the third well region 14U is connected to the well region 12dU that extends in the X direction on the side of the power supply wiring 82, and is connected to the power supply wiring 82, although it is not shown in Figure 7. In other words, the well region 12cU of the first pnpn junction 1U and the well region 12dU of the second pn junction 5U are electrically connected by the power supply wiring 82. The well region 12cU and the well region 12dU may be directly connected without being separated in the X direction.

[0081] As shown in Figure 7, a second pn junction 5U may also be arranged on the negative side in the X direction of the first pnpn junction 1U, similar to the positive side. The second pn junction 5U arranged on the negative side in the X direction is equivalent to the second pn junction 5U arranged on the positive side in the X direction, but inverted in the X direction, so no further explanation is needed.

[0082] Furthermore, the plan view of the first pnpn junction 1L and the second pn junction 5L included in the second overvoltage protection element 102aL corresponds to the first overvoltage protection element 102aU being arranged inverted in the Y direction with the power supply wiring 82 as the axis of symmetry, so its explanation is omitted. Note that the arrangement shown in Figure 7 is just one example, and the second overvoltage protection element 102aL may be arranged without inverting in the Y direction, in a location where the position in the X direction is different but the position in the Y direction is the same as the first overvoltage protection element 102aU.

[0083] (Effects of the third embodiment) The overvoltage protection element 102 reduces the volume occupied by the overvoltage protection element, reduces parasitic capacitance connected to the signal line and manufacturing costs, shortens the current path to reduce the overall resistance and improves the forward characteristics. Furthermore, the overvoltage protection element 102 allows the current that escapes the overcurrent to flow in both directions in the X direction of the well region, thus improving the ESD withstand capability. With the overvoltage protection element 102, the first pn junction 2 and the second pn junction 5 are connected in parallel between the second electrode T2 and the first electrode T1, allowing forward current to flow in parallel, thus improving the forward characteristics.

[0084] [Fourth Embodiment] (Configuration of Overvoltage Protection Element) Figure 8 is a cross-sectional view of the main part 103a of the overvoltage protection element 103 according to the fourth embodiment. Figure 8 is a cross-sectional view along the line IX1-IX2 in the plan view of Figure 10, which will be described later.

[0085] In Figure 8, the overvoltage protection element 103 comprises a second well region 52 of the second conductivity type, and a first well region 51 and a third well region 53 of the first conductivity type, which are embedded separately but in close proximity to each other on the positive and negative sides in the X direction.

[0086] The overvoltage protection element 103 further comprises a first diffusion region 51b1 and a second diffusion region 51b2 of a second conductivity type, embedded in a part of the upper surface of the first well region 51 at a distance from each other, and a third diffusion region 51a of a first conductivity type, embedded at a distance between the first diffusion region 51b1 and the second diffusion region 51b2. The overvoltage protection element 103 further comprises a fourth diffusion region 52a1 and a fifth diffusion region 52a2 of a first conductivity type, embedded in a part of the upper surface of the second well region 52 at a distance from each other, and a sixth diffusion region 52b of a second conductivity type, embedded at a distance between the fourth diffusion region 52a1 and the fifth diffusion region 52a2. The overvoltage protection element 103 further comprises a seventh diffusion region 53b1 and an eighth diffusion region 53b2 of the second conductivity type, which are embedded in a part of the upper surface of the third well region 53 at a distance from each other, and a ninth diffusion region 53a of the first conductivity type, which is embedded at a distance from each other between the seventh diffusion region 53b1 and the eighth diffusion region 53b2.

[0087] The first diffusion region 51b1 to the third diffusion region 51a and the seventh diffusion region 53b1 to the ninth diffusion region 53a are electrically connected to the first electrode T1. The fourth diffusion region 52a1 to the sixth diffusion region 52b are electrically connected to the second electrode T2. In Figure 8, the contacts connecting the first diffusion region 51b1 to the ninth diffusion region 53a are shown included in the wiring layers 41, 42, and 43.

[0088] In Figure 8, the first pnpn junction 1, which is a thyristor, is formed by the arrangement of the second diffusion region 51b2, the first well region 51, the second well region 52, and the fourth diffusion region 52a1. Furthermore, the second pnpn junction 4, which is a thyristor, is formed by the arrangement of the seventh diffusion region 53b1, the third well region 53, the second well region 52, and the fifth diffusion region 52a2. In addition, the first pn junction 2 is formed by the arrangement of the second well region 52 and the first well region 51, and the second pn junction 5 is formed by the arrangement of the second well region 52 and the third well region 53.

[0089] Compared to the main part 100a of the overvoltage protection element 100 according to the first embodiment shown in Figure 1A, Figure 8 differs in the following respects. In Figure 1A, the semiconductor substrate 3 has a first groove 21 and a second groove 22 surrounded by well regions on the upper surface of the first main surface 3a, and diffusion regions are arranged on the side and bottom surfaces of each groove at a distance in the depth direction. On the other hand, in Figure 8, the semiconductor substrate 3 does not have the first groove 21 and the second groove 22, and the diffusion regions are arranged on the upper surface of the well regions. Also, Figure 8 does not have trench contacts arranged in contact with the side and bottom surfaces of the first groove 21 and the second groove 22.

[0090] As will be described later with reference to Figures 9A and 9B, current flows in both the positive and negative directions in the X direction through the second well region 52. As mentioned above with reference to Figure 3, current flows in both directions through the second well region 12U in Figure 3 as well, so in this respect Figure 8 is the same as Figure 3. The overvoltage protection element 103 in Figure 8 can reduce the number of layers and manufacturing steps required to form the first groove 21 and the second groove 22 in the semiconductor substrate 3.

[0091] Figures 9A and 9B show the cross-section and current path of the overvoltage protection element 103 according to the fourth embodiment. Although Figures 9A and 9B are separated for space reasons, they are arranged on the same semiconductor substrate 3 and connected at connection point A. Figure 9A is a cross-sectional view along the line IX1-IX2 in the plan view of Figure 10, which will be described later, and Figure 9B is a cross-sectional view along the line IX4-IX3 in Figure 10. The overvoltage protection element 103 in Figures 9A and 9B is constructed by arranging two of the main parts 103a of the overvoltage protection element 103 described with reference to Figure 8 on the same semiconductor substrate 3 and connecting their second electrodes T2 together.

[0092] In Figure 9A, the main part 103a of the overvoltage protection element 103 in Figure 8 is shown, and the constituent components are denoted by the letter "U". In Figure 9B, the main part 103a of Figure 8 is shown inverted in the X direction with the end on the side where the third well region 53 of Figure 8 is located as the axis of symmetry, and the constituent components are denoted by the letter "L". However, the substantial configurations of Figures 9A and 9B are the same as those of Figure 8. The points that are the same as those of Figure 8 will not be explained. The overvoltage protection element in Figure 9A will be referred to as the first overvoltage protection element 103aU, and the overvoltage protection element in Figure 9B will be referred to as the second overvoltage protection element 103aL. For ease of understanding, the M2 wiring among the wiring layers 41 and 42, the contacts connecting the M1 wiring and the M2 wiring, and the insulating films 71 and 72, which are arranged at a height greater than or equal to the height of the upper surface of the M1 wiring, are not shown.

[0093] A first voltage V1 is input to the first electrode T1U of the first overvoltage protection element 103aU in Figure 9A, and a second voltage V2 is input to the first electrode T1L of the second overvoltage protection element 103aL in Figure 9B. Although the first overvoltage protection element 103aU and the second overvoltage protection element 103aL each have unidirectional polarity, bidirectional polarity is achieved by connecting their respective second electrodes T2 and inputting voltages to their respective first electrodes T1.

[0094] When the first voltage V1 is lower than the second differential voltage relative to the second voltage V2, and the second voltage V2 is lower than the second differential voltage relative to the first voltage V1, no current flows between the first electrode T1U and the first electrode T1L of the overvoltage protection element 103.

[0095] When the first voltage V1 becomes higher than the second differential voltage relative to the second voltage V2, current flows from the first electrode T1U to the first electrode T1L along the path indicated by the solid arrows in Figures 9A and 9B. Specifically, when the first voltage V1 becomes higher than the second differential voltage relative to the second voltage V2, the voltage of the first electrode T1U becomes higher than the voltage of the second electrode T2U along the first differential voltage. The first and second differential voltages may be in the range of 5V to 120V, for example, or in the range of 8V to 12V. Then, in Figure 9A, a breakdown voltage is applied to the first pnpn junction 1U and the second pnpn junction 4U, which are thyristors formed as shown in Figure 8. Then, current flows from the first electrode T1U to the second electrode T2U along the path indicated by the solid arrows in Figure 9A, and flows to the second electrode T2L in Figure 9B via connection point A. Current can flow into the second well region 52U from both the positive and negative sides in the X direction.

[0096] In Figure 9B, the first pn junction 2L and the second pn junction 5L, which are diodes formed as shown in Figure 8, are each subjected to a forward voltage greater than the voltage at which they turn on. Therefore, the current flowing through the second electrode T2L flows through the first pn junction 2L and the second pn junction 5L of the second overvoltage protection element 103aL to the first electrode T1L. The current can flow on both the positive and negative sides in the X direction of the second well region 52L.

[0097] On the other hand, when the second voltage V2 becomes higher than the second differential voltage relative to the first voltage V1, current flows from the first electrode T1L of the second overvoltage protection element 103aL to the first electrode T1U of the first overvoltage protection element 103aU, along the path indicated by the dashed arrows in Figures 9A and 9B. A detailed explanation is omitted as this is the same as when the first voltage V1 becomes higher than the second differential voltage relative to the second voltage V2, but the current flowing through each well region can flow in both the positive and negative directions in the X direction.

[0098] As described above, the overvoltage protection element 103 dissipates the overvoltage input to the first electrode T1U to the first electrode T1L, and dissipates the overvoltage input to the first electrode T1L to the first electrode T1U. This protects the input terminals of the IC or LSI connected downstream of the overvoltage protection element 103 from overvoltage. In the overvoltage protection element 103, since the current that dissipates the overvoltage flows in both directions in the X direction of the well region, the overvoltage can be dissipated in a shorter time compared to the case where the current that dissipates the overvoltage flows in one direction, and the ESD withstand capability can be improved.

[0099] Figure 10 is a plan view of the overvoltage protection element 103 according to the fourth embodiment. In Figure 10, for ease of understanding, the wiring layers 41, 42, 43 and insulating films 71, 72 are omitted from the illustration, and the well region and diffusion region located on the upper surface of the semiconductor substrate 3, and the power supply wiring that supplies power to them are shown.

[0100] Figure 9A, mentioned above, is a cross-sectional view along the line IX1-IX2 in Figure 10, and Figure 9B is a cross-sectional view along the line IX4-IX3 in Figure 10. Figure 10 shows the case where the second overvoltage protection element 103aL is positioned at the same location as the first overvoltage protection element 103aU in the X direction but at a different location in the Y direction, with the power supply wiring 82 as the axis of symmetry and the second overvoltage protection element 103aL being inverted in the Y direction. However, the second overvoltage protection element 103aL may be positioned at the same location as the first overvoltage protection element 103aU, but at a different location in the X direction but at the same location in the Y direction, without being inverted in the Y direction relative to the first overvoltage protection element 103aU.

[0101] (Effects of the fourth embodiment) With the overvoltage protection element 103, the current that dissipates the overvoltage flows in both directions in the X direction of the well region, thus improving the ESD withstand capability. With the overvoltage protection element 103, the number of layers and manufacturing steps required to form the first groove 21 and the second groove can be reduced.

[0102] [Fifth Embodiment] (Configuration of Overvoltage Protection Element) Figures 11A and 11B show the cross-section and current path of the overvoltage protection element 104 according to the fifth embodiment. Although Figures 11A and 11B are separated for the sake of space, they are arranged on the same semiconductor substrate 3 and connected at connection point A. Figure 11A is a cross-sectional view along the line XI1-XI2 of the plan view of Figure 12, which will be described later, and Figure 11B is a cross-sectional view along the line XI4-XI3 of Figure 12. The overvoltage protection element in Figure 11A is referred to as the first overvoltage protection element 104aU, and the overvoltage protection element in Figure 11B is referred to as the second overvoltage protection element 104aL. The same reference numerals are used for parts that are the same as the cross-section of the overvoltage protection element 103 according to the fourth embodiment shown in Figures 9A and 9B, and their explanation is omitted.

[0103] Compared to the first overvoltage protection element 103aU in Figure 9A, the first overvoltage protection element 104aU in Figure 11A differs in the following respects. In Figure 11A, a fourth well region 54U of p-type second conductivity is embedded on the positive side in the X direction of the first well region 51U, separated from the first well region 51U, the second well region 52U, and the third well region 53U. A tenth diffusion region 54bU of second conductivity is embedded in a part of the upper surface of the fourth well region 54U. Furthermore, a fifth well region 55U of n-type first conductivity is embedded on the positive side in the X direction of the fourth well region 54U, separated from the first well region 51U, the second well region 52U, the third well region 53U, and the fourth well region 54U. An eleventh diffusion region 55aU of first conductivity is embedded in a part of the upper surface of the fifth well region 55U.

[0104] The tenth diffusion region 54bU is electrically connected to the second electrode T2U, and the eleventh diffusion region 55aU is electrically connected to the first electrode T1U. The arrangement of the fourth well region 54U and the fifth well region 55U constitutes the third pn junction 6U.

[0105] The second overvoltage protection element 104aL in Figure 11B is the same as the first overvoltage protection element 104aU in Figure 11A, but inverted in the X direction with the end on the side with connection point A as the axis of symmetry, and the reference numeral of the constituent member is changed from "U" to "L". However, the actual configuration of Figure 11B is the same as that of Figure 11A, so the explanation is omitted.

[0106] A first voltage V1 is input to the first electrode T1U of the first overvoltage protection element 104aU, and a second voltage V2 is input to the first electrode T1L of the second overvoltage protection element 104aL.

[0107] When the first voltage V1 is lower than the second differential voltage relative to the second voltage V2, and the second voltage V2 is lower than the second differential voltage relative to the first voltage V1, no current flows between the first electrode T1U and the first electrode T1L of the overvoltage protection element 104.

[0108] When the first voltage V1 becomes higher than the second differential voltage V2, current flows from the first electrode T1U to the first electrode T1L along the path indicated by the solid arrows in Figures 11A and 11B.

[0109] Specifically, in Figure 11A, current flows from the first electrode T1U of the first overvoltage protection element 104aU through the first pnpn junction 1U and the second pnpn junction 4U, which are formed as shown in Figure 8, to the second electrode T2U, and then to the second electrode T2L in Figure 11B. In Figure 11B, a first pn junction 2L, a second pn junction 5L, and a third pn junction 6L, which are diodes, are connected in parallel between the second electrode T2L and the first electrode T1L. A forward voltage greater than the voltage at which each pn junction turns on is applied to the first pn junction 2L, the second pn junction 5L, and the third pn junction 6L in Figure 11B. Therefore, the current that flows through the second electrode T2L flows through the first pn junction 2L, the second pn junction 5L, and the third pn junction 6L of the second overvoltage protection element 104aL, and then to the first electrode T1L. Since forward current can be passed in parallel to the first pn junction 2L, the second pn junction 5L, and the third pn junction 6L, the forward characteristics can be improved.

[0110] On the other hand, when the second voltage V2 becomes higher than or equal to the second differential voltage relative to the first voltage V1, current flows from the first electrode T1L to the first electrode T1U along the path indicated by the dashed arrows in Figures 11A and 11B. In Figure 11A, the first pn junction 2U, the second pn junction 5U, and the third pn junction 6U are connected in parallel between the second electrode T2U and the first electrode T1U, allowing forward current to flow in parallel and thus improving the forward characteristics.

[0111] (Effects of the fifth embodiment) With the overvoltage protection element 104, the current that relieves the overvoltage flows in both directions in the X direction of the well region, so the ESD withstand capability can be improved. With the overvoltage protection element 104, the number of layers and manufacturing steps for forming the first groove 21 and the second groove can be reduced. With the overvoltage protection element 104, the first pn junction 2, the second pn junction 5, and the third pn junction 6 are connected in parallel between the second electrode T2 and the first electrode T1, so that a forward current can flow in parallel, so the forward characteristics can be improved.

[0112] Although the present disclosure has been described in detail above, it will be clear to those skilled in the art that the present disclosure is not limited to the embodiments described herein. One or more elements of one embodiment can be combined with one or more elements of another embodiment. The present disclosure can be implemented in modified and altered forms without departing from the spirit and scope of the present disclosure as defined by the claims. Therefore, the descriptions in the present disclosure are illustrative and not intended to be restrictive in any way.

[0113] For example, in the main part 102a of the overvoltage protection element 102 according to the third embodiment of this disclosure, the configuration of the second well region 12 is the same as that of the main part 100a of the overvoltage protection element 100 in the first embodiment. However, the configuration of the second well region 12 may be the same as that of the main part 101a of the overvoltage protection element 101 in the second embodiment.

[0114] For example, in the overvoltage protection elements 100, 102, 103, and 104 of this disclosure, two of the main parts 100a, 102a, 103a, and 104a are arranged and their second electrodes T2 are connected to form an overvoltage protection element having bidirectional polarity. However, an overvoltage protection element having unidirectional polarity may be formed by arranging only one of the main parts.

[0115] (Note) The technical concepts that can be grasped from this disclosure are described below. Not with the intention of limiting, but for the purpose of aiding understanding, the components described in the notes are denoted by the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples for the purpose of aiding understanding, and the components described in each note should not be limited to those indicated by the reference numerals.

[0116] (Note 1) The overvoltage protection elements 100a and 102a each include a semiconductor substrate 3 having a first main surface 3a extending in a first direction which is the X direction and a second direction which is the Y direction intersecting the first direction, and a first groove 21 and a second groove 22 formed on the first main surface 3a at mutual distances. The overvoltage protection elements 100a and 102a further include a first well region 11 of a first conductivity type embedded so as to surround the first groove 21 in the first and second directions on the first main surface 3a and in the depth direction of the semiconductor substrate 3 perpendicular to the first main surface 3a. The overvoltage protection elements 100a and 102a further include a first diffusion region 11b1 and 11b2 of a second conductivity type embedded in the upper part of the first well region 11 located on both sides of the first groove 21 in the first direction, in contact with the side surfaces 21a1 and 21a2 of the first groove 21. The overvoltage protection elements 100a and 102a further include a second diffusion region 11a of a first conductivity type, which is embedded on the upper surface of the first well region 11 located at the bottom surface 21b of the first groove 21, and is spaced apart from the first diffusion regions 11b1 and 11b2 in the depth direction of the semiconductor substrate 3.

[0117] The overvoltage protection elements 100a and 102a further include a second well region 12 of a second conductivity type, which is embedded in the first and second directions on the first main surface 3a and in the depth direction of the semiconductor substrate 3, surrounding the second groove 22 and spaced apart from the first well region 11. The overvoltage protection elements 100a and 102a further include a third diffusion region 12a1 and 12a2 of a first conductivity type, which is embedded in the upper part of the second well region 12 located on both sides of the second groove 22 in the first direction, in contact with the side surfaces 22a1 and 22a2 of the second groove 22. The overvoltage protection elements 100a and 102a further include a fourth diffusion region 12b of a second conductivity type, which is embedded on the upper surface of the second well region 12 located on the bottom surface 22b of the second groove 22, spaced apart from the third diffusion regions 12a1 and 12a2 in the depth direction of the semiconductor substrate 3.

[0118] The overvoltage protection elements 100a and 102a further include a first contact 31 that is arranged in contact with the side surfaces 21a1 and 21a2 on both sides in the first direction of the first groove 21 and the bottom surface 21b, and is electrically connected to the first diffusion regions 11b1 and 11b2 and the second diffusion region 11a. The overvoltage protection elements 100a and 102a further include a second contact 32 that is arranged in contact with the side surfaces 22a1 and 22a2 on both sides in the first direction of the second groove 22 and the bottom surface 22b, and is electrically connected to the third diffusion regions 12a1 and 12a2 and the fourth diffusion region 12b. The overvoltage protection elements 100a and 102a further include a first electrode T1 that is electrically connected to the first contact 31 and a second electrode T2 that is electrically connected to the second contact 32. A first pnpn junction 1 is formed by the arrangement of first diffusion regions 11b1, 11b2, first well region 11, second well region 12, and third diffusion regions 12a1, 12a2, and a first pn junction 2 is formed by the arrangement of second well region 12 and first well region 11.

[0119] With the overvoltage protection elements 100a and 102a, since the diffusion regions of different conductivity types are spaced apart in the depth direction, spacing in the X direction is unnecessary, and the width of the first well region 11 and the second well region 12 in the X direction can be reduced. In addition, the thyristor and diode can be placed in locations that are at the same position in the X direction but at different depths. As a result, the volume occupied by the overvoltage protection element can be reduced, parasitic capacitance connected to the signal line and manufacturing costs can be reduced, and the current path can be shortened to reduce the overall resistance and improve the forward characteristics. Furthermore, with the overvoltage protection elements 100a and 102a, the current that escapes overcurrent flows in both directions in the X direction of the well region, so the overvoltage can escape in a shorter time and the ESD withstand capability can be improved.

[0120] (Note 2) The overvoltage protection element 101a comprises a semiconductor substrate 3 having a first main surface 3a extending in a first direction which is the X direction and a second direction which is the Y direction intersecting the first direction, and a first groove 21 and a second groove 22 formed on the first main surface 3a at mutual distances. The overvoltage protection element 101a further comprises a first well region 11 of a first conductivity type embedded so as to surround the first groove 21 in the first and second directions on the first main surface 3a and in the depth direction of the semiconductor substrate 3 perpendicular to the first main surface 3a. The overvoltage protection element 101a further comprises first diffusion regions 11b1 and 11b2 of a second conductivity type embedded in the upper part of the first well region 11 located on both sides of the first groove 21 in the first direction, in contact with the side surfaces 21a1 and 21a2 of the first groove 21. The overvoltage protection element 101a further comprises a second diffusion region 11a of a first conductivity type, which is embedded on the upper surface of the first well region 11 located at the bottom surface 21b of the first groove 21, and is spaced apart from the first diffusion regions 11b1 and 11b2 in the depth direction of the semiconductor substrate 3.

[0121] The overvoltage protection element 101a further comprises a second well region 12 of a second conductivity type, which is embedded in the first and second directions on the first main surface 3a and in the depth direction of the semiconductor substrate 3, surrounding the second groove 22 and spaced apart from the first well region 11. The overvoltage protection element 101a further comprises a third diffusion region 12b1, 12b2 of a second conductivity type, which is embedded in the upper part of the second well region 12 located on both sides of the second groove 22 in the first direction, in contact with the side surfaces 22a1, 22a2 of the second groove 22. The overvoltage protection element 101a further comprises a fourth diffusion region 12a of a first conductivity type, which is embedded on the upper surface of the second well region 12 located on the bottom surface 22b of the second groove 22, spaced apart from the third diffusion regions 12b1, 12b2 in the depth direction of the semiconductor substrate 3.

[0122] The overvoltage protection element 101a further comprises a first contact 31 that is arranged in contact with the side surfaces 21a1, 21a2 on both sides in the first direction and the bottom surface 21b of the first groove 21 and electrically connected to the first diffusion regions 11b1, 11b2 and the second diffusion region 11a. The overvoltage protection element 101a further comprises a second contact 32 that is arranged in contact with the side surfaces 22a1, 22a2 on both sides in the first direction and the bottom surface 22b of the second groove 22 and electrically connected to the third diffusion regions 12b1, 12b2 and the fourth diffusion region 12a. The overvoltage protection element 101a further comprises a first electrode T1 electrically connected to the first contact 31 and a second electrode T2 electrically connected to the second contact 32. The first pnpn junction 1 is formed by the arrangement of the first diffusion regions 11b1, 11b2, the first well region 11, the second well region 12, and the fourth diffusion region 12a, and the first pn junction 2 is formed by the arrangement of the second well region 12 and the first well region 11.

[0123] The overvoltage protection element 101a reduces the volume occupied by the overvoltage protection element, reduces parasitic capacitance connected to the signal line and manufacturing costs, shortens the current path to reduce the overall resistance and improves forward characteristics. Furthermore, with the overvoltage protection element 101a, the current that escapes overcurrent flows in both directions in the X direction of the well region, thus improving ESD withstand capability. The overvoltage protection element 101a also reduces the number of layers and manufacturing processes required to form the diffusion region, thereby reducing manufacturing costs.

[0124] (Note 3) The overvoltage protection element 102a described in Note 1 or 2 further comprises a third well region 14 of second conductivity type embedded on the upper surface of the semiconductor substrate 3, spaced apart from the first well region 11 and the second well region 12. The overvoltage protection element 102a further comprises a fifth diffusion region 14b of second conductivity type embedded in a part of the upper surface of the third well region 14. The overvoltage protection element 102a further comprises a fourth well region 15 of first conductivity type embedded on the upper surface of the semiconductor substrate 3, spaced apart from the first well region 11 to the third well region 14, and a sixth diffusion region 15a of first conductivity type embedded in a part of the upper surface of the fourth well region 15. The fifth diffusion region 14b is electrically connected to the second electrode T2, and the sixth diffusion region 15a is electrically connected to the first electrode T1, and the arrangement of the third well region 14 and the fourth well region 15 constitutes a second pn junction 5.

[0125] With the overvoltage protection element 102a, the first pn junction 2 and the second pn junction 5 are connected in parallel between the second electrode T2 and the first electrode T1, allowing forward current to flow in parallel, thus improving the forward characteristics.

[0126] (Note 4) In the overvoltage protection elements 100a, 101a, and 102a described in any one of Notes 1 to 3, a first voltage V1 is input to the first electrode T1 and a second voltage V2 is input to the second electrode T2. When the first voltage V1 becomes higher than or equal to a first differential voltage relative to the second voltage V2, a voltage equal to or greater than the breakdown voltage or breakover voltage is applied to the first pnpn junction 1. With the overvoltage protection elements 100a, 101a, and 102a, the input terminal of an IC or LSI connected downstream of the overvoltage protection elements 100a, 101a, and 102a can be protected from overvoltage by diverting the overvoltage input to the first electrode T1 to the second electrode T2.

[0127] (Note 5) The overvoltage protection elements 100 and 102 include a first overvoltage protection element 100aU, 102aU and a second overvoltage protection element 100aL, 102aL, which are arranged on the first main surface 3a at a distance from each other from the overvoltage protection elements 100a and 102a described in Note 1 or 2. The overvoltage protection elements 100 and 102 further include a connecting electrode that connects the second electrode T2U of the first overvoltage protection elements 100aU and 102aU to the second electrode T2L of the second overvoltage protection elements 100aL and 102aL. With the overvoltage protection elements 100 and 102, bidirectional polarity can be realized.

[0128] (Note 6) In the overvoltage protection elements 100 and 102 described in Note 5, a first voltage V1 is input to the first electrode T1U of the first overvoltage protection elements 100aU and 102aU, and a second voltage V2 is input to the first electrode T1L of the second overvoltage protection elements 100aL and 102aL. When the first voltage V1 becomes higher than or equal to the second differential voltage relative to the second voltage V2, a voltage equal to or equal to the breakdown voltage or breakover voltage is applied to the first pnpn junction 1U of the first overvoltage protection elements 100aU and 102aU. When the second voltage V2 becomes higher than or equal to the second differential voltage relative to the first voltage V1, a voltage equal to or equal to the breakdown voltage or breakover voltage is applied to the first pnpn junction 1L of the second overvoltage protection elements 100aL and 102aL.

[0129] The overvoltage protection elements 100 and 102 allow the overvoltage input to the first electrode T1U to be discharged to the first electrode T1L, and the overvoltage input to the first electrode T1L to be discharged to the first electrode T1U. This protects the input terminals of the IC or LSI connected downstream of the overvoltage protection elements 100 and 102 from overvoltage.

[0130] (Note 7) In the overvoltage protection element described in Note 4, the first differential voltage is in the range of 5V to 120V. This makes it possible to protect the input terminals of the IC or LSI connected to the subsequent stage from overvoltage within an appropriate voltage range.

[0131] (Note 8) In the overvoltage protection elements 100a, 101a, and 100 described in any one of Notes 1 to 3 or 5, the semiconductor substrate 3 is p-type.

[0132] (Note 9) In the overvoltage protection elements 100a, 101a, and 100 described in any one of Notes 1 to 3 or 5, the semiconductor substrate 3 is an intrinsic semiconductor. This makes it possible to reduce parasitic capacitance caused by junction capacitance.

[0133] (Note 10) In the overvoltage protection element 100a described in Note 1 or 2, the first well region 11 and the second well region 12 extend in the second direction, which is the Y direction, and are arranged in close proximity in the first direction, which is the X direction. The first groove 21, the second groove 22, and the first diffusion regions 11b1, 11b2 to the fourth diffusion region 12a are arranged to extend in the second direction.

[0134] (Note 11) The overvoltage protection element 100a described in Note 10 further includes a second conductivity type connection region 132 that connects the first well region 11 and the second well region 12 in a portion of the region between the first well region 11 and the second well region 12. With the overvoltage protection element 100a, the breakdown voltage can be set to an appropriate value while suppressing parasitic capacitance.

[0135] (Note 12) In the overvoltage protection element 100a described in Note 11, the width of the first well region 11 is relatively wider near the portion in contact with the connection region 132, and relatively narrower in portions further away from the portion in contact with the connection region 132. The overvoltage protection element 100a can reduce parasitic capacitance caused by junction capacitance.

[0136] (Note 13) In the overvoltage protection element 102a described in Note 3, the first well region 11 and the second well region 12 extend in the second direction and are arranged in close proximity in the first direction. The first groove 21, the second groove 22, the first diffusion regions 11b1, 11b2 to the fourth diffusion regions 12b, 12a extend in the second direction and are arranged in close proximity in the first direction, and the fifth diffusion region 14b and the sixth diffusion region 15a extend in the second direction and are arranged in close proximity in the first direction.

[0137] (Note 14) In the overvoltage protection elements 100a, 101a, 102a, 100, and 102 described in any one of Notes 1 to 3, 5, or 10 to 13, the first conductivity type is n-type and the second conductivity type is p-type.

[0138] (Note 15) The overvoltage protection elements 103a and 104a each include a semiconductor substrate 3 and a first well region 51 of a first conductivity type embedded in the upper surface of the semiconductor substrate 3. The overvoltage protection elements 103a and 104a further include a first diffusion region 51b1 and a second diffusion region 51b2 of a second conductivity type, embedded in a part of the upper surface of the first well region 51 at a distance from each other. The overvoltage protection elements 103a and 104a further include a third diffusion region 51a of a first conductivity type, embedded at a distance between the first diffusion region 51b1 and the second diffusion region 51b2.

[0139] The overvoltage protection elements 103a and 104a further comprise a second well region 52 of a second conductivity type, which is embedded on the upper surface of the semiconductor substrate 3 at a distance from the first well region 51 and in close proximity in a first direction. The overvoltage protection elements 103a and 104a further comprise a fourth diffusion region 52a1 and a fifth diffusion region 52a2 of a first conductivity type, which are embedded at a distance from each other in a part of the upper surface of the second well region 52. The overvoltage protection elements 103a and 104a further comprise a sixth diffusion region 52b of a second conductivity type, which is embedded at a distance between the fourth diffusion region 52a1 and the fifth diffusion region 52a2.

[0140] The overvoltage protection elements 103a and 104a further include a third well region 53 of a first conductivity type, which is embedded in a part of the upper surface of the semiconductor substrate 3, spaced apart from the first well region 51 and the second well region 52, and adjacent to the second well region 52 in a first direction. The overvoltage protection elements 103a and 104a further include a seventh diffusion region 53b1 and an eighth diffusion region 53b2 of a second conductivity type, which are embedded in a part of the upper surface of the third well region 53, spaced apart from each other. The overvoltage protection elements 103a and 104a further include a ninth diffusion region 53a of a first conductivity type, which is embedded spaced apart between the seventh diffusion region 53b1 and the eighth diffusion region 53b2.

[0141] The overvoltage protection elements 103a and 104a further include a first electrode T1 electrically connected to the first diffusion region 51b1 to the third diffusion region 51a and the seventh diffusion region 53b1 to the ninth diffusion region 53a. The overvoltage protection elements 103a and 104a further include a second electrode T2 electrically connected to the fourth diffusion region 52a1 to the sixth diffusion region 52b.

[0142] A first pnpn junction 1 is formed by the arrangement of a second diffusion region 51b2, a first well region 51, a second well region 52, and a fourth diffusion region 52a1, and a first pn junction 2 is formed by the arrangement of a second well region 52 and a first well region 51. A second pnpn junction 4 is formed by the arrangement of a seventh diffusion region 53b1, a third well region 53, a second well region 52, and a fifth diffusion region 52a2, and a second pn junction 5 is formed by the arrangement of a second well region 52 and a third well region 53.

[0143] With the overvoltage protection elements 103a and 104a, the current that dissipates the overvoltage flows in both directions in the X direction of the well region, thereby improving the ESD withstand capability. With the overvoltage protection elements 103a and 104a, the number of layers and manufacturing steps required to form the first groove and the second groove in the semiconductor substrate 3 can be reduced.

[0144] (Note 16) The overvoltage protection element 104a described in Note 15 further comprises a fourth well region 54 of second conductivity type, which is embedded on the upper surface of the semiconductor substrate 3, spaced apart from the first well region 51 to the third well region 53 and adjacent to the first well region 51 in a first direction. The overvoltage protection element 104a further comprises a tenth diffusion region 54b of second conductivity type, which is embedded in a part of the upper surface of the fourth well region 54. The overvoltage protection element 104a further comprises a fifth well region 55 of first conductivity type, which is embedded on the upper surface of the semiconductor substrate 3, spaced apart from the first well region 51 to the fourth well region 54 and adjacent to the fourth well region 54 in a first direction. The overvoltage protection element 104a further comprises an eleventh diffusion region 55a of first conductivity type, which is embedded in a part of the upper surface of the fifth well region 55.

[0145] The tenth diffusion region 54b is electrically connected to the second electrode T2, and the eleventh diffusion region 55a is electrically connected to the first electrode. The arrangement of the fourth well region 54 and the fifth well region 55 constitutes a third pn junction.

[0146] With the overvoltage protection element 104a, the first pn junction 2, the second pn junction 5, and the third pn junction 6 are connected in parallel between the second electrode T2 and the first electrode T1, allowing forward current to flow in parallel, thus improving the forward characteristics.

[0147] (Note 17) In the overvoltage protection elements 103a and 104a described in Note 15 or 16, a first voltage V1 is input to the first electrode T1 and a second voltage V2 is input to the second electrode T2. When the first voltage V1 becomes higher than or equal to a first differential voltage relative to the second voltage V2, a voltage equal to or greater than the breakdown voltage or breakover voltage is applied to the first pnpn junction 1 and the second pnpn junction 4. With the overvoltage protection elements 103a and 104a, the input terminals of an IC or LSI connected downstream of the overvoltage protection elements 103a and 104a can be protected from overvoltage by diverting the overvoltage input to the first electrode T1 to the second electrode T2.

[0148] (Note 18) In the overvoltage protection elements 103a and 104a described in Note 15 or 16, the first well region 51 to the third well region 53 are arranged to extend in a second direction intersecting the first direction, and the first diffusion region 51b1 to the ninth diffusion region 53a are arranged to extend in the second direction.

[0149] (Note 19) In the overvoltage protection elements 103a and 104a described in Note 15 or 16, the first conductivity type is n-type and the second conductivity type is p-type.

[0150] (Note 20) In the overvoltage protection elements 103a and 104a described in Note 15 or 16, the first conductivity type is p-type and the second conductivity type is n-type.

[0151] (Note 21) In the overvoltage protection elements 100 and 102 described in Note 6, the second differential voltage is in the range of 5V to 120V. This makes it possible to protect the input terminals of the IC or LSI connected to the subsequent stage from overvoltage within an appropriate voltage range.

[0152] (Note 22) In the overvoltage protection element 100a described in Note 11, the positions of the connection regions 131, 132, and 133 in the Y direction are different from each other between adjacent pairs of first and second well regions, and are arranged to be the same every other time. The overvoltage protection element 100a allows for improved withstand voltage by distributing the positions of the current path in the Y direction.

[0153] 1, 1L, 1U First pnpn junction 2, 2L, 2U First pn junction 3 Semiconductor substrate 3a First main surface 4, 4L, 4U Second pnpn junction 5, 5L, 5U Second pn junction 6, 6L, 6U Third pn junction 11, 11L, 11U First well region 11a Second diffusion region 11b1, 11b1U, 11b2, 11b2U First diffusion region 11cU, 11dU, 12cL, 12cU, 12dU Well region 12, 12L, 12U Second well region 12a, 12b Fourth diffusion region 12a1, 12a2, 12b1, 12b2 Third diffusion region 13L, 13U, 14, 14L, 14U Third well region 14b, 14bU Fifth diffusion region 15, 15L, 15U, 16L, 16U Fourth well region 15a, 15aU Sixth diffusion region 21 First groove 21a1, 21a2, 22a1, 22a2 Side 21b, 22b Bottom 22 Second groove 31, 31U First contact 32, 32U Second contact 41, 41U, 42, 42U Wiring layer 51, 51L, 51U First well region 51a Third diffusion region 51b1 First diffusion region 51b2 Second diffusion region 52, 52L, 52U Second well region 52a1 Fourth diffusion region 52a2 Fifth diffusion region 52b Sixth diffusion region 53 Third well region 53a Ninth diffusion region 53b1 Seventh diffusion region 53b2 Eighth diffusion region 53U Third well region 54, 54L, 54U Fourth well region 54b, 54bU Tenth diffusion region 55, 55L, 55U Fifth well region 55a, 55aU Eleventh diffusion region 71, 72 Insulating film 81, 82 Power supply wiring 100, 101, 102, 103, 104 Overvoltage protection elements 100a, 101a, 103a Main parts 100aL, 102aL, 103aL, 104aL Second overvoltage protection elements 100aU, 102aU, 103aU, 104aU First overvoltage protection elements 131, 132, 133 Connection region T1, T1L, T1U First electrode T2, T2L, T2U Second electrode V1 First voltage V2 Second voltage

Claims

1. A semiconductor substrate having a first main surface extending in a first direction and a second direction intersecting the first direction, and a first groove and a second groove formed on the first main surface at a distance from each other; a first well region of a first conductivity type embedded so as to surround the first groove in the first direction and the second direction on the first main surface and in the depth direction of the semiconductor substrate perpendicular to the first main surface; a first diffusion region of a second conductivity type embedded in the upper part of the first well region located on both sides of the first groove in the first direction, in contact with the side surface of the first groove; a second diffusion region of a first conductivity type embedded on the upper surface of the first well region located at the bottom surface of the first groove, at a distance from the first diffusion region in the depth direction of the semiconductor substrate; a second well region of a second conductivity type embedded so as to surround the second groove and at a distance from the first well region in the first direction and the second direction on the first main surface and in the depth direction of the semiconductor substrate. The semiconductor substrate comprises: a third diffusion region of a first conductivity type, embedded in the upper part of the second well region located on both sides of the second groove in the first direction, in contact with the side surface of the second groove; a fourth diffusion region of a second conductivity type, embedded on the upper surface of the second well region located on the bottom surface of the second groove, spaced apart from the third diffusion region in the depth direction of the semiconductor substrate; a first contact, arranged in contact with the side surfaces and bottom surface of the first groove in the first direction, and electrically connected to the first diffusion region and the second diffusion region; a second contact, arranged in contact with the side surfaces and bottom surface of the second groove in the first direction, and electrically connected to the third diffusion region and the fourth diffusion region; a first electrode, electrically connected to the first contact; and a second electrode, electrically connected to the second contact. The arrangement of the first diffusion region, the first well region, the second well region, and the third diffusion region constitutes a first pnpn junction, and the arrangement of the second well region and the first well region constitutes a first pn junction. Overvoltage protection element.

2. A semiconductor substrate having a first main surface extending in a first direction and a second direction intersecting the first direction, and a first groove and a second groove formed on the first main surface at mutual distances; a first well region of a first conductivity type embedded so as to surround the first groove in the first direction and the second direction on the first main surface and in the depth direction of the semiconductor substrate perpendicular to the first main surface; a first diffusion region of a second conductivity type embedded in the upper part of the first well region located on both sides of the first groove in the first direction, in contact with the side surface of the first groove; a second diffusion region of a first conductivity type embedded on the upper surface of the first well region located at the bottom surface of the first groove, at distance from the first diffusion region in the depth direction of the semiconductor substrate; a second well region of a second conductivity type embedded so as to surround the second groove and at distance from the first well region in the first direction and the second direction on the first main surface and in the depth direction of the semiconductor substrate. The semiconductor substrate comprises: a third diffusion region of a second conductivity type, embedded in the upper part of the second well region located on both sides of the second groove in the first direction, in contact with the side surface of the second groove; a fourth diffusion region of a first conductivity type, embedded on the upper surface of the second well region located on the bottom surface of the second groove, spaced apart from the third diffusion region in the depth direction of the semiconductor substrate; a first contact, arranged in contact with the side surfaces and bottom surface of the first groove in the first direction, and electrically connected to the first diffusion region and the second diffusion region; a second contact, arranged in contact with the side surfaces and bottom surface of the second groove in the first direction, and electrically connected to the third diffusion region and the fourth diffusion region; a first electrode, electrically connected to the first contact; and a second electrode, electrically connected to the second contact. The arrangement of the first diffusion region, the first well region, the second well region, and the fourth diffusion region constitutes a first pnpn junction, and the arrangement of the second well region and the first well region constitutes a first pn junction. Overvoltage protection element.

3. The overvoltage protection element according to claim 1 or 2, further comprising: a third well region of a second conductivity type embedded on the upper surface of the semiconductor substrate, spaced apart from the first well region and the second well region; a fifth diffusion region of a second conductivity type embedded in a part of the upper surface of the third well region; a fourth well region of a first conductivity type embedded on the upper surface of the semiconductor substrate, spaced apart from the first to third well regions; and a sixth diffusion region of a first conductivity type embedded in a part of the upper surface of the fourth well region, wherein the fifth diffusion region is electrically connected to the second electrode, the sixth diffusion region is electrically connected to the first electrode, and the arrangement of the third well region and the fourth well region constitutes a second pn junction.

4. An overvoltage protection element according to any one of claims 1 to 3, wherein a first voltage is input to the first electrode, a second voltage is input to the second electrode, and when the first voltage becomes higher than or equal to a first differential voltage with respect to the second voltage, a voltage equal to or greater than the breakdown voltage or breakover voltage is applied to the first pnpn junction.

5. An overvoltage protection element comprising: a first overvoltage protection element and a second overvoltage protection element, wherein the overvoltage protection elements described in claim 1 or 2 are arranged on the first main surface at a distance from each other; and a connecting electrode that connects the second electrode of the first overvoltage protection element and the second electrode of the second overvoltage protection element.

6. The overvoltage protection element according to claim 5, wherein a first voltage is input to the first electrode of the first overvoltage protection element, a second voltage is input to the first electrode of the second overvoltage protection element, and when the first voltage becomes higher than or equal to a second differential voltage relative to the second voltage, a voltage equal to or equal to the breakdown voltage or breakover voltage is applied to the first pnpn junction of the first overvoltage protection element, and when the second voltage becomes higher than or equal to a second differential voltage relative to the first voltage, a voltage equal to or equal to the breakdown voltage or breakover voltage is applied to the first pnpn junction of the second overvoltage protection element.

7. The overvoltage protection element according to claim 4, wherein the first differential voltage is in the range of 5V to 120V.

8. The overvoltage protection element according to any one of claims 1 to 3, 5, wherein the semiconductor substrate is p-type.

9. The overvoltage protection element according to any one of claims 1 to 3, 5, wherein the semiconductor substrate is an intrinsic semiconductor.

10. The overvoltage protection element according to claim 1 or 2, wherein the first well region and the second well region extend in the second direction and are arranged in close proximity in the first direction, and the first groove, the second groove, and the first to fourth diffusion regions are arranged to extend in the second direction.

11. The overvoltage protection element according to claim 10, further comprising a second conductive type connecting region connecting the first well region and the second well region in a portion of the region between the first well region and the second well region.

12. The overvoltage protection element according to claim 11, wherein the width of the first well region is relatively wider in the vicinity of the portion in contact with the connection region and relatively narrower in the portion away from the vicinity of the portion in contact with the connection region.

13. The overvoltage protection element according to claim 3, wherein the first well region and the second well region extend in the second direction and are arranged in close proximity in the first direction, the first groove, the second groove, and the first to fourth diffusion regions are arranged to extend in the second direction, the third well region and the fourth well region extend in the second direction and are arranged in close proximity in the first direction, and the fifth diffusion region and the sixth diffusion region are arranged to extend in the second direction.

14. An overvoltage protection element according to any one of claims 1 to 3, 5, or 10 to 13, wherein the first conductivity type is n-type and the second conductivity type is p-type.

15. A semiconductor substrate; a first well region of a first conductivity type embedded in the upper surface of the semiconductor substrate; a first diffusion region and a second diffusion region of a second conductivity type embedded in a part of the upper surface of the first well region, spaced apart from each other; a third diffusion region of a first conductivity type embedded spaced apart between the first diffusion region and the second diffusion region; a second well region of a second conductivity type embedded in the upper surface of the semiconductor substrate, spaced apart from the first well region and in close proximity in a first direction; a fourth diffusion region and a fifth diffusion region of a first conductivity type embedded in a part of the upper surface of the second well region, spaced apart from each other; a sixth diffusion region of a second conductivity type embedded spaced apart between the fourth diffusion region and the fifth diffusion region; a third well region of a first conductivity type embedded in a part of the upper surface of the semiconductor substrate, spaced apart from the first well region and the second well region and in close proximity to the second well region in a first direction. An overvoltage protection element comprising: a seventh diffusion region and an eighth diffusion region of a second conductivity type, embedded in a part of the upper surface of the third well region at a distance from each other; a ninth diffusion region of a first conductivity type, embedded at a distance between the seventh and eighth diffusion regions; a first electrode electrically connected to the first to third diffusion regions and the seventh to ninth diffusion regions; and a second electrode electrically connected to the fourth to sixth diffusion regions, wherein the arrangement of the second diffusion region, the first well region, the second well region, and the fourth diffusion region constitutes a first pn junction; the arrangement of the second well region and the first well region constitutes a first pn junction; the arrangement of the seventh diffusion region, the third well region, the second well region, and the fifth diffusion region constitutes a second pn junction; and the arrangement of the second well region and the third well region constitutes a second pn junction.

16. The overvoltage protection element according to claim 15, further comprising: a fourth well region of a second conductivity type embedded on the upper surface of the semiconductor substrate, spaced apart from the first to third well regions and adjacent to the first well region in a first direction; a tenth diffusion region of a second conductivity type embedded in a part of the upper surface of the fourth well region; a fifth well region of a first conductivity type embedded on the upper surface of the semiconductor substrate, spaced apart from the first to fourth well regions and adjacent to the fourth well region in a first direction; and an eleventh diffusion region of a first conductivity type embedded in a part of the upper surface of the fifth well region, wherein the tenth diffusion region is electrically connected to the second electrode, the eleventh diffusion region is electrically connected to the first electrode, and a third pn junction is formed by the arrangement of the fourth and fifth well regions.

17. An overvoltage protection element according to claim 15 or 16, wherein a first voltage is input to the first electrode, a second voltage is input to the second electrode, and when the first voltage becomes higher than or equal to a first differential voltage with respect to the second voltage, a voltage equal to or greater than the breakdown voltage or breakover voltage is applied to the first pnpn junction and the second pnpn junction.

18. The overvoltage protection element according to claim 15 or 16, wherein the first to third well regions are arranged to extend in a second direction intersecting the first direction, and the first to ninth diffusion regions are arranged to extend in the second direction.

19. The overvoltage protection element according to claim 15 or 16, wherein the first conductivity type is n-type and the second conductivity type is p-type.

20. The overvoltage protection element according to claim 15 or 16, wherein the first conductivity type is p-type and the second conductivity type is n-type.

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