Semiconductor device

Abstract

In this semiconductor device, an epitaxial layer on a substrate includes a drift region, a drift high-concentration region which is disposed between the drift region and the substrate, and a first transition region which is disposed between the drift region and the drift high-concentration region. The drift region has a drift concentration Nd of a first conductivity type that is lower than a substrate concentration Ns of the substrate. The drift high-concentration region has an impurity concentration Nr of the first conductivity type that is equal to or higher than the substrate concentration Ns. In the first transition region, the impurity concentration of the first conductivity type changes at a specific first concentration gradient in the depth direction of the epitaxial layer, and the first concentration gradient is expressed by d(log10Nt1(x)) / dx and satisfies formula (1). (1): d(log10Nt1(x)) / dx < 2log10(cm-3) / µm (In the formula (1), Nt1(x) is the concentration of the first transition region at a depth x, and x is the depth from the main surface of the epitaxial layer.)

Description

Semiconductor equipment Related applications

[0001] This application corresponds to Japanese Patent Application No. 2025-010555, filed with the Japan Patent Office on 24 January 2025, and the full disclosure of this application is incorporated herein by reference.

[0002] This disclosure relates to semiconductor devices.

[0003] Patent Document 1 discloses a semiconductor device including a drift layer. The drift layer includes a first region, a second region, and a third region. The first region has a first impurity concentration n1, the second region has a second impurity concentration n2, and the third region has a third impurity concentration n3. The first to third impurity concentrations n1 to n3 are set to values ​​that satisfy the condition "n2 < n1 < n3" considering cosmic ray tolerance.

[0004] Japanese Patent Publication No. 2006-245475

[0005] [Summary] One embodiment of the present disclosure provides a semiconductor device that can achieve both excellent cosmic ray tolerance and suppression of bipolar degradation.

[0006] Figure 1 is a plan view showing a semiconductor device according to the first embodiment. Figure 2 is a cross-sectional view taken along the line II-II shown in Figure 1. Figure 3 is a diagram illustrating the concentration distribution of n-type impurities in the chip (first form). Figure 4 is a diagram illustrating the concentration distribution of n-type impurities in the chip (second form). Figure 5 is a diagram illustrating the concentration distribution of n-type impurities in the chip (third form). Figure 6 is a cross-sectional view showing a semiconductor device according to the second embodiment. Figure 7 is a diagram illustrating the concentration distribution of n-type impurities in the chip (fourth form). Figure 8 is a diagram illustrating the concentration distribution of n-type impurities in the chip (fifth form). Figure 9 is a diagram illustrating the concentration distribution of n-type impurities in the chip (sixth form). Figure 10 is a plan view showing a semiconductor device according to the third embodiment. Figure 11 is a cross-sectional view taken along the line XI-XI shown in Figure 10. Figure 12 is a plan view showing the main part of the semiconductor device shown in Figure 10. Figure 13 is a cross-sectional view taken along the line XIII-XIII shown in Figure 12. Figure 14 is an enlarged cross-sectional view showing the peripheral edge of the chip. Figure 15 is a cross-sectional view showing a semiconductor device according to the fourth embodiment.

[0007] The embodiments will now be described in detail with reference to the attached drawings. The attached drawings are schematic diagrams and not strictly accurate; the scale and other aspects may not necessarily match. Corresponding structures in the attached drawings are given the same reference numerals, and redundant descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the description given before the omission or simplification applies.

[0008] When the phrase "substantially equal" is used in a description where a comparison target exists, this phrase includes not only numerical values ​​(forms) that are equal to the numerical value (form) of the comparison target, but also numerical errors (form errors) within a range of ±10% based on the numerical value (form) of the comparison target. In the embodiments, phrases such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of explanation and are not intended to limit the names of each structure.

[0009] Figure 1 is a plan view showing a semiconductor device 1A according to the first embodiment. Figure 2 is a cross-sectional view taken along the line II-II shown in Figure 1. Referring to Figures 1 and 2, the semiconductor device 1A in this embodiment includes a single crystal of a wide-bandgap semiconductor and includes a chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In other words, the semiconductor device 1A is a "wide-bandgap semiconductor device".

[0010] Chip 2 may also be referred to as a "semiconductor chip" or a "wide-bandgap semiconductor chip." A wide-bandgap semiconductor is a semiconductor that has a bandgap greater than that of Si (silicon). GaN (gallium nitride), SiC (silicon carbide), and C (diamond) are examples of wide-bandgap semiconductors.

[0011] In this embodiment, chip 2 is a "SiC chip" containing a hexagonal SiC single crystal as an example of a wide-bandgap semiconductor. In other words, semiconductor device 1A is a "SiC semiconductor device". Hexagonal SiC single crystals have multiple polytypes, including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, 6H-SiC single crystals, etc. In this embodiment, an example is shown in which chip 2 contains a 4H-SiC single crystal, but chip 2 may be made of other polytypes.

[0012] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 is the device surface on which the main structure of the functional device is formed. The second main surface 4 is the non-device surface on the opposite side from the first main surface 3. The first main surface 3 and the second main surface 4 are formed in a rectangular shape in a plan view (hereinafter simply referred to as "plan view") as seen from their normal direction Z. The normal direction Z is also the thickness direction of the chip 2. Preferably, the first main surface 3 and the second main surface 4 are formed by the c-plane of a SiC single crystal.

[0013] In this case, it is preferable that the first main surface 3 is formed by the silicon surface of the SiC single crystal, and the second main surface 4 is formed by the carbon surface of the SiC single crystal. The first main surface 3 and the second main surface 4 may have an off-angle that is inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane. The off-direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off-angle may be greater than 0° and less than or equal to 10°. The off-angle is preferably 5° or less. The second main surface 4 may consist of a ground surface having grinding marks, or it may consist of a smooth surface without grinding marks.

[0014] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The third side surface 5C and the fourth side surface 5D extend in a second direction Y and face the first direction X. The first direction X may be the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y may be the a-axis direction of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal. The first to fourth side surfaces 5A to 5D may consist of ground surfaces having grinding marks, or they may consist of smooth surfaces without grinding marks.

[0015] The chip 2 may have a thickness of 50 μm or more and 600 μm or less. The thickness of the chip 2 may be set to a value that falls within one of the following ranges: 50 μm or more and 100 μm or less, 100 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, 400 μm or more and 500 μm or less, and 500 μm or more and 600 μm or less.

[0016] The first to fourth sides 5A to 5D may have a length of 0.5 mm or more and 20 mm or less in a plan view. The length of the first to fourth sides 5A to 5D may be set to a value that falls within one of the following ranges: 0.5 mm or more and 5 mm or less, 5 mm or more and 10 mm or less, 10 mm or more and 15 mm or less, and 15 mm or more and 20 mm or less. Preferably, the length of the first to fourth sides 5A to 5D is 5 mm or more.

[0017] The semiconductor device 1A includes an n-type (first conductivity type) substrate 6 formed in the region on the second main surface 4 side within the chip 2. The substrate 6 is formed in layers extending along the second main surface 4 and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the substrate 6 is exposed from the entire area of ​​the second main surface 4. In other words, the substrate 6 forms the second main surface 4. In this embodiment, the substrate 6 is made of a SiC substrate (semiconductor substrate). The substrate 6 may also be referred to as the "base region" located on the second main surface 4 side of the chip 2.

[0018] The semiconductor device 1A includes an n-type epitaxial layer 33 formed inside the chip 2 in the region on the first main surface 3 side relative to the substrate 6. In this embodiment, the epitaxial layer 33 is made of a SiC epitaxial layer.

[0019] The epitaxial layer 33 includes a high-drift concentration region 7 and a drift region 8. The high-drift concentration region 7 is formed in a layered manner that extends along the substrate 6 so as to be connected to the substrate 6, and is exposed from the first to fourth side surfaces 5A to 5D. In this embodiment, the high-drift concentration region 7 consists of an epitaxial layer (specifically, a SiC epitaxial layer) laminated on the substrate 6 (SiC substrate).

[0020] The drift region 8 is formed in a layered manner, extending along the substrate 6 so as to be connected to the high-concentration drift region 7, and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. In this embodiment, the drift region 8 is exposed from the entire area of ​​the first main surface 3. In other words, the drift region 8 forms the first main surface 3. In this embodiment, the drift region 8 consists of an epitaxial layer (specifically, a SiC epitaxial layer) laminated on top of the high-concentration drift region 7 (epitaxial layer).

[0021] The specific configurations of the substrate 6, the high-concentration drift region 7, and the drift region 8 will be described below with reference to Figures 3 to 5. Figures 3 to 5 are diagrams illustrating the first to third examples of the concentration distribution of n-type impurities within the chip 2, respectively.

[0022] Figures 3 to 5 show the arrangement of each impurity region in the chip 2 on the left side of the page, and the concentration profile 11 of n-type impurities on the right side of the page. In Figures 3 to 5, the arrows extending to the right side of the page indicate the concentration of n-type impurities, with higher concentrations to the right. The arrows extending to the bottom of the page indicate the depth of the chip 2 from the first main surface 3, with deeper areas to the bottom. The concentration profile 11 may be the result of a concentration distribution obtained by, for example, SIMS (Secondary Ion Mass Spectrometry). The concentration profile 11 may also show the shape after removing detection noise from the profile actually obtained by SIMS.

[0023] The concentration profiles 11 in FIGS. 3 and 5 include a first flat portion 12, a first convex portion 13, a first transition portion 14, and a second flat portion 15. The first flat portion 12, the first convex portion 13, the first transition portion 14, and the second flat portion 15 are continuous in this order from the second main surface 4 side toward the first main surface 3 side. The concentration profile 11 in FIG. 4 does not have the first convex portion 13, and the first flat portion 12, the first transition portion 14, and the second flat portion 15 are continuous in this order from the second main surface 4 side toward the first main surface 3 side.

[0024] The first flat portion 12 exhibits a substantially constant concentration value from the second main surface 4 side toward the first main surface 3 side. "Substantially constant" may be a profile in which the concentration error is 10% or less, preferably 5% or less, particularly preferably 3% or less in the thickness range of the chip 2 constituting the first flat portion 12. The concentration error may be calculated by the following formula. Since the concentration error in the following is calculated in the same manner, the description of the calculation method is omitted.

[0025] Concentration error (%) = standard deviation / average concentration in the target interval × 100 (%) The first flat portion 12 exhibits an n-type first concentration C1. The first concentration C1 is adjusted to a substantially constant value from the second main surface 4 side toward the first main surface 3 side. The first concentration C1 is in the range of 1.0×10 １８ cm －３ or more and 1.0×10 ２１ cm －３ or less. The first concentration C1 may be set in the range of 1.0×10 １８ cm －３ or more and 1.0×10 １９ cm －３ or less. Preferably, the first concentration C1 is set in the range of 0.9×10 １８ cm －３ or more and 2.0×10 １８ cm －３ or less.

[0026] The first flat section 12 may indicate the concentration value of the substrate 6, or it may indicate the concentration values ​​of the substrate 6 and the drift high-concentration region 7. The first flat section 12 may indicate only the total concentration value of the substrate 6 (see Figure 3), or it may indicate the total concentration value of the substrate 6 and the drift high-concentration region 7 (see Figure 4), or it may indicate the concentration value of the substrate 6 and a part of the drift high-concentration region 7 (see Figure 5). In the case of Figure 3, the first concentration C1 indicated by the first flat section 12 may be called "substrate concentration," "base concentration," etc.

[0027] Referring to Figures 3 and 5, the first protrusion 13 is a portion that selectively protrudes from the first flat portion 12 and the second flat portion 15. The first protrusion 13 is convex in shape, with the impurity concentration at the end on the first main surface 3 side being lower than the impurity concentration at the end on the second main surface 4 side. The first protrusion 13 includes a first apex 16, a first side portion 17 on the second main surface 4 side relative to the first apex 16, and a second side portion 18 on the first main surface 3 side relative to the first apex 16.

[0028] The first apex 16 exhibits a substantially constant density value from the second main surface 4 side toward the first main surface 3 side. "Substantially constant" means that the density error in the thickness section of the chip 2 constituting the first apex 16 may be 10% or less, preferably 5% or less, and particularly preferably 3% or less. The first apex 16 may also be referred to as a "flat apex," "fourth flat section," etc.

[0029] The first apex 16 exhibits an n-type second concentration C2. The second concentration C2 may also be referred to as the "recombination concentration," "hole-killer concentration," etc. The second concentration C2 is adjusted to a nearly constant value from the second main surface 4 side towards the first main surface 3 side. The second concentration C2 is higher than the impurity concentration (first concentration C1) of the substrate 6. The second concentration C2 is 1.5 × 10⁻⁶ １８ cm －３ The above 1.0 x 10 ２１ cm －３ The following range may be used: The second concentration C2 is 1.5 × 10 １８ cm －３ The above 1.5 x 10 １９ cm －３It is preferable to set the second concentration C2 to 1.5 × 10⁻⁶. １８ cm －３ The above 2.0 x 10 １８ cm －３ The following is also acceptable.

[0030] The first peak 16 indicates the concentration value of the drift high-concentration region 7. The first peak 16 may indicate only the total concentration value of the drift high-concentration region 7 (see Figure 3), or it may indicate the concentration value of a part of the drift high-concentration region 7 (see Figure 5).

[0031] In the case of Figure 5, the boundary between the first flat portion 12 and the first apex portion 16 may be further toward the first main surface 3 than the boundary between the substrate 6 and the drift high-concentration region 7. The boundary between the first flat portion 12 and the first apex portion 16 may be located within the drift high-concentration region 7 in the thickness direction of the chip 2. In this case, the drift high-concentration region 7 may include a first concentration portion 19 showing a first concentration C1 due to the first flat portion 12 and a second concentration portion 20 showing a second concentration C2 due to the first apex portion 16.

[0032] The first side portion 17 corresponds to the transition portion of the concentration profile 11 where the concentration of n-type impurities changes (increases) from a flat first concentration C1 to a flat second concentration C2. In the first side portion 17, the n-type impurity concentration increases from the first concentration C1 to the second concentration C2. As shown in Figures 3 and 5, the first side portion 17 may rise vertically from the first concentration C1 to the second concentration C2, or it may extend in an upward sloping manner at a constant rate. In either case, the n-type impurity concentration in the first side portion 17 may increase linearly from the first concentration C1 to the second concentration C2.

[0033] The second side portion 18 corresponds to the transition portion of the concentration profile 11 where the concentration of n-type impurities changes (decreases) from a flat second concentration C2 to a flat third concentration C3. The third concentration C3 is the concentration value indicated by the second flat portion 15.

[0034] In this configuration, the drift region 8 includes a first transition region 9 and a retention region 10 formed in this order from the substrate 6 side. The second flat portion 15 indicates the concentration value of the retention region 10, and the second side portion 18 indicates the concentration value of the first transition region 9.

[0035] The second flat portion 15 exhibits a substantially constant density value from the second main surface 4 side toward the first main surface 3 side. "Substantially constant" may mean a profile in which the density error in the thickness section of the chip 2 constituting the second flat portion 15 is 10% or less, preferably 5% or less, and particularly preferably 3% or less.

[0036] The third concentration C3 is less than the impurity concentration of the substrate 6 (first concentration C1). The third concentration C3 is 1.0 × 10⁻⁶ １４ cm －３ The above 1.0 x 10 １７ cm －３ The following range may be used: The third concentration C3 is 1.0 × 10 １５ cm －３ The above 1.0 x 10 １７ cm －３ It is preferable to set it within the following range: The third concentration C3 is 4.0 × 10 １５ cm －３ The above 2.0 x 10 １６ cm －３ The following is also possible. The third concentration C3 may be called the "drift concentration," "epitaxial concentration," etc.

[0037] The second side portion 18 corresponds to the first transition portion 14 in this configuration. In the first transition portion 14 (second side portion 18), the n-type impurity concentration decreases from the second concentration C2 to the third concentration C3. The first transition portion 14 may extend in a downward sloping manner from the second concentration C2 to the third concentration C3, as shown in Figures 3 and 5. In the first transition portion 14, the n-type impurity concentration may decrease linearly from the second concentration C2 to the third concentration C3.

[0038] A more detailed explanation will be given regarding the slope of the first transition section 14. In this configuration, the first transition region 9, where the concentration profile is defined by the first transition section 14, gradually decreases from the second concentration C2 to the third concentration C3 toward the first main surface 3. More specifically, in the first transition region 9, the n-type impurity concentration changes in the depth direction of the chip 2 with a predetermined first concentration gradient S1. The first concentration gradient S1 is d(log １０ ND １It is expressed as (x) / dx, and it is particularly preferable that it satisfies equation (1) below and equation (1') below. d(log １０ ND １ (x)) / dx<2log １０ (cm －３ ) / μm...(1) d(log １０ ND １ (x)) / dx<1log １０ (cm －３ ) / μm...(1')

[0039] In the above equation, ND １ (x) is the donor concentration of the first transition region 9 at depth x, and x is the depth from the first main surface 3. ND １ When Nt shows an impurity concentration of a different conductivity type than n-type, １ It may also be indicated as follows.

[0040] More specifically, the concentration ND of the first transition region 9 １ (cm －３ The common logarithm of ) １０ ND １ (log １０ (cm －３ The value obtained by differentiating ) with respect to the depth x (μm) from the first main surface 3 is 2 (log １０ (cm －３ It is preferable that it is smaller than ) / μm, and 1 (log １０ (cm －３ It is particularly preferable that it be smaller than ) / μm).

[0041] With respect to the thickness of each impurity region of the chip 2, the substrate 6 may have a thickness of 50 μm or more and 500 μm or less. The thickness of the substrate 6 may be 400 μm or less, 300 μm or less, 200 μm or less, or 100 μm or less. By reducing the thickness of the substrate 6, the resistance value caused by the substrate 6 within the chip 2 can be reduced.

[0042] The drift high-concentration region 7 is preferably thinner than the substrate 6. The drift high-concentration region 7 may have a thickness of 1 μm or more and 5 μm or less. The thickness of the drift high-concentration region 7 is preferably 1 μm or more and 3 μm or less. As shown in Figure 5, if the drift high-concentration region 7 includes a first concentration portion 19 and a second concentration portion 20, the thickness of the first concentration portion 19 is preferably thinner than that of the second concentration portion 20. The thickness of the first concentration portion 19 is, for example, 0.1 μm or more and 50 μm or less, and preferably 0.5 μm or more and 1 μm or less. The thickness of the second concentration portion 20 is, for example, 0.1 μm or more and 50 μm or less, and preferably 0.5 μm or more and 1 μm or less.

[0043] The drift region 8 is preferably thicker than the high-concentration drift region 7 and thinner than the substrate 6. The drift region 8 may have a thickness of 1 μm or more and 50 μm or less. The thickness of the drift region 8 is preferably 3 μm or more and 30 μm or less. The thickness of the drift region 8 is particularly preferably 25 μm or less.

[0044] Of the drift region 8, the first transition region 9 is preferably thinner than the retention region 10. The thickness of the first transition region 9 may be 1 μm or more. The thickness of the first transition region 9 is preferably 1 μm or more and 5 μm or less. The thickness of the first transition region 9 is particularly preferably 1 μm or more and 3 μm or less. The thickness of the retention region 10 is preferably 2 μm or more and 40 μm or less. The thickness of the retention region 10 is particularly preferably 4 μm or more and 20 μm or less.

[0045] Referring again to Figure 2, the semiconductor device 1A includes an n-type diode region 21 formed on the first main surface 3. The diode region 21 is formed on the surface of the drift region 8. Specifically, the diode region 21 is formed on the surface of the drift region 8, utilizing a part of the drift region 8.

[0046] The semiconductor device 1A includes a p-type (second conductivity type) guard region 22 formed on the surface layer of the first main surface 3 along the diode region 21. In this embodiment, the guard region 22 is formed on the surface layer of the drift region 8 so as to demarcate the diode region 21 from the peripheral edge side of the first main surface 3. In a plan view, the guard region 22 is formed in a band shape extending along the diode region 21. In a plan view, the guard region 22 is formed in an annular shape (a rectangular annular shape in this embodiment) surrounding the diode region 21.

[0047] The semiconductor device 1A includes at least one (preferably two to twenty) p-type field regions 23 formed in the surface layer of the first main surface 3 in the region between the periphery of the first main surface 3 and the guard region 22. In this embodiment, the semiconductor device 1A includes four field regions 23.

[0048] In this configuration, multiple field regions 23 are formed on the surface of the drift region 8. The multiple field regions 23 relax the electric field within the chip 2 at the periphery of the first main surface 3. The number, width, depth, and p-type impurity concentration of the field regions 23 are arbitrary and can take various values ​​depending on the electric field to be relaxed.

[0049] Multiple field regions 23 are arranged with gaps between them, extending from the guard region 22 towards the periphery of the first main surface 3. In a plan view, the multiple field regions 23 are formed in a band shape extending along the periphery of the first main surface 3. In this configuration, in a plan view, the multiple field regions 23 are formed in an annular shape (specifically, a rectangular annular shape) surrounding the diode region 21 (guard region 22).

[0050] The semiconductor device 1A includes an insulating film 24 that selectively covers the first main surface 3. The insulating film 24 covers a plurality of field regions 23 at the peripheral edge of the first main surface 3 and has contact openings 25 that expose the inner edges of the diode region 21 and the guard region 22 in the inner part of the first main surface 3.

[0051] The insulating film 24 may be continuous with the periphery of the first main surface 3 and form a single grinding surface with the first to fourth side surfaces 5A to 5D. Of course, the insulating film 24 may be formed with a gap inward from the periphery of the first main surface 3, exposing the drift region 8 from the periphery of the first main surface 3.

[0052] The semiconductor device 1A includes a first polar electrode 26 (first main surface electrode) disposed on the first main surface 3. The first polar electrode 26 may also be called an "anode electrode". The first polar electrode 26 is positioned at a distance from the periphery of the first main surface 3 inward. In this embodiment, the first polar electrode 26 is formed in a rectangular shape along the periphery of the first main surface 3 in a plan view. The first polar electrode 26 enters the contact opening 25 from above the insulating film 24 and is electrically connected to the inner edges of the diode region 21 and the guard region 22. In other words, the first polar electrode 26 is electrically connected to the drift region 8 within the contact opening 25.

[0053] The first polar electrode 26 forms a Schottky junction with the diode region 21 (i.e., the drift region 8). This forms an SBD structure 27 as an example of a device structure. The planar area of ​​the first polar electrode 26 is preferably 50% or more of the first main surface 3. The planar area of ​​the first polar electrode 26 is particularly preferably 75% or more of the first main surface 3. The first polar electrode 26 may have a thickness of 0.5 μm or more and 15 μm or less. The first polar electrode 26 is preferably thicker than the insulating film 24.

[0054] The semiconductor device 1A includes a second polar electrode 28 (second main surface electrode) that covers the second main surface 4. The second polar electrode 28 may also be called a "cathode electrode". The second polar electrode 28 forms ohmic contact with the substrate 6 exposed from the second main surface 4. The second polar electrode 28 may cover the entire area of ​​the second main surface 4 so as to be continuous with the periphery of the chip 2 (first to fourth side surfaces 5A to 5D). The second polar electrode 28 may cover the second main surface 4 with a gap inward from the periphery of the chip 2.

[0055] The breakdown voltage that can be applied between the first polar electrode 26 and the second polar electrode 28 may be between 500V and 3000V. In other words, the chip 2 may be formed so that a breakdown voltage of between 500V and 3000V is applied between the first main surface 3 and the second main surface 4. Depending on the voltage application conditions, the chip 2 is formed such that the electric field strength on the first main surface 3 side, which is the device surface, is higher than the electric field strength on the second main surface 4 side, which is the non-device surface.

[0056] One known cause of accidental failures in semiconductor devices is Single Event Burnout (SEB), which is caused by cosmic rays that bombard the Earth from space. Cosmic rays that bombard the Earth cause nuclear decomposition reactions with the nuclei of atoms that make up the atmosphere, producing neutrons, which are relatively penetrating and difficult-to-shield radiation (high-energy particles).

[0057] Neutrons colliding with semiconductor devices cause electric field anomalies within the device, generating localized overvoltages and overcurrents. This results in SEB breakdown. SEB breakdown occurs with an extremely low probability, but its mode of breakdown is often fatal. In particular, SEB breakdown tends to be caused by dynamic avalanche breakdown occurring in high-electric field areas within semiconductor devices.

[0058] The inventors of this application have found that SEB breakdown at the boundary between high-concentration impurity regions and low-concentration impurity regions is the rate-limiting factor in the SEB failure rate. For example, n ＋ n on a substrate of type － When type 1 epitaxial layers are stacked, n ＋ / n － It was found that SEB failure is likely to occur at the joint.

[0059] Therefore, in semiconductor device 1A, n ＋ Type substrate 6 and n － A first transition region 9 is interposed between the drift region 8 (epitaxial layer 33) and the n-type impurity. In the first transition region 9, the n-type impurity concentration changes in the depth direction of the chip 2 with a predetermined first concentration gradient S1. The first concentration gradient S1 is d(log １０ ND １It is expressed as (x) / dx, and it is particularly preferable that it satisfies equation (1) below and equation (1') below. d(log １０ ND １ (x)) / dx<2log １０ (cm －３ ) / μm...(1) d(log １０ ND １ (x)) / dx<1log １０ (cm －３ ) / μm...(1') (where ND １ (x) is the concentration of the first transition region 9 at depth x, and x is the depth from the first main surface 3.

[0060] By setting the first concentration gradient S1 of the first transition region 9 to the above conditions, the electric field strength between the substrate 6 and the drift region 8 can be reduced. As a result, n ＋ / n － This can increase the cosmic ray tolerance (SEB fracture tolerance) at the joint.

[0061] Furthermore, the SiC single crystals constituting the substrate 6 and the drift region 8 contain various crystal defects. These crystal defects include, for example, basal plane dislocations. Basal plane dislocations are abundant in the substrate 6 (SiC substrate) and less abundant in the drift region 8 (SiC epitaxial layer). Therefore, they may expand toward the first main surface 3, leading to stacking faults. One example of an expansion factor is the arrival of holes injected into the drift region 8 at basal plane dislocations during parasitic diode operation. Since stacking faults caused by the expansion of basal plane dislocations are one of the factors contributing to bipolar degradation (such as increased on-resistance), it is preferable to suppress their occurrence as much as possible.

[0062] Therefore, in this semiconductor device 1A, a high-concentration drift region 7 is interposed between the substrate 6 and the drift region 8. Since the high-concentration drift region 7 consists of a part of the SiC epitaxial layer, it is a region in the chip 2 with fewer basal plane dislocations than the substrate 6. As a result, many holes are eliminated by recombining with electrons within the high-concentration drift region 7, which has a high donor concentration, and the number of holes reaching the substrate 6, which has a relatively large number of basal plane dislocations, can be reduced. Consequently, basal plane dislocations are less likely to expand, and bipolar degradation can be suppressed.

[0063] Chip 2 preferably contains a single crystal of a wide-bandgap semiconductor. This structure makes it possible to provide a wide-bandgap semiconductor device (semiconductor device 1A) as a power semiconductor device to which high voltage and high electric field can be applied. Since wide-bandgap semiconductor devices are used in high-voltage and high-electric field environments, the risk of SEB breakdown is higher than that of Si semiconductor devices. In this respect, semiconductor device 1A can improve cosmic ray tolerance by reducing the electric field strength due to the first transition region 9, thereby suppressing SEB breakdown. Therefore, reliability can be improved even when semiconductor device 1A consists of a wide-bandgap semiconductor device.

[0064] Furthermore, the semiconductor device 1A, as a wide-bandgap semiconductor device, can indirectly improve the reliability of the application in which it is installed by reducing the risk of SEB failure. For example, by installing the semiconductor device 1A as a wide-bandgap semiconductor device in vehicles that use motors as a power source, such as hybrid vehicles, electric vehicles, and fuel cell vehicles, it is possible to reduce the power consumption of these applications while enhancing safety.

[0065] Chip 2 preferably includes a SiC single crystal as an example of a wide-bandgap semiconductor single crystal. In this case, a SiC semiconductor device (semiconductor device 1A) with excellent reliability can be provided. The breakdown voltage that can be applied between the first main surface 3 and the second main surface 4 may be 500V or more and 3000V or less. Chip 2 may have a thickness of 200 μm or less. Preferably, Chip 2 has a thickness of 150 μm or less.

[0066] The chip 2 may have a first main surface 3 with a planar area of ​​1 mm square or more. A chip 2 with a relatively large planar area improves current processing capability, thus improving electrical characteristics. However, increasing the planar area of ​​the chip 2 increases the risk of cosmic ray collision. In this regard, the drift region 8 can improve cosmic ray tolerance by reducing the electric field strength on the side of the first main surface 3 with a relatively large planar area. Therefore, even when a first main surface 3 with a relatively large planar area is used, SEB breakdown can be suppressed.

[0067] The drift region 8 may form the first main surface 3. In this case, the semiconductor device 1A may include a first polar electrode 26 disposed on the drift region 8 so as to form a Schottky junction with the drift region 8. This structure provides a semiconductor device 1A equipped with an SBD structure 27. The semiconductor device 1A may also include a second polar electrode 28 disposed on the second main surface 4. This structure provides a semiconductor device 1A equipped with a vertical SBD structure 27 in which a forward current flows from the first main surface 3 to the second main surface 4.

[0068] Figure 6 is a cross-sectional view showing a semiconductor device 1B according to the second embodiment. Referring to Figure 6, in this embodiment, the semiconductor device 1B includes an n-type surface drift region 29 formed in the region on the first main surface 3 side relative to the drift region 8 within the chip 2. The surface drift region 29 is formed in layers extending along the drift region 8 so as to be connected to the drift region 8, and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. In this embodiment, the surface drift region 29 is exposed from the entire area of ​​the first main surface 3. In other words, the surface drift region 29 forms the first main surface 3.

[0069] In this configuration, the surface drift region 29 consists of an epitaxial layer (specifically, a SiC epitaxial layer) stacked on top of the drift region 8 (epitaxial layer).

[0070] Hereinafter, referring to FIGS. 7 to 9, the specific configuration of the surface drift region 29 will be described. FIGS. 7 to 9 are diagrams for explaining the fourth to sixth morphological examples of the concentration distribution of n-type impurities in the chip 2, respectively. FIG. 7 corresponds to the concentration profile 11 in FIG. 3, FIG. 8 corresponds to the concentration profile 11 in FIG. 4, and FIG. 9 corresponds to the concentration profile 11 in FIG. 5.

[0071] Referring to FIGS. 7 to 9, the concentration profile 11 further includes a second transition portion 30 and a third flat portion 31.

[0072] The second transition portion 30 corresponds to a transition portion of the concentration profile 11 where the concentration of n-type impurities changes (increases) from the flat third concentration C3 to the flat fourth concentration C4. The fourth concentration C4 is the concentration value indicated by the third flat portion 31.

[0073] The third flat portion 31 may indicate the concentration value of the surface drift region 29. The third flat portion 31 indicates a substantially constant concentration value from the second main surface 4 side toward the first main surface 3 side. "Substantially constant" may be a profile in which the concentration error is 10% or less, preferably 5% or less, and particularly preferably 3% or less in the thickness interval of the chip 2 constituting the third flat portion 31.

[0074] The fourth concentration C4 is higher than the impurity concentration (third concentration C3) of the drift region 8. The fourth concentration C4 may be set in the range of 1.0×10 １５ cm －３ or more and 1.0×10 １８ cm －３ or less. The fourth concentration C4 may be set in the range of 1.0×10 １５ cm －３ or more and 1.0×10 １７ cm －３ or less is preferable. The fourth concentration C4 may be in the range of 7.5×10 １５ cm －３ or more and 2.0×10 １６ cm －３ or less. The fourth concentration C4 may be referred to as the "surface drift concentration", the "cap concentration", etc.

[0075] In the second transition section 30, the n-type impurity concentration increases from the third concentration C3 to the fourth concentration C4. As shown in FIGS. 7 to 9, the second transition section 30 may extend in an upwardly inclined shape from the third concentration C3 to the fourth concentration C4. In the second transition section 30, the n-type impurity concentration may increase linearly from the third concentration C3 to the fourth concentration C4.

[0076] A more detailed explanation of the slope of the second transition section 30 will be given. In this form, the second transition region 32 defined by the concentration profile by the second transition section 30 gradually increases from the third concentration C3 to the fourth concentration C4 toward the first main surface 3 side. More specifically, in the second transition region 32, the n-type impurity concentration changes with a predetermined second concentration gradient S2 in the depth direction of the chip 2. The second concentration gradient S2 is represented by d(log １０ ND ２ (x)) / dx, and it is particularly preferable that it satisfies the following formula (2) and the following formula (2'). d(log １０ ND ２ (x)) / dx < 2 log １０ (cm －３ ) / μm... (2) d(log １０ ND ２ (x)) / dx < 1 log １０ (cm －３ ) / μm... (2')

[0077] In the above formula, ND ２ (x) is the donor concentration of the second transition region 32 at the depth x, and x is the depth from the first main surface 3. When ND ２ represents the impurity concentration of a conductivity type different from the n-type, it may be denoted as Nt ２ .

[0078] More specifically, the value obtained by differentiating the common logarithm value log ２ ND －３ (cm １０ ) of the concentration ND ２ (log １０ (cm －３ ) with respect to the depth x (μm) from the first main surface 3 is preferably smaller than 2 (log １０ (cm －３ ) / μm), and 1 (log １０ (cm－３ It is particularly preferable that it be smaller than ) / μm).

[0079] With respect to the thickness of each impurity region of the chip 2, the surface drift region 29 is preferably thicker than the high drift concentration region 7. The thickness of the surface drift region 29 is preferably less than the thickness of the drift region 8. The thickness of the surface drift region 29 may be 1 μm or more and 10 μm or less. The thickness of the surface drift region 29 is preferably 3 μm or more and 5 μm or less.

[0080] The second transition region 32 is preferably thinner than the first transition region 9. The thickness of the second transition region 32 may be 0.5 μm or more. The thickness of the second transition region 32 is preferably 0.5 μm or more and 3 μm or less. The thickness of the second transition region 32 is particularly preferably 0.5 μm or more and 1 μm or less.

[0081] As described above, in semiconductor device 1B, a surface drift region 29 with a higher density than the drift region 8 is formed on the surface of the first main surface 3, which is the device surface. This makes it possible to reduce the resistance of the path through which the forward current flows.

[0082] Furthermore, in semiconductor device 1B, n ＋ The surface drift region 29 and n － A second transition region 32 is interposed between the drift region 8 and the n-type impurity region. In the second transition region 32, the n-type impurity concentration changes in the depth direction of the chip 2 with a predetermined second concentration gradient S2. The second concentration gradient S2 is d(log １０ ND ２ It is expressed as (x) / dx, and it is particularly preferable that it satisfies equation (2) below and equation (2') below. d(log １０ ND ２ (x)) / dx<2log １０ (cm －３ ) / μm...(2) d(log １０ ND ２ (x)) / dx<1log １０ (cm －３ ) / μm...(2') (where ND ２ (x) is the concentration of the second transition region 32 at depth x, and x is the depth from the first main surface 3.

[0083] By setting the second concentration gradient S2 of the second transition region 32 to the above conditions, the electric field strength between the surface drift region 29 and the drift region 8 can be reduced. As a result, n ＋ / n － This can increase the cosmic ray tolerance (SEB fracture tolerance) at the joint.

[0084] Figure 10 is a plan view showing the semiconductor device 1C according to the third embodiment. Figure 11 is a cross-sectional view along the line XI-XI shown in Figure 10. Figure 12 is a plan view showing the main part of the semiconductor device 1C shown in Figure 10. Figure 13 is a cross-sectional view along the line XII-XII shown in Figure 12. Figure 14 is an enlarged cross-sectional view showing the peripheral edge of the chip 2.

[0085] Referring to Figures 10 to 14, the semiconductor device 1C, like the semiconductor device 1B described above, includes a chip 2, a substrate 6, a high-concentration drift region 7, a drift region 8, and a surface drift region 29. A first transition region 9 is interposed between the high-concentration drift region 7 and the drift region 8 (holding region 10), and a second transition region 32 is interposed between the drift region 8 (holding region 10) and the surface drift region 29 (see Figures 7 to 9).

[0086] The semiconductor device 1C includes an active surface 41, an outer surface 42, and first to fourth connecting surfaces 43A to 43D formed on the first main surface 3. The active surface 41, the outer surface 42, and the first to fourth connecting surfaces 43A to 43D define a mesa portion 44 (plateau) on the first main surface 3.

[0087] The active surface 41 may be referred to as the "first surface portion," the outer surface 42 as the "second surface portion," and the first to fourth connecting surfaces 43A to 43D as the "connecting surface portion." The active surface 41, the outer surface 42, and the first to fourth connecting surfaces 43A to 43D (i.e., the mesa portion 44) may be considered components of the tip 2 (first main surface 3).

[0088] The active surface 41 is formed in the inner part of the first main surface 3, spaced apart from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The active surface 41 is formed by a surface drift region 29. The active surface 41 has a flat surface extending in the first direction X and the second direction Y. In this embodiment, the active surface 41 is formed in a quadrilateral shape with four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.

[0089] The outer surface 42 is located at the periphery of the first main surface 3 and is recessed in the thickness direction of the tip 2 (towards the second main surface 4) from the active surface 41. The outer surface 42 is recessed to a depth less than the thickness of the surface drift region 29 so as to expose the surface drift region 29.

[0090] The outer surface 42 extends in a band shape along the active surface 41 in a plan view and is formed in an annular shape (specifically, a square annular shape) surrounding the active surface 41. The outer surface 42 has a flat surface extending in the first direction X and the second direction Y and is formed substantially parallel to the active surface 41. The outer surface 42 is continuous with the first to fourth outer surfaces 5A to 5D.

[0091] The first connecting surface 43A is located on the first side surface 5A side, the second connecting surface 43B is located on the second side surface 5B side, the third connecting surface 43C is located on the third side surface 5C side, and the fourth connecting surface 43D is located on the fourth side surface 5D side. The first connecting surface 43A and the second connecting surface 43B extend in the first direction X and face the second direction Y. The third connecting surface 43C and the fourth connecting surface 43D extend in the second direction Y and face the first direction X.

[0092] The first to fourth connecting surfaces 43A to 43D extend in the normal direction Z and connect the active surface 41 and the outer surface 42. The first to fourth connecting surfaces 43A to 43D are formed by a surface drift region 29.

[0093] The first to fourth connecting surfaces 43A to 43D may extend substantially vertically between the active surface 41 and the outer surface 42 so as to define the rectangular prism-shaped mesa portion 44. The first to fourth connecting surfaces 43A to 43D may also be inclined diagonally downward from the active surface 41 toward the outer surface 42 so as to define the pyramidal cone-shaped mesa portion 44.

[0094] Thus, the semiconductor device 1C includes a mesa portion 44 formed in the surface drift region 29 on the first main surface 3. The mesa portion 44 is formed only in the surface drift region 29 and does not expose the drift region 8.

[0095] As an example of a device structure, semiconductor device 1C includes a MISFET (Metal Insulator Semiconductor Field Effect Transistor) structure 50 formed on the active surface 41 (first main surface 3). In Figure 11, the MISFET structure 50 is shown in a simplified form with dashed lines. The MISFET structure 50 and the structure on the outer surface 42 will be described in detail below.

[0096] Referring to Figures 12 to 14, the MISFET structure 50 includes a p-type (second conductivity type) body region 51 formed on the surface of the active surface 41. The body region 51 is formed on the surface of the surface drift region 29, spaced apart from the drift region 8 toward the active surface 41. The body region 51 may be exposed from parts of the first to fourth connection surfaces 43A to 43D.

[0097] The MISFET structure 50 includes an n-type source region 52 formed on the surface of the body region 51. The source region 52 has a higher n-type impurity concentration than the surface drift region 29. The source region 52 is formed with a gap between the bottom of the body region 51 and the active surface 41.

[0098] The source region 52 is formed in a layered manner, extending along the active surface 41. The source region 52 may be exposed from the entire area of ​​the active surface 41. The source region 52 may be exposed from a portion of the first to fourth connecting surfaces 43A to 43D. The source region 52 forms a channel within the body region 51 between itself and the surface drift region 29.

[0099] The MISFET structure 50 includes a plurality of trench gate structures 53 formed on the active surface 41. The plurality of trench gate structures 53 are arranged at intervals in the first direction X in a plan view and are each formed in a strip shape extending in the second direction Y. The plurality of trench gate structures 53 are formed on the surface of the surface drift region 29 at intervals from the drift region 8 toward the active surface 41. The plurality of trench gate structures 53 control the inversion and non-inversion of channels within the body region 51.

[0100] Each trench gate structure 53 in this embodiment includes a gate trench 53a, a gate insulating film 53b, and a gate embedded electrode 53c. The gate trench 53a is formed on the active surface 41 and defines the wall surface of the trench gate structure 53. The gate insulating film 53b covers the wall surface of the gate trench 53a. The gate embedded electrode 53c is embedded in the gate trench 53a with the gate insulating film 53b in between and faces the channel with the gate insulating film 53b in between.

[0101] The MISFET structure 50 includes a plurality of trench source structures 54 formed on the active surface 41. The plurality of trench source structures 54 are each located in the region between a pair of adjacent trench gate structures 53 on the active surface 41. The plurality of trench source structures 54 are each formed in a strip shape extending in the second direction Y in a plan view. The plurality of trench source structures 54 are formed on the surface of the surface drift region 29, spaced apart from the drift region 8 toward the active surface 41.

[0102] The multiple trench source structures 54 are formed deeper than the trench gate structures 53. The multiple trench source structures 54 may have a depth of 1.5 to 4 times the depth of the multiple trench gate structures 53. Preferably, the depth of the multiple trench source structures 54 is 2.5 times or less the depth of the multiple trench gate structures 53. In this embodiment, the multiple trench source structures 54 have a depth approximately equal to the depth of the outer surface 42. Of course, the multiple trench source structures 54 may have a depth approximately equal to the depth of the multiple trench gate structures 53.

[0103] Each trench source structure 54 includes a source trench 54a, a source insulating film 54b, and a source embedded electrode 54c. The source trench 54a is formed on the active surface 41 and defines the wall surface of the trench source structure 54. The source insulating film 54b covers the wall surface of the source trench 54a. The source embedded electrode 54c is embedded in the source trench 54a with the source insulating film 54b in between.

[0104] The MISFET structure 50 includes a plurality of p-type contact regions 60 formed in regions along the plurality of trench source structures 54 within the chip 2. The plurality of contact regions 60 have a higher p-type impurity concentration than the body region 51. Each contact region 60 covers the sidewall and bottom wall of each trench source structure 54 and is electrically connected to the body region 51. Each contact region 60 is formed within the surface drift region 29, spaced apart from the drift region 8 toward the active surface 41.

[0105] The MISFET structure 50 includes a plurality of p-type well regions 61 formed in regions along a plurality of trench source structures 54 within the chip 2. Each well region 61 may have a p-type impurity concentration higher than that of the body region 51 and lower than that of the contact region 60. Each well region 61 covers the corresponding trench source structure 54, sandwiching the corresponding contact region 60.

[0106] Each well region 61 covers the side and bottom walls of the corresponding trench source structure 54 and is electrically connected to the body region 51 and the contact region 60. Each well region 61 is formed within the surface drift region 29, spaced apart from the drift region 8 toward the active surface 41.

[0107] Referring to Figure 14, the semiconductor device 1C includes a p-type outer contact region 62 formed on the surface layer of the outer surface 42. The outer contact region 62 has a p-type impurity concentration that exceeds the p-type impurity concentration of the body region 51. Preferably, the outer contact region 62 has a p-type impurity concentration that is approximately equal to the p-type impurity concentration of the contact region 60.

[0108] The outer contact region 62 is formed at a distance from the periphery of the active surface 41 and the periphery of the outer surface 42 in a plan view, and is formed in a band shape that extends along the active surface 41. In this configuration, the outer contact region 62 is formed in an annular shape (specifically, a rectangular annular shape) that surrounds the active surface 41 in a plan view.

[0109] The outer contact region 62 is formed on the surface of the surface drift region 29, spaced apart from the drift region 8 towards the outer surface 42. The outer contact region 62 is located on the bottom side of the surface drift region 29 relative to the bottom walls of the multiple trench gate structures 53 (trench source structures 54).

[0110] The semiconductor device 1C includes a p-type outer well region 63 formed on the surface layer of the outer surface 42. The outer well region 63 has a p-type impurity concentration lower than that of the outer contact region 62. Preferably, the p-type impurity concentration of the outer well region 63 is approximately equal to that of the well region 61.

[0111] The outer well region 63 is formed in the region between the active surface 41 and the outer contact region 62 in a plan view, and is formed in a band shape extending along the active surface 41. In this configuration, the outer well region 63 is formed in an annular shape (specifically, a square annular shape) surrounding the active surface 41 in a plan view.

[0112] The outer well region 63 is formed on the surface of the surface drift region 29, spaced apart from the drift region 8 towards the outer surface 42. The outer well region 63 is located on the bottom side of the surface drift region 29 relative to the bottom walls of the multiple trench gate structures 53 (trench source structures 54).

[0113] The outer well region 63 is electrically connected to the outer contact region 62. In this configuration, the outer well region 63 extends from the outer contact region 62 side toward the first to fourth connection surfaces 43A to 43D and covers the first to fourth connection surfaces 43A to 43D. The outer well region 63 is electrically connected to the body region 51 at the surface of the active surface 41.

[0114] The semiconductor device 1C includes at least one (preferably two to twenty) p-type field regions 64 formed in the surface layer of the outer surface 42 in the region between the periphery of the outer surface 42 and the outer contact region 62. In this embodiment, the semiconductor device 1C includes five field regions 64. The multiple field regions 64 mitigate the electric field within the chip 2 on the outer surface 42. The number, width, depth, and p-type impurity concentration of the field regions 64 are arbitrary and can take various values ​​depending on the electric field to be mitigate.

[0115] Multiple field regions 64 are arranged at intervals from the outer contact region 62 to the peripheral edge of the outer surface 42. In a plan view, the multiple field regions 64 are formed in a band shape extending along the active surface 41. In this configuration, the multiple field regions 64 are formed in an annular shape (specifically, a square annular shape) surrounding the active surface 41 in a plan view. The multiple field regions 64 are formed on the surface of the surface drift region 29 at intervals from the drift region 8 to the outer surface 42.

[0116] The multiple field regions 64 are located on the bottom side of the surface drift region 29 relative to the bottom walls of the multiple trench gate structures 53 (trench source structures 54). The multiple field regions 64 may be formed deeper than the outer contact region 62. The innermost field region 64 may be connected to the outer contact region 62.

[0117] The semiconductor device 1C includes a main surface insulating film 70 that covers the first main surface 3. The main surface insulating film 70 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the main surface insulating film 70 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the main surface insulating film 70 includes a silicon oxide film made of the oxide of the chip 2.

[0118] The main surface insulating film 70 covers the active surface 41, the outer surface 42, and the first to fourth connection surfaces 43A to 43D. The main surface insulating film 70 is continuous with the gate insulating film 53b and the source insulating film 54b, and covers the active surface 41 so as to expose the gate embedded electrode 53c and the source embedded electrode 54c. The main surface insulating film 70 covers the outer surface 42 and the first to fourth connection surfaces 43A to 43D so as to cover the outer contact region 62, the outer well region 63, and the multiple field regions 64.

[0119] The main surface insulating film 70 may be continuous with the first to fourth side surfaces 5A to 5D. In this case, the outer wall of the main surface insulating film 70 may form a single grinding surface with the first to fourth side surfaces 5A to 5D. Of course, the outer wall of the main surface insulating film 70 may be formed with a gap inward from the periphery of the outer surface 42, and the surface drift region 29 may be exposed from the periphery of the outer surface 42.

[0120] The semiconductor device 1C includes a sidewall structure 71 formed on the main surface insulating film 70 so as to cover at least one of the first to fourth connecting surfaces 43A to 43D on the outer surface 42. In this embodiment, the sidewall structure 71 is formed in an annular (quadrilateral annular) shape surrounding the active surface 41 in a plan view.

[0121] The sidewall structure 71 may have a portion that overlaps the active surface 41. The sidewall structure 71 may contain an inorganic insulator or polysilicon. The sidewall structure 71 may also be a sidewall wiring electrically connected to the trench source structure 54.

[0122] The semiconductor device 1C includes an interlayer insulating film 72 formed on a main surface insulating film 70. The interlayer insulating film 72 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the interlayer insulating film 72 includes a silicon oxide film. The interlayer insulating film 72 covers the active surface 41, the outer surface 42, and the first to fourth connecting surfaces 43A to 43D with the main surface insulating film 70 in between.

[0123] Specifically, the interlayer insulating film 72 covers the active surface 41, the outer surface 42, and the first to fourth connecting surfaces 43A to 43D via the sidewall structure 71. The interlayer insulating film 72 covers the MISFET structure 50 on the active surface 41 side and covers the outer contact region 62, the outer well region 63, and the multiple field regions 64 on the outer surface 42 side.

[0124] In this embodiment, the interlayer insulating film 72 is continuous with the first to fourth side surfaces 5A to 5D. The outer wall of the interlayer insulating film 72 may form a single grinding surface with the first to fourth side surfaces 5A to 5D. Of course, the outer wall of the interlayer insulating film 72 may be formed with a gap inward from the periphery of the outer surface 42, exposing the surface drift region 29 from the periphery of the outer surface 42.

[0125] The semiconductor device 1C includes a gate electrode 73 disposed on the first main surface 3 (interlayer insulating film 72). The gate electrode 73 is positioned inward of the first main surface 3, spaced apart from its periphery. In this embodiment, the gate electrode 73 is positioned on the active surface 41. Specifically, the gate electrode 73 is positioned in a region of the active surface 41 that is close to the center of the third connecting surface 43C (third side surface 5C) at the periphery.

[0126] In this embodiment, the gate electrode 73 is formed in a rectangular shape in plan view. Of course, the gate electrode 73 may be formed in a polygonal shape other than a rectangle, a circular shape, or an elliptical shape in plan view. Preferably, the gate electrode 73 has a planar area of ​​25% or less of the first main surface 3. The planar area of ​​the gate electrode 73 may be 10% or less of the first main surface 3. The gate electrode 73 may have a thickness of 0.5 μm or more and 15 μm or less.

[0127] The semiconductor device 1C includes a source electrode 74 disposed on the first main surface 3 (interlayer insulating film 72) at a distance from the gate electrode 73. The source electrode 74 is disposed in the inner part of the first main surface 3 at a distance from the periphery of the first main surface 3. In this embodiment, the source electrode 74 is disposed on the active surface 41. In this embodiment, the source electrode 74 has a main electrode portion 75 and at least one (multiple in this embodiment) lead-out electrode portions 76A, 76B.

[0128] The main electrode portion 75 is positioned in the region on the fourth side surface 5D (fourth connection surface 43D) side, spaced apart from the gate electrode 73 in a plan view, and faces the gate electrode 73 in the first direction X. In this configuration, the main electrode portion 75 is formed in a polygonal shape (specifically, a quadrilateral shape) having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.

[0129] The multiple lead-out electrode portions 76A and 76B include a first lead-out electrode portion 76A on one side (the first side surface 5A side) and a second lead-out electrode portion 76B on the other side (the second side surface 5B side). In a plan view, the first lead-out electrode portion 76A is drawn out from the main electrode portion 75 to a region located on one side (the first side surface 5A side) in the second direction Y relative to the gate electrode 73, and faces the gate electrode 73 in the second direction Y.

[0130] The second lead-out electrode portion 76B is drawn out from the main electrode portion 75 in a plan view to a region located on the other side (second side surface 5B side) of the second direction Y relative to the gate electrode 73, and faces the gate electrode 73 in the second direction Y. In other words, the multiple lead-out electrode portions 76A and 76B sandwich the gate electrode 73 from both sides in the second direction Y in a plan view.

[0131] The source electrode 74 (main electrode portion 75 and lead-out electrode portions 76A, 76B) penetrates the interlayer insulating film 72 and the main surface insulating film 70 and is electrically connected to a plurality of trench source structures 54, source regions 52 and a plurality of well regions 61. Of course, the source electrode 74 may not have the lead-out electrode portions 76A, 76B and may consist only of the main electrode portion 75.

[0132] The source electrode 74 has a planar area exceeding that of the gate electrode 73. Preferably, the planar area of ​​the source electrode 74 is 50% or more of the first main surface 3. Particularly preferable is that the planar area of ​​the source electrode 74 is 75% or more of the first main surface 3. The source electrode 74 may have a thickness of 0.5 μm to 15 μm. Preferably, the source electrode 74 contains the same conductive material as the gate electrode 73.

[0133] The semiconductor device 1C includes at least one (in this embodiment, more than one) gate wirings 77A, 77B drawn out from the gate electrode 73 onto the first main surface 3 (interlayer insulating film 72). Preferably, the multiple gate wirings 77A, 77B contain the same conductive material as the gate electrode 73. In this embodiment, the multiple gate wirings 77A, 77B cover the active surface 41 but not the outer surface 42. In a plan view, the multiple gate wirings 77A, 77B are drawn out into the region between the periphery of the active surface 41 and the source electrode 74 and extend in a strip along the source electrode 74.

[0134] Specifically, the multiple gate wirings 77A and 77B include a first gate wiring 77A and a second gate wiring 77B. The first gate wiring 77A is drawn out from the gate electrode 73 to the region on the first side surface 5A in a plan view. The first gate wiring 77A has a portion that extends in a strip shape in the second direction Y along the third side surface 5C, and a portion that extends in a strip shape in the first direction X along the first side surface 5A. The second gate wiring 77B is drawn out from the gate electrode 73 to the region on the second side surface 5B in a plan view. The second gate wiring 77B has a portion that extends in a strip shape in the second direction Y along the third side surface 5C, and a portion that extends in a strip shape in the first direction X along the second side surface 5B.

[0135] Multiple gate wirings 77A and 77B intersect (specifically orthogonally) with both ends of the multiple trench gate structures 53 at the periphery of the active surface 41 (first main surface 3). Multiple gate wirings 77A and 77B are electrically connected to the multiple trench gate structures 53 by penetrating the interlayer insulating film 72. Multiple gate wirings 77A and 77B may be directly connected to the multiple trench gate structures 53, or they may be electrically connected to the multiple trench gate structures 53 via a conductive film.

[0136] The semiconductor device 1C includes a source wiring 78 drawn out from the source electrode 74 onto the first main surface 3 (interlayer insulating film 72). Preferably, the source wiring 78 contains the same conductive material as the source electrode 74. The source wiring 78 is formed in a strip shape extending along the periphery of the active surface 41 in the region on the outer surface 42 side of the plurality of gate wirings 77A, 77B. In this embodiment, the source wiring 78 is formed in an annular shape (specifically, a rectangular annular shape) surrounding the gate electrode 73, the source electrode 74 and the plurality of gate wirings 77A, 77B in a plan view.

[0137] The source wiring 78 covers the sidewall structure 71 with the interlayer insulating film 72 in between, and is drawn out from the active surface 41 side to the outer surface 42 side. Preferably, the source wiring 78 covers the entire area of ​​the sidewall structure 71 around its entire circumference. The source wiring 78 has a portion that penetrates the interlayer insulating film 72 and the main surface insulating film 70 on the outer surface 42 side and is connected to the outer surface 42 (specifically the outer contact region 62). The source wiring 78 may also be electrically connected to the sidewall structure 71 by penetrating the interlayer insulating film 72.

[0138] The semiconductor device 1C includes a drain electrode 79 that covers the second main surface 4. The drain electrode 79 forms ohmic contact with the substrate 6 exposed from the second main surface 4. The drain electrode 79 may cover the entire area of ​​the second main surface 4 so as to be continuous with the periphery of the chip 2 (first to fourth side surfaces 5A to 5D). The drain electrode 79 may cover the second main surface 4 with a gap inward from the periphery of the chip 2.

[0139] The breakdown voltage that can be applied between the source electrode 74 and the drain electrode 79 may be between 500V and 3000V. In other words, the chip 2 may be formed so that a breakdown voltage of between 500V and 3000V is applied between the first main surface 3 and the second main surface 4. Furthermore, the chip 2 is formed such that, depending on the voltage application conditions, the electric field strength on the first main surface 3 side, which is the device surface, is higher than the electric field strength on the second main surface 4 side, which is the non-device surface.

[0140] As described above, semiconductor device 1C has the same concentration profile 11 as semiconductor device 1B, and therefore can achieve both excellent cosmic ray tolerance and suppression of bipolar degradation.

[0141] Figure 15 is a plan view showing a semiconductor device 1D according to the fourth embodiment. The MISFET structure 50 of the semiconductor device 1D includes a plurality of planar gate structures 55 formed on the active surface 41.

[0142] Multiple planar gate structures 55 are arranged at intervals on the first main surface 3 so as to overlap at least one body region 51 in the thickness direction of the chip 2. Each of the multiple planar gate structures 55 has a stacked structure including a gate insulating film 55b disposed on the first main surface 3 and a gate main surface electrode 55c disposed on the gate insulating film 55b.

[0143] The contact region 60 is formed on the surface of the body region 51. The contact region 60 penetrates the source region 52 in the thickness direction of the chip 2 and is electrically connected to the body region 51. The interlayer insulating film 72 is formed on the first main surface 3 so as to cover the planar gate structure 55. The interlayer insulating film 72 exposes the source region 52 and the contact region 60.

[0144] As described above, since semiconductor device 1D has the same concentration profile 11 as semiconductor device 1B, it is possible to achieve both excellent cosmic ray tolerance and suppression of bipolar degradation.

[0145] Each of the embodiments described above can be implemented in other forms. For example, the features disclosed in each of the embodiments described above can be combined in appropriate ways. That is, a form may be adopted that simultaneously includes at least two of the features disclosed in the first and second embodiments described above.

[0146] In the third embodiment described above, a chip 2 having a mesa portion 44 was shown. However, a chip 2 having a flat, extending first main surface 3 without a mesa portion 44 may also be used. In this case, the sidewall structure 71 is removed. Of course, in the first embodiment described above, a chip 2 having a mesa portion 44 may also be used. In this case, an SBD structure 27 is formed on the active surface 41.

[0147] In the third embodiment described above, a configuration having a source wiring 78 was shown. However, a configuration without a source wiring 78 may also be adopted.

[0148] In the embodiments described above, the SBD structure 27 and the MISFET structure 50 are shown to be formed on different chips 2. However, the SBD structure 27 and the MISFET structure 50 may be formed on different regions of the first main surface 3 on the same chip 2. In this case, the SBD structure 27 may be formed as a freewheeling diode for the MISFET structure 50. Furthermore, in this case, the source electrode 74 may also serve as the first polarity electrode 26, and the drain electrode 79 may also serve as the second polarity electrode 28.

[0149] In the embodiments described above, a configuration was shown in which the "first conductivity type" is "n type" and the "second conductivity type" is "p type". However, in the embodiments described above, a configuration in which the "first conductivity type" is "p type" and the "second conductivity type" is "n type" may also be adopted. The specific configuration in this case can be obtained by replacing "n type" with "p type" and simultaneously replacing "p type" with "n type" in the above description and attached drawings.

[0150] In the second embodiment described above, an n-type substrate 6 was shown. However, a p-type substrate 6 may also be used. In this case, an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure 50. In this case, as described above, the "source" of the MISFET structure 50 is replaced by the "emitter" of the IGBT structure, and the "drain" of the MISFET structure 50 is replaced by the "collector" of the IGBT structure. The p-type substrate 6 may also be an impurity region containing p-type impurities introduced into the surface layer of the second main surface 4 of the chip 2 by ion implantation.

[0151] The following are examples of features extracted from this specification and drawings. The alphanumeric characters in parentheses below represent the corresponding components in each of the embodiments described above, but this is not intended to limit the scope of each item (Clause) to the embodiments. The term "semiconductor device" in the following items may be replaced with "wide bandgap semiconductor device," "SiC semiconductor device," "semiconductor switching device," "semiconductor rectifier," etc., as needed.

[0152] [Note 1-1] A vertical element structure (27, 53, 55) is formed on the main surface (3) side of the epitaxial layer (33) and through which current flows in the vertical direction which is the thickness direction of the epitaxial layer (33), wherein the epitaxial layer (33) includes a drift region (8), a high-concentration drift region (7) disposed between the drift region (8) and the substrate (6), and a first transition region (9) disposed between the drift region (8) and the high-concentration drift region (7), wherein the drift region (8) has a drift concentration Nd of the first conductivity type lower than the substrate concentration Ns, and the high-concentration drift region (7) has an impurity concentration Nr of the first conductivity type greater than or equal to the substrate concentration Ns. In the first transition region (9), the impurity concentration of the first conductivity type changes in the depth direction of the epitaxial layer (33) with a predetermined first concentration gradient (S1), where the first concentration gradient (S1) is d(log １０ Nt １ A semiconductor device (1A, 1B, 1C, 1D) is given by (x) / dx and satisfies equation (1) below. d(log １０ Nt １ (x)) / dx<2log １０ (cm －３ ) / μm...(1) (However, Nt １ (x) is the concentration of the first transition region (9) at depth x, and x is the depth of the epitaxial layer (33) from the main surface (3).

[0153] [Note 1-2] The semiconductor device described in Note 1-1 (1A, 1B, 1C, 1D) wherein the impurity concentration Nr in the drift high concentration region (7) is higher than the substrate concentration Ns.

[0154] [Appendix 1-3] The semiconductor device (1B, 1C, 1D) according to Appendix 1-1 or Appendix 1-2, wherein the epitaxial layer (33) is located on the main surface (3) side of the drift region (8) and further includes a surface drift region (29) having a surface concentration Nc of a first conductivity type that is higher than the drift concentration Nd.

[0155] [Appendix 1-4] The semiconductor device (1B, 1C, 1D) described in Appendix 1-3, wherein the surface drift region (29) has a thickness less than the thickness of the drift region (8).

[0156] [Note 1-5] The epitaxial layer (33) further includes a second transition region (32) located between the drift region (8) and the surface drift region (29), wherein in the second transition region (32), the impurity concentration of the first conductivity type changes in the depth direction of the epitaxial layer (33) with a predetermined second concentration gradient (S2), and the second concentration gradient (S2) is d(log １０ Nt ２ A semiconductor device (1B, 1C, 1D) described in Appendix 1-3 or Appendix 1-4, which is represented by (x) / dx and satisfies equation (2) below. d(log １０ Nt ２ (x)) / dx<2log １０ (cm －３ ) / μm...(2) (However, Nt ２ (x) is the concentration of the second transition region (32) at depth x, and x is the depth of the epitaxial layer (33) from the main surface (3).

[0157] [Appendix 1-6] The semiconductor device (1B, 1C, 1D) according to Appendix 1-5, wherein the first transition region (9) has a thickness greater than the thickness of the second transition region (32).

[0158] [Note 1-7] The semiconductor device (1B, 1C, 1D) described in Note 1-6, wherein the thickness of the first transition region (9) is 1 μm or more.

[0159] [Appendix 1-8] The semiconductor device (1B, 1C, 1D) according to Appendix 1-6 or Appendix 1-7, wherein the thickness of the second transition region (32) is 0.5 μm or more.

[0160] [Appendix 1-9] The semiconductor device (1A, 1B) according to any one of Appendix 1-3 to 1-8, wherein the element structure (27) includes an electrode (26) disposed on the surface drift region (29) and forming a Schottky junction with the surface drift region (29).

[0161] [Appendix 1-10] The semiconductor device (1A, 1B) according to Appendix 1-9, further comprising a first conductivity type diode region (21) formed using a part of the surface drift region (29), and a second conductivity type guard region (22) formed along the diode region (21) in the surface portion of the main surface (3), wherein the electrode (26) covers the diode region (21) and the guard region (22) so as to form a Schottky junction with the diode region (21) and be electrically connected to the guard region (22).

[0162] [Appendix 1-11] The semiconductor device (1C) according to any one of Appendix 1-3 to 1-8, wherein the element structure (53) includes a trench gate structure (53) formed on the main surface (3) so as to be located within the surface drift region (29).

[0163] [Appendix 1-12] The trench gate structure (53) is formed with a gap between the drift region (8) and the main surface (3), as described in Appendix 1-11, semiconductor device (1C).

[0164] [Appendix 1-13] The semiconductor device (1C) according to Appendix 1-11 or Appendix 1-12, wherein the element structure (53) further includes a trench source structure (54) formed on the main surface (3) so as to be located within the surface drift region (29).

[0165] [Appendix 1-14] The trench source structure (54) is formed with a gap between the drift region (8) and the main surface (3), as described in Appendix 1-13, semiconductor device (1C).

[0166] [Appendix 1-15] The semiconductor device (1D) according to any one of Appendix 1-3 to 1-8, wherein the element structure (55) includes a planar gate structure (55) formed on the main surface (3) so as to be located on the surface drift region (29).

[0167] [Appendix 1-16] The substrate (6) is a semiconductor device (1A, 1B, 1C, 1D) according to any one of Appendix 1-1 to 1-15, including a single crystal of a wide-bandgap semiconductor.

[0168] [Note 1-17] The substrate (6) is a semiconductor device (1A, 1B, 1C, 1D) as described in Note 1-16, which includes a SiC single crystal.

[0169] [Appendix 1-18] The epitaxial layer (33) includes a single crystal of a wide-bandgap semiconductor, as described in any one of Appendix 1-1 to 1-17 (1A, 1B, 1C, 1D).

[0170] [Appendix 1-19] The epitaxial layer (33) is a semiconductor device (1A, 1B, 1C, 1D) as described in Appendix 1-18, comprising a SiC single crystal.

[0171] [Note 1-20] The first concentration gradient (S1) is a semiconductor device (1A, 1B, 1C, 1D) that satisfies the following equation (1'). d(log １０ Nt １ (x)) / dx<1log １０ (cm －３ ) / μm...(1')

[0172] [Appendix 1-21] The semiconductor device (1A, 1B, 1C, 1D) described in any one of Appendix 1-1 to 1-20, wherein the concentration profile (11) of the first conductivity type impurity in the depth direction of the epitaxial layer (33) includes a first flat portion (12), a first convex portion (13), a first transition portion (14), and a second flat portion (15) in this order in the direction from the substrate (6) toward the epitaxial layer (33), and the first convex portion (13) is convex in which the impurity concentration at the end on the main surface (3) side is lower than the impurity concentration at the end on the opposite side, and indicates the concentration value of the drift high concentration region (7).

[0173] [Appendix 1-22] The semiconductor device (1A, 1B, 1C, 1D) described in Appendix 1-21, wherein the first transition portion (14) corresponds to the side portion (18) of the first convex portion (13) on the main surface (3) side and has an inclination corresponding to the concentration gradient shown in equation (1) above.

[0174] [Note 2-1] A chip (2) having a first main surface (3) which is a device surface and a second main surface (4) on the opposite side of the chip (2) A base region (6) of a first conductivity type disposed on the second main surface (4) side of the chip (2) A drift region (8) of a first conductivity type disposed on the first main surface (3) side of the chip (2) A recombination region (7) disposed between the drift region (8) and the base region (6) A first transition region (9) disposed between the drift region (8) and the recombination region (7) The recombination region (7) has an impurity concentration of the first conductivity type that is higher than the impurity concentration of the base region (6) In the first transition region (9), the impurity concentration of the first conductivity type changes in the depth direction of the chip (2) with a predetermined first concentration gradient (S1) The first concentration gradient (S1) is d(log １０ Nt １ A semiconductor device (1A, 1B, 1C, 1D) is given by (x) / dx and satisfies equation (1) below. d(log １０ Nt １ (x)) / dx<2log １０ (cm －３ ) / μm...(1) (However, Nt １ (x) is the concentration of the first transition region (9) at depth x, and x is the depth from the first principal surface (3).

[0175] [Note 2-2] The first concentration gradient (S1) is a semiconductor device (1A, 1B, 1C, 1D) that satisfies the following equation (1'). d(log １０ Nt １ (x)) / dx<1log １０ (cm －３ ) / μm...(1')

[0176] [Note 2-3] The base region (6) is 0.9 × 10 １８ cm －３ The above 2.0 x 10１８ cm －３ The following impurity concentrations and thicknesses of 50 μm to 500 μm are present, and the recombination region (7) is 1.5 × 10 １８ cm －３ The above 2.0 x 10 １８ cm －３ The semiconductor device described in Appendix 2-1 or Appendix 2-2 (1A, 1B, 1C, 1D) has the following impurity concentrations and a thickness of 1 μm or more.

[0177] [Appendix 2-4] The semiconductor device (1A, 1B, 1C, 1D) described in any one of Appendix 2-1 to 2-3, wherein the concentration profile (11) of the first conductivity type impurity in the depth direction of the chip (2) includes a first flat portion (12), a first convex portion (13), a first transition portion (14), and a second flat portion (15) in this order in the direction from the second main surface (4) toward the first main surface (3), and the first convex portion (13) is convex in which the impurity concentration at the end on the first main surface (3) side is lower than the impurity concentration at the end on the second main surface (4) side, and indicates the concentration value of the recombination region (7).

[0178] [Note 2-5] The semiconductor device (1A, 1B, 1C, 1D) described in Note 2-4, wherein the first transition portion (14) corresponds to the side portion (18) of the first convex portion (13) on the first main surface (3) side and has a slope corresponding to the concentration gradient shown in equation (1) above.

[0179] Although embodiments have been described in detail above, these are merely specific examples used to clarify the technical content, and the present invention should not be interpreted as being limited to these specific examples. The scope of the present invention is limited by the appended claims.

[0180] 1A...Semiconductor device, 1B...Semiconductor device, 1C...Semiconductor device, 1D...Semiconductor device, 2...Chip, 3...First main surface, 4...Second main surface, 5A...First side surface, 5B...Second side surface, 5C...Third side surface, 5D...Fourth side surface, 6...Substrate, 7...High-concentration drift region, 8...Drift region, 9...First transition region, 10...Retention region, 11...Concentration profile, 12...First flat portion, 13...First convex portion, 14...First transition portion, 15...Second flat portion, 16...First apex, 17...First side portion, 18...Second side portion, 19...First concentration portion, 20...Second concentration portion, 21...Diode region, 22...Guard region, 23...Field region, 24...Insulating film, 25...Contact opening, 26...First polar electrode, 27...SBD structure, 28...Second polar electrode, 29...Surface drift region, 30...Second transition region, 31...Third flat portion, 32...Second transition region, 33...Epitaxial layer, 41...Active surface, 42...Outer surface, 43A...First connection surface, 43B...Second connection surface, 43C...Third connection surface, 43D...Fourth connection surface, 44...Mesa portion, 50...Structure, 51...Body region, 52...Source region, 53...Trench gate structure, 53a...Gate trench, 53b...Gate insulating film, 53c...Gate embedded electrode, 54...Trench source structure, 54a...Source trench, 54b...Source insulating film, 54c...Source embedded electrode, 55...Planar gate structure, 55b...Gate insulating film, 55c...Gate main surface Electrode, 60...Contact region, 61...Well region, 62...Outer contact region, 63...Outer well region, 64...Field region, 70...Main surface insulating film, 71...Sidewall structure, 72...Interlayer insulating film, 73...Gate electrode, 74...Source electrode, 75...Main electrode section, 76A...First lead electrode section, 76B...Second lead electrode section, 77A...First gate wiring, 77B...Second gate wiring, 78...Source wiring, 79...Drain electrode

Claims

1. A vertical element structure comprising a substrate having a substrate concentration Ns of a first conductivity type, and an epitaxial layer laminated on the substrate, wherein the epitaxial layer is formed on the main surface side of the epitaxial layer and current flows in the vertical direction which is the thickness direction of the epitaxial layer, the epitaxial layer comprising a drift region, a high-concentration drift region disposed between the drift region and the substrate, and a first transition region disposed between the drift region and the high-concentration drift region, the drift region having a drift concentration Nd of a first conductivity type lower than the substrate concentration Ns, the high-concentration drift region having an impurity concentration Nr of a first conductivity type greater than or equal to the substrate concentration Ns, the first transition region, the impurity concentration of the first conductivity type changes in the depth direction of the epitaxial layer with a predetermined first concentration gradient, the first concentration gradient is d(log １０ Nt １ A semiconductor device that is denoted by (x) / dx and satisfies equation (1) below. d(log １０ Nt １ (x)) / dx<2log １０ (cm －３ ) / μm...(1) (However, Nt １ (x) is the concentration of the first transition region at depth x, and x is the depth from the main surface of the epitaxial layer.

2. The semiconductor device according to claim 1, wherein the impurity concentration Nr in the drift high concentration region is higher than the substrate concentration Ns.

3. The semiconductor device according to claim 1 or 2, wherein the epitaxial layer further comprises a surface drift region located on the main surface side of the drift region and having a surface concentration Nc of a first conductivity type that is higher than the drift concentration Nd.

4. The semiconductor device according to claim 3, wherein the surface drift region has a thickness less than the thickness of the drift region.

5. The epitaxial layer further includes a second transition region disposed between the drift region and the surface layer drift region. In the second transition region, the impurity concentration of the first conductivity type changes with a predetermined second concentration gradient in the depth direction of the epitaxial layer. The second concentration gradient is represented by d(log １０ Nt ２ (x)) / dx and satisfies the following formula (2). The semiconductor device according to claim 3 or 4. d(log １０ Nt ２ (x)) / dx < 2log １０ (cm －３ ) / μm... (2) (However, Nt ２ (x) is the concentration of the second transition region at the depth x, and x is the depth from the main surface of the epitaxial layer.) 6. The semiconductor device according to claim 5, wherein the first transition region has a thickness greater than the thickness of the second transition region.

7. The semiconductor device according to claim 6, wherein the thickness of the first transition region is 1 μm or more.

8. The semiconductor device according to claim 6 or 7, wherein the thickness of the second transition region is 0.5 μm or more.

9. The semiconductor device according to any one of claims 3 to 8, wherein the element structure includes an electrode disposed on the surface drift region and forming a Schottky junction with the surface drift region.

10. The semiconductor device according to claim 9, further comprising a first conductivity type diode region formed using a portion of the surface drift region, and a second conductivity type guard region formed along the diode region in the surface portion of the main surface, wherein the electrode covers the diode region and the guard region so as to form a Schottky junction with the diode region and be electrically connected to the guard region.

11. The semiconductor device according to any one of claims 3 to 8, wherein the element structure includes a trench gate structure formed on the main surface so as to be located within the surface drift region.

12. The semiconductor device according to claim 11, wherein the trench gate structure is formed at a distance from the drift region toward the main surface.

13. The semiconductor device according to claim 11 or 12, wherein the element structure further comprises a trench source structure formed on the main surface so as to be located within the surface drift region.

14. The semiconductor device according to claim 13, wherein the trench source structure is formed at a distance from the drift region toward the main surface.

15. The semiconductor device according to any one of claims 3 to 8, wherein the element structure includes a planar gate structure formed on the main surface so as to be located on the surface drift region.

16. The semiconductor device according to any one of claims 1 to 15, wherein the substrate includes a single crystal of a wide-bandgap semiconductor.

17. The semiconductor device according to claim 16, wherein the substrate includes a SiC single crystal.

18. The semiconductor device according to any one of claims 1 to 17, wherein the epitaxial layer comprises a single crystal of a wide-bandgap semiconductor.

19. The semiconductor device according to claim 18, wherein the epitaxial layer comprises a SiC single crystal.

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