Semiconductor device

Abstract

A semiconductor device (1) includes: a first conductivity type low-concentration impurity layer (33) formed on a first conductivity type semiconductor substrate (32); a second conductivity type body region (18) formed on the low-concentration impurity layer (33); a plurality of gate trenches (17) extending in a first direction that is parallel to the upper surface of the semiconductor substrate (32) and that is formed at equal intervals in a second direction parallel to the upper surface and orthogonal to the first direction; and a plurality of first conductivity type source regions (14) and a plurality of second conductivity type body contact regions (13), which are alternately formed in the first direction during a first period in each of the plurality of mesa portions (20) sandwiched between the plurality of gate trenches (17) in the second direction. Each upper surface of the plurality of mesa portions (20) has a plurality of first recessed portions (71) that are recessed in the first direction during a second period that is n (where n is an integer of 1 or more) times the first period, and at least a portion of the lower surface of the recessed portions are in contact with a body contact region (13) or the body region (18).

Description

Semiconductor device

[0001] The present invention relates to a semiconductor device including a vertical MOS (Metal Oxide Semiconductor) transistor.

[0002] Conventionally, semiconductor devices including vertical MOS transistors have been known (see, for example, Patent Document 1 and Patent Document 2).

[0003] Japanese Patent No. 3999225 Japanese Patent No. 7114824

[0004] In a semiconductor device including a vertical MOS transistor, it is desired to improve the ASO (Area of Safe Operation) breakdown resistance.

[0005] Therefore, an object of the present disclosure is to provide a semiconductor device including a vertical MOS transistor that can improve the ASO breakdown resistance.

[0006] A semiconductor device according to one aspect of the present disclosure is a semiconductor device comprising a vertical MOS transistor, comprising: a semiconductor substrate of a first conductivity type containing an impurity of a first concentration; a low-concentration impurity layer of the first conductivity type containing an impurity of a second concentration lower than the first concentration, formed in contact with the semiconductor substrate; a body region of a second conductivity type different from the first conductivity type, containing an impurity of a third concentration, formed in the low-concentration impurity layer including the upper surface of the low-concentration impurity layer; a plurality of gate trenches extending in a first direction parallel to the upper surface of the semiconductor substrate and in a second direction perpendicular to the first direction, formed at equal intervals in the second direction parallel to the upper surface of the semiconductor substrate, from the upper surface of the low-concentration impurity layer to a depth penetrating the body region and to a part of the low-concentration impurity layer; a plurality of gate conductors formed in each of the plurality of gate trenches; and a plurality of source regions and a plurality of body contact regions alternately formed in the first direction with a first period in each of the plurality of mesa portions sandwiched between the plurality of gate trenches in the second direction, wherein the mesa portion The vertical MOS transistor comprises: a plurality of source regions of a first conductivity type formed in the mesa portion including its upper surface; a plurality of body contact regions of a second conductivity type formed in the mesa portion including its upper surface and containing an impurity at a fourth concentration higher than the third concentration; and the source electrode of the vertical MOS transistor, wherein the upper surface of each of the plurality of mesa portions has a plurality of first recesses that are recessed in the first direction at a second period of n (where n is an integer of 1 or more) times the first period, and the interior of the first recesses is filled with the source electrode; at least a portion of the lower surface of each of the plurality of first recesses is in contact with one of the plurality of body contact regions or the body region; the entire lower surface of the plurality of source regions is above the lower surface of the body region and is in contact with the body region; the entire lower surface of the plurality of body contact regions is above the lower surface of the body region and is in contact with the body region; the entire upper surface of the plurality of source regions is in contact with the source electrode; and the entire upper surface of the plurality of body contact regions is in contact with the source electrode.

[0007] According to one aspect of the present disclosure, a semiconductor device is provided that includes a vertical MOS transistor capable of improving ASO breakdown resistance.

[0008] Figure 1 is a schematic plan view showing an example of the structure of a semiconductor device according to an embodiment. Figure 2 is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to an embodiment. Figure 3 is a circuit diagram of a semiconductor device according to an embodiment. Figure 4 is a schematic enlarged cross-sectional perspective view showing an example of the structure around a gate trench in a semiconductor device according to an embodiment. Figure 5 is a schematic enlarged cross-sectional view showing an example of the structure around a gate trench in a semiconductor device according to an embodiment. Figure 6 is a schematic enlarged plan view showing an example of the structure around a gate trench in a semiconductor device according to an embodiment. Figure 7 is an enlarged cross-sectional perspective view of a vertical MOS transistor according to an embodiment, showing how a parasitic bipolar transistor and a parasitic capacitor are formed. Figure 8 is a schematic enlarged cross-sectional view showing an example of the structure around a gate trench in a semiconductor device according to an embodiment. Figure 9 is a schematic enlarged cross-sectional view showing an example of the structure around a gate trench in a semiconductor device according to an embodiment. Figure 10 is a schematic enlarged cross-sectional view showing an example of the structure around a gate trench in a semiconductor device according to an embodiment. Figure 11 is a schematic enlarged cross-sectional view showing an example of the structure around a gate trench in a semiconductor device according to an embodiment. Figure 12 is a schematic enlarged cross-sectional view showing an example of the structure around a gate trench in a semiconductor device according to an embodiment. Figure 13 is a schematic enlarged cross-sectional view showing an example of the structure around a gate trench in a semiconductor device according to an embodiment. Figure 14 is a schematic enlarged cross-sectional view showing an example of the structure around a gate trench in a semiconductor device according to an embodiment. Figure 15 is a schematic enlarged cross-sectional view showing an example of the structure around a gate trench in a semiconductor device according to an embodiment. Figure 16 is a schematic enlarged cross-sectional view showing an example of the structure around a gate trench in a semiconductor device according to an embodiment. Figure 17 is a schematic enlarged cross-sectional view showing an example of the structure around a gate trench in a semiconductor device according to an embodiment. Figure 18 is a schematic enlarged cross-sectional view showing an example of the structure around a gate trench in a semiconductor device according to an embodiment. Figure 19 is a schematic enlarged cross-sectional view showing an example of the structure around a gate trench in a semiconductor device according to an embodiment.Figure 20 is a schematic enlarged cross-sectional perspective view showing an example of the structure around the gate trench in a semiconductor device according to an embodiment. Figure 21 is a schematic enlarged plan view showing an example of the structure around the gate trench in a semiconductor device according to an embodiment. Figure 22 is a schematic enlarged cross-sectional perspective view showing an example of the structure around the gate trench in a conventional vertical MOS transistor. Figure 23 is an enlarged cross-sectional perspective view of a conventional vertical MOS transistor showing the formation of a parasitic bipolar transistor and a parasitic capacitor. Figure 24 is a schematic diagram illustrating the mechanism of the phenomenon in which a conventional vertical MOS transistor is destroyed.

[0009] (Background to obtaining one aspect of this disclosure) As described above, in semiconductor devices equipped with vertical MOS transistors, improvement in ASO breakdown resistance is desired.

[0010] On the other hand, a reduction in the conduction resistance of vertical MOS transistors is desirable.

[0011] Therefore, the inventors diligently conducted experiments and studies to achieve both a reduction in the conduction resistance of the vertical MOS transistor and an improvement in the ASO breakdown resistance of the vertical MOS transistor in a semiconductor device equipped with a vertical MOS transistor.

[0012] Figure 22 is an enlarged cross-sectional perspective view showing the structure around the gate trenches 517 in a conventional vertical MOS transistor 500, which has multiple gate trenches 517 arranged at equal intervals.

[0013] In Figure 22, the source electrode 551 of the vertical MOS transistor 500 is depicted as if it were transparent. However, in reality, the source electrode 551 is not transparent, and structures on the other side of the source electrode 551 cannot be directly seen by passing through the source electrode 551.

[0014] In Figure 22, the Y-axis direction is the direction in which the gate trench 517 extends, the Z-axis direction is the opposite direction to the depth direction of the gate trench 517, and the X-axis direction is perpendicular to the Y-axis and Z-axis directions, and is the direction in which the multiple gate trenches 517 are arranged at equal intervals.

[0015] Here, we will explain assuming that the vertical MOS transistor 500 is an N-channel vertical MOS transistor.

[0016] As shown in Figure 22, in the vertical MOS transistor 500, a gate conductor 515 is formed inside the gate trench 517, surrounded by a gate oxide film 516 that extends in the direction of the gate trench 517. On the upper side of the body region 518 in the Z-axis direction, multiple source regions 514 and multiple body contact regions 513 are formed alternately in the Y-axis direction at a predetermined period. The multiple source regions 514 and multiple body contact regions 513 are connected by contact with the source electrode 551.

[0017] The inventors believed that to reduce the on-resistance of the vertical MOS transistor 500, it would be effective to increase the density of the gate trenches 517 by narrowing the mesa width Lxm, which is the width between gate trenches 517 that are arranged at equal intervals in the X-axis direction.

[0018] However, the inventors noticed that narrowing the mesa width Lxm reduced the ASO breakdown resistance of the vertical MOS transistor 500. Through experiments and investigations, the inventors elucidated the mechanism behind this phenomenon where narrowing the mesa width Lxm reduces the ASO breakdown resistance of the vertical MOS transistor 500.

[0019] Figure 23 is an enlarged cross-sectional perspective view of a vertical MOS transistor 500, showing how a parasitic bipolar transistor and a parasitic capacitor are formed on the vertical MOS transistor 500. However, in Figure 23, the source electrode 551 is omitted from the illustration to avoid making the drawing unnecessarily complex.

[0020] As shown in Figure 23, a parasitic bipolar transistor 510 is formed on the vertical MOS transistor 500, with the body region 518 as the base, the low-concentration impurity layer 533 (hereinafter also referred to as the "drain region 533") as the collector, and the source region 514 as the emitter.

[0021] Furthermore, as shown in Figure 23, a parasitic capacitor 520 is formed on the junction surface between the body region 518 and the drain region 533 of the vertical MOS transistor 500.

[0022] In Figure 23, the internal resistance Rb is the internal resistance between the base and source electrode 551 (not shown in Figure 23; see Figure 22) of the parasitic bipolar transistor 510.

[0023] As shown in Figure 23, the internal resistance Rb consists of the contact resistance Rbc between the source electrode 551 and the body contact region 513, the internal resistance Rb1 in the Z-axis direction of the body contact region 513, the internal resistance Rb2 in the Z-axis direction of the body region 518, and the internal resistance Rb3 in the Y-axis direction of the body region 518.

[0024] Figure 24 is a schematic diagram illustrating the mechanism of the phenomenon in which the vertical MOS transistor 500 is destroyed.

[0025] As shown in Figure 24, immediately after the vertical MOS transistor 500 is switched from a conductive state to a non-conductive state, a current (hereinafter also referred to as "temporary current") flows from the drain region 533 to the source electrode 551 (not shown in Figure 24; see Figure 22) via the parasitic capacitor 520, the body region 518, and the body contact region 513 (see Turn OFF (1)).

[0026] Here, when the product of the temporary current value Ioff [A] and the internal resistance value Rb [Ω] becomes greater than the base-emitter saturation voltage VBEsat [V] of the parasitic bipolar transistor 510, the emitter-collector of the parasitic bipolar transistor 510 becomes conductive. As a result, a large current flows from the drain region 533 to the source electrode 551 (see Turn OFF immediately after (2)), destroying the vertical MOS transistor 500.

[0027] Here, narrowing the mesa width Lxm increases the internal resistance Rb.

[0028] Therefore, when the mesa width Lxm is narrowed and the internal resistance Rb [Ω] becomes larger, only a smaller amount of transient current flows, and the product of the transient current Ioff [A] and the internal resistance Rb [Ω] becomes larger than the base-emitter saturation voltage VBEsat [V] of the parasitic bipolar transistor 510. As a result, the ASO breakdown tolerance of the vertical MOS transistor 500 decreases.

[0029] Based on the mechanism by which narrowing the mesa width Lxm reduces the ASO breakdown resistance of the vertical MOS transistor 500, the inventors conducted further experiments and studies. They then discovered that even when the mesa width Lxm is narrowed, if the internal resistance Rb1 in the Z-axis direction of the body contact region 513 can be reduced, the resistance value Rb [Ω] of the internal resistance Rb can be reduced, thereby improving the ASO breakdown resistance of the vertical MOS transistor 500.

[0030] Based on this knowledge, the inventors conducted further experiments and studies, leading them to conceive of the semiconductor device described in this disclosure.

[0031] A semiconductor device according to one aspect of the present disclosure is a semiconductor device comprising a vertical MOS transistor, comprising: a semiconductor substrate of a first conductivity type containing an impurity of a first concentration; a low-concentration impurity layer of the first conductivity type containing an impurity of a second concentration lower than the first concentration, formed in contact with the semiconductor substrate; a body region of a second conductivity type different from the first conductivity type, containing an impurity of a third concentration, formed in the low-concentration impurity layer including the upper surface of the low-concentration impurity layer; a plurality of gate trenches extending in a first direction parallel to the upper surface of the semiconductor substrate and in a second direction perpendicular to the first direction, formed at equal intervals in the second direction parallel to the upper surface of the semiconductor substrate, from the upper surface of the low-concentration impurity layer to a depth penetrating the body region and to a part of the low-concentration impurity layer; a plurality of gate conductors formed in each of the plurality of gate trenches; and a plurality of source regions and a plurality of body contact regions alternately formed in the first direction with a first period in each of the plurality of mesa portions sandwiched between the plurality of gate trenches in the second direction, wherein the mesa portion The vertical MOS transistor comprises: a plurality of source regions of a first conductivity type formed in the mesa portion including its upper surface; a plurality of body contact regions of a second conductivity type formed in the mesa portion including its upper surface and containing an impurity at a fourth concentration higher than the third concentration; and the source electrode of the vertical MOS transistor, wherein the upper surface of each of the plurality of mesa portions has a plurality of first recesses that are recessed in the first direction at a second period of n (where n is an integer of 1 or more) times the first period, and the interior of the first recesses is filled with the source electrode; at least a portion of the lower surface of each of the plurality of first recesses is in contact with one of the plurality of body contact regions or the body region; the entire lower surface of the plurality of source regions is above the lower surface of the body region and is in contact with the body region; the entire lower surface of the plurality of body contact regions is above the lower surface of the body region and is in contact with the body region; the entire upper surface of the plurality of source regions is in contact with the source electrode; and the entire upper surface of the plurality of body contact regions is in contact with the source electrode.

[0032] In the semiconductor device with the above configuration, the upper surface of the body contact area is recessed in each of the multiple first recesses.

[0033] Therefore, the internal resistance Rb1 of the body contact region where the upper surface is recessed in each of the multiple first recesses is reduced.

[0034] Therefore, the semiconductor device with the above configuration provides a semiconductor device equipped with a vertical MOS transistor that can improve ASO breakdown resistance.

[0035] Furthermore, in a plan view of the semiconductor substrate, each of the plurality of first recesses may be contained within one of the plurality of body contact regions, and the source electrode may not contact any of the plurality of source regions within the interior of the plurality of first recesses.

[0036] As a result, in each of the multiple first recesses, the source electrode and the body contact area come into contact with at least one of the sides of the first recess in a first direction.

[0037] Therefore, in each of the multiple first recesses, the contact area between the source electrode and the body contact region can be increased in the body contact region where the upper surface is recessed.

[0038] This reduces the contact resistance Rbc between the source electrode and the body contact region in each of the multiple first recesses where the upper surface of the body contact region is recessed.

[0039] Therefore, the semiconductor device with the above configuration can further improve ASO degradation resistance.

[0040] Furthermore, the width of the first recess in the second direction may be equal to the width of the plurality of mesa portions in the second direction.

[0041] This makes it possible to form multiple first recesses relatively easily.

[0042] Further, each upper surface of the plurality of mesa portions is further provided with a plurality of second concave portions that are recessed in the second period in the first direction, and the plurality of second concave portions are filled with the source electrodes inside, and at least a part of the lower surface of each of the plurality of second concave portions may be in contact with one of the plurality of body contact regions or the body region.

[0043] As a result, the upper surface of the body contact region is recessed in each of the plurality of second concave portions.

[0044] For this reason, the internal resistance Rb1 of the body contact region whose upper surface is recessed in each of the plurality of second concave portions is reduced.

[0045] Therefore, according to the semiconductor device having the above configuration, the ASO breakdown resistance can be further improved.

[0046] Also, n may be 1.

[0047] As a result, the upper surface of the body contact region is recessed in all of the plurality of body contact regions.

[0048] For this reason, the internal resistance Rb1 is reduced in all of the plurality of body contact regions.

[0049] Therefore, according to the semiconductor device having the above configuration, the ASO breakdown resistance can be further improved.

[0050] Also, in each of the plurality of first concave portions, the lower surface of the first concave portion may be above the lower surface of one of the plurality of body contact regions that encloses the first concave portion.

[0051] As a result, in each of the plurality of first concave portions, the source electrode and the body contact region are in contact with each other at the lower surface of the first concave portion.

[0052] For this reason, the contact area between the source electrode and the body contact region of the body contact region whose upper surface is recessed in each of the plurality of first concave portions can be increased.

[0053] This reduces the contact resistance Rbc between the source electrode and the body contact region in each of the multiple first recesses where the upper surface of the body contact region is recessed.

[0054] Therefore, the semiconductor device with the above configuration can further improve ASO degradation resistance.

[0055] Furthermore, in each of the plurality of first recesses, the lower surface of the first recess may be lower than the lower surface of one of the plurality of body contact regions that enclose the first recess.

[0056] As a result, the internal resistance Rb2 in the Z-axis direction of the body region of each of the multiple first recesses is reduced.

[0057] Therefore, the semiconductor device with the above configuration can further improve ASO degradation resistance.

[0058] Furthermore, the concentration of impurities in the body region may be higher in the region including at least a portion of the part in contact with the plurality of first recesses than in other regions.

[0059] This reduces the contact resistance Rbc between the source electrode and the body region.

[0060] Therefore, the semiconductor device with the above configuration can further improve ASO degradation resistance.

[0061] Furthermore, the lower surface of each of the plurality of body contact areas may include a first lower surface and a second lower surface that is lower than the first lower surface, and in each of the plurality of first recesses, the lower surface of the first recess may be lower than the first lower surface of one of the plurality of body contact areas that enclose the first recess and higher than the second lower surface of one of the plurality of body contact areas.

[0062] Furthermore, the lower surface of each of the plurality of first recesses may include a third lower surface and a fourth lower surface that is lower than the third lower surface, and in each of the plurality of first recesses, the third lower surface of the first recess may be above the lower surface of one of the plurality of body contact regions that enclose the first recess.

[0063] This makes it possible to increase the contact area between the source electrode and the body contact region, where the upper surface of each of the multiple first recesses is recessed.

[0064] Therefore, the contact resistance Rbc between the source electrode and the body contact region is reduced in each of the multiple first recesses where the upper surface of the body contact region is recessed.

[0065] Therefore, the semiconductor device with the above configuration can further improve ASO degradation resistance.

[0066] Furthermore, the plurality of mesa portions may consist of a plurality of first mesa portions and a plurality of second mesa portions arranged alternately in the second direction, wherein the phase of the position in the first direction in which the plurality of source regions and the plurality of body contact regions are formed in each of the plurality of first mesa portions may be different from the phase of the position in the first direction in which the plurality of source regions and the plurality of body contact regions are formed in each of the plurality of second mesa portions.

[0067] Hereinafter, a specific example of a semiconductor device according to one aspect of this disclosure will be described with reference to the drawings. The embodiments shown here are all examples of this disclosure. Therefore, the numerical values, shapes, components, arrangement and connection configurations of components, as well as the steps (processes) and the order of steps shown in the following embodiments are examples and are not intended to limit this disclosure. Furthermore, each figure is a schematic diagram and is not necessarily a strict illustration. In each figure, substantially identical components are denoted by the same reference numerals, and redundant explanations are omitted or simplified.

[0068] (Embodiment) The following describes a semiconductor device equipped with a vertical MOS transistor according to an embodiment.

[0069] Here, we will explain using the example of a semiconductor device according to the embodiment that has one vertical MOS transistor. However, the number of vertical MOS transistors in the semiconductor device according to the embodiment is not necessarily limited to one, and may be multiple.

[0070] Furthermore, in this description, the semiconductor device according to the embodiment is described as a face-down mountable chip-size package (CSP) type semiconductor device. However, the semiconductor device according to the embodiment is not necessarily limited to a face-down mountable semiconductor device, nor is it necessarily limited to a chip-size package type semiconductor device.

[0071] [1. Structure of Semiconductor Device] Figure 1 is a schematic plan view showing an example of the structure of a semiconductor device 1 according to Embodiment 1.

[0072] In Figure 1, the source electrode 51 (described later), the drain electrode 52 (described later), and the gate electrode 53 (described later) are shown with dashed lines as if they were directly visible from outside the semiconductor device 1. However, in reality, these cannot be directly visible from outside the semiconductor device 1.

[0073] Figure 2 is a schematic cross-sectional view showing an example of the structure of the semiconductor device 1. Figure 2 shows the cross-section along line I-I in Figure 1.

[0074] Figure 3 is a circuit diagram of semiconductor device 1.

[0075] As shown in Figures 1 to 3, the semiconductor device 1 comprises a semiconductor layer 40, an oxide film 34, a protective film 35, a source electrode 51, a drain electrode 52, a gate electrode 53, a source pad 61A, a source pad 61B, a drain pad 62, a gate pad 63, and a vertical MOS transistor 10.

[0076] The semiconductor layer 40 is constructed by stacking a semiconductor substrate 32 and a low-concentration impurity layer 33.

[0077] The semiconductor substrate 32 is made of silicon of a first conductivity type containing a first concentration of impurities.

[0078] The low-concentration impurity layer 33 is formed on the semiconductor substrate 32 in contact with the semiconductor substrate 32 and consists of silicon of a first conductivity type containing impurities at a second concentration lower than the first concentration. The low-concentration impurity layer 33 may be formed on the semiconductor substrate 32 by, for example, epitaxial growth.

[0079] Generally, semiconductors have two types of conductivity: P-type and N-type. The first conductivity type may be either P-type or N-type. For the sake of explanation, we will assume that the first conductivity type is N-type and the second conductivity type (described later) is P-type. However, it is also acceptable for the first conductivity type to be P-type and the second conductivity type to be N-type.

[0080] The oxide film 34 is formed on the low-concentration impurity layer 33, in contact with the low-concentration impurity layer 33.

[0081] The protective film 35 is a protective film that covers the oxide film 34, the source electrode 51, the drain electrode 52, and the upper surface of the gate electrode 53.

[0082] The protective film 35 includes an opening that exposes a portion of the upper surface of the source electrode 51 to the outside of the protective film 35, another opening that exposes a portion of the upper surface of the source electrode 51 to the outside of the protective film 35, an opening that exposes a portion of the upper surface of the drain electrode 52 to the outside of the protective film 35, and an opening that exposes a portion of the upper surface of the gate electrode 53 to the outside of the protective film 35.

[0083] The upper surface of the source electrode 51 is exposed to the outside of the protective film 35 through two openings in the protective film 35. The upper surfaces of the source electrode 51 that are exposed to the outside of the protective film 35 through these two openings form the source pad 61A and the source pad 61B.

[0084] In other words, source pad 61A is the portion of the upper surface of the source electrode 51 that is exposed to the outside of the protective film 35 at the opening, and source pad 61B is the portion of the upper surface of the source electrode 51 that is exposed to the outside of the protective film 35 at the other opening.

[0085] The upper surface of the drain electrode 52 is exposed to the outside of the protective film 35 at the opening of the protective film 35. The upper surface of the drain electrode 52 that is exposed to the outside of the protective film 35 at the opening of the protective film 35 forms the drain pad 62.

[0086] In other words, the drain pad 62 is the portion of the upper surface of the drain electrode 52 that is exposed to the outside of the protective film 35 at the opening.

[0087] The upper surface of the gate electrode 53 is exposed to the outside of the protective film 35 at the opening in the protective film 35. The upper surface of the gate electrode 53 that is exposed to the outside of the protective film 35 at the opening in the protective film 35 is the gate pad 63.

[0088] In other words, the gate pad 63 is the portion of the upper surface of the gate electrode 53 that is exposed to the outside of the protective film 35 at the opening.

[0089] The low-concentration impurity layer 33, including its upper surface, has a body region 18 formed therein that contains impurities of a third concentration and has a second conductivity type different from the first conductivity type.

[0090] Furthermore, the low-concentration impurity layer 33 has a plurality of gate trenches 17 formed at equal intervals in a second direction (the Y-axis direction in Figures 1 and 2) that is perpendicular to the first direction and parallel to the first direction, extending from the upper surface of the low-concentration impurity layer 33 through the body region 18 to a depth up to a part of the low-concentration impurity layer 33.

[0091] Furthermore, a gate conductor 15 surrounded by a gate oxide film 16 is formed in each of the multiple gate trenches 17.

[0092] Furthermore, the low-concentration impurity layer 33 has a drain-pulling region 36 of first conductivity type that contains impurities of a fifth concentration higher than the second concentration, extending from the upper surface of the low-concentration impurity layer 33 through the low-concentration impurity layer 33 to the semiconductor substrate 32.

[0093] In other words, the semiconductor device 1 further comprises a body region 18, a plurality of gate trenches 17, a plurality of gate conductors 15, a plurality of gate oxide films 16, and a drain pulling region 36.

[0094] Figure 4 is a schematic, enlarged cross-sectional perspective view showing an example of the structure around the gate trench 17 of the semiconductor device 1.

[0095] In Figure 4, the source electrode 51 is depicted as if it were transparent, but in reality, the source electrode 51 is not transparent, and structures on the other side of the source electrode 51 cannot be directly seen by passing through the source electrode 51.

[0096] Figure 5 is a schematic, enlarged cross-sectional view showing an example of the structure around the gate trench 17 of the semiconductor device 1. Figure 5 shows the cross-section along line II-II in Figure 4.

[0097] Figure 6 is a schematic enlarged plan view showing an example of the structure around the gate trench 17 of the semiconductor device 1.

[0098] In Figure 6, the source electrode 51 is omitted from the diagram, as if it were not present. However, in reality, the source electrode 51 is located above the Z-axis in Figure 6.

[0099] As shown in Figures 4 to 6, the low-concentration impurity layer 33 has multiple source regions 14 and multiple body contact regions 13 that are alternately formed in a first period in the first direction (Y direction in Figures 4 to 6) in each of the multiple mesa portions 20 sandwiched between multiple gate trenches 17 in the second direction (X direction in Figures 4 to 6). These include multiple source regions 14 of a first conductivity type formed in the mesa portion 20 including the upper surface of the mesa portion 20, and multiple body contact regions 13 of a second conductivity type that contain impurities of a fourth concentration higher than the third concentration formed in the mesa portion 20 including the upper surface of the mesa portion 20.

[0100] In other words, the semiconductor device 1 further comprises a plurality of source regions 14 and a plurality of body contact regions 13.

[0101] As shown in Figures 4 to 6, the upper surface of each of the multiple mesa portions 20 is provided with a plurality of first recesses 71 that are recessed in a first direction with a second period that is n (where n is an integer of 1 or more) times the first period, and the interior of these first recesses 71 is filled with source electrodes 51.

[0102] Figures 4 to 6 illustrate the structure around the gate trench 17 when n is 1. However, n is not necessarily limited to 1 and can be an integer of 2 or more.

[0103] Furthermore, Figures 4 to 6 illustrate the structure around the gate trench 17 when the width of the first recess 71 in the second direction is equal to the width of the mesa portion 20 in the second direction. However, the width of the first recess 71 in the second direction is not necessarily limited to being equal to the width of the mesa portion 20 in the second direction; it may be narrower than the width of the mesa portion 20 in the second direction.

[0104] However, if the width of the first recess 71 in the second direction is equal to the width of the multiple mesa portions 20 in the second direction, there is an advantage that the multiple first recesses 71 can be formed relatively easily.

[0105] Furthermore, Figures 4 to 6 illustrate the structure around the gate trench 17 when the width of the first recess 71 in the first direction is equal to the width of the body contact area 13 in the first direction. However, the width of the first recess 71 in the first direction is not necessarily limited to being equal to the width of the body contact area 13 in the first direction; it may be larger or smaller than the width of the body contact area 13 in the first direction.

[0106] As shown in Figures 4 to 6, at least a portion of the lower surface of each of the multiple first recesses 71 is in contact with one of the multiple body contact areas 13 or with a body area 18.

[0107] Figures 4 to 6 illustrate the structure around the gate trench 17 when the entire lower surface of each of the multiple first recesses 71 is in contact with one of the multiple body contact areas 13. However, the configuration is not limited to the entire lower surface of each of the multiple first recesses 71 being in contact with one of the multiple body contact areas 13. It may also be a configuration in which at least a portion of the lower surface of each of the multiple first recesses 71 is in contact with the body area 18, or a configuration in which at least a portion of the lower surface of each of the multiple first recesses 71 is in contact with one of the multiple body contact areas 13 and the body area 18.

[0108] Furthermore, as shown in Figures 4 to 6, the entire lower surface of the multiple source regions 14 is above the lower surface of the body region 18 and is in contact with the body region 18, the entire lower surface of the multiple body contact regions 13 is above the lower surface of the body region 18 and is in contact with the body region 18, the entire upper surface of the multiple source regions 14 is in contact with the source electrode 51, and the entire upper surface of the multiple body contact regions 13 is in contact with the source electrode 51.

[0109] With the above configuration, the semiconductor device 1 includes a vertical MOS transistor 10.

[0110] As shown in Figures 2, 4, and 5, the source electrode 51 is an electrode that contacts and connects to multiple source regions 14 and multiple body contact regions 13. Thus, the source electrode 51 functions as the source electrode of the vertical MOS transistor 10.

[0111] In other words, the source electrode 51 is the source electrode of the vertical MOS transistor 10.

[0112] The source electrode 51 is, as an example, made of one or more metals, including a metal mainly composed of aluminum, although this is not necessarily limited to this example.

[0113] The drain electrode 52 is an electrode that contacts and connects to the drain pulling region 36. As a result, the drain electrode 52 functions as the drain electrode of the vertical MOS transistor 10.

[0114] In other words, the drain electrode 52 is the drain electrode of the vertical MOS transistor 10.

[0115] The drain electrode 52 is, as an example, made of one or more metals, including a metal mainly composed of aluminum, although this is not necessarily limited to this example.

[0116] The gate electrode 53 is an electrode electrically connected to the gate conductor 15. Thus, the gate electrode 53 functions as the gate electrode of the vertical MOS transistor 10.

[0117] In other words, the gate electrode 53 is the gate electrode of the vertical MOS transistor 10.

[0118] The gate electrode 53 is, as an example, made of one or more metals, including a metal mainly composed of aluminum, although this is not necessarily an exhaustive example.

[0119] [2. Discussion] In the semiconductor device 1 with the above configuration, a parasitic bipolar transistor and a parasitic capacitor are formed on the vertical MOS transistor 10.

[0120] Figure 7 is an enlarged cross-sectional perspective view of a vertical MOS transistor 10, showing how a parasitic bipolar transistor and a parasitic capacitor are formed on the vertical MOS transistor 10. However, in Figure 7, the source electrode 51 is omitted from the illustration to avoid making the drawing unnecessarily complex.

[0121] As shown in Figure 7, a parasitic bipolar transistor 110 is formed in the vertical MOS transistor 10, with the body region 18 as the base, the low-concentration impurity layer 33 (hereinafter also referred to as the "drain region 33") as the collector, and the source region 14 as the emitter.

[0122] Furthermore, as shown in Figure 7, a parasitic capacitor 120 is formed on the junction surface between the body region 18 and the drain region 33 of the vertical MOS transistor 10.

[0123] In Figure 7, the internal resistance Rb is the internal resistance between the base and source electrode 51 (not shown in Figure 7; see Figure 4, etc.) of the parasitic bipolar transistor 110.

[0124] As shown in Figure 7, the internal resistance Rb consists of the contact resistance Rbc between the source electrode 51 and the body contact region 13, the internal resistance Rb1 in the Z-axis direction of the body contact region 13, the internal resistance Rb2 in the Z-axis direction of the body region 18, and the internal resistance Rb3 in the Y-axis direction of the body region 18.

[0125] As shown in Figures 4 and 5, with the semiconductor device 1 having the above configuration, the upper surface of the body contact area 13 is recessed in each of the multiple first recesses 71.

[0126] Therefore, with the semiconductor device 1 having the above configuration, the internal resistance Rb1 of the body contact region 13, in which the upper surface is recessed in each of the multiple first recesses 71, is reduced compared to a conventional semiconductor device that does not have the first recess 71 (for example, a conventional semiconductor device equipped with a conventional vertical MOS transistor 500 as shown in Figures 22 and 23).

[0127] Therefore, the semiconductor device 1 with the above configuration provides a semiconductor device equipped with a vertical MOS transistor 10 that can improve ASO breakdown resistance.

[0128] In this embodiment, the integer n representing the ratio of the second period to the first period is not necessarily limited to 1, and may be an integer of 2 or more. However, it is preferable that n is 1.

[0129] If n is 1, the upper surface of the body contact area 13 is concave in all of the multiple body contact areas 13.

[0130] Therefore, the internal resistance Rb1 is reduced in all of the multiple body contact regions 13.

[0131] Therefore, if n is 1, the resistance to ASO destruction can be further improved.

[0132] In addition, in a plan view of the semiconductor substrate 32, each of the multiple first recesses 71 may be contained within one of the multiple body contact regions 13, and the source electrode 51 may not contact any of the multiple source regions 14 within the multiple first recesses 71.

[0133] Figure 8 is a schematic enlarged cross-sectional view showing an example of the structure around the gate trench 17 in the semiconductor device 1 with the above configuration.

[0134] As a result, in each of the multiple first recesses 71, the source electrode 51 and the body contact region 13 come into contact with each other on at least one of the side surfaces of the first recess 71 in the first direction.

[0135] Therefore, in each of the multiple first recesses 71, the contact area between the source electrode 51 and the body contact region 13, where the upper surface is recessed, can be increased.

[0136] As a result, the contact resistance Rbc between the source electrode 51 and the body contact region 13 is reduced in each of the multiple first recesses 71, where the upper surface of the body contact region 13 is recessed.

[0137] Therefore, the semiconductor device 1 with the above configuration can further improve ASO degradation resistance.

[0138] In addition, in a plan view of the semiconductor substrate 32, each of the multiple first recesses 71 may contain one of the multiple body contact regions 13.

[0139] Figure 9 is a schematic enlarged cross-sectional view showing an example of the structure around the gate trench 17 in the semiconductor device 1 with the above configuration.

[0140] Furthermore, the upper surface of each of the multiple mesa portions 20 has a plurality of second recesses 72 (see Figure 10 described later) that are recessed in a second period in a first direction, and the interior of the second recesses 72 is filled with source electrodes 51, and at least a portion of the lower surface of each of the plurality of second recesses 72 may be in contact with one of the plurality of body contact regions 13 or with a body region 18.

[0141] Figure 10 is a schematic enlarged cross-sectional view showing an example of the structure around the gate trench 17 in the semiconductor device 1 with the above configuration.

[0142] As a result, the upper surface of the body contact area 13 is recessed in each of the multiple second recesses 72.

[0143] Therefore, the internal resistance Rb1 of the body contact region 13, in which the upper surface is recessed in each of the multiple second recesses 72, is reduced.

[0144] Therefore, the semiconductor device 1 with the above configuration can further improve ASO degradation resistance.

[0145] Furthermore, the upper surface of each of the multiple mesa portions 20 has a plurality of third to k (where k is an integer greater than or equal to 0) recesses 73 (see Figure 11 below) that are recessed in the first direction with a second period, and the interior of each of the third to k recesses 73 is filled with a source electrode 51, and at least a portion of the lower surface of each of the plurality of third to k recesses 73 may be in contact with one of the plurality of body contact regions 13 or with a body region 18.

[0146] Figure 11 is a schematic enlarged cross-sectional view showing an example of the structure around the gate trench 17 in the semiconductor device 1 with the above configuration when k is 0.

[0147] As a result, the upper surface of the body contact area 13 is recessed in each of the third to k recesses 73.

[0148] Therefore, the internal resistance Rb1 of the body contact region 13, in which the upper surface is recessed in each of the third to k recesses 73, is reduced.

[0149] Therefore, the semiconductor device 1 with the above configuration can further improve ASO degradation resistance.

[0150] Furthermore, in the semiconductor device 1 illustrated in Figures 5 and 8 to 11, the lower surface of each of the multiple first recesses 71 is positioned above the lower surface of one of the multiple body contact regions 13 that enclose the first recess 71.

[0151] As a result, in each of the multiple first recesses 71, the source electrode 51 and the body contact region 13 come into contact on the lower surface of the first recess 71.

[0152] Therefore, in each of the multiple first recesses 71, the contact area between the source electrode 51 and the body contact region 13, where the upper surface is recessed, can be increased.

[0153] As a result, the contact resistance Rbc between the source electrode 51 and the body contact region 13 is reduced in each of the multiple first recesses 71, where the upper surface of the body contact region 13 is recessed.

[0154] Therefore, the semiconductor device 1 with the above configuration can further improve ASO degradation resistance.

[0155] In contrast, in each of the multiple first recesses 71, the lower surface of the first recess 71 may be lower than the lower surface of one of the multiple body contact regions 13 that enclose the first recess 71.

[0156] Figure 12 is a schematic enlarged cross-sectional view showing an example of the structure around the gate trench 17 in the semiconductor device 1 with the above configuration.

[0157] As a result, the internal resistance Rb2 in the Z-axis direction of the body region 18 is reduced in each of the multiple first recesses 71.

[0158] Therefore, the semiconductor device 1 with the above configuration can further improve ASO degradation resistance.

[0159] Furthermore, the concentration of impurities in the body region 18 may be higher in the region including at least a portion of the part in contact with the plurality of first recesses 71 than in other regions.

[0160] This reduces the contact resistance Rbc between the source electrode 51 and the body region 18.

[0161] Therefore, the semiconductor device 1 with the above configuration can further improve ASO degradation resistance.

[0162] Furthermore, each of the multiple body contact areas 13 has a lower surface including a first lower surface 131 (see Figure 13 below) and a second lower surface 132 (see Figure 13 below) which is lower than the first lower surface 131. In each of the multiple first recesses 71, the lower surface of the first recess 71 may be lower than the first lower surface 131 of one of the multiple body contact areas 13 that enclose the first recess 71, and higher than the second lower surface 132 of one of the multiple body contact areas 13.

[0163] Figure 13 is a schematic enlarged cross-sectional view showing an example of the structure around the gate trench 17 in the semiconductor device 1 with the above configuration.

[0164] Furthermore, each of the multiple first recesses 71 has a lower surface including a third lower surface 711 (see Figures 14 to 19 described later) and a fourth lower surface 712 (see Figures 14 to 19 described later) which is lower than the third lower surface 711, and in each of the multiple first recesses 71, the third lower surface 711 of the first recess 71 may be above the lower surface of one of the multiple body contact areas 13 that enclose the first recess 71.

[0165] Figures 14 to 19 are enlarged cross-sectional views schematically showing an example of the structure around the gate trench 17 in the semiconductor device 1 with the above configuration.

[0166] This makes it possible to increase the contact area between the source electrode 51 and the body contact region 13 in each of the multiple first recesses 71, where the upper surface of the body contact region 13 is recessed.

[0167] Therefore, the contact resistance Rbc between the source electrode 51 and the body contact region 13 is reduced in each of the multiple first recesses 71, where the upper surface of the body contact region 13 is recessed.

[0168] Therefore, the semiconductor device 1 with the above configuration can further improve ASO degradation resistance.

[0169] The multiple mesa portions 20 consist of multiple first mesa portions 201 (see Figures 20 and 21 below) and multiple second mesa portions 202 (see Figures 20 and 21 below) that are alternately arranged in the second direction, and the phase of the position in the first direction in which multiple source regions 14 and multiple body contact regions 13 are formed in each of the multiple first mesa portions 201 may be different from the phase of the position in the first direction in which multiple source regions 14 and multiple body contact regions 13 are formed in each of the multiple second mesa portions 202.

[0170] Figure 20 is a schematic enlarged cross-sectional perspective view showing an example of the structure around the gate trench 17 of the semiconductor device 1 with the above configuration.

[0171] In Figure 20, the source electrode 51 is depicted as if it were transparent, but in reality, the source electrode 51 is not transparent, and structures on the other side of the source electrode 51 cannot be directly seen by passing through the source electrode 51.

[0172] Figure 21 is a schematic enlarged plan view showing an example of the structure around the gate trench 17 of the semiconductor device 1.

[0173] In Figure 21, the source electrode 51 is omitted from the diagram, as if it were not present. However, in reality, the source electrode 51 is located above the Z-axis in Figure 21.

[0174] Furthermore, the multiple mesa sections 20 consist of a plurality of first mesa sections to the mth mesa section (where m is an integer of 3 or more) arranged sequentially in the second direction, and the phases of the positions in the first direction in which the plurality of source regions 14 and the plurality of body contact regions 13 are formed in each of the plurality of first mesa sections to the mth mesa section may be different from each other.

[0175] (Supplement) The above description of a semiconductor device according to one aspect of the present disclosure was based on an embodiment, but the present disclosure is not limited to this embodiment. Without departing from the spirit of the present disclosure, various modifications that a person skilled in the art could conceive of this embodiment, or forms constructed by combining components from different modifications, may also be included within the scope of one or more aspects of the present disclosure.

[0176] This disclosure is widely applicable to semiconductor devices and the like that equipped with vertical MOS transistors.

[0177] 1 Semiconductor device 10, 500 Vertical MOS transistor 13, 513 Body contact region 14, 514 Source region 15, 515 Gate conductor 16, 516 Gate oxide film 17, 517 Gate trench 18, 518 Body region 20 Mesa region 32 Semiconductor substrate 33 Low-concentration impurity layer, drain region 34 Oxide film 35 Protective film 36 Drain pulling region 40 Semiconductor layer 51, 551 Source electrode 52 Drain electrode 53 Gate electrode 61A, 61B Source pad 62 Drain pad 63 Gate pad 71 First recess 72 Second recess 73 Third to k recesses 110 Parasitic bipolar transistor 120 Parasitic capacitor 131 First bottom surface 132 Second bottom surface 201 First mesa region 202 Second mesa section 533 Low-concentration impurity layer, drain region 711 Third lower surface 712 Fourth lower surface

Claims

1. A semiconductor device comprising a vertical MOS (Metal Oxide Semiconductor) transistor, comprising: a semiconductor substrate of a first conductivity type containing an impurity of a first concentration; a low-concentration impurity layer of the first conductivity type, formed in contact with the semiconductor substrate and containing an impurity of a second concentration lower than the first concentration; a body region of a second conductivity type different from the first conductivity type, formed in the low-concentration impurity layer including the upper surface of the low-concentration impurity layer and containing an impurity of a third concentration; a plurality of gate trenches extending in a first direction parallel to the upper surface of the semiconductor substrate and in a second direction perpendicular to the first direction, formed at equal intervals in the second direction parallel to the upper surface of the semiconductor substrate, extending from the upper surface of the low-concentration impurity layer to a depth penetrating the body region and reaching a part of the low-concentration impurity layer; a plurality of gate conductors formed in each of the plurality of gate trenches, Each of the plurality of mesa portions sandwiched between the plurality of gate trenches in the second direction has a plurality of source regions and a plurality of body contact regions alternately formed in the first direction with a first period, wherein the plurality of source regions of a first conductivity type formed in the mesa portion including the upper surface of the mesa portion, and the plurality of body contact regions of a second conductivity type containing an impurity of a fourth concentration higher than the third concentration formed in the mesa portion including the upper surface of the mesa portion, and the source electrode of the vertical MOS transistor, the upper surface of each of the plurality of mesa portions has a plurality of first recesses that are recessed in the first direction with a second period of n (n is an integer of 1 or more) times the first period, and the interior of the first recesses is filled with the source electrode, at least a part of the lower surface of each of the plurality of first recesses is in contact with one of the plurality of body contact regions or the body region, and the entire lower surface of the plurality of source regions is above the lower surface of the body region and is in contact with the body region A semiconductor device wherein the entire lower surface of the plurality of body contact regions is above the lower surface of the body region and in contact with the body region, the entire upper surface of the plurality of source regions is in contact with the source electrode, and the entire upper surface of the plurality of body contact regions is in contact with the source electrode.

2. The semiconductor device according to claim 1, wherein, in a plan view of the semiconductor substrate, each of the plurality of first recesses is contained within one of the plurality of body contact regions, and the source electrode does not contact any of the plurality of source regions within the plurality of first recesses.

3. The semiconductor device according to claim 1, wherein the width of the first recess in the second direction is equal to the width of the plurality of mesa portions in the second direction.

4. The semiconductor device according to claim 1, wherein the upper surface of each of the plurality of mesa portions further has a plurality of second recesses which are recessed in the first direction with a second period, and whose interiors are filled with the source electrode, and at least a portion of the lower surface of each of the plurality of second recesses is in contact with one of the plurality of body contact regions or the body region.

5. The semiconductor device according to claim 1, wherein n is 1.

6. The semiconductor device according to claim 2, wherein in each of the plurality of first recesses, the lower surface of the first recess is higher than the lower surface of one of the plurality of body contact regions that enclose the first recess.

7. The semiconductor device according to claim 2, wherein in each of the plurality of first recesses, the lower surface of the first recess is lower than the lower surface of one of the plurality of body contact regions that enclose the first recess.

8. The semiconductor device according to claim 7, wherein the concentration of impurities in the body region is higher in the region including at least a portion of the portion in contact with the plurality of first recesses than in other regions.

9. The semiconductor device according to claim 2, wherein the lower surface of each of the plurality of body contact regions includes a first lower surface and a second lower surface which is lower than the first lower surface, and in each of the plurality of first recesses, the lower surface of the first recess is lower than the first lower surface of one of the plurality of body contact regions enclosing the first recess and higher than the second lower surface of one of the plurality of body contact regions.

10. The semiconductor device according to claim 1, wherein the lower surface of each of the plurality of first recesses includes a third lower surface and a fourth lower surface which is lower than the third lower surface, and in each of the plurality of first recesses, the third lower surface of the first recess is above the lower surface of one of the plurality of body contact regions which enclose the first recess.

11. The semiconductor device according to claim 1, wherein the plurality of mesa portions consist of a plurality of first mesa portions and a plurality of second mesa portions arranged alternately in the second direction, and the phase of the position in the first direction in which the plurality of source regions and the plurality of body contact regions are formed in each of the plurality of first mesa portions is different from the phase of the position in the first direction in which the plurality of source regions and the plurality of body contact regions are formed in each of the plurality of second mesa portions.

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