Circuit board and semiconductor package comprising same

Abstract

Disclosed in an embodiment of the present invention is a circuit board comprising: a build-up structure; a protective layer disposed on the build-up structure; and a bump portion disposed on the protective layer, wherein the bump portion includes a first layer and a second layer disposed on the first layer, and the second layer has a concave portion extending toward the first layer.

Description

Circuit board and semiconductor package including the same

[0001] An embodiment according to the present invention relates to a circuit board and a semiconductor package.

[0002] As the performance of electrical and electronic products advances, technologies are being proposed and researched to attach a larger number of packages to substrates of limited size. However, since conventional packages are based on mounting a single semiconductor chip, there are limitations in achieving the desired performance.

[0003] A typical circuit board or package board consists of a processor package housing a processor chip and a memory package housing a memory chip, connected as a single unit. By manufacturing the processor and memory chips into a single integrated package, such package boards offer the advantages of reducing the chip mounting area and enabling high-speed signals through short paths. Due to these benefits, such package boards are widely applied in mobile devices and the like.

[0004] Meanwhile, recently, due to the high specifications of electronic devices such as servers and PCs, the size of packages is increasing. In addition, as the functions required of processors increase, there is a demand for circuit boards capable of configuring these functions separately as processor chips, mounting these processor chips, and interconnecting the processor chips. Furthermore, regarding the above processor, even when it is separated into two processor chips according to function, the number of terminals (Input / Output) provided on each processor chip is increasing.

[0005] Recently, due to factors such as 5G, the Internet of Things (IoT), improved image quality, and increased communication speeds, the number of terminals on processor chips is gradually increasing as the number of power and signals grows. Consequently, the area, thickness, and circuit pattern density of circuit boards are also increasing. When the area and thickness of a circuit board increase, it becomes difficult to miniaturize the product, and problems such as increased reliability (e.g., board warping), yield, and product cost arise. Furthermore, to ensure inter-processor chips, miniaturization of circuit patterns is required to align the pitch between the chips and the circuit board. In other words, increasing the density of circuit patterns is more advantageous in terms of product cost, reliability (e.g., warping), and product characteristics than increasing the area and thickness of the circuit board. Therefore, miniaturization of circuit patterns or through-electrodes is required.

[0006] Furthermore, bumps formed on a protective layer covering fine line widths or small circuit patterns can be bonded to the chip. However, forming a solder layer for bonding to the chip is difficult, and if a solder layer is formed, the solder swells and flows down from the bumps with fine line widths, leading to a problem of reduced electrical reliability.

[0007] An embodiment of the present invention provides a circuit board and a semiconductor package including the same, wherein the second layer has a concave portion extending downward in a bump portion composed of a first layer and a second layer, thereby improving the formation of a solder layer on the second layer and the bonding strength with the bump portion, and improving the problem of electrical reliability being reduced due to the solder layer flowing down to the side of the bump portion.

[0008] In addition, the embodiment can provide a circuit board and a semiconductor package including the same in which uniformity in solder layer formation is ensured by forming solder layers on both the chip and the bump portions and bonding them to each other.

[0009] In addition, the embodiment can provide a circuit board and a semiconductor package including the same, in which electrical reliability is further improved by more effectively suppressing the blurring of the solder layer mounted on the upper part of the second layer by making the width of the second layer and the width of the first layer different.

[0010] The problems intended to be solved in the embodiments are not limited thereto, and may also include objectives or effects that can be identified from the means of solving the problems or the forms of implementation described below.

[0011] A circuit board according to an embodiment of the present invention comprises a build-up structure; a protective layer disposed on the build-up structure; and a bump portion disposed on the protective layer; wherein the bump portion comprises a first layer and a second layer disposed on the first layer, and the second layer has a concave portion extending toward the first layer.

[0012] The upper surface of the first layer may have a concave surface corresponding to the concave portion.

[0013] The width of the second layer above may be greater than the width of the first layer above.

[0014] The first layer may include a protrusion disposed on the upper surface of the protective layer and a penetration that penetrates the protective layer.

[0015] The width of the penetration portion of the first layer above may be larger than the width of the concave portion above.

[0016] The thickness of the first layer may be greater than the thickness of the second layer.

[0017] The bump portion may include a third layer disposed on the second layer.

[0018] The width of the third layer above may be smaller than the width of the second layer above.

[0019] The thickness of the third layer may be smaller than the thickness of the first layer.

[0020] It may further include a solder layer disposed on the second layer.

[0021] The above solder layer may have a higher proportion of copper (Cu) in the lower region than in the middle region.

[0022] The above-described build-up structure comprises: a plurality of insulating layers stacked along a vertical direction; a plurality of wiring portions disposed on the upper surface of each of the plurality of insulating layers; and a plurality of via portions that penetrate at least a portion of each of the insulating layers to electrically connect the plurality of wiring portions to each other, wherein the plurality of wiring portions include pad portions disposed on the upper surface of the build-up structure, and the penetration portions may be electrically connected to the pad portions.

[0023] The bump portion comprises a first bump portion and a second bump portion that is spaced apart from the first bump portion and has a large width; and each of the first bump portion and the second bump portion may include the first layer and the second layer.

[0024] The lowest surface of the second layer of the first bump portion may be spaced vertically apart from the lowest surface of the second layer of the second bump portion.

[0025] The second layer of the second bump portion may be convex upward, and the second layer of the first bump portion may be convex downward.

[0026] An embodiment of the present invention implements a circuit board and a semiconductor package including the same, wherein the second layer has a concave portion extending downward in a bump portion composed of a first layer and a second layer, thereby improving the formation of a solder layer on the second layer and the bonding strength with the bump portion, and improving the problem of electrical reliability being reduced due to the solder layer flowing down to the side of the bump portion.

[0027] In addition, the embodiment can realize a circuit board and a semiconductor package including the same in which uniformity in solder layer formation is ensured by forming solder layers on both the chip and the bump portions and bonding them to each other.

[0028] In addition, the embodiment can realize a circuit board and a semiconductor package including the same, in which electrical reliability is further improved by more effectively suppressing the blurring of the solder layer mounted on the upper part of the second layer by making the width of the second layer and the width of the first layer different.

[0029] The various and beneficial advantages and effects of the present invention are not limited to those described above and may be more easily understood in the process of explaining specific embodiments of the present invention.

[0030] FIG. 1 is a plan view of a circuit board according to an embodiment of the present invention, and

[0031] FIG. 2 is a cross-sectional view of a circuit board according to an embodiment, and

[0032] FIG. 3 is an enlarged view of the K1 portion in FIG. 2, and

[0033] FIG. 4 is an enlarged view of the K2 portion in FIG. 2, and

[0034] FIG. 5 is an enlarged view of part K3 in FIG. 2, and

[0035] FIG. 6 is an enlarged view of the K4 portion in FIG. 2, and

[0036] FIGS. 7 and 8 are drawings illustrating the mounting of a chip on a circuit board according to an embodiment, and

[0037] FIG. 9 is a cross-sectional view of a circuit board according to another embodiment, and

[0038] FIGS. 10 to 19 are drawings illustrating a method for manufacturing a circuit board according to an embodiment, and

[0039] FIG. 20 is a cross-sectional view showing a semiconductor package according to a first embodiment, and

[0040] FIG. 21 is a cross-sectional view showing a semiconductor package according to a second embodiment, and

[0041] FIG. 22 is a cross-sectional view showing a semiconductor package according to a third embodiment, and

[0042] FIG. 23 is a cross-sectional view showing a semiconductor package according to a fourth embodiment.

[0043] The present invention is susceptible to various modifications and may have various embodiments, and specific embodiments are illustrated and described in the drawings. However, this does not specify the present invention.

[0044] It should be understood that the embodiments are not intended to be limited and include all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention.

[0045] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0046] However, the technical concept of the present invention is not limited to some of the described embodiments but can be implemented in various different forms, and within the scope of the technical concept of the present invention, one or more of the components among the embodiments may be selectively combined or substituted.

[0047] In addition, terms used in the embodiments of the present invention (including technical and scientific terms) may be interpreted in a sense that is generally understood by those skilled in the art to which the present invention belongs, unless explicitly and specifically defined otherwise. Terms that are commonly used, such as terms defined in advance, may be interpreted in consideration of their meaning in the context of the relevant technology.

[0048] Additionally, the terms used in the embodiments of the present invention are for describing the embodiments and are not intended to limit the present invention. In this specification, the singular form may include the plural form unless specifically stated otherwise in the text, and when described as “at least one of A and B and C (or more than one),” it may include one or more of all combinations that can be combined with A, B, and C.

[0049] Terms including ordinal numbers, such as second, first, etc., may be used to describe various components, but the components are not limited by the terms. The terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the second component may be named the first component, and similarly, the first component may be named the second component. The term "and / or" includes a combination of multiple related described items or any of the multiple related described items. Such terms are intended only to distinguish the component from other components and are not limited by the essence, order, sequence, etc. of the component.

[0050] And, where it is stated that a component is 'connected', 'combined', or 'joined' to another component, this may include not only cases where the component is directly connected, combined, or joined to the other component, but also cases where it is 'connected', 'combined', or 'joined' due to another component located between the component and the other component.

[0051] The terms used in this application are used merely to describe specific embodiments and are not intended to limit the invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, terms such as "comprising" or "having" are intended to specify the presence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0052] Furthermore, when described as being formed or placed "above or below" each component, "above" or "below" includes not only cases where two components are in direct contact with each other, but also cases where one or more other components are formed or placed between the two components. Additionally, when expressed as "above or below," it may include the meaning of a downward direction as well as an upward direction relative to a single component.

[0053] In addition, the expression that configuration A is positioned between configuration B and configuration C must include the meaning that configuration A is positioned such that at least a portion of it overlaps with configurations B and C in the horizontal and / or vertical directions.

[0054] Expressions referring to directions include horizontal and vertical directions, and the horizontal direction includes a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction. These are referred to as the first horizontal direction (X-axis), the second horizontal direction (Y-axis), and the vertical direction (Z-axis) according to the Cartesian coordinate system, and the meaning of being superimposed along the horizontal direction must include the meaning of being superimposed along the first horizontal direction and / or superimposed along the second horizontal direction.

[0055] Furthermore, the statement that Configuration A is exposed from Configuration B should be understood as meaning that Configuration A is exposed from Configuration B, not that Configuration A is exposed from the entire product. In other words, when Configuration A is stated to be exposed from Configuration B, it should be understood to mean that Configuration A is covered by at least a portion of Configuration C.

[0056] Furthermore, when it is stated that Component A 'contacts' Component B, this may include not only cases where the component 'contacts' the other component directly, but also cases where it 'contacts' due to another component located between the component and the other component. Therefore, if Component A is to be understood only as 'directly contacting' Component B, it is described as 'directly contacting'.

[0057] In addition, when it is stated that configuration A is 'covered' by configuration B, it should be understood that configuration A is covered by configuration B, and that the part intended for the function and purpose to be resolved is covered, and unless there are special circumstances, it should not be understood that the entire configuration A is covered by configuration B.

[0058] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in this application.

[0059] Before describing the embodiments, the electronic device to which the circuit board and semiconductor package of the embodiments are applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. The semiconductor package may include a circuit board and a semiconductor device, and the semiconductor device may be mounted on the circuit board.

[0060] Semiconductor devices may include active devices and / or passive devices. Active devices may be semiconductor chips in the form of integrated circuits (ICs) in which hundreds to millions or more of devices are integrated into a single chip. Semiconductor chips may be logic chips, memory chips, etc. Logic chips may be non-memory chips such as central processors (CPUs), graphics processors (GPUs), and FPGAs (Field Programmable Gate Arrays). For example, a logic chip may be an application processor (AP) chip comprising at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, or a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), etc., or a chip set comprising a specific combination of those listed above.

[0061] The memory chip may be a stacked memory such as HBM. In addition, the memory chip may include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory.

[0062] Meanwhile, the product family to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package) and SIP (System In Package), but is not limited thereto.

[0063] In addition, electronic devices may include smartphones, personal digital assistants, digital video cameras, digital still cameras, vehicles, high-performance servers, network systems, computers, monitors, tablets, laptops, netbooks, televisions, video games, smartwatches, automotive devices, etc. However, they are not limited to these, and it goes without saying that they may be any other electronic devices that process data in addition to these.

[0064] FIG. 1 is a plan view of a circuit board according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of a circuit board according to an embodiment, FIG. 3 is an enlarged view of portion K1 in FIG. 2, FIG. 4 is an enlarged view of portion K2 in FIG. 2, FIG. 5 is an enlarged view of portion K3 in FIG. 2, FIG. 6 is an enlarged view of portion K4 in FIG. 2, and FIG. 7 and FIG. 8 are drawings illustrating the mounting of a chip on a circuit board according to an embodiment.

[0065] Referring to FIGS. 1 and 2, a circuit board (100) according to an embodiment may include a build-up structure (110) and an electrode portion (120). In the following embodiments of the present invention, the build-up structure (110) may include a plurality of insulating layers and may be provided in a structure in which a plurality of insulating layers are stacked. The wiring or electrode portion (120) is embedded and disposed in each layer (e.g., insulating layer) of the build-up structure (110), thereby enabling the function of transmitting signals and / or power from a main board (not shown) to a semiconductor device.

[0066] Additionally, such a circuit board may include a core layer disposed within a build-up structure (110). Accordingly, the circuit board may be divided into an outer stacking area and an inner stacking area, and the inner stacking area may correspond to the core layer. When the circuit board includes a core layer, the outer stacking area disposed above the core layer may be referred to as the upper build-up layer, and the outer stacking area disposed below the core layer may be referred to as the lower build-up layer. As described above, the upper build-up layer and / or the lower build-up layer may be formed in a structure in which a plurality of insulating layers are stacked.

[0067] In an embodiment, the build-up structure (110) may be composed of a plurality of insulating layers stacked between the upper surface of the upper build-up layer and the lower surface of the lower build-up layer. For example, the build-up structure (110) may include a core layer (111), an upper build-up layer (112), and a lower build-up layer (113). Additionally, a protective layer (SR) described later may be further disposed on the build-up structure (110). Furthermore, if the circuit board is coreless, the insulating layer may be located between the upper build-up layer (112) and the lower build-up layer (113) without the aforementioned core layer (111).

[0068] Additionally, the build-up structure (110) of the circuit board (100) may be rigid or flexible. For example, the build-up structure (110) of the circuit board (100) may include glass or plastic. For example, the build-up structure (110) of the circuit board or each insulating layer forming the build-up structure (110) may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass. For example, the build-up structure (110) of the circuit board may include reinforced or flexible plastics such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, the build-up structure (110) of the circuit board may include sapphire. For example, the build-up structure (110) of the circuit board may include an optically isotropic film. For example, the build-up structure (110) of the circuit board may include COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA). For example, the build-up structure (110) of the circuit board may be formed from a material including a filler and an insulating resin. For example, the build-up structure (110) of the circuit board may have a structure in which a silica or alumina filler is disposed in a thermosetting resin or a thermoplastic resin. Furthermore, the build-up structure (110) may have a structure in which a plurality of different insulating materials are laminated, and an exemplary arrangement structure is described in more detail as follows.

[0069] In one embodiment, the build-up structure (110) may include a core layer containing a reinforcing member. Here, the core layer may refer to an insulating layer that includes a reinforcing member and has a thickness exceeding several tens (e.g., 30) μm in its vertical direction (Y-axis direction, or stacking direction). Additionally, it may include a plurality of layers that do not include a reinforcing member, which are respectively disposed on the upper and lower parts of the core layer, the upper build-up layer (112) and the lower build-up layer (113). In this case, the circuit board may be a core board. The reinforcing member may also be a reinforcing fiber or glass fiber embedded within the core layer. The following description is based on the upper build-up layer (112). Although the upper build-up layer is depicted in the drawings as including only one insulating layer, it may be composed of multiple insulating layers as depicted.

[0070] Reinforcing members may refer to glass fiber material extended along a direction perpendicular to the vertical direction of the insulation layer (e.g., horizontal direction (X-axis direction)), and may have a different meaning from spaced-apart fillers.

[0071] The core layer (111) may be made of various insulating materials. For example, the core layer (111) may be part of a copper clad laminate (CCL). Alternatively, the core layer may correspond to a copper clad laminate. Furthermore, the core layer (111) may be composed of multiple layers, and the multiple layers may be made of the same or different materials. Additionally, the core layer (111) may include via electrodes penetrating the upper and lower surfaces of the core layer (111).

[0072] And the upper build-up layer (112) or the lower build-up layer (113) may be provided with any insulating resin, such as a thermosetting and / or photocurable resin. As a thermosetting resin, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto, may be used, and materials such as prepreg (PPG) containing glass fibers may be used. As a photocurable resin, any insulating resin such as PID (Photo Imageable Dielectric) resin may be used. The aforementioned any insulating resin may be, for example, epoxy resin, bismaleimide triazine resin (BT resin), phenolic resin, etc., and may include inorganic fillers such as silica. When an insulating resin is used as a core, it may include a reinforcing material provided with glass fibers or aramid fibers. For example, when manufacturing the build-up structure (110), ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Corporation, may be used, and FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric Resin), BT, etc. may be used. For example, if the circuit board (100) is coreless, the build-up structure (110) may be provided by laminating ABF without a core layer.

[0073] In addition, the circuit board (100) according to the embodiment may further include a protective layer (SR) and a bump portion (BP).

[0074] The protective layer (SR) can function to protect the pad from external moisture or contaminants, and to prevent short-circuit problems during bonding between the semiconductor device and / or main board and the circuit board, the protective layer (SR) may, for example, be provided as a solder resist. Specifically, the semiconductor device and / or main board, etc., have multiple terminals for connecting the circuit board. In addition, multiple terminals may be arranged at a high density. When multiple terminals and the pad of the circuit board are bonded, solder may be used, for example. When solder is used, solder short-circuit problems may occur between terminals with high density; therefore, to solve such short-circuit problems, a solder resist with poor wettability with solder may be placed. In addition, the protective layer (SR) may be made of a material that has insulating properties for electrical connections. The protective layer (SR) may include resin, curing agent, photoinitiator, pigment, solvent, filler, additive, acrylic monomer, etc. Additionally, the protective layer (SR) may include any one of a photosolder resist layer, a cover-lay, and a polymer material. The protective layer (SR) may have at least one opening for connection between a terminal of a semiconductor device and a pad of a circuit board. For example, in an embodiment, the protective layer (SR) may be composed of a filler, which is a reinforcing member, and a resin.

[0075] A protective layer (SR) is disposed on a build-up structure (110). Specifically, the protective layer (SR) may include a first protective layer (SR1) disposed on an upper build-up layer (112) and a second protective layer (SR2) disposed below a lower build-up layer (113). The first protective layer (SR1) and the second protective layer (SR2) may be spaced apart from each other along the stacking direction. Hereinafter, the protective layer is described based on the first protective layer (SR1).

[0076] The bump portion (BP) may be disposed on the protective layer (SR). The bump portion (BP) may be disposed on the protective layer (SR). The bump portion (BP) may include a plurality of layers. A portion of the layer of the bump portion (BP) or the bump portion (BP) may include a protrusion (PP) disposed on the upper surface and a penetration portion (TP) penetrating the protective layer (SR). A detailed explanation thereof will be provided later.

[0077] Furthermore, the bump portion (BP) may be composed of multiple layers and may include various metals. Accordingly, the bump portion (BP) can provide improved electrical connection, durability, and reliability. For example, the bump portion (BP) may be composed of copper (Cu), gold (Au), nickel (Ni), palladium (Pd), tungsten (W), titanium (Ti), or a combination thereof. As a result, the bonding strength between the bump portion (BP) and the solder (or solder layer) mounted on the bump portion (BP) or the electrode portion (120) below the bump portion (BP) is improved, the corrosion resistance and durability of the bump portion (BP) are improved, and the loss of electrical signals can be minimized. Additionally, the bump portion (BP) may be formed on a protective layer (SR) by deposition, electroplating, etc. of various metals.

[0078] Additionally, the wiring or electrode portion (120) according to the embodiment is arranged for electrical connection between a main board, etc. and a chip (or semiconductor device, die), and includes a wiring portion (circuit pattern or circuit pattern layer, pad) and a via electrode. For example, the wiring portion of the electrode portion (120) may include a circuit pattern and a pad on the upper surface of the insulating layer. And the electrode portion (120) may include a via portion (121) penetrating the insulating layer. Accordingly, in the embodiment, the electrode portion (120) may include a via portion (121) and a wiring portion (122).

[0079] In the electrode portion (120), the circuit pattern can be designed in various forms for semiconductor devices and signal and / or power transmission and is placed within each insulating layer of the stacked build-up structure (110).

[0080] In the electrode portion (120), the via portion (121) is positioned to penetrate at least a portion of each insulating layer for vertical connection between circuit patterns placed in each insulating layer of the build-up structure (110). The via portion (121) can connect a plurality of wiring portions (122) to each other. The via portion (121) may also be composed of a plurality of parts, similar to the wiring portion. That is, the insulating layer may include via holes for the placement of via electrodes. And the via electrode may have a width wider than the circuit pattern for optimizing impedance or heat dissipation, but is not limited thereto and can be freely designed.

[0081] In the electrode portion (120), the wiring portion (122) can be placed in each insulating layer. The wiring portion (122) can be electrically connected to a circuit pattern. Additionally, the wiring portion (122) can be connected to each via portion (121). The wiring portion (122) placed on the upper and lower surfaces of the build-up structure (110) can be electrically connected to a semiconductor device and / or a main board or substrate, etc. For example, such an electrode portion (120) can be located in each layer (insulating layer) of the core layer (111), the upper build-up layer (112), and the lower build-up layer (113).

[0082] According to an embodiment, the circuit pattern of the wiring portion (122) in the electrode portion (120) may include a circuit pattern having a fine pitch (or mixed with the first pattern) and a second pattern having a pitch larger than that of the first pattern. Referring to FIG. 2, the first pattern and the second pattern may be placed on the upper build-up layer (112). The first pattern may be connected to a connecting member (SD). The second pattern may be spaced apart from the connecting member (SD) in the horizontal direction (X-axis direction). Also, the width of the second pattern in the horizontal direction (X-axis direction) of the wiring portion (122) is greater than the width of the first pattern in the horizontal direction (X-axis direction). The second pattern may refer to a pattern having the same width and spacing as a pattern used in a conventional circuit board, and the first pattern refers to a fine circuit pattern having a narrower width and spacing than the width and spacing of a pattern used in a conventional circuit board for interconnection between semiconductor devices, impedance matching, or the formation of an inductor.

[0083] And the electrode portion (120) can be connected to the aforementioned bump portion (BP). For example, the bump portion (BP) can be electrically connected to the wiring portion (122).

[0084] Additionally, the circuit board (100) may include a cavity (CV) formed inside. The cavity (CV) may be formed within the core layer (111), the upper build-up layer (112), or the lower build-up layer (113). The cavity (CV) may consist of multiple cavities. For example, the cavity (CV) may include a first cavity (CV1) and a second cavity (CV2). A connecting member (SD), which is a bridge, may be disposed in the first cavity (CV1). Other electrical components (e.g., passive components) may be disposed in the second cavity (CV2). The first cavity (CV1) and the second cavity (CV2) may be spaced apart from each other. For example, the first cavity (CV1) and the second cavity (CV2) may be positioned so as to overlap at least partially with the core layer (111) in a horizontal direction (X-axis direction). The following description is based on the first cavity (CV1) where the connecting member (SD) is placed.

[0085] The connecting member (SD) can be mounted within the first cavity (CV1). The connecting member (SD) can be electrically connected to a plurality of other chips placed on the upper part of the circuit board (100) by being disposed within the first cavity (CV1). The connecting member (SD) is made of, for example, an inorganic material (e.g., Si) or an organic material, and can be called a bridge. Additionally, the connecting member (SD) can be interchangeably referred to as a 'semiconductor device', 'chip', 'die', etc.

[0086] Additionally, the connecting member (SD) may include a connecting electrode portion on one side. For example, the connecting electrode portion may be located on the upper side of the connecting member (SD). With this configuration, the connecting member (SD) can be electrically connected to a connecting member and a substrate disposed on the outside of the circuit board (100). For example, the connecting electrode portion may be electrically connected to the electrode portion of the circuit board and may be electrically connected to other semiconductor devices or chips (CH1, CH2) on the circuit board. Additionally, different chips (CH1, CH2) may be electrically connected through the connecting member (SD).

[0087] Furthermore, the wiring portion (122) of the electrode portion (120) may include a pad portion (PD) disposed on the outer surface (e.g., upper surface / lower surface) of the build-up structure (110). For example, in an embodiment, the pad portion (PD) may be disposed on the upper surface of the build-up structure (110) or on the upper surface of the upper build-up layer (112). The pad portion (PD) may be connected to the bump portion (BP). For example, the pad portion (PD) may be electrically connected to the penetration portion (TP) of the bump portion (BP). Below, the description is based on the pad portion (PD) disposed on the upper surface of the upper build-up layer (112) of the build-up structure (110). Additionally, the pad portion (PD) disposed on the outermost side of the build-up structure (110) may be bonded to a semiconductor device, substrate, board, etc., using solder, wire, conductive adhesive, etc., and may be disposed with a width greater than the width of the circuit pattern to solve problems such as securing yield. However, not limited to this, it may have a width equal to or smaller than the width of the circuit pattern depending on the technical limitations of the bonding process.

[0088] And the pad placed on the inner side (inside the outer surface) of the build-up structure (110) among the electrode portion (120) functions to connect the via electrode and the circuit pattern. When the via electrode is placed with a width wider than the circuit pattern, a pad with a width wider than the circuit pattern is provided to ensure positional alignment during the manufacturing process of the via electrode to be placed on each circuit pattern. Accordingly, each via electrode may have an upper surface located on the same plane as the lower surface of the upper pad that is in direct contact with the via electrode, and a lower surface located on the same plane as the upper surface of the lower pad that is in direct contact with the lower surface of the via electrode. Here, the lower surface of the upper pad and the upper surface of the lower pad do not necessarily mean flat surfaces, and it should be understood that concave or convex surfaces that may appear depending on various processes may also be present.

[0089] Additionally, the electrode portion (120) may include a conductive member or a conductive coupling portion (SB) disposed below the lower build-up layer (113) and the second protective layer (SR2). The conductive member or the conductive coupling portion (SB) can perform electrical connection with other substrates, etc. Accordingly, the conductive member or the conductive coupling portion (SB) can serve as an intermediate medium for electrical signal transmission. Furthermore, the conductive member or the conductive coupling portion (SB) can dissipate heat from the circuit board or package board through heat transfer.

[0090] Furthermore, circuit boards can be classified into package boards and interposers based on their function. Package boards serve the function of mounting semiconductor devices and / or interposers. As data increases, the area of ​​the circuit board expands, or as the number of insulating layers increases, the yield of the circuit board can significantly decrease. Therefore, to improve the yield of circuit boards with high stacking counts, the yield can be enhanced by separating the circuit board into an interposer and a package board. In addition, as the density of semiconductor device terminals increases, it may be difficult to implement package board pads with an area corresponding to the terminals of the semiconductor devices. Accordingly, the interposer can act as a buffer between the pad size of the package board and the fine pattern size of the semiconductor device terminals.

[0091] The package substrate and interposer described above can be classified into a core substrate and a coreless substrate, respectively, depending on the composition of the insulating layer. In the case of a core substrate, the insulating layer may include a core layer, and the core layer may refer to a layer containing a reinforcing member among the stacked insulating layers. The reinforcing member may refer to glass fiber. By being positioned thicker than other insulating layers, the core layer may have the function of preventing warping of the circuit board during the process. However, the core layer may cause problems such as voltage drop and signal loss, or make thinning difficult. Therefore, depending on the application, a coreless substrate that does not include a core layer may be used as the insulating layer of the circuit board.

[0092] For example, as illustrated, the core layer (111) may be positioned in the center of the vertical direction of the build-up structure (110). When build-up layers are stacked on both sides of the core layer (111), the core layer (111) may be located in the center of the build-up structure (110). That is, the upper build-up layer (112) may be positioned on the core layer (111), and the lower build-up layer (113) may be positioned below the core layer (111). However, as another example as described above, if the core layer (111) is absent, the upper build-up layer (112) and the lower build-up layer (113) may be in contact with each other, and a first cavity (CV1) may be formed in the upper build-up layer (112) and / or the lower build-up layer (113).

[0093] Referring to FIG. 3, in a circuit board according to an embodiment, there may be a plurality of bump portions (BP). In particular, the bump portions (BP) may include a first bump portion (BP1) and a second bump portion (BP2). The first bump portion (BP1) is in contact with the aforementioned first pattern and may be electrically connected to the first pattern. The second bump portion (BP2) is in contact with the aforementioned second pattern and may be electrically connected to the second pattern. Accordingly, the width (W2) of the first bump portion (BP1) may be smaller than the width (W4) of the second bump portion (BP2).

[0094] Furthermore, the first bump portion (BP1) and the second bump portion (BP2) may each include multiple layers. The following description is based on the bump portion (BP).

[0095] The bump portion (BP) may include a first layer (L1), a second layer (L2), and a third layer (L3). The first layer (L1), the second layer (L2), and the third layer (L3) may be arranged sequentially along the vertical direction (Y-axis direction). That is, the first layer (L1) may be located on the first protective layer (SR1), the second layer (L2) may be placed on top of the first layer (L1), and the third layer (L3) may be placed on top of the second layer (L2).

[0096] The first layer (L1), the second layer (L2), and the third layer (L3) may be made of a conductive material. For example, the first layer (L1), the second layer (L2), and the third layer (L3) may be made of copper (Cu), gold (Au), nickel (Ni), palladium (Pd), tungsten (W), titanium (Ti), or a combination thereof, as described above. For example, the first layer (L1) and the third layer (L3) may be made of the same material, and the second layer (L2) may be made of a material different from the first layer (L1) and the third layer (L3). As an example, the first layer / second layer / third layer may be made of 'Cu / Ni / Cu'.

[0097] Additionally, the first layer (L1) may include a protrusion (PP) disposed on the upper surface of the first protective layer (SR1) and a penetration part (TP) penetrating the protective layer (SR). The penetration part (TP) and the protrusion (PP) may each include a plurality of protrusions or convex parts protruding toward the adjacent first protective layer (SR1). With this configuration, the bonding strength between the first protective layer (SR1) and the first layer (L1) can be improved. The first layer (L1) may overlap at least partially with the first protective layer (SR1) in the horizontal direction (X-axis direction).

[0098] And the second layer (L2) may be placed on the first layer (L1) and spaced apart from the first protective layer (SR1) in a vertical direction (Y-axis direction). The second layer (L2) may have a concave portion extending toward the first layer (L1).

[0099] Referring further to FIG. 4, the second layer (L2) may include a concave portion (CLP1) extending toward the first layer (L1) based on the first bump portion (BP1). Correspondingly, the upper surface of the first layer (L1) may include a concave surface (CLS1) corresponding to the concave portion (CLP1). The concave surface (CLS1) may be a surface that is convex toward the bottom.

[0100] Furthermore, the third layer (L3) may include a groove (GR1) corresponding to the concave portion (CLP1) of the second layer (L2). Similarly, the groove (GR1) of the third layer (L3) may be convex toward the bottom from the first bump portion (BP1). With this configuration, the phenomenon of the solder layer mounted on the third layer (L3) flowing down through the second layer (L2) to the first layer (L1) can be prevented. Accordingly, electrical disconnection between the first bump portions, which have a width smaller than that of the second bump portion corresponding to the first pattern which is a fine pattern, can be easily suppressed. In addition, uniformity regarding the formation of the IMC (intermetallic compound) described later can be ensured through the groove (GR1). Furthermore, the groove (GR1) can enhance wettability and adhesion with the solder layer and improve reliability by reducing stress concentration.

[0101] Additionally, in the first bump portion (BP1), the width (W1) of the first layer (L1) may be smaller than the width (W2) of the second layer (L2). Also, the width (W3) of the third layer (L3) may be smaller than the width (W2) of the second layer (L2). With this configuration, the second layer (L2) can more effectively suppress the solder layer mounted on the third layer (L3) from flowing down to the side. Furthermore, a partial solder layer can be formed on the bump portion of the circuit board without forming solder on the chip and mounting it on the circuit board. Accordingly, when bonding the solder layer of the chip with the solder layer on the bump portion of the circuit board, the solder of the chip flowing down from the bump portion of the circuit board can be more easily suppressed. In particular, during bonding, even if the solder swells during the reflow process, the phenomenon of the solder (or solder layer) swelling on the circuit board and the chip respectively and flowing down from the upper surface of the bump to the side can be prevented.

[0102] Furthermore, the width (W1) of the first layer (L1) may be the same as or different from the width (W3) of the third layer (L3). In particular, the third layer (L3) may be mixed with the solder layer mounted on top during a bonding process, etc., and become an intermetallic compound (IMC). For example, the third layer (L3) may contain copper (Cu), and by capturing Sn in Sn or SnAg of the solder layer, the overflow of the solder layer can be effectively suppressed.

[0103] Additionally, in the embodiment, the width (Wb) of the penetration portion (TP) of the first layer (L1) may be larger than the width (Wa) of the concave portion (CLP1). Accordingly, a groove (GR1) is formed on a part of the upper surface of the third layer (L3) to effectively provide bonding strength with the solder layer.

[0104] Furthermore, the thickness (T1) of the first layer (L1) may differ from the thickness (T2) of the second layer (L2) and the thickness (T3) of the third layer (L3). The thickness (T1) of the first layer (L1) may be greater than the thickness (T2) of the second layer (L2). Also, the thickness (T1) of the first layer (L1) may be greater than the thickness (T3) of the third layer (L3). And the thickness (T3) of the third layer (L3) may be less than or equal to the thickness of the second layer (L2).

[0105] Additionally, referring further to FIG. 5, in the circuit board according to the embodiment, the second bump portion (BP2) is spaced apart from the first bump portion (BP1) and may have a large width as described above. This second bump portion (BP2) may also be composed of a plurality of layers.

[0106] For example, the second bump portion (BP2) may also have a structure in which the first layer (L1), the second layer (L2), and the third layer (L3) are stacked in a vertical direction (Y-axis direction).

[0107] Additionally, in the second bump portion (BP2), the second layer (L2) may include a concave portion (CLP2) extending toward the first layer (L1). Correspondingly, the upper surface of the first layer (L1) may include a concave surface (CLS2) corresponding to the concave portion (CLP2). The concave surface (CLS2) may be a surface that is convex toward the bottom.

[0108] Furthermore, the third layer (L3) in the second bump portion (BP2) may include a groove (GR2) corresponding to the concave portion (CLP2) of the second layer (L2). Similarly, the groove (GR2) of the third layer (L3) in the second bump portion (BP2) may be convex toward the bottom. With this configuration, the phenomenon of the solder layer mounted on the third layer (L3) flowing down through the second layer (L2) to the first layer (L1) can be prevented. Accordingly, electrical disconnection between the first bump portions, which have a width smaller than that of the second bump portion corresponding to the first pattern which is a fine pattern, can be easily suppressed. In addition, uniformity regarding the formation of the IMC (intermetallic compound) described later can be ensured through the groove (GR2). Furthermore, the groove (GR2) can enhance wettability and adhesion with the solder layer and improve reliability by reducing stress concentration.

[0109] Additionally, in the second bump portion (BP2), the width (W4) of the first layer (L1) may be smaller than the width (W5) of the second layer (L2). Also, the width (W6) of the third layer (L3) may be smaller than the width (W5) of the second layer (L2). With this configuration, the second layer (L2) can more effectively suppress the solder layer mounted on the third layer (L3) from flowing down to the side. Furthermore, a partial solder layer can be formed on the bump portion of the circuit board without forming solder on the chip and mounting it on the circuit board. Accordingly, when bonding the solder layer of the chip with the solder layer on the bump portion of the circuit board, the solder of the chip flowing down from the bump portion of the circuit board can be more easily suppressed. In addition, there is an advantage of reducing the amount of solder when forming the solder layer of the chip. In addition, during bonding, even if the solder swells during the reflow process, the phenomenon of the solder (or solder layer) swelling on the circuit board and the chip respectively and flowing down from the upper surface of the bump area to the side can be prevented.

[0110] Furthermore, in the second bump portion (BP2), the width (W4) of the first layer (L1) may be the same as or different from the width (W6) of the third layer (L3). In particular, the third layer (L3) may be mixed with the solder layer mounted on top during a bonding process, etc., and become an intermetallic compound (IMC). For example, the third layer (L3) may contain copper (Cu), and by capturing Sn in Sn or SnAg of the solder layer, the overflow of the solder layer can be effectively suppressed.

[0111] As with the first bump portion, the width (Wd) of the penetration portion (TP) of the first layer (L1) in the second bump portion (BP2) may be larger than the width (Wc) of the concave portion (CLP2). Accordingly, a groove (GR2) is formed on a part of the upper surface in the third layer (L3), so that bonding strength with the solder layer can be effectively achieved.

[0112] Additionally, the width (W4 to W6) of the first layer (L1) to the third layer (L3) of the second bump portion (BP2) may be larger than the width of the first layer to the third layer of the first bump portion (BP1). In particular, the width (W4 to W6) of the first layer (L1) to the third layer (L3) of the second bump portion (BP2) may be larger than the width of the second layer, which is the maximum width of the first bump portion (BP1).

[0113] Furthermore, the difference (gap1) between the width (W4) of the first layer (L1) and the width (W5) of the second layer (L2) in the second bump portion (BP2) may be greater than the difference between the width of the first layer and the width of the second layer in the first bump portion.

[0114] Additionally, the width of the concave portion (CLP2) in the second bump portion (BP2) may be larger than the width of the concave portion in the first bump portion. Furthermore, the width of the concave portion (CLP2) in the second bump portion (BP2) may be larger than the width of the first to third layers in the first bump portion.

[0115] With this configuration, not only can the chip be mounted on the circuit board, but electrical connections via soldering with circuit elements other than the chip or additional packages can also be easily made.

[0116] Furthermore, the thickness (T4) of the first layer (L1) may differ from the thickness (T5) of the second layer (L2) and the thickness (T6) of the third layer (L3). The thickness (T4) of the first layer (L1) may be greater than the thickness (T5) of the second layer (L2). Additionally, the thickness (T4) of the first layer (L1) may be greater than the thickness (T6) of the third layer (L3).

[0117] And the thickness (T6) of the third layer (L3) may be less than or equal to the thickness of the second layer (L2).

[0118] Additionally, the first bump portion and the second bump portion (BP2) may overlap each other along the horizontal direction. In particular, the first layer of the first bump portion may overlap the first layer (L1) of the second bump portion (BP2) in the horizontal direction. And the thickness of the first layer of the first bump portion may be the same as the thickness of the first layer (L1) of the second bump portion (BP2).

[0119] Additionally, the second layer of the first bump portion may overlap horizontally with the second layer (L2) of the second bump portion (BP2). And the thickness of the second layer of the first bump portion may be the same as the thickness of the second layer (L2) of the second bump portion (BP2).

[0120] Additionally, the third layer of the first bump portion may overlap horizontally with the third layer (L3) of the second bump portion (BP2). Also, the third layer of the first bump portion and the third layer (L3) of the second bump portion (BP2) may have the same thickness.

[0121] However, the concave portion (CLP2) of the second bump portion (BP2) and the concave portion (CLP1) of the first bump portion (BP1) may have different lengths extending downwards. This may be due to the difference in width between the first bump portion (BP1) and the second bump portion (BP2). For example, the lowest surface of the second layer in the second bump portion (BP2) and the lowest surface of the second layer in the first bump portion (BP1) may not overlap in the horizontal direction but may be spaced apart in the vertical direction. As another example, the lowest surface of the second layer in the second bump portion (BP2) and the lowest surface of the second layer in the first bump portion (BP1) may be located at the same height from the first layer.

[0122] Referring further to FIG. 6, the chip (CH1) may be superimposed in a vertical direction with the first bump portion (BP1). The chip (CH1) may be electrically connected to the first bump portion (BP1). Furthermore, the chip (CH1) may include a chip bump portion (CBP) corresponding to the first bump portion (BP1). A solder layer may be mounted on each of the chip bump portion (CBP) and the first bump portion (BP1) as described above.

[0123] For example, a second solder layer (SD2) may be located on the chip bump portion (CBP). And a first solder layer (SD1) may be located on the first bump portion (BP1). In this way, solder layers are formed on both the substrate and the chip, so that bonding between the chip and the circuit board can be achieved even if the amount of the solder layer (e.g., the second solder layer) is reduced compared to the case where the solder layer is formed only on the chip. At this time, the reduced amount may correspond to the first solder layer.

[0124] FIG. 7 is a drawing of the first solder layer and the second solder layer before bonding, and FIG. 8 is a drawing of the first solder layer and the second solder layer after bonding. Referring further to FIG. 7 and FIG. 8, a bonding process can be performed when the chip (CH1) is connected to a circuit board. At this time, the first solder layer (SD1) and the second solder layer (SD2) can come into contact with each other.

[0125] The first solder layer (SD1) and the second solder layer (SD2) may have a smaller amount compared to the amount in the case where the second solder layer (SD2) is formed only on the chip (CH1).

[0126] Furthermore, the chip bump portion (CBP) may include a first sublayer (CL1), a second sublayer (CL2), and a third sublayer (CL3), similar to the first bump portion (BP1). The first sublayer (CL1), the second sublayer (CL2), and the third sublayer (CL3) may be stacked sequentially toward the first bump portion (BP1). Furthermore, the width of the second sublayer (CL2) may be greater than the widths of the first sublayer (CL1) and the third sublayer (CL3). Accordingly, the second sublayer (CL2) can also prevent overflow of the solder layer. In this way, the first bump portion (BP1) and the second bump portion (BP2) may have a symmetrical structure with respect to the horizontal direction. Furthermore, the first solder layer (SD1) and the second solder layer (SD2) may also have a symmetrical shape. For example, in the chip bump portion (CBP) of the chip, the second sublayer (CL2) may include a concave portion (CLP3) that is convex toward the top. Accordingly, overflow of the second solder layer (SD2) can be more easily prevented. Also, the extension direction of the concave portion (CLP3) in the chip bump portion (CBP) and the extension direction of the concave portion (CLP1) in the first bump portion (BP1) may be opposite to each other.

[0127] Furthermore, when bonding the chip to a circuit board, even if the first bump portion on the circuit board is miniaturized to correspond to the first pattern (e.g., pitch is 55 µm or less / diameter is 30 µm or less), the solder layer can be suppressed from flowing down along the side of the first bump portion (BP1). In addition, there may be an advantage in that the amount of the second solder layer (SD2) mounted on the chip (CH1) is reduced, making it easier to form the solder layer.

[0128] When bonding the first solder layer (SD1) and the second solder layer (SD2), a compound layer (SD) that is an intermetallic compound (IMC) can be formed in the first solder layer (SD1), the third layer (L3) of the first bump portion (BP1), the second solder layer (SD2), and the third sublayer (CL3) of the chip bump portion (CBP). That is, a compound layer (SD) can be formed by bonding.

[0129] As shown in FIG. 8, the compound layer (SD) may be a single layer. The compound layer (SD) may be located between the second layer of the first bump portion (BP1) and the second sublayer (CL2) of the chip bump portion (CBP). In addition, the concentration of the metal material of the third layer and the third sublayer may vary along the stacking direction of the compound layer (SD). For example, the third layer and the third sublayer may be made of the same metal (e.g., Cu). In this case, the concentration of the metal (Cu) in the compound layer (SD) may be greater in the upper region (UA) and the lower region (BA) than in the middle region (MA) along the stacking direction. That is, the proportion of copper in the middle region (MA) may be smaller than the proportion of copper in the lower region (BA) and the upper region (UA).

[0130] FIG. 9 is a cross-sectional view of a circuit board according to another embodiment.

[0131] A circuit board according to another embodiment may further include a build-up structure (110), an electrode portion (120), a protective layer (SR), and a bump portion (BP). Except for the details described below, the above-mentioned details may be applied in the same way.

[0132] The first bump portion (BP1) may include a concave portion (CLP1) extending downward from the second layer (L2). In other words, the concave portion (CLP1) in the first bump portion (BP1) may be convex toward the bottom. In this example, the second layer (L2) of the second bump portion (BP2) may not have a concave portion extending downward.

[0133] Accordingly, the lowest surface of the second layer (L2) in the second bump section (BP2) and the lowest surface of the second layer (L2) in the first bump section (BP1) may be separated by a predetermined distance (gap) in the vertical direction (Y-axis direction). Furthermore, the entire second layer (L2) in the second bump section (BP2) may overlap horizontally with the second layer (L2) in the first bump section (BP1). Conversely, a portion of the second layer (L2) in the first bump section (BP1) may overlap horizontally with the second layer (L2) of the second bump section (BP2). That is, at least a portion of the second layer (L2) of the first bump section (BP1) may not overlap horizontally with the second layer (L2) of the second bump section (BP2).

[0134] Furthermore, the upper surface of the first layer (L1) in the second bump portion (BP2) may not have a concave surface. Accordingly, the first layer (L1) in the second bump portion (BP2) may overlap horizontally with the first layer (L1) and the second layer (L2) of the first bump portion (BP1).

[0135] Additionally, the third layer (L3) of the second bump portion (BP2) may not have a groove. And the third layer (L3) of the first bump portion (BP1) may have a groove. Accordingly, the groove (GR1) of the third layer (L3) of the first bump portion (BP1) may overlap horizontally with the third layer (L3) and the second layer (L2) of the second bump portion (BP2).

[0136] Accordingly, at the first bump portion (BP1) in contact with the fine pitch, wettability and adhesion with the solder layer are significantly enhanced through the concave portion and groove, etc., so that the IMC formation can be performed uniformly and stably. Furthermore, by preventing the flow of the solder layer at the first bump portion (BP), electrical disconnection between the bump portions of the fine pitch is prevented, thereby improving the electrical reliability of the circuit board.

[0137] Furthermore, by not forming a concave portion in the second layer at the second bump portion that is not a fine pitch, there may be an advantage in that the processing and manufacturing process is simpler. As a variation, the second layer at the second bump portion may have a structure that is convex upward. Accordingly, bonding with the solder layer is advantageous in the beginning, and strong mechanical reliability and heat dissipation effects can be provided depending on the stress distribution characteristics.

[0138] Furthermore, the details regarding the structure of the second bump portion described above can be applied in the same way to the bump portion formed in the second protective layer below the lower build-up layer.

[0139] FIGS. 10 to 19 are drawings illustrating a method for manufacturing a circuit board according to an embodiment.

[0140] First, the circuit board according to the embodiment may include the steps of providing a core layer, forming a cavity, mounting a connecting member in the cavity, laminating a build-up layer (insulating layer) and forming an electrode portion, forming a protective layer and an opening in the protective layer, and forming a bump portion. Furthermore, the method for manufacturing the circuit board may further include the step of forming a solder layer. Except for the details described below, the description of each component may be applied as described above.

[0141] Referring to FIG. 10, a core layer (111) may be provided. Then, via holes may be formed in the core layer (111), and electrode portions may be formed. In the core layer (111), via portions (121) penetrating the core layer (111) and wiring portions (122) located on the upper and lower surfaces of the core layer (111) may be formed. Electrode portions (120) may be formed in the core layer (111). The electrode portions may be formed using manufacturing processes for printed circuit boards, such as the Additive Process, Subtractive Process, Modified Semi Additive Process (MSAP), and Semi Additive Process (SAP). Additionally, the pattern of the wiring portions may be formed by a dry film, etc.

[0142] Referring to FIG. 11, a cavity can be formed in the core layer (111). As previously described, there may be multiple cavities. For example, the cavity may include a first cavity and a second cavity, and the following description will be based on the first cavity (CV1). A bonding member (PF) may be disposed on one side (e.g., the bottom surface) of the core layer (111). The area within the side of the cavity (CV1) in the core layer (111) may be exposed. That is, the bonding member (PF) within the cavity (CV1) may be exposed by the cavity (CV1).

[0143] After the cavity (CV1) is formed, the core layer (111) can be placed on the bonding member (PF). Additionally, the cavity (CV1) may be formed after the core layer (111) is seated on the bonding member (PF).

[0144] Additionally, a connecting member (SD) may be placed on the bonding member (PF). The connecting member (SD) may be located within the cavity (CV1) of the core layer (111).

[0145] As the core layer (111) and the connecting member (SD) are placed on the bonding member (PF), the bonding member (PF) may include a convex portion extending upward between the side of the cavity (CV1) and the connecting member (SD). Furthermore, the seating of the core layer (111) or the connecting member (SD) may be performed in various sequences. The following description is based on what is shown in the drawings.

[0146] Referring to FIG. 12, an upper build-up layer (112) and a lower build-up layer (113) may be formed on the upper and lower surfaces of the core layer (111). At this time, the lower build-up layer (113) may be formed with the bonding member (PF) removed.

[0147] Referring to FIG. 13, via holes (VH1, VH2) may be formed in the upper build-up layer (112) and the lower build-up layer (113). The following description is based on the upper build-up layer, and the description of the upper build-up layer can be applied in the same way to the lower build-up layer, excluding the structure of the bump portion.

[0148] Via holes (VH1, VH2) can penetrate the upper build-up layer (112). Via holes (VH1, VH2) may include a first via hole (VH1) and a second via hole (VH2). The width of the pattern of the first via hole (VH1) may be larger than that of the second via hole (VH2). For example, the first via hole (VH1) may correspond to the second pattern, and the second via hole (VH2) may correspond to the first pattern.

[0149] Referring to FIG. 14, electrode portions (120) may be formed on the upper build-up layer (112) and the lower build-up layer (113). Electrode portions (120) may be formed on each insulating layer in the upper build-up layer (112) and the lower build-up layer (113). In the upper build-up layer and the lower build-up layer, via portions (121) penetrating each layer and wiring portions (122) located on the upper and lower surfaces of each layer may be formed. The electrode portions may be formed using manufacturing processes for printed circuit boards, such as the Additive Process, Subtractive Process, Modified Semi Additive Process (MSAP), and Semi Additive Process (SAP). Additionally, the pattern of the wiring portions may be formed by a dry film, etc.

[0150] Referring to FIG. 15, protective layers (SR1, SR2) may be formed on the upper build-up layer (112) and the lower build-up layer (113), respectively. The first protective layer (SR1) may be located on the upper build-up layer (112). The second protective layer (SR2) may be located below the lower build-up layer (113). The following description is based on the first protective layer (SR1).

[0151] Referring to FIG. 16, via holes (VH3, VH4) for forming bump portions (BP) can be formed in the first protective layer (SR1). For example, a third via hole (VH3) and a fourth via hole (VH4) can each be formed in the first protective layer (SR1). The third via hole (VH3) and the fourth via hole (VH4) can be formed by various drilling (laser, mechanical) and etching methods.

[0152] And various etching methods can be performed on the upper surface of the first protective layer (SR1). For example, etching can be performed with plasma.

[0153] Chemical copper can be formed on the first protective layer (SR1). To form the chemical copper, cleaning, etc., may be performed.

[0154] Referring to FIG. 17, a dry film (DF) can be formed on the protective layer. An opening or via (PT) having a predetermined pattern can be formed on the dry film (DF). Such opening or via (PT) can be formed corresponding to the pad.

[0155] Referring further to FIG. 18, a bump portion (BP) may be formed in an opening or via (PT). A penetration portion (TP) penetrates at least a portion of the first protective layer, and a protrusion (PP) may be located on the penetration portion (TP). The bump portion (BP) may be formed in a plurality of layers as described above. In particular, the second layer above the first layer in the bump portion (BP) may be formed to have a concave portion extending downward. For example, the aforementioned concave portion may be formed through sputtering, etching, plating solution concentration control, current density control, plating time control, and a mask.

[0156] FIG. 20 is a cross-sectional view showing a semiconductor package according to a first embodiment, FIG. 21 is a cross-sectional view showing a semiconductor package according to a second embodiment, FIG. 22 is a cross-sectional view showing a semiconductor package according to a third embodiment, and FIG. 23 is a cross-sectional view showing a semiconductor package according to a fourth embodiment.

[0157] In various semiconductor packages described below, the circuit board described above may be located in a part of the area or correspond to a single substrate.

[0158] Referring to FIG. 20, the semiconductor package of the first embodiment may include a first substrate (1100), a second substrate (1200), and a semiconductor device (1300).

[0159] The first substrate (1100) may mean a 'package substrate' or a 'circuit board', or may include such meanings. For example, the first substrate (1100) may provide a space to which at least one external substrate is coupled. The external substrate may mean a second substrate (1200) coupled on the first substrate (1100). Additionally, the external substrate may mean a main board included in an electronic device coupled to the lower part of the first substrate (1100).

[0160] Additionally, although not shown in the drawing, the first substrate (1100) can provide a space for mounting at least one semiconductor device.

[0161] The first substrate (1100) may include at least one insulating layer and an electrode portion disposed on at least one insulating layer.

[0162] A second substrate (1200) can be placed on the first substrate (1100).

[0163] The second substrate (1200) may be an interposer. For example, the second substrate (1200) may provide a space for mounting at least one semiconductor device. The second substrate (1200) may be connected to at least one semiconductor device (1300). For example, the second substrate (1200) may provide a space for mounting a first semiconductor device (1310) and a second semiconductor device (1320). The second substrate (1200) may electrically connect the first semiconductor device (1310) and the second semiconductor device (1320), and electrically connect the first and second semiconductor devices (1310, 1320) and the first substrate (1100). That is, the second substrate (1200) may perform a horizontal connection function between multiple semiconductor devices and a vertical connection function between a semiconductor device and a package substrate.

[0164] Additionally, although it has been illustrated that two semiconductor devices (1310, 1320) are disposed on the second substrate (1200) as in the example above, it is not limited thereto. For example, one semiconductor device may be disposed on the second substrate (1200), or three or more semiconductor devices may be disposed therein.

[0165] The second substrate (1200) can be placed between at least one semiconductor device (1300) and the first substrate (1100).

[0166] In one embodiment, the second substrate (1200) may be an active interposer that functions as a semiconductor device. When the second substrate (1200) functions as a semiconductor device, the semiconductor package of the embodiment may have a stacked structure in a vertical direction on the first substrate (1100) and may function as a plurality of logic chips. The ability to function as a logic chip may mean that it may have the functions of an active device and a passive device. In the case of an active device, unlike a passive device, the characteristics of current and voltage may not be linear, and in the case of an active interposer, it may have the function of an active device. Additionally, while the active interposer functions as a logic chip, it may perform a signal transmission function between the second logic chip placed on top of it and the first substrate (1100).

[0167] According to another embodiment, the second substrate (1200) may be a passive interposer. For example, the second substrate (1200) may function as a signal relay between the semiconductor device (1300) and the first substrate (1100), and may have passive device functions such as a resistor, capacitor, or inductor. For example, the number of terminals in the semiconductor device (1300) is gradually increasing due to reasons such as 5G, the Internet of Things (IOT), increased image quality, and increased communication speed. That is, the number of terminals provided in the semiconductor device (1300) is increasing, and as a result, the width of the terminals or the spacing between multiple terminals is decreasing. At this time, the first substrate (1100) may be connected to the main board of an electronic device. Accordingly, in order for the electrodes provided on the first substrate (1100) to have a width and spacing for being connected to the semiconductor device (1300) and the main board, respectively, there is a problem in that the thickness of the first substrate (1100) increases or the layer structure of the first substrate (1100) becomes complex. Therefore, in the first embodiment, a second substrate (1200) can be placed on the first substrate (1100) and the semiconductor device (1300). The second substrate (1200) may include electrodes having a fine width and spacing corresponding to the terminals of the semiconductor device (1300).

[0168] The semiconductor device (1300) may be a logic chip, a memory chip, etc. The logic chip may be a central processor (CPU), a graphics processor (GPU), etc. The memory chip may be a stacked memory such as HBM.

[0169] Meanwhile, the semiconductor package of the first embodiment may include a connection portion.

[0170] For example, the semiconductor package may include a first connection portion (1410) disposed between a first substrate (1100) and a second substrate (1200). The first connection portion (1410) can electrically connect the two substrates while coupling the second substrate (1200) to the first substrate (1100).

[0171] For example, the semiconductor package may include a second connection portion (1420) disposed between a second substrate (1200) and a semiconductor device (1300). The second connection portion (1420) can electrically connect the semiconductor device (1300) while coupling it to the second substrate (1200).

[0172] The semiconductor package may include a third connection portion (1430) disposed on the lower surface of the first substrate (1100). The third connection portion (1430) can electrically connect the first substrate (1100) to the main board while coupling them together.

[0173] At this time, the first connection part (1410), the second connection part (1420), and the third connection part (1430) can electrically connect multiple components using at least one bonding method among wire bonding, solder bonding, and direct metal-to-metal bonding. That is, since the first connection part (1410), the second connection part (1420), and the third connection part (1430) have the function of electrically connecting multiple components, when direct metal-to-metal bonding is used, the semiconductor package can be understood as an electrically connected part rather than solder or wire.

[0174] Wire bonding may refer to electrically connecting multiple components using a conductor such as gold (Au). Additionally, solder bonding may refer to electrically connecting multiple components using a material containing at least one of Sn, Ag, and Cu. Furthermore, direct metal-to-metal bonding may refer to directly bonding multiple components by applying heat and pressure between them to cause recrystallization without the use of solder, wire, conductive adhesive, etc. And direct metal-to-metal bonding may refer to a bonding method using the second connection part (1420). In this case, the second connection part (1420) may refer to a solder layer formed between multiple components by recrystallization.

[0175] Specifically, the first connection part (1410), the second connection part (1420), and the third connection part (1430) can join multiple components together by a thermal compression bonding method. A thermal compression bonding method may refer to a method of directly joining multiple components by applying heat and pressure to the first connection part (1410), the second connection part (1420), and the third connection part (1430).

[0176] At this time, in at least one of the first substrate (1100) and the second substrate (1200), the electrode on which the first connection part (1410), the second connection part (1420), and the third connection part (1430) are disposed may be provided with a protrusion extending outwardly away from the insulating layer of the corresponding substrate. The protrusion may extend outwardly from the first substrate (1100) or the second substrate (1200).

[0177] The protrusion may be referred to as a bump. The protrusion may also be referred to as a post. The protrusion may also be referred to as a pillar. Preferably, the protrusion may refer to an electrode on which a second connection portion (1420) for coupling with a semiconductor device (1300) is disposed among the electrodes of the second substrate (1200). That is, as the pitch of the terminals of the semiconductor device (1300) becomes finer, a short circuit may occur between a plurality of second connection portions (1420) that are each connected to a plurality of terminals of the semiconductor device (1300) by a conductive adhesive such as solder. Therefore, the embodiment may perform thermal compression bonding to reduce the volume of the second connection portion (1420). Accordingly, the embodiment may include a protrusion on the electrode of the second substrate (1200) on which the second connection portion (1420) is disposed, in order to secure a degree of alignment, diffusion power, and a diffusion prevention power that prevents an intermetallic compound (IMC) formed between a conductive adhesive such as solder and the protrusion from diffusing into the interposer and / or substrate.

[0178] Additionally, looking further at FIG. 20, the semiconductor package of the first embodiment may further include a connecting member (1210).

[0179] The connecting member (1210) can be a bridge substrate. For example, the connecting member (1210) may include a redistribution layer. The connecting member (1210) can function to electrically connect a plurality of semiconductor devices horizontally to each other. For example, because the area that a semiconductor device generally needs to have is too large, the connecting member (1210) may include a redistribution layer. Since the semiconductor package and the semiconductor device have a large difference in the width or breadth of the circuit pattern, a buffering role for the circuit pattern for electrical connection is required. The buffering role may mean having an intermediate size between the size of the width or breadth of the circuit pattern of the semiconductor package and the size of the width or breadth of the circuit pattern of the semiconductor device, and the redistribution layer may include a function that performs the buffering role.

[0180] In an embodiment, the connecting member (1210) may be an organic bridge. For example, the connecting member (1210) may include an organic material. For example, the connecting member (1210) may include an organic substrate containing an organic material instead of a silicon substrate. The connecting member (1210) may be embedded within the second substrate (1200).

[0181] To this end, the second substrate (1200) may include a cavity, and a connecting member (1210) may be disposed within the cavity of the second substrate (1200). The connecting member (1210) may horizontally connect a plurality of semiconductor elements disposed on the second substrate (1200).

[0182] Referring to FIG. 21, the semiconductor package of the second embodiment may include a second substrate (1200) and a semiconductor device (1300). In this case, the semiconductor package of the second embodiment may have a structure in which the first substrate (1100) is omitted compared to the semiconductor package of the first embodiment.

[0183] That is, the second substrate (1200) of the second embodiment can function as a package substrate while also functioning as an interposer.

[0184] The first connection part (1410) disposed on the lower surface of the second substrate (1200) can connect the second substrate (1200) to the main board of the electronic device.

[0185] Referring to FIG. 22, the semiconductor package of the third embodiment may include a first substrate (1100) and a semiconductor device (1300).

[0186] At this time, the semiconductor package of the third embodiment may have a structure in which the second substrate (1200) is omitted compared to the semiconductor package of the first embodiment.

[0187] That is, the first substrate (1100) of the third embodiment functions as a package substrate and can also function to connect between a semiconductor device (1300) and a main board. To this end, the first substrate (1100) may include a connecting member (1110) for connecting between a plurality of semiconductor devices. The connecting member (1110) may be an organic bridge connecting between a plurality of semiconductor devices.

[0188] Referring to FIG. 23, the semiconductor package of the fourth embodiment may further include a third semiconductor element (1330) compared to the semiconductor package of the fourth embodiment. To this end, a fourth connection portion may be further disposed on one side of the first substrate (1100).

[0189] Thus, the semiconductor package of the fourth embodiment may have a structure in which semiconductor devices are mounted on the upper and lower sides, respectively. At this time, the third semiconductor device (1330) may have a structure in which it is placed on the lower surface of the second substrate (1200) in the aforementioned circuit board or semiconductor package.

[0190] And a connecting member (1110) may be embedded in the first substrate (1100). The connecting member (1110) may horizontally connect the first and second semiconductor devices (1310, 1320).

[0191] Additionally, the first substrate (1100) may include a conductive coupling portion (1450). The conductive coupling portion (1450) may protrude further from the first substrate (1100) toward the second semiconductor device (1320). The conductive coupling portion (1450) may be referred to as a bump, or alternatively, a post. The conductive coupling portion (1450) may be disposed having a structure protruding on an electrode disposed on the uppermost side of the first substrate (1100).

[0192] A third semiconductor device (1330) may be disposed on the conductive coupling portion (1450). At this time, the third semiconductor device (1330) may be connected to the first substrate (1100) through the conductive coupling portion (1450). Additionally, a second connection portion (1420) may be disposed between the first and second semiconductor devices (1310, 1320) and the third semiconductor device (1330).

[0193] Accordingly, the third semiconductor device (1330) can be electrically connected to the first and second semiconductor devices (1310, 1320) through the second connection part (1420).

[0194] That is, the third semiconductor device (1330) is connected to the first substrate (1100) through the conductive coupling portion (1450), and can also be connected to the first and second semiconductor devices (1310, 1320) through the second connection portion (1420).

[0195] At this time, the third semiconductor device (1330) can receive a power signal and / or power through the conductive coupling portion (1450). In addition, the third semiconductor device (1330) can exchange communication signals with the first and second semiconductor devices (1310, 1320) through the second connection portion (1420).

[0196] The semiconductor package of the fourth embodiment can supply a power signal and / or power to the third semiconductor device (1330) through a conductive coupling portion (1450), thereby enabling the provision of sufficient power for driving the third semiconductor device (1330) or smooth control of power operation.

[0197] Accordingly, the embodiment can improve the driving characteristics of the third semiconductor device (1330). That is, the embodiment can solve the problem of insufficient power being supplied to the third semiconductor device (1330). Furthermore, the embodiment can allow at least one of the power signal, power, and communication signal of the third semiconductor device (1330) to be provided through different paths via the conductive coupling part (1450) and the second connection part (1420). By doing so, the embodiment can solve the problem of loss of the communication signal caused by the power signal. For example, the embodiment can minimize mutual interference between the power signal and the communication signal.

[0198] Meanwhile, the third semiconductor device (1330) in the fourth embodiment may be disposed on the first substrate (1100) having a POP (Package On Package) structure in which a plurality of package substrates are stacked. For example, the third semiconductor device (1330) may be a memory package including a memory chip. The memory package may be coupled to the conductive coupling portion (1450). At this time, the memory package may not be connected to the first and second semiconductor devices (1310, 1320).

[0199] Furthermore, the semiconductor package of the modified example may include a first substrate (1100) and first and second semiconductor devices (1310, 1320) disposed on the first substrate (1100) as in the example above. Furthermore, the semiconductor package may include a first connection portion (1410) disposed between the first substrate (1100) and the first and second semiconductor devices (1310, 1320). That is, the semiconductor package may have a structure in which the second substrate and the second connection portion are omitted in the example above.

[0200] Meanwhile, when a circuit board having the features of the invention described above is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the invention performs a semiconductor package function, it can safely protect the semiconductor chip from external moisture or contaminants, and can resolve issues such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. In addition, when it is responsible for signal transmission, it can resolve noise issues. Through this, the circuit board having the features of the invention described above enables the stable operation of IT devices or home appliances, thereby allowing the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability.

[0201] When a circuit board having the features of the invention described above is used in a transportation device such as a vehicle, it can resolve the problem of signal distortion transmitted to the transportation device, or safely protect a semiconductor chip controlling the transportation device from the outside, and further improve the stability of the transportation device by resolving problems such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0202] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment may be combined or modified and implemented in other embodiments by a person skilled in the art to which the embodiments belong. Therefore, details regarding such combinations and modifications should be interpreted as being included within the scope of the embodiments.

[0203] Although the above description has focused on the embodiments, this is merely an example and is not intended to limit the embodiments. A person skilled in the art will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For instance, each component specifically shown in the embodiments may be modified and implemented. Furthermore, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. Build-up structure; A protective layer disposed on the above-mentioned build-up structure; and Includes a bump portion disposed on the above protective layer; and The bump portion comprises a first layer and a second layer disposed on the first layer, and The second layer is a circuit board having a recess extending toward the first layer.

2. In Paragraph 1, The upper surface of the first layer is a circuit board having a concave surface corresponding to the concave portion.

3. In Paragraph 1, A circuit board in which the width of the second layer is greater than the width of the first layer.

4. In Paragraph 1, The first layer is a circuit board comprising a protrusion disposed on the upper surface of the protective layer and a penetration portion penetrating the protective layer.

5. In Paragraph 4, A circuit board in which the width of the penetration portion of the first layer is larger than the width of the concave portion.

6. In Paragraph 1, A circuit board in which the thickness of the first layer is greater than the thickness of the second layer.

7. In Paragraph 1, The above bump portion is a circuit board comprising a third layer disposed on the second layer.

8. In Paragraph 7, A circuit board in which the width of the third layer is smaller than the width of the second layer.

9. In Paragraph 7, A circuit board in which the thickness of the third layer is smaller than the thickness of the first layer.

10. In Paragraph 1, A circuit board further comprising a solder layer disposed on the second layer.

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