Circuit board and semiconductor package

Abstract

This circuit board comprises: a build-up structure including a plurality of insulating layers stacked in the vertical direction; a protective layer disposed on the build-up structure; and a plurality of insulating members disposed on the protective layer and spaced apart from each other, wherein the insulating members include a side surface, and at least a portion of the side surface is a curved surface.

Description

Circuit boards and semiconductor packages

[0001] The present embodiment relates to a circuit board and a semiconductor package.

[0002]

[0003] As the performance of electrical and electronic products advances, technologies are being proposed and researched to place a larger number of semiconductor devices on semiconductor package substrates of limited size. However, since conventional semiconductor packages are based on the mounting of a single semiconductor device, there are limitations in achieving the desired performance.

[0004] Accordingly, a semiconductor package in which multiple semiconductor devices are arranged using multiple substrates is provided. This semiconductor package has a structure in which multiple semiconductor devices are connected to each other in a horizontal direction and / or a vertical direction on the substrate. Accordingly, the semiconductor package has the advantage of efficiently utilizing the mounting area of ​​the semiconductor devices and enabling high-speed signal transmission through a short signal transmission path between the semiconductor devices.

[0005] Furthermore, semiconductor packages applied to products providing the Internet of Things (IoT), autonomous vehicles, and high-performance servers are expanding their concept into semiconductor chiplets in accordance with the trend toward high integration, as the number and / or size of semiconductor elements increase, or the functional parts of semiconductor elements are divided.

[0006] Meanwhile, as the number and / or types of semiconductor devices and / or semiconductor chiplets mounted on circuit boards become more diverse, semiconductor devices and / or semiconductor chiplets are mounted on circuit boards in various ways. For example, semiconductor devices with relatively fine electrodes can be mounted on a circuit board using a connecting member such as a microball, and semiconductor devices with relatively large electrodes can be mounted on a circuit board using a connecting member such as solder paste.

[0007] At this time, when mounting semiconductor devices using a connecting material such as solder paste, a reflow process can be performed after applying the solder paste onto pads provided on the circuit board. At this time, the solder paste is provided with flux, and the aforementioned flux may flow around the pads during the reflow process. The flow of flux can contaminate the surface of the circuit board or cause electrical short circuits that electrically connect adjacent pads. Therefore, after performing the reflow process, a defluxing process is performed to remove the aforementioned flux.

[0008] At this time, as the thickness of recent semiconductor packages decreases, the vertical distance between the pads provided on the circuit board and the electrodes of the semiconductor device may also decrease. If the aforementioned vertical distance decreases, the solution for the defluxing process may not be able to sufficiently penetrate into the space between the circuit board and the semiconductor device, and as a result, electrical reliability and / or mechanical reliability problems may occur due to the flux not being completely removed.

[0009] At this time, the aforementioned problem can be solved by increasing the vertical distance between the pad and the terminal of the semiconductor device to allow the solution for the defluxing process to penetrate sufficiently. However, as described above, semiconductor devices using microballs can be mounted on a single circuit board along with semiconductor devices using solder paste. Furthermore, if the vertical distance between the pad and the terminal of the semiconductor device is increased to improve the penetration of the aforementioned defluxing solution, the size of the microball (e.g., width in the horizontal direction and thickness in the vertical direction) may increase, and consequently, the pitch of the pads provided on the circuit board may also increase. In this case, the area of ​​the circuit board may increase, making it difficult to miniaturize the semiconductor package, or it may be difficult to place all the pads connected to the electrodes of the semiconductor device within a limited space.

[0010] Therefore, a method is required to increase the vertical distance between a pad and a semiconductor device to a certain level or more when a connecting member, such as solder paste, is placed, while implementing a fine pitch of pads provided on a circuit board.

[0011]

[0012] The present invention provides a circuit board capable of securing a penetration space for a solution for defluxing, and a semiconductor package including the same.

[0013] In addition, the invention provides a circuit board capable of preventing flux from detaching from the adhesive member from remaining, and a semiconductor package including the same.

[0014] In addition, the invention provides a circuit board capable of increasing the distance in the vertical direction with respect to a semiconductor device while implementing a fine pitch of pads, and a semiconductor package including the same.

[0015] In addition, a circuit board having a structure capable of improving the injection characteristics of a molding member and a semiconductor package including the same are provided.

[0016] In addition, the invention provides a circuit board capable of minimizing cracks and damage to an insulating member caused by external force, and a semiconductor package including the same.

[0017] In addition, the invention provides a circuit board capable of facilitating the movement of a solution for defluxing and a semiconductor package including the same.

[0018]

[0019] A circuit board according to the present embodiment comprises a build-up structure including a plurality of insulating layers stacked along a vertical direction; a protective layer disposed on the build-up structure; and a plurality of insulating members disposed on the protective layer and spaced apart from each other, wherein the insulating members include sides, and at least a portion of the sides is a curved surface.

[0020] The side of the insulating member includes a corner surface connecting a plurality of mutually perpendicular surfaces, and the curved surface may be disposed on the corner surface.

[0021] The above curved surface may have a predetermined curvature to connect the plurality of surfaces in a rounded manner.

[0022] The plurality of insulating members above may be provided with the same material as the protective layer.

[0023] The above-described build-up structure includes a pad portion disposed on the upper surface, and the plurality of insulating members may be disposed spaced apart from each other in the peripheral area of ​​the pad portion on the protective layer.

[0024] The protective layer has a through hole that exposes the pad portion from the protective layer, and the plurality of insulating members may be spaced apart from each other in the area surrounding the through hole.

[0025] The inner wall of the above-mentioned through hole may include a curved surface having a predetermined curvature.

[0026] The above-mentioned curved surface may be positioned between two regions that are mutually perpendicular or inclined at a predetermined angle.

[0027] The above curved portions may be provided in multiple numbers and arranged along the perimeter of the inner wall of the through hole.

[0028] A semiconductor package according to the present embodiment comprises: a build-up structure including a plurality of insulating layers stacked along a vertical direction; a protective layer disposed on the build-up structure; a plurality of insulating members disposed on the protective layer and spaced apart from each other; and an electronic element disposed on the plurality of insulating members, wherein the insulating members include a side surface, and at least a portion of the side surface is a curved surface.

[0029]

[0030] According to the present embodiment, the circuit board according to the embodiment may include a build-up structure comprising a plurality of insulating layers stacked along a vertical direction, a protective layer disposed on the build-up structure, and a plurality of insulating members disposed on the protective layer and spaced apart from each other. That is, the embodiment may place insulating members in a localized area on the protective layer, and by using the aforementioned insulating members, the vertical distance between the upper surface of the build-up structure and the lower surface of the semiconductor device is increased so that a sufficient space is secured for the defluxing solution to penetrate.

[0031] In other words, the insulating member can function to maintain a vertical separation distance between the upper surface of the build-up structure and the lower surface of the semiconductor device at a predetermined distance. The insulating member can function to allow the deflux solution to easily penetrate into the space between the upper surface of the build-up structure and the lower surface of the semiconductor device, thereby preventing flux from remaining on the build-up structure. Furthermore, the insulating member can allow the molding member, which will be described later, to easily flow into the space between the upper surface of the build-up structure and the lower surface of the semiconductor device, thereby enabling the semiconductor device to be stably molded into the molding member. Accordingly, the embodiment can stably protect the semiconductor device from external substances such as moisture and enable the semiconductor device to operate more stably.

[0032] In addition, the vertical thickness of the protective layer may be smaller than the vertical thickness of the insulating member, thereby resolving the problem of circuit board bending that occurs as the stress acting on the insulating member increases. Furthermore, the embodiment can prevent the width and thickness of the adhesive member from increasing in the area where a micro-ball bonding method is used, and thereby improves circuit integration density by finely refining the pitch of the pads in the micro-ball bonding area. Through this, the embodiment ensures that sufficient space is secured for the defluxing solution to penetrate, thereby resolving electrical short circuit problems and / or surface contamination problems that may occur due to residual flux.

[0033] An insulating member may be placed around the pad portion on the protective layer. For example, the insulating member may have first to fourth insulating members spaced apart from each other, thereby ensuring a space for the solution for defluxing in different areas to penetrate, and thereby solving electrical short-circuit problems and / or surface contamination problems that may occur due to residual flux.

[0034] Furthermore, multiple insulating members may be placed in the area between each of the multiple pads, thereby allowing the semiconductor device to be mounted more stably on the circuit board. For example, if the insulating members are placed only in a specific area, a problem may arise where the semiconductor device is mounted on the circuit board in a tilted state, which may degrade the electrical reliability and / or mechanical reliability of the circuit board and the semiconductor package. Accordingly, the embodiment allows the first to fourth insulating members to be placed between each pad, thereby stably supporting the semiconductor device mounted on the circuit board and improving the flatness of the semiconductor device, thus enabling the semiconductor device to be mounted more stably. Accordingly, the embodiment enables the semiconductor device to operate more stably.

[0035] In addition, by including a curved surface having a predetermined curvature on the side of the insulating member, it is possible to minimize the occurrence of cracks in the insulating member or the detachment of the insulating member from the protective layer due to damage caused by impact with a semiconductor device or jig.

[0036] In addition, the inner wall of the through hole within the protective layer includes a curved surface, which has the advantage of guiding the flow of the solution for defluxing.

[0037]

[0038] FIG. 1a is a schematic perspective view of a circuit board according to an embodiment.

[0039] FIG. 1b is a cross-sectional view taken along the AA' direction of the circuit board of FIG. 1a according to the first embodiment.

[0040] FIG. 1c is a cross-sectional view taken along the BB' direction of the circuit board of FIG. 1a according to the first embodiment.

[0041] FIG. 1d is a cross-sectional view taken along the AA' direction of the circuit board of FIG. 1a according to a second embodiment.

[0042] Figure 2a (a) is a perspective view showing a two-phase MLCC.

[0043] Figure 2a (b) is a plan view showing the circuit board after two-phase MLCCs have been mounted on it.

[0044] Figure 2b (a) is a perspective view showing a three-phase MLCC.

[0045] Figure 2b (b) is a plan view showing the circuit board after three-phase MLCCs have been mounted on it.

[0046] FIG. 3a is a plan view of the state before the protective layer and insulating member are placed in one region (R1) of FIG. 1b.

[0047] FIG. 3b is a plan view of the protective layer having through holes as shown in FIG. 3a.

[0048] FIG. 3c is a plan view of the state in which an insulating member is placed on the protective layer in FIG. 3b.

[0049] FIG. 4a is a schematic perspective view of a semiconductor package according to a first embodiment.

[0050] FIG. 4b is a plan view of the state in which a semiconductor device is mounted on a circuit board in FIG. 3c.

[0051] FIG. 4c is a cross-sectional view taken along the AA' direction in FIG. 4b.

[0052] FIG. 4d is a cross-sectional view taken along the BB' direction in FIG. 4b.

[0053] Figure 4e is a cross-sectional view taken along the CC' direction in Figure 4b.

[0054] FIG. 4f is a cross-sectional view taken along the DD' direction in FIG. 4b.

[0055] FIG. 5 is a cross-sectional view showing a semiconductor package according to a second embodiment.

[0056] FIG. 6 is a cross-sectional view showing a semiconductor package according to a third embodiment.

[0057] FIG. 7 is a cross-sectional view showing a semiconductor package according to a fourth embodiment.

[0058]

[0059] The present invention is susceptible to various modifications and may have various embodiments, and specific embodiments are illustrated and described in the drawings. However, this does not specify the present invention.

[0060] It should be understood that the embodiments are not intended to be limited and include all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention.

[0061] However, the technical concept of the present invention is not limited to some of the described embodiments but can be implemented in various different forms, and within the scope of the technical concept of the present invention, one or more of the components among the embodiments may be selectively combined or substituted.

[0062] In addition, terms used in the embodiments of the present invention (including technical and scientific terms) should be interpreted in a meaning generally understood by those skilled in the art to which the present invention pertains, unless explicitly and specifically defined otherwise. Commonly used terms, such as those defined in a dictionary, should be interpreted in consideration of their contextual meaning as described in the present invention. If a commonly used term defined in a dictionary does not match the meaning it has in the context of the description of the present invention, it should be interpreted in accordance with the meaning it has in the context of the description of the present invention. Furthermore, even if not explicitly defined in this application, it should not be interpreted in an ideal or overly formal sense based on the description of the present invention.

[0063] Furthermore, the terms used in the embodiments of the present invention are for describing the embodiments and are not intended to limit the present invention. In this specification, the singular form may include the plural form unless specifically stated otherwise in the text.

[0064] Terms containing ordinal numbers, such as "first," "second," etc., may be used to describe various components, but the meaning of the components is not limited by the ordinal numbers. Terms containing ordinal numbers are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the second component may be named the first component, and similarly, the first component may be named the second component. Furthermore, if the meaning of the component does not depart from the scope of the present invention even without ordinal numbers such as "first" and "second," the component may be referred to by excluding the ordinal number.

[0065] The term "and / or" includes a combination of multiple related listed items or any of the multiple related listed items. Such a term is used merely to distinguish a component from other components and is not limited by the nature, order, sequence, etc. of the component.

[0066] In this application, terms such as “comprising,” “provided,” and “having” are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not excluding in advance the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0067] When referring to directions, vertical and horizontal directions are used for convenience of explanation. Additionally, the horizontal direction may include a first horizontal direction perpendicular to the vertical direction, and a second horizontal direction perpendicular to the first horizontal direction and the vertical direction. Furthermore, if the vertical and horizontal directions follow a Cartesian coordinate system, they may correspond to the first horizontal direction (X-axis), the second horizontal direction (Y-axis), and the vertical direction (Z-axis), respectively; if they follow a cylindrical coordinate system, the first horizontal direction may refer to the azimuth (Φ) direction (or circumferential direction), and the second horizontal direction may refer to the radius (ρ) direction (or centrifugal direction) separated from a specific configuration; and if they follow a spherical coordinate system, the first horizontal direction may refer to the azimuth (Φ) direction (or circumferential direction), and the second horizontal direction may refer to the radius (r) direction (or centrifugal direction) separated from a specific configuration. In particular, the vertical direction may refer to the polar angle (θ) direction formed by the second horizontal direction and the Z-axis. For convenience of explanation, the first horizontal direction, the second horizontal direction, and the vertical direction may be used by combining the Cartesian coordinate system, the cylindrical coordinate system, and the spherical coordinate system described above. However, unless otherwise specified, the vertical direction refers to the Z-axis according to the Cartesian coordinate system, and the horizontal direction refers to any direction that can be defined on the XY plane; when referring to the first horizontal direction and the second horizontal direction perpendicular to the first horizontal direction, the first horizontal direction refers to the X-axis and the second horizontal direction refers to the Y-axis.

[0068] Furthermore, when described as being formed or placed "above or below" each component, "above" or "below" includes not only cases where two components are in direct contact with each other, but also cases where one or more other components are formed or placed between the two components. Additionally, when expressed as "above or below," it may include the meaning of a downward direction as well as an upward direction relative to a single component.

[0069] Furthermore, the meaning that Configuration A is positioned between Configuration B and Configuration C may include the meaning that Configuration A is positioned such that at least a portion of it overlaps with Configurations B and C in the horizontal and / or vertical directions. Unless otherwise noted, even if Configuration C is located between a virtual line extending vertically and / or horizontally from Configuration A and a virtual line extending vertically and / or horizontally from Configuration B, the meaning may include that Configuration C is positioned between Configuration A and Configuration B.

[0070] Furthermore, the statement that Configuration A is exposed from Configuration B should be understood as meaning that Configuration A is exposed from Configuration B, not that Configuration A is exposed from the entire product; and unless there are special circumstances, it should not be understood as meaning that the entirety of Configuration A is covered by Configuration B. In other words, when Configuration A is stated to be exposed from Configuration B, it should be understood to mean that Configuration C, in addition to Configurations A and B, covers Configuration A exposed from Configuration B.

[0071] Additionally, where it is stated that a component is 'connected,' 'combined,' 'connected,' or 'contacted' with another component, this may include not only cases where the component is directly connected, combined, or connected to the other component, but also cases where it is 'connected,' 'combined,' or 'connected' due to another component located between the component and the other component. Accordingly, if component A is to be understood only as being directly 'connected,' 'combined,' 'connected,' or 'contacted' with component B, it is described as being 'directly connected,' 'directly combined,' 'directly connected,' or 'directly contacted.'

[0072] In addition, when it is stated that configuration A is 'fixed' to configuration B, it should be understood that configuration A is indirectly fixed to configuration B through configuration C and / or configuration D, etc., unless otherwise specifically mentioned, considering the function and purpose to be solved, and in cases where configuration A is to be understood only as being 'directly fixed' to configuration B, it is stated as being 'directly fixed'.

[0073] In addition, when described as “flat” or “located on the same plane,” it should not be interpreted according to the dictionary definition, but rather understood by a person with ordinary knowledge in the relevant technical field to the extent that process deviations are taken into account.

[0074] Before describing the embodiment, we will briefly describe an electronic device (not shown) to which the semiconductor package of the embodiment is applied. The electronic device may be a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, etc. However, it is not limited to these, and it is obvious that it may be any other electronic device that processes data in addition to these.

[0075] The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to a semiconductor package of the embodiment. Additionally, the semiconductor package includes a circuit board, a semiconductor chip, a bonding portion for electrically connecting the semiconductor device and the circuit board, a resin portion for filling the space between the semiconductor device and the circuit board, and a molding portion for completely enclosing the semiconductor device.

[0076] Semiconductor devices may include active and / or passive components and may have various functions. Active components may be in the form of an integrated circuit (IC) in which hundreds to millions or more transistors are integrated within a single semiconductor device, and may be, for example, a logic chip, a memory chip, etc. For example, a logic chip may be an application processor (AP) device including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, or a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), etc., or a set of devices including a specific combination of those listed above. Memory chips may be stacked memory such as HBM. Additionally, memory chips may include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), or flash memory. Furthermore, passive components may be resistors, capacitors, and inductors, etc., and are not limited to semiconductor materials, and may be, for example, a Multi-Layer Ceramic Capacitor (MLCC).

[0077] The semiconductor package of the embodiment may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package) and SIP (System In Package), but is not limited thereto.

[0078] FIG. 1a is a schematic perspective view of a circuit board according to an embodiment, FIG. 1b is a cross-sectional view cut along the AA' direction of the circuit board of FIG. 1a according to a first embodiment, FIG. 1c is a cross-sectional view cut along the BB' direction of the circuit board of FIG. 1a according to a first embodiment, FIG. 1d is a cross-sectional view cut along the AA' direction of the circuit board of FIG. 1a according to a second embodiment, FIG. 2a(a) is a perspective view showing a two-phase MLCC, FIG. 2a(b) is a plan view showing the circuit board after the two-phase MLCC is mounted, FIG. 2b(a) is a perspective view showing a three-phase MLCC, FIG. 2b(b) is a plan view showing the circuit board after the three-phase MLCC is mounted, FIG. 3a is a state before the protective layer and insulating member are disposed in one region (R1) of FIG. 1b. FIG. 3B is a plan view in which a protective layer having a through hole is arranged in FIG. 3A, FIG. 3C is a plan view in which an insulating member is arranged on the protective layer in FIG. 3B, FIG. 4A is a schematic perspective view of a semiconductor package according to a first embodiment, FIG. 4B is a plan view in which a semiconductor device is mounted on a circuit board in FIG. 3C, FIG. 4C is a cross-sectional view cut along the AA' direction in FIG. 4B, FIG. 4D is a cross-sectional view cut along the BB' direction in FIG. 4B, FIG. 4e is a cross-sectional view cut along the CC' direction in FIG. 4B, FIG. 4f is a cross-sectional view cut along the DD' direction in FIG. 4B, FIG. 5 is a cross-sectional view of a semiconductor package according to a second embodiment, FIG. 6 is a cross-sectional view of a semiconductor package according to a third embodiment, and FIG. 7 is a cross-sectional view of a semiconductor package according to a fourth embodiment.

[0079] Hereinafter, with reference to FIGS. 1a to 7, a circuit board according to an embodiment and a semiconductor package including the same will be described in detail.

[0080] Referring to FIG. 1a, FIG. 1b and FIG. 1c, a circuit board (10) according to the first embodiment may include a build-up structure (100), a protective layer (140, 150) disposed on the upper and / or lower surface of the build-up structure (100), and an insulating member (160) disposed on the upper surface of the protective layer (140).

[0081] Here, the meaning of being placed on one side and the other side is not understood only as a configuration in direct contact with one side and the other side, but should also be understood as having other configurations between one side of the build-up structure (100) and the first protective layer (140), and between the other side of the build-up structure (100) and the second protective layer (150).

[0082] The build-up structure (100) includes a build-up insulating layer (110), a wiring layer (120), and a through electrode (130).

[0083] The build-up insulating layer (110) may have a structure in which a plurality of insulating layers are stacked along the vertical direction. The build-up insulating layer (110) may include a first insulating layer (111) closest to the first protective layer (140) along the vertical direction, a second insulating layer (112) located further along the vertical direction from the first protective layer (140) than the first insulating layer (111), a third insulating layer (113) located further along the vertical direction from the first protective layer (140) than the second insulating layer (112), and a fourth insulating layer (114) located further along the vertical direction from the first protective layer (140) than the third insulating layer (113). In this case, the first insulating layer (111) may refer to the uppermost insulating layer positioned at the top of the build-up insulating layer (110) having a structure in which a plurality of layers are stacked, and the fourth insulating layer (114) may refer to the lowest insulating layer positioned at the bottom of the build-up insulating layer (110) having a structure in which a plurality of layers are stacked. However, the embodiment is not limited thereto, and the build-up insulating layer (110) may further include a fifth insulating layer (not shown) positioned between the fourth insulating layer (114) and the second protective layer (125), a sixth insulating layer (not shown) positioned between the fifth insulating layer (not shown) and the second protective layer (125), etc.

[0084] The first to fourth insulating layers (111, 112, 113, 114) are arranged for vertical insulation between the first to fifth wiring layers (121, 122, 123, 124, 125) to be described later. For example, the first to fourth insulating layers (111, 112, 113, 114) may use a thermosetting insulating material containing inorganic fillers in a resin, and Ajinomoto Build-up Film (ABF) from Ajinomoto Corporation may be used. However, the embodiments are not limited thereto, and a photo-curable insulating material (Photo Image-able Dielectric, PID) for forming fine patterns may be used.

[0085] At least one of the first to fourth insulating layers (111, 112, 113, 114) may be provided with an insulating material different from at least one other. For example, at least one of the first to fourth insulating layers (111, 112, 113, 114) may include a reinforcing member (114R). In one embodiment, the reinforcing member (114R) may mean glass fiber. In another embodiment, the reinforcing member (114R) may mean GCP (Glass Core Primer). The reinforcing member (114R) may be provided within at least one insulating layer of the first to fourth insulating layers (111, 112, 113, 114) to improve the rigidity of the circuit board (10). The reinforcing member (114R) can prevent the circuit board (10) from bending significantly in a specific direction, thereby improving the positional alignment of the wiring layer (120) and the through electrode (130), and thereby improving the electrical reliability and / or mechanical reliability of the circuit board (10) and the semiconductor package. In addition, the reinforcing member (114R) can improve the rigidity of the circuit board (10), thereby improving processability in the process of mounting semiconductor devices on the circuit board (10) and improving product yield. Therefore, the reinforcing member (114R) can ensure that semiconductor devices are mounted stably on the circuit board (10) and that semiconductor devices operate stably. Through this, electronic products such as servers to which the semiconductor package is applied can operate stably, thereby improving operational reliability. As shown in FIG. 1b or FIG. 1c, the reinforcing member (114R) may be provided in the fourth insulating layer (114). That is, the circuit board (10) can be manufactured with a carrier member (not shown) placed thereon, and the fourth insulating layer (114) can be the layer furthest away from the carrier member. At this time, if a reinforcing member (114R) is placed on the fourth insulating layer (114), it can further prevent the circuit board (10) from bending in a specific direction during the process of removing the carrier member.However, the embodiments are not limited thereto, and the reinforcing member (114R) may be provided in an insulating layer other than the fourth insulating layer (114). For example, the reinforcing member (114R) may be alternately arranged along the vertical direction within the first to fourth insulating layers (111, 112, 113, 114), thereby further improving the rigidity of the circuit board (10).

[0086] The wiring layer (120) may include a first wiring layer (121) closest along a vertical direction from the first protection layer (140), a second wiring layer (122) further from the first protection layer (140) than the first wiring layer (121), a third wiring layer (123) further from the first protection layer (140) than the second wiring layer (122), a fourth wiring layer (124) further from the first protection layer (140) than the third wiring layer (121), and a fifth wiring layer (125) further from the first protection layer (140) than the fourth wiring layer (124). The wiring layer (120) may have an Embedded Trace Substrate (ETS) structure, for example, to implement a fine pattern. Specifically, among the first to fifth wiring layers (121, 122, 123, 124, 125), the wiring layer positioned at the uppermost or lowermost side can be embedded within the build-up insulating layer (110). Here, being embedded means that at least a portion of the side of the wiring layer having an ETS structure is covered by the build-up insulating layer (110). The first wiring layer (121) can be embedded within the first insulating layer (121). The first wiring layer (121) is the wiring layer closest to the semiconductor device placed on the circuit board (10). At this time, when the first wiring layer (121) is manufactured through the ETS method, the pads and traces constituting the first wiring layer (121) can be stably protected by the insulating layer, thereby enabling miniaturization and improving the circuit integration density of the first wiring layer (121). Accordingly, the semiconductor device placed on the circuit board (10) can be electrically connected more easily, and the semiconductor device can be operated more stably.

[0087] Additionally, according to an embodiment having an ETS structure, a concave recess may be provided on the upper surface of the first insulating layer (111) toward the lower surface of the first build-up insulating layer (110), and the first wiring layer (121) may be disposed within the recess of the first insulating layer (111). Additionally, the second wiring layer (122) may be disposed within the recess provided on the upper surface of the second insulating layer (112), the third wiring layer (123) may be disposed within the recess provided on the upper surface of the third insulating layer (113), the fourth wiring layer (124) may be disposed within the recess provided on the upper surface of the fourth insulating layer (114), and the fifth wiring layer (125) may protrude below the lower surface of the fourth insulating layer (114). Accordingly, as described above, the first to fifth wiring layers (121, 122, 123, 124, 125) can be miniaturized to improve circuit integration density, the first to fifth wiring layers (121, 122, 123, 124, 125) can be protected from contaminants such as external moisture, and the reliability of the semiconductor package can be improved.

[0088] The first to fifth wiring layers (121, 122, 123, 124, 125) may each include a trace that transmits signals and / or power, and a pad for connecting each trace of the first to fifth wiring layers (121, 122, 123, 124, 125) to another configuration. For example, referring to FIG. 1b or FIG. 1c, the first wiring layer (121) and the second wiring layer (122) are connected by a first through electrode (131). In this case, for the first through electrode (131) and the trace of the second wiring layer (122) to be connected, the second wiring layer (122) may include a pad connected to the first through electrode (131). FIG. 1b and FIG. 1c show only the pad of the first wiring layer (121), but the first wiring layer (121) may further include a trace connecting a plurality of pads.

[0089] The first to fifth wiring layers (121, 122, 123, 124, 125) can function to electrically connect with semiconductor devices disposed on the circuit board (10). Each of the first to fifth wiring layers (121, 122, 123, 124, 125) can be freely designed with consideration of impedance.

[0090] The first wiring layer (121) may include a plurality of pads (121a, 121b, 121c, 121d). The plurality of pads (121a, 121b, 121c, 121d) of the first wiring layer (121) may represent electrodes connected to terminals of semiconductor devices mounted on the circuit board (10). In this case, FIGS. 1b and / or FIGS. 1c are illustrated as having the first wiring layer (121) including four pads (121a, 121b, 121c, 121d), but are not limited thereto. That is, FIGS. 1b and FIGS. 1c may represent a portion of the entire area of ​​the circuit board (10) (R1), and the first wiring layer (121) may be further provided with additional pads connected to other semiconductor devices in areas other than the first area. At this time, the plurality of pads (121a, 121b, 121c, 121d) may represent a portion that overlaps along the vertical direction with the through hole (141) of the first protective layer (140) to be described later in the first wiring layer (121). Accordingly, at least two of the plurality of pads (121a, 121b, 121c, 121d) may represent an area that overlaps along the vertical direction with the through hole (141) of the first protective layer (140) to be described later in a single integrated pad.

[0091] Additionally, a through electrode (130) may be disposed within the build-up insulating layer (110) to connect each of the first to fifth wiring layers (121, 122, 123, 124, 125). The through electrode (130) may include first to fourth through electrodes (131, 132, 133, 134). For example, the first through electrode (131) is disposed between the first wiring layer (121) and the second wiring layer (122), the second through electrode (132) is disposed between the second wiring layer (122) and the third wiring layer (123), the third through electrode (133) is disposed between the third wiring layer (123) and the fourth wiring layer (124), and the fourth through electrode (134) is disposed between the fourth wiring layer (124) and the fifth wiring layer (125). The first to fifth wiring layers (121, 122, 123, 124, 125) are electrically connected to each other through the first to fourth through electrodes (131, 132, 133, 134).

[0092] The first to fourth through electrodes (131, 132, 133, 134) can be formed simultaneously in the process of placing the second to fifth wiring layers (122, 123, 124, 125). For example, in the process of placing the second wiring layer (122) below the first wiring layer (121), a through hole can be formed in the first insulating layer (111) to expose a portion of the first wiring layer (121), and thereby the second wiring layer (122) can be formed together with the first through electrode (131) that fills the through hole of the first insulating layer (111). Accordingly, the first through electrode (131) can be distinguished as a protrusion of the second wiring layer (122). Likewise, each of the second to fourth through electrodes (132, 133, 134) can be separated by a protrusion of each of the third to fifth wiring layers (123, 234, 125) and connected to another wiring layer disposed on each wiring layer.

[0093] Additionally, since the first to fifth wiring layers (121, 122, 123, 124, 125) are sequentially stacked along a vertical direction on the lower surface of the first protective layer (140), the inclination direction of each of the first to fourth through electrodes (131, 132, 133, 134) may be the same as each other. For example, each of the first to fourth through electrodes (131, 132, 133, 134) provided in the build-up structure (100) may have an inclination that widens as it faces the second protective layer (150).

[0094] The protective layer (140, 150) may include a first protective layer (140) disposed on the upper surface of the build-up structure (100) and / or a second protective layer (150) disposed on the lower surface of the build-up structure (100). The first protective layer (140) can protect the upper surface of the first wiring layer (121) and / or the first insulating layer (111) from external moisture or contaminants. Additionally, when a semiconductor element is disposed on a circuit board (10) using a material such as solder, the first protective layer (140) functions to prevent short circuits between solders due to low wettability with the solder. The first protective layer (140) may be made of a photocurable insulating material, and, for example, a solder resist may be used. However, the embodiments are not limited thereto, and the first protective layer (140) may be provided with a thermocurable insulating material that is the same insulating material as the build-up insulating layer (110). The first protective layer (140) may be provided with the same insulating material as the first insulating layer (111), and, for example, may be provided as Ajinomoto Build-up Film (ABF) from Ajinomoto Corporation.

[0095] The first protective layer (140) may have a through hole (141). The through hole (141) may penetrate the first protective layer (140) from the upper surface of the first protective layer (140) toward the lower surface of the first protective layer (140). For example, the first protective layer (140) may have a through hole (141) that exposes at least a portion of the upper surface of the build-up structure (100). The build-up structure (100) may provide a space in which at least one semiconductor element is placed, and the first protective layer (140) may include a through hole (141) that overlaps along a vertical direction with the space described above of the build-up structure (100). For example, the protective layer (140) may have a through hole (141) that overlaps along the vertical direction with a plurality of pads (121a, 121b, 121c, 121d) of the first wiring layer (121).

[0096] The through hole (141) may include a plurality of inner surfaces perpendicular to each other and a corner surface connecting the plurality of inner surfaces. Here, the corner surface may have a curved shape that connects the plurality of inner surfaces in a rounded manner. The corner surface may have a predetermined curvature. This will be described later.

[0097] An insulating member (160) may be locally disposed on a first protective layer (140) disposed on one side of a build-up structure (100). For example, the insulating member (160) may be an insulating patch disposed on the first protective layer (140), and a plurality of them may be provided on the first protective layer (140) spaced apart from each other. The insulating member (160) may be provided around a through hole (141) of the first protective layer (140). The insulating member (160) may not overlap or may be offset along a vertical direction with respect to the through hole (141) of the first protective layer (140). The insulating member (160) may be provided at a position spaced apart along a horizontal direction toward the outer side of the build-up structure (100) from the inner wall forming the through hole (141) of the first protective layer (140).

[0098] The insulating member (160) may have a cuboid shape. The insulating member (160) may have a rectangular cross-sectional shape. The side surface of the insulating member (160) may include a first surface, a second surface facing the first surface, a third surface connecting the first surface and the second surface, a fourth surface facing the third surface, a first corner surface positioned between the first surface and the third surface, a second corner surface positioned between the second surface and the third surface, a third corner surface positioned between the second surface and the fourth surface, and a fourth corner surface positioned between the first surface and the fourth surface. Here, the first to fourth corner surfaces may each be curved surfaces that roundly connect a plurality of mutually perpendicular sides. The corner surfaces of the insulating member (160) may be curved surfaces having a predetermined curvature. This will be described later.

[0099] The structure of the circuit board (10) described above is merely an example for explaining the present invention, and the technical concept of the present invention is not limited to the stacked structure of this example.

[0100] For example, the circuit board according to the embodiments of FIG. 1b and FIG. 1c may be a coreless substrate that does not have a core layer. For example, the circuit board of the first embodiment may be a circuit board manufactured by the Embedded Trace Substrate (ETS) method, and accordingly, the first to fourth insulating layers (111, 112, 113, 114) may have a structure in which they are sequentially stacked along a vertical direction from the upper side to the lower side.

[0101] Alternatively, according to the embodiment of FIG. 1d, the circuit board may be a core board having a core layer. For example, the circuit board of the second embodiment may be a circuit board manufactured by the SAP method or the MSAP method. In this case, as shown in FIG. 1c, the circuit board may have a core layer (110a), a first build-up layer (UB) disposed on one side of the core layer (110a), and a second build-up layer (LB) disposed on the lower side of the core layer (110a).

[0102] The core layer (110a) is composed of a resin such as epoxy resin or BT (bis-maleimide triazine) and a reinforcing member (110aR) such as glass fiber, and functions to improve the rigidity of the circuit board. As the number of terminals of semiconductor devices placed on the circuit board increases recently, wiring becomes more complex, and accordingly, there is a trend of increasing the thickness of the first and second build-up insulating layers (110b, 110c). Accordingly, the core layer (110a) of the present embodiment may have a thickness of 120 μm to 1200 μm to improve the overall rigidity of the circuit board and prevent excessive signal loss. A via hole penetrating one side and the other side may be formed in the core layer (110a). The via hole of the core layer (110a) may be formed using a mechanical drilling process or a CO2 laser. When a via hole of the core layer (110a) is formed using a mechanical drill, the slope of the inner wall of the via hole may be perpendicular to one side and / or the other side of the core layer (110a), and when a via hole of the core layer (110a) is formed using a CO2 laser, the inner wall of the via hole may have a plurality of concave and / or convex portions alternately stacked along the vertical direction. Here, the concave portion may refer to a concave area extending away from the horizontal center of the via hole provided in the core layer (110a), and the convex portion may refer to a protruding and / or convex area extending toward the horizontal center of the via hole provided in the core layer (110a). Additionally, the concave portion and the convex portion may be alternately provided along the vertical direction of the inner wall forming the via hole of the core layer (110a). Here, being alternately provided may mean that a convex portion is provided between a plurality of concave portions, and a concave portion is provided between a plurality of convex portions. In the case of via holes formed using a mechanical drilling process, the path for transmitting electrical signals is shortened, which may be advantageous for electrical characteristics, but the process cost may increase.In addition, when a concave and convex portion is formed on the inner wall of a via hole using a CO2 laser, the thickness of the core via electrode (130-1) provided on the inner wall of the via hole can be increased in a subsequent process, thereby having the advantage of lowering the impedance and lowering the process cost. Accordingly, the processing method of the via hole provided in the core layer (110a) can be freely and selectively used depending on the application field of the semiconductor package.

[0103] A core via electrode (130-1) may be disposed within the via hole of the core layer (110a). The core via electrode (130-1) functions to electrically connect the first build-up layer (UB) and the second build-up layer (LB). Therefore, it is desirable for the core via electrode (130-1) to densely fill the via hole for the function of resistance or heat dissipation. However, if the thickness of the core layer (110a) becomes thick as described above, it may become difficult to densely fill the core via electrode (130-1) within the via hole. For example, if one attempts to fill the via hole provided in the thick core layer (110a) as described above according to the plating process, a void may occur inside the core via electrode (130-1). The void expands due to heat generated during the operation of the semiconductor package and becomes a factor that reduces the mechanical reliability of the circuit board. Accordingly, a core via electrode (130-1) having a predetermined thickness is disposed on the inner wall of the via hole of the core layer (110a). The thickness of the core via electrode (130-1) refers to the thickness in the horizontal direction perpendicular thereto, rather than the thickness in the vertical direction in which the first build-up layer (UB), the core layer (110a), and the second build-up layer (LB) are stacked. The thickness of the core via electrode (130-1) can be disposed to have a thickness of 5㎛ to 20㎛ to prevent voltage drop occurring as the thickness of the core layer (110a) increases and to prevent the occurrence of voids. The inner side of the core via electrode (130-1) is difficult to densely fill with metal due to processes such as plating, resulting in empty spaces. These empty spaces can become a problem that makes it difficult to arrange the first build-up layer (UB) flatly when stacking the first build-up layer (UB).

[0104] Accordingly, the filling member (110aF) can be placed inside the core via electrode (130-1), thereby ensuring the flatness of the core layer (110a). For example, the filling member (110aF) can be placed in the via hole of the core layer (110a), and the core via electrode (130-1) can be placed between the inner wall of the via hole and the outer surface of the filling member (110aF), while surrounding the side of the filling member (110aF).

[0105] The upper surface of the filling member (110aF) may be in the same plane as the upper surface of the core layer (110a), or may be positioned closer to the first build-up layer (UB) along the vertical direction than the upper surface of the core layer (110a). The lower surface of the filling member (110aF) may be in the same plane as the lower surface of the core layer (110a), or may be positioned closer to the second build-up layer (LB) along the vertical direction than the lower surface of the core layer (110a). This can be freely designed to address flatness when stacking the first build-up layer (UB) and the second build-up layer (LB).

[0106] A first build-up layer (UB) is disposed on one side of the core layer (101). The first build-up layer (UB) includes a plurality of insulating layers (110b), a plurality of circuit layers (120-1), a plurality of through electrodes (130-2), a first protective layer (140a), and an insulating member (160a). A second build-up layer (LB) is disposed on the other side of the core layer (101). The second build-up layer (LB) includes a plurality of insulating layers (110c), a plurality of circuit layers (120-2), a plurality of through electrodes (130-3), and a first protective layer (150a). The respective insulating layers (110b, 110c), circuit layers (120-1, 120-2), through-electrodes (130-2, 130-3), insulating members (160a), and protective layers (140a, 150a) of the first build-up layer (UB) and the second build-up layer (LB) may correspond to the build-up insulating layer (110), wiring layer (120), through-electrode (130), and protective layers (140, 150) described in the first embodiment, and a detailed description thereof is omitted. Hereinafter, the detailed structure of the present invention will be described based on the coreless substrate shown in FIG. 1b and FIG. 1c.

[0107] The circuit board (10) can provide a space for mounting semiconductor devices. At this time, the types of semiconductor devices mounted on the circuit board (10) may vary, and the method of mounting semiconductor devices on the circuit board (10) may also vary depending on the type of semiconductor device. For example, in the case of semiconductor devices having terminals with a relatively large size or low terminal density, a bonding method using an adhesive material such as general solder paste may be used.

[0108] A bonding method using solder paste can be achieved by applying an adhesive member, such as solder paste containing flux, onto pads (121a, 121b, 121c, 121d), and then performing a reflow process while a semiconductor device is placed on the adhesive member. At this time, as the reflow process proceeds, the flux contained within the adhesive member may flow, and the flowed flux may come into contact with adjacent pads, causing electrical short circuit problems, and may come into contact with the upper surface of the build-up insulating layer, causing contamination problems on the surface of the circuit board. Therefore, after the reflow process is performed, a defluxing process to remove the aforementioned flux may be performed. The defluxing process can be achieved by infiltrating a solution for defluxing into the space between the circuit board and the semiconductor device to remove the aforementioned flux. At this time, depending on whether there is sufficient space for the solution to infiltrate, the flux may be completely removed or remain on the build-up structure (100).

[0109] At this time, the size of the space into which the solution for the defluxing process can penetrate can be determined by the horizontal distance between terminals provided on the semiconductor device and the vertical distance between the semiconductor device and the build-up structure (100). At this time, the vertical distance between the semiconductor device and the build-up structure (100) can be determined by the vertical thickness of the first protective layer (140) disposed on the build-up structure (100).

[0110] However, as circuit boards and / or semiconductor packages become thinner and lighter, the vertical thickness of the first protective layer (140) is becoming thinner, and as a result, there is a limit to increasing the vertical distance between the semiconductor device and the build-up structure (100). Furthermore, semiconductor devices using a bonding method other than a bonding method using solder paste can be mounted on the circuit board. For example, in the case of a semiconductor device having terminals with a relatively high density, a thermal compression bonding (hereinafter TC bonding) to reduce the amount of solder used can be used, or a bonding method using an adhesive member having a conductive ball inside can be used. At this time, when using a TC bonding method or a bonding method using an adhesive member equipped with a conductive ball, as the vertical thickness of the first protective layer (140) increases, the horizontal width and vertical thickness of the adhesive member increase, and as a result, the pitch between the pads (121a, 121b, 121c, 121d) may increase. At this time, recently, as the functions provided by the semiconductor device increase and the performance of the semiconductor device improves, the number of I / O terminals provided in the semiconductor device is also increasing. Accordingly, as the width and / or pitch of the I / O terminals provided in the semiconductor device become finer, if the size of the adhesive member increases as the vertical thickness of the first protective layer (140) increases, an electrical short circuit may occur in which multiple connection members come into contact with each other during the process of connecting the I / O terminals of the semiconductor device. As a result, there is a limit to increasing the vertical distance between the semiconductor device and the build-up structure (100) due to the constraint on the vertical thickness of the first protective layer (140).

[0111] Furthermore, the horizontal distance between terminals provided in the semiconductor device can be determined by the number and / or density of terminals provided in the semiconductor device. In this case, the number of terminals provided in the semiconductor device may vary depending on the type of semiconductor device. In this case, as the number of terminals provided in the semiconductor device increases, the horizontal distance between adjacent terminals may decrease, and as a result, it may be difficult to secure sufficient space for the solution for the defluxing process to penetrate.

[0112] Recently, there has been a trend to place capacitors adjacent to semiconductor devices to improve power droop characteristics when transferring power to semiconductor devices. However, when capacitors are placed as discrete devices, such as chips, there is a problem with increased inductance. For example, when considering the case where the capacitor is an MLCC, the existing 2-terminal capacitor is replaced with a 4-terminal capacitor to lower the equivalent inductance, thereby reducing the inductance and improving the power transfer characteristics delivered to the semiconductor chip.

[0113] Referring to FIG. 2a, a conventional MLCC may have two terminals. FIG. 2a (a) is a perspective view showing a two-phase MLCC, and FIG. 2a (b) is a plan view showing the two-phase MLCC after it has been mounted on a circuit board. The MLCC has a device body (200), a first terminal (210) provided on a first surface of the device body (200), and a second terminal (220) provided on a second surface opposite to the first surface of the device body (200). In this case, since the MLCC may only have two terminals (210, 220), the horizontal distance between the two terminals (210, 220) may be greater than in the case where there are more terminals. Therefore, when an MLCC is mounted on a circuit board (10), the flux can be completely removed because sufficient space can be secured for the solution to penetrate in accordance with the horizontal distance between the two terminals (210, 220).

[0114] Referring to FIG. 2b, the MLCC may have four terminals. FIG. 2b (a) is a perspective view showing a three-phase MLCC, and FIG. 2b (b) is a plan view showing the three-phase MLCC after it has been mounted on a circuit board. The MLCC may have a device body (230), a first terminal (240) provided on a first surface of the device body (230), a second terminal (250) provided on a second surface opposite to the first surface of the device body (230), a third terminal (260) provided on a third surface between the first surface and the second surface of the device body (230), and a fourth terminal (270) provided on a fourth surface opposite to the third surface of the device body (230). In this case, since the MLCC has four terminals (240, 250, 260, 270), the horizontal distance between the four terminals (240, 250, 260, 270) may be smaller than the horizontal distance when only two terminals (210, 220) are provided. Therefore, when the MLCC is mounted on the circuit board (10), it may be difficult to secure sufficient space for the solution to penetrate as the horizontal distance between the four terminals (240, 250, 260, 270) is relatively small. Consequently, the flux may not be completely removed, which may cause electrical short circuit problems or contamination of the surface of the circuit board, or become a factor that causes voids during subsequent processes such as underfill or molding, thereby reducing the reliability of the semiconductor package.

[0115] To this end, the embodiment may place an insulating member (160) in a local area on the first protective layer (140), and use the insulating member (160) to increase the vertical distance between the upper surface of the build-up structure (100) and the lower surface of the semiconductor device, thereby ensuring sufficient space for the solution for defluxing to penetrate.

[0116] That is, the insulating member (160) can function to secure a vertical separation distance greater than a predetermined distance between the upper surface of the build-up structure (100) and the lower surface of the semiconductor device. The insulating member (160) can function to allow the deflux solution to easily penetrate into the space between the upper surface of the build-up structure (100) and the lower surface of the semiconductor device, thereby preventing flux from remaining on the build-up structure (100). In addition, the insulating member (160) can function to allow the molding member, which will be described later, to easily flow into the space between the upper surface of the build-up structure (100) and the lower surface of the semiconductor device. For convenience of explanation, in FIGS. 1a to 7, the insulating member (160) is separated from the first protective layer (140) as a different layer, but is not limited thereto, and the insulating member (160) may refer to a protrusion of the first protective layer (140). For example, the first protective layer (140) and the insulating member (160) may be integrally formed, and accordingly, the insulating member (160) may be a protrusion provided horizontally spaced apart from each other on the upper surface of the first protective layer (140). As another example, the first protective layer (140) and the insulating member (160) may be separate layers. In this case, the first protective layer (140) and the insulating member (160) may be provided with the same insulating material, and as an example, solder resist may be used.

[0117] The vertical thickness (H1) of the first protective layer (140) may differ from the vertical thickness (H2) of the insulating member (160). Preferably, the vertical thickness (H1) of the first protective layer (140) may be smaller than the vertical thickness (H2) of the insulating member (160).

[0118] If the vertical thickness of the first protective layer (140) is greater than the vertical thickness (H2) of the insulating member (160), the stress caused by the heat cycle generated by the first protective layer (140) may increase, and as a result, the circuit board may bend significantly in a specific direction. Additionally, if the vertical thickness of the first protective layer (140) is greater than the vertical thickness (H2) of the insulating member (160), the width and thickness of the adhesive member in the area where the bonding method using the micro-ball described above is used may increase, and this may make it difficult to fine-tune the pitch of the pads. Furthermore, if the thickness (H2) of the insulating member (160) is smaller than the thickness (H1) of the first protective layer (140), it may be difficult to secure sufficient space for the defluxing solution to penetrate, and this may cause electrical short circuit problems and / or surface contamination problems due to residual flux.

[0119] For example, the vertical thickness (H2) of the insulating member (160) may have a range between 1.2 times and 5 times the vertical thickness (H1) of the first protective layer (140). If the vertical thickness (H2) of the insulating member (160) is less than 1.2 times the vertical thickness (H1) of the first protective layer (140), the effect achieved by the arrangement of the insulating member (160) may be insufficient, and electrical short-circuit problems and / or surface contamination problems may occur due to residual flux. If the vertical thickness (H2) of the insulating member (160) is greater than five times the vertical thickness (H1) of the first protective layer (140), the vertical distance between the build-up structure and the semiconductor device may increase excessively, and the volume of the adhesive member for mounting the semiconductor device may increase. Due to the increase in the volume of the adhesive member, cracks may occur in the adhesive member even with a small impact, causing electrical reliability problems between the semiconductor device and the build-up structure, or an electrical short circuit problem may occur where multiple adjacent adhesive members come into contact with each other due to the horizontal diffusion of the adhesive member.

[0120] Additionally, the upper surface area of ​​the insulating member (160) may differ from the upper surface area of ​​the pads (121a, 121b, 121c, 121d). For example, the insulating member (160) may be provided in multiple numbers, and the upper surface area of ​​each of the multiple insulating members (160) may be smaller than the upper surface area of ​​the pads (121a, 121b, 121c, 121d). Through this, the embodiment can minimize the area where the insulating member (160) is placed, minimize the transmission of stress acting on the insulating member (160) due to the heat cycle to the pads (121a, 121b, 121c, 121d), and further minimize the occurrence of cracks in the connecting member placed on the pads (121a, 121b, 121c, 121d).

[0121] That is, when mounting a semiconductor device on a circuit board using solder, a first protective layer (140) is placed with a predetermined thickness to have a predetermined pitch, and an insulating member (160) can be placed thicker than the first protective layer (140) to improve the Z-height and facilitate the penetration of a deflux solution when mounting an MLCC.

[0122] Additionally, as described above, for convenience of explanation, the insulating member (160) and the first protective layer (140) are described as being different layers, but are not limited thereto, and the insulating member (160) may be a protruding part of the first protective layer (140). That is, the insulating member (160) may be provided with the same material as the first protective layer (140) to reduce the difference in the coefficient of thermal expansion with the first protective layer (140), and may be provided with a different material from the first protective layer (140) to facilitate the improvement of the Z-height described above. Specifically, the first protective layer (140) described in this specification may be provided with a solder resist material, and the insulating member (160) may also be provided with a solder resist material. Additionally, the first protective layer (140) may be provided with a solder resist material, and the insulating member (160) may be provided with a thermosetting insulating material containing inorganic fillers in a resin, and Ajinomoto Build-up Film (ABF) from Ajinomoto Corporation may be used. However, the embodiments are not limited thereto, and a photo-image-able dielectric (PID) material for forming fine patterns may be used. Preferably, to reduce the difference in the coefficient of thermal expansion between the first protective layer (140) and the insulating member (160), the first protective layer (140) and the insulating member (160) are provided with the same material, and exemplarily, may be provided with solder resist. However, they are not limited thereto, and to more stably secure the Z-height, the insulating member (160) may be provided with a material different from the first protective layer (140).

[0123] Hereinafter, the arrangement structure of the pads (121a, 121b, 121c, 121d), the first protective layer (140), and the insulating member (160) of the build-up structure (100) of the embodiment will be described in more detail. At this time, the circuit board of the embodiment may provide a space for mounting a semiconductor device, and for example, may provide a space for mounting a three-phase MLCC having four terminals. Hereinafter, the arrangement structure of the pads (121a, 121b, 121c, 121d), the first protective layer (140), and the insulating member (160) of the build-up structure (100) in the space for mounting the three-phase MLCC will be described. However, the embodiments are not limited thereto, and the structure of the pads (121a, 121b, 121c, 121d), the first protective layer (140), and the insulating member (160) of the build-up structure (100) described later may also be implemented in a space where other passive and / or active components other than MLCCs are placed.

[0124] Referring to FIG. 3a, a wiring layer (320) may be disposed on the upper surface of the build-up insulating layer (310). The wiring layer (320) may represent wiring layers disposed on the upper surface of the build-up insulating layer (310) that are used as pads connected to terminals of semiconductor devices.

[0125] The wiring layer (320) may include a first wiring pattern (321), a second wiring pattern (322), and a third wiring pattern (323). The second wiring pattern (322) and the third wiring pattern (323) may be spaced apart along a first horizontal direction on the upper surface of the build-up insulation layer (310). Additionally, the first wiring pattern (321) may be provided surrounding the second wiring pattern (322) and the third wiring pattern (323) at a position spaced apart from the second wiring pattern (322) and the third wiring pattern (323).

[0126] Referring to FIG. 3b, a protective layer (330) may be disposed on a build-up insulating layer (310). The protective layer (330) may have a through hole (331) that penetrates from the upper surface of the protective layer (330) to the lower surface of the protective layer (330). At least a portion of the through hole (331) may overlap along a vertical direction with respect to the upper surface of the wiring layer (320), and another portion may overlap along a vertical direction with respect to the upper surface of the build-up insulating layer (310) in an area where the wiring layer (320) is not disposed. Through the through hole (331), a portion of the upper surface of the wiring layer (320) and a portion of the upper surface of the build-up insulating layer (310) may be exposed above the protective layer (330). Additionally, each of the first wiring pattern (321), the second wiring pattern (322), and the third wiring pattern (323) may have a pad that overlaps along the vertical direction with the through hole (331) of the protective layer (330).

[0127] For example, the first wiring pattern (321) may be superimposed along the vertical direction with respect to the through hole (331) at different locations. For example, the first wiring pattern (321) may have a first pad (321-1) superimposed along the vertical direction with respect to the through hole (331) on the first side of the through hole (331). Additionally, it may have a second pad (321-2) superimposed along the vertical direction with respect to the through hole (331) on the second side of the first wiring layer (320). The first pad (321-1) and the second pad (321-2) are part of the first wiring pattern (321), and accordingly, the first pad (321-1) and the second pad (321-2) may be connected to each other.

[0128] Additionally, the second wiring pattern (322) may include a third pad (322-1) that overlaps along a vertical direction with respect to the through hole (331) on the third side of the through hole (331). Additionally, the third wiring pattern (323) may include a fourth pad (323-1) that overlaps along a vertical direction with respect to the through hole (331) on the fourth side of the through hole (331). The direction in which the first pad (321-1) and the second pad (321-2) face each other may be perpendicular to the direction in which the third pad (322-1) and the fourth pad (323-1) face each other.

[0129] That is, a portion of the through hole (331) of the protective layer (330) may overlap along the vertical direction with the wiring layer (320), and the area overlapped along the vertical direction with the through hole (331) in the wiring layer (320) may be used as a pad (321-1, 321-2, 322-1, 323-1) connected to a terminal of a semiconductor device.

[0130] Additionally, at least a portion of the through hole (331) of the protective layer (330) may not overlap with or may be offset along the vertical direction with respect to the wiring layer (320). That is, at least a portion of the upper surface of the build-up insulating layer (310) may overlap with the through hole of the protective layer (330) in the vertical direction without overlapping with (or being offset from) the wiring layer (320). For example, one through hole (331) provided in the protective layer (330) may expose the upper surface of the build-up insulating layer (310) provided between the pads (321-1, 321-2, 322-1, 323-1) from the protective layer (330), while exposing each of the pads (321-1, 321-2, 322-1, 323-1). However, the embodiments are not limited thereto, and as another example, the through hole of the protective layer (330) may have a plurality of hole parts spaced apart from each other along the horizontal direction, and each of the plurality of hole parts may overlap along the vertical direction with each of the pads (321-1, 321-2, 322-1, 323-1). Hereinafter, we will focus on an embodiment in which a single through hole (331) overlaps in the vertical direction with the pads (321-1, 321-2, 322-1, 323-1) and also overlaps in the vertical direction with the upper surface of the build-up insulating layer (310) between the pads (321-1, 321-2, 322-1, 323-1).

[0131] For example, the area between the first pad (321-1) and the second pad (321-2), and / or the area between the third pad (322-1) and the fourth pad (323-1) may overlap along the vertical direction with the through hole (331) of the protective layer (330). In this way, the vertical distance between the circuit board and the semiconductor device in the area between the pads (321-1, 321-2, 322-1, 323-1) described above may be the vertical distance between the upper surface of the build-up insulating layer (310) and the upper surface of the semiconductor device. Accordingly, the embodiment may increase the vertical distance between the circuit board and the semiconductor device in the area between the pads (321-1, 321-2, 322-1, 323-1), thereby allowing the solution for defluxing to penetrate more easily into the area between the pads described above, and thereby allowing the flux to be removed more completely. Accordingly, the embodiment can resolve electrical reliability issues that may arise from flux not being completely removed, and furthermore, can resolve surface contamination issues that may arise from residual flux. Therefore, the embodiment can improve the electrical reliability of the circuit board and enable semiconductor devices placed on the circuit board to be placed more stably. Furthermore, the embodiment can enable semiconductor devices to operate more stably and enable products such as servers to which the semiconductor package is applied to operate more stably.

[0132] Referring to FIG. 3c, insulating members (341, 342, 343, 344) may be disposed on the protective layer (330). The insulating members (341, 342, 343, 344) may protrude from the protective layer (330) with a certain height. The insulating members (341, 342, 343, 344) may be disposed in an area that overlaps along a vertical direction with a semiconductor device mounted on a circuit board. For example, the insulating member (341, 342, 343, 344) may include an area that overlaps along a vertical direction with respect to a semiconductor device placed on a circuit board, and the overlapping area may increase the vertical distance between the semiconductor device and the pads, thereby ensuring sufficient space for a solution for deflux to penetrate. The insulating member (341, 342, 343, 344) may be placed around the pads (321-1, 321-2, 322-1, 323-1). For example, the first insulating member (341) may be placed between the first pad (321-1) and the third pad (322-1), the second insulating member (342) may be placed between the first pad (321-1) and the fourth pad (323-1), the third insulating member (343) may be placed between the second pad (321-2) and the fourth pad (323-1), and the fourth insulating member (344) may be placed between the second pad (321-2) and the third pad (322-1). The placement area of ​​the through hole (331) and the insulating members (341, 342, 343, 344) on the protective layer (330) may have a roughly rectangular shape, and each insulating member (341, 342, 343, 344) may be placed in a corner area. Accordingly, since the first to fourth insulating members (341, 342, 343, 344) are spaced apart from each other at different locations, a solution for deflux can be easily penetrated into the space between each insulating member.Furthermore, as the first to fourth insulating members (341, 342, 343, 344) are placed between each pad (321-1, 321-2, 322-1, 323-1), the semiconductor device can be more stably mounted on the circuit board (10). For example, if the insulating members (341, 342, 343, 344) are placed only in specific areas, a problem may occur in which the semiconductor device is mounted on the circuit board (10) in a tilted state, and thereby the electrical reliability and / or mechanical reliability of the circuit board and the semiconductor package may be reduced. Accordingly, the embodiment allows the first to fourth insulating members (341, 342, 343, 344) to be positioned between their respective pads (321-1, 321-2, 322-1, 323-1) so as to stably support a semiconductor device placed on a circuit board (10), thereby improving the flatness of the semiconductor device and enabling the semiconductor device to be mounted more stably. Accordingly, the embodiment enables the semiconductor device to operate more stably.

[0133] Additionally, insulating members (341, 342, 343, 344) may be placed around a through hole (331) provided in the protective layer (330). At this time, the insulating members (341, 342, 343, 344) may not overlap or may be misaligned along the vertical direction with respect to the through hole (331) provided in the protective layer (330). If the insulating member (341, 342, 343, 344) overlaps along the vertical direction with the through hole (331), the processability in the process of mounting the semiconductor device may be reduced, or at least a portion of the pad (321-1, 321-2, 322-1, 323-1) overlaps along the vertical direction with the insulating member (341, 342, 343, 344), which may reduce the processability in the process of applying the adhesive member, and the area of ​​the pad (321-1, 321-2, 322-1, 323-1) may be reduced, thereby increasing the contact resistance between the semiconductor device and the circuit board.

[0134] Insulating members (341, 342, 343, 344) may be provided at a position spaced apart along the horizontal direction from the inner wall of the through hole (331) of the protective layer (330). For example, the inner wall of the through hole (331) may have a first inner wall (331-1) extending along the first horizontal direction on the build-up insulating layer (310), and insulating members (341, 342, 343, 344) may be spaced apart from the first inner wall (331-1) by a first distance (W1) along the horizontal direction. For example, insulating members (341, 342, 343, 344) may be spaced apart from the upper perimeter of the first inner wall (331-1) by a first distance (W1) along the horizontal direction.

[0135] Additionally, the inner wall of the through hole (331) may have a second inner wall (331-2) extending along a second horizontal direction on the build-up insulating layer (310), and the insulating members (341, 342, 343, 344) may be spaced apart from the second inner wall (331-2) by a second distance (W2) along the horizontal direction. The insulating members (341, 342, 343, 344) may be spaced apart from the upper perimeter of the second inner wall (331-2) by a second distance (W2) along the horizontal direction. The first distance (W1) and the second distance (W2) may be the same or different from each other.

[0136] The first distance (W1) and the second distance (W2) may be greater than the vertical thickness of the protective layer (330). Additionally, if the first distance (W1) and the second distance (W2) are smaller than the vertical thickness of the protective layer (330), at least a portion of the insulating members (341, 342, 343, 344) may cover the through holes of the protective layer (330) due to process errors in the process of forming the insulating members (341, 342, 343, 344), and the electrical reliability and / or mechanical reliability may be reduced accordingly.

[0137] The first distance (W1) and the second distance (W2) may be smaller than the vertical thickness of the insulating member (341, 342, 343, 344). If the first distance (W1) and the second distance (W2) are larger than the vertical thickness of the insulating member (341, 342, 343, 344), the area of ​​the vertical overlap region between the insulating member (341, 342, 343, 344) and the semiconductor device may be reduced, and furthermore, a problem may occur in which at least a portion of the insulating member (341, 342, 343, 344) does not overlap with the semiconductor device in the vertical direction. Therefore, if the first distance (W1) and the second distance (W2) are greater than the vertical thickness of the insulating member (341, 342, 343, 344), the semiconductor device may not be stably placed on the circuit board, and thus mechanical reliability and / or electrical reliability problems may occur.

[0138] The side surface (347) of the insulating member (341, 342, 343, 344) may include a first surface (347a), a second surface (347b) facing the first surface (347a), a third surface (347c) connecting the first surface (347a) and the second surface (347b), and a fourth surface (347d) facing the third surface (347c). By the first to fourth surfaces (347a, 347b, 347c, 347d), the insulating member (341, 342, 343, 344) may have a roughly rectangular cross-sectional shape. The first to fourth surfaces (347a, 347b, 347c, 347d) of the insulating members (341, 342, 343, 344) may each be perpendicular to an adjacent surface.

[0139] The insulating member (341, 342, 343, 344) may include a corner surface (348). The corner surface (348) may form an edge on the side of the insulating member (341, 342, 343, 344). For example, the corner surface (348) may include a first corner surface connecting the first surface (347a) and the third surface (347c), a second corner surface connecting the second surface (347b) and the third surface (347c), a third corner surface connecting the second surface (347b) and the fourth surface (347d), and a fourth corner surface connecting the first surface (347a) and the fourth surface (347d).

[0140] The corner surface (348) of the insulating member (341, 342, 343, 344) may be formed rounded to connect a plurality of mutually perpendicular sides. The corner surface (348) of the insulating member (341, 342, 343, 344) may be a curved surface having a predetermined curvature. Due to the curved shape of the corner surface (348) of the insulating member (341, 342, 343, 344), the insulating member (341, 342, 343, 344) may have an increased horizontal separation area from the inner wall of the through hole (331).

[0141] In the process of bonding a semiconductor device onto a pad (321-1, 321-2, 322-1, 323-1), if misalignment of the semiconductor device occurs, contact may occur between the side of the semiconductor device and the insulating member (341, 342, 343, 344). In this case, a crack may occur in the corner area of ​​the insulating member (341, 342, 343, 344), which has relatively weak rigidity, due to contact with the semiconductor device or a jig for aligning the semiconductor device, or a problem may occur in which the insulating member (341, 342, 343, 344) separates from the protective layer (330).

[0142] According to the embodiment, external impact can be minimized by forming the corner surface (348), which is the corner area of ​​the insulating member (341, 342, 343, 344) that has relatively weak rigidity, into a curved surface having a predetermined curvature. In addition, by increasing the horizontal distance from the inner wall of the through hole (331) through the curved corner surface (348), the process of applying an adhesive member for bonding semiconductor devices can be easily performed, and the placement space for the pads (321-1, 321-2, 322-1, 323-1) can be secured widely, thereby minimizing contact resistance between the semiconductor device and the circuit board. In addition, the penetration of the solution for defluxing toward the through hole (331) can be guided by the rounded curved shape.

[0143] In the embodiment, it was described as an example where all four corner surfaces of the insulating member (341, 342, 343, 344) are curved, but this is not limited thereto, and among the four corner surfaces of the insulating member (341, 342, 343, 344), only the corner surface facing the inner wall of the through hole (331) in a horizontal direction may be formed with a curved surface. For example, based on FIG. 3c, the second corner surface, the third corner surface, and the fourth corner surface facing the inner wall of the through hole (331) may be formed with a curved surface, and the first corner surface connecting the first surface (347a) and the third surface (347c) may not be a curved surface.

[0144] As a variation example, a cushioning member (not shown) having a curved shape with an outer surface having a predetermined curvature may be disposed on the four corner surfaces of the insulating member (341, 342, 343, 344), and the cushioning member may be coupled to the outer surface of the insulating member (341, 342, 343, 344). The cushioning member may be made of the same material as the insulating member (341, 342, 343, 344), but is not limited thereto, and may be made of a different material from the insulating member (341, 342, 343, 344). The cushioning member is disposed in the corner area of ​​the insulating member (341, 342, 343, 344) so ​​as to minimize the transmission of impact with the semiconductor device or jig to the insulating member (341, 342, 343, 344).

[0145] Referring to FIG. 3c, the inner wall of the through hole (331) may include a curved portion (333). The curved portion (333) may be positioned in the corner area of ​​the inner wall of the through hole (331). Here, the corner area may refer to an area positioned between two areas that are mutually perpendicular or inclined at a predetermined angle. For example, the inner wall of the through hole (331) may include a first inner wall (331-1) extending along a first horizontal direction and a second inner wall (331-2) extending along a second horizontal direction perpendicular to the first horizontal direction. In this case, the curved portion (333) may be positioned between the first inner wall (331-1) and the second inner wall (331-2). The curved portion (333) may have a predetermined curvature and may be a surface that roundly connects the first inner wall (331-1) and the second inner wall (331-2). Due to the curved portion (333), impact resulting from contact with a semiconductor device or jig can be minimized in the corner area of ​​the inner wall of the through hole (331), where rigidity is relatively weak. Accordingly, the separation of the protective layer (330) from the build-up insulating layer (310) or the deformation of the formation area of ​​the through hole (331) into a shape different from the set area can be minimized. In addition, due to the curved shape of the corner area of ​​the inner wall of the through hole (331), there is an advantage that the flow of the solution in the corner area can be easily guided.

[0146] The corner area of ​​the inner wall of the through hole (331) may overlap in a vertical direction with at least one of the pads (321-1, 321-2, 322-1, 323-1), and accordingly, the curved portion (333) may also overlap in a vertical direction with at least one of the pads (321-1, 321-2, 322-1, 323-1). Accordingly, the flow of the solution for defluxing in the placement area of ​​the pads (321-1, 321-2, 322-1, 323-1) can be more easily guided. The curved portion (333) may be provided in multiple numbers along the perimeter of the inner wall of the through hole (331) and arranged spaced apart from each other.

[0147] Referring to FIGS. 4a and 4b, the semiconductor package of the embodiment may include a circuit board and a semiconductor element (440) disposed on the circuit board.

[0148] The circuit board may include a build-up structure (400), a first protective layer (410), and a second protective layer (420), and a plurality of insulating members (430) spaced apart from each other may be disposed on the first protective layer (410).

[0149] Additionally, the build-up structure (400) may include a build-up insulating layer (401) and a plurality of pads (402, 403, 404, 405). Additionally, the first protective layer (410) may be disposed on the build-up insulating layer (401) and may have a through hole (411) that overlaps along the vertical direction with the plurality of pads (402, 403, 404, 405).

[0150] A semiconductor device (440) may be placed on a build-up structure (400). The semiconductor device (440) may have a device body (441) and first to fourth terminals (441, 443, 444, 445). Each of the first to fourth terminals (441, 443, 444, 445) may be electrically connected through a pad (402, 403, 404, 405) and an adhesive member (450).

[0151] The semiconductor device (440) may include regions (OR1, OR2, OR3, OR4) that overlap with insulating members (431, 432, 433, 434) along the vertical direction. Here, the semiconductor device (440) includes active devices such as CPU, Memory, GPU, FPGA, etc., and should be interpreted to mean not only devices made of semiconductor materials such as silicon (Si), but also capacitors such as MLCC and electronic devices.

[0152] For example, the semiconductor device (440) may include a first overlapping region (OR1) that overlaps along a vertical direction with the first insulating member (431), a second overlapping region (OR2) that overlaps along a vertical direction with the second insulating member (432), a third overlapping region (OR3) that overlaps along a vertical direction with the third insulating member (433), and a fourth overlapping region (OR4) that overlaps along a vertical direction with the fourth insulating member (434). Additionally, the first to fourth overlapping regions (OR1, OR2, OR3, OR4) may be located in the corner regions of the semiconductor device (440). By positioning the first to fourth overlapping regions (OR1, OR2, OR3, OR4) in the corner regions of the semiconductor device (440), the transmission of stress caused by the heat cycle of the insulating members (431, 432, 433, 434) to the semiconductor device (440) can be minimized, thereby allowing the semiconductor device (440) to be placed more stably on the circuit board.

[0153] Additionally, the planar area of ​​each of the first to fourth overlapping regions (OR1, OR2, OR3, OR4) may satisfy a range of 2% to 7% of the planar area of ​​the semiconductor device (440). If the planar area of ​​each of the first to fourth overlapping regions (OR1, OR2, OR3, OR4) is less than 2% of the planar area of ​​the semiconductor device (440), the semiconductor device (440) may not be stably supported by the insulating member (431, 432, 433, 434), and thereby the semiconductor device (440) may be mounted on the circuit board in a tilted state. If the planar area of ​​each of the first to fourth overlapping regions (OR1, OR2, OR3, OR4) exceeds 7% of the planar area of ​​the semiconductor device (440), the effect of expanding the space for the solution for defluxing may be insufficient, and the resulting improvement effect for removing flux may be insufficient.

[0154] That is, the semiconductor device (440) includes a plurality of terminals, and the plurality of terminals may include an overlapping area that overlaps with an insulating member (431, 432, 433, 434) along the vertical direction and a non-overlapping area that is offset from an insulating member (160) along the vertical direction. In addition, the overlapping area may include a part of the lower surface of the first terminal (442) of the semiconductor device (440) and a part of the lower surface of the second terminal (443). Furthermore, the non-overlapping area may include the remaining part of the lower surface of the first terminal (442) of the semiconductor device, the remaining part of the lower surface of the second terminal (443), the entire area of ​​the lower surface of the third terminal (444), and the entire area of ​​the lower surface of the fourth terminal (445).

[0155] Additionally, each of the above-described non-overlapping regions may overlap along a vertical direction with the pads and may come into contact with the adhesive member (445). Furthermore, each of the above-described overlapping regions may be positioned in direct contact with the insulating members (431, 432, 433, 434), or may be spaced apart along a vertical direction from the insulating members (431, 432, 433, 434) with the adhesive member (445) in between.

[0156] As described above, the corner surface (438) of the insulating member (431, 432, 433, 434) is formed as a rounded curved surface, so that impact with the semiconductor device (440) or the jig can be minimized during the coupling process with the semiconductor device (440). At least a portion of the corner surface (438) may be arranged to overlap with the semiconductor device (440) in a vertical direction.

[0157] In addition, as a curved portion (413) is also provided in the corner area of ​​the inner wall of the through hole (411), impact with the semiconductor device (440) or jig is minimized, and the flow of the solution for deflux can be easily guided within the through hole (411).

[0158] Referring to FIGS. 4c to 4f, a first pad (402), a second pad (403), a third pad (404), and a fourth pad (405) may be disposed on the upper surface of the build-up insulating layer (401). Additionally, a protective layer (410) having through holes that overlap along a vertical direction with the first pad (402), the second pad (403), the third pad (404), and the fourth pad (405) may be disposed on the upper surface of the build-up insulating layer (401).

[0159] An adhesive member (450) may be disposed on the first pad (402), the second pad (403), the third pad (404), and the fourth pad (405). Additionally, a semiconductor device (440) may be disposed on the adhesive member (450). The semiconductor device (440) may have a device body (441), a first terminal (442) connected to the first pad (402), a second terminal (443) connected to the second pad (403), a third terminal (444) connected to the third pad (404), and a fourth terminal (445) connected to the fourth pad (405). At this time, each of the first terminal (442), second terminal (443), third terminal (444), and fourth terminal (445) of the semiconductor device (440) may include an area that overlaps in a vertical direction with each of the first pad (402), second pad (403), third pad (404), and fourth pad (405), and this area may include an area that does not come into contact with the circuit board. For example, the area overlapping along the vertical direction with the first pad (402), second pad (403), third pad (404), and fourth pad (405) of each of the first terminal (442), second terminal (443), third terminal (444), and fourth terminal (445) of the semiconductor device (440) may be spaced apart by a first vertical distance (H2) from the upper surface of the protective layer (410) of the circuit board without contacting the insulating member (431, 432, 433, 434), and the first vertical distance (H2) may correspond to the thickness of the insulating member (431, 432, 433, 434) disposed on the protective layer (410).By doing so, the embodiment can increase the vertical distance between the semiconductor device (440) and the circuit board by a first vertical distance (H2) corresponding to the thickness of the insulating member (431, 432, 433, 434), thereby sufficiently securing a space for the solution for defluxing to penetrate, which can improve the problem of voids occurring during subsequent processes such as underfill and / or molding, and accordingly, significantly improve the electrical reliability and / or mechanical reliability of the circuit board and the semiconductor package.

[0160] Additionally, the semiconductor device (440) may include an area that overlaps along the vertical direction with the insulating member (431, 432, 433, 434). Furthermore, the overlapped areas (OR1, OR, OR3, OR4) of the semiconductor device (440) that overlap along the vertical direction with the insulating member (431, 432, 433, 434) may be positioned in direct contact with the insulating member (431, 432, 433, 434). Through this, the semiconductor device (440) can be supported by the insulating member (431, 432, 433, 434) and more stably seated on the circuit board. However, the embodiment is not limited thereto.

[0161] For example, by adjusting the volume of the adhesive member (450), the overlapping area (OR1, OR, OR3, OR4) of the semiconductor device (440) can be spaced apart along the vertical direction from the insulating member (431, 432, 433, 434). In this case, the adhesive member (450) can be placed between the insulating member (431, 432, 433, 434) and the overlapping area (OR1, OR, OR3, OR4) of the semiconductor device (440). In this case, the embodiment can further increase the contact area between the adhesive member (450) and the semiconductor device (440), thereby allowing the semiconductor device (440) to be more stably seated on the circuit board.

[0162] Referring to FIG. 4b, when an MLCC having four terminals is placed on a circuit board, the terminals of the MLCC have areas that overlap vertically with the insulating members (431, 432, 433, 434) and areas that do not overlap vertically. Specifically, the first and second terminals (442, 443) overlap vertically with the insulating members (431, 432, 433, 434), and the third and fourth terminals (444, 445) do not overlap vertically. Thus, the penetration of a solution for defluxing into the space between the third terminal (444) and the first and second terminals (442, 443) and the space between the fourth terminal (445) and the first and second terminals (442, 443) can be facilitated, and the MLCC can be stably mounted.

[0163] The first protective layer (410) may include a curved portion (419). The curved portion (419) may have a curved shape that connects the inner wall of the through hole (411) and the upper surface of the first protective layer (410) in a rounded manner. In this case, the curved portion (413) positioned in the corner area of ​​the inner wall of the aforementioned through hole (411) may be named the first curved portion, and the curved portion (419) connecting the upper surface of the first protective layer (410) and the inner wall of the through hole (411) may be named the second curved portion.

[0164] For example, as illustrated in FIG. 4d, the second curved portion (419) roundly connects the upper surface of the first protective layer (410) and the inner wall of the through hole (411) and may have a predetermined curvature. In the area where the second curved portion (419) is formed, the vertical thickness of the first protective layer (410) may gradually decrease as it approaches the through hole (411). Because the solution for deflux applied on the first protective layer (410) can be easily guided toward the through hole (411) along the second curved portion (419) by the second curved portion (419), the deflux efficiency may be improved. The second curved portion (419) may be arranged along the perimeter of the through hole (411).

[0165] Referring to FIG. 5, a semiconductor package according to the second embodiment may include a build-up structure (500), a first semiconductor device (540), and a second semiconductor device (560).

[0166] The first semiconductor device (540) and the second semiconductor device (560) may be mounted on the build-up structure (500) using different bonding methods. For example, the first semiconductor device (540) may be mounted on the build-up structure (500) through a first adhesive member (530) using solder paste. In this case, a first pad portion (501) may be provided on the upper surface of the build-up structure (500), and the first adhesive member (530) may be placed on the first pad portion (501). Additionally, a protective layer (510) having a through hole that overlaps along a vertical direction with the first pad portion (501) may be disposed on the build-up structure (500), and an insulating member (520) may be disposed around the through hole of the protective layer (510) and / or around the first pad portion (501). Accordingly, the first semiconductor device (540) can be mounted on the first pad portion (501) while being supported on the insulating member (520) through the first adhesive member (450).

[0167] Additionally, the second semiconductor device (560) can be mounted on the build-up structure (500) through a second adhesive member (550) using TC bonding and / or micro balls. In this case, a second pad portion (502) is further provided on the build-up structure (500), and the second adhesive member (560) can be placed on the second pad portion (502).

[0168] At this time, the second semiconductor device (560) may not overlap or may be misaligned along the vertical direction with the insulating member (520). For example, the insulating member (520) may not be provided around the area where the second semiconductor device (560) is mounted and / or around the second pad portion (502). Accordingly, the embodiment may be able to reduce the size of the second adhesive member (550), thereby making it possible to finer the pitch of the second pad portion (502).

[0169] Additionally, the semiconductor package may further include a molding member (570). The molding member (570) may be provided to surround the first semiconductor device (540) and the second semiconductor device (550).

[0170]

[0171] Referring to FIG. 6, the semiconductor package may include a build-up structure (600), and a first semiconductor device (640), a second semiconductor device (670), and a third semiconductor device (675) may be mounted on the build-up structure (600).

[0172] The first semiconductor device (640) can be mounted on the build-up structure (600) by a bonding method different from that of the second semiconductor device (670) and the third semiconductor device (680). For example, the first semiconductor device (640) can be mounted on the build-up structure (600) through a first adhesive member (630) using solder paste. In this case, a first pad portion (601) may be provided on the upper surface of the build-up structure (600), and the first adhesive member (630) may be placed on the first pad portion (601). Additionally, a protective layer (610) having a through hole that overlaps along a vertical direction with the first pad portion (601) may be disposed on the build-up structure (600), and an insulating member (620) may be disposed around the through hole of the protective layer (610) and / or around the first pad portion (601). Accordingly, the first semiconductor device (640) can be mounted on the first pad portion (601) while being supported on the insulating member (620) through the first adhesive member (650).

[0173] Additionally, the second and third semiconductor devices (670, 675) may be mounted on the build-up structure (600) through a second adhesive member (650) using TC bonding and / or micro balls. In this case, the second and third pad portions (602, 603) may be further provided on the build-up structure (600), and the second adhesive member (560) may be placed on the second and third pad portions (602, 603).

[0174] At this time, the second and third semiconductor devices (670, 675) may not overlap or may be misaligned along the vertical direction with respect to the insulating member (620). For example, the insulating member (620) may not be provided around the area where the second and third semiconductor devices (670, 675) are mounted and / or around the second and third pad portions (602, 603). Accordingly, the embodiment may be able to reduce the size of the second adhesive member (650), thereby making it possible to finer the pitch of the second and third pad portions (602, 603).

[0175] Additionally, the circuit board may further include a connecting member (680) embedded within the build-up structure (600). Recently, as the number of signals that a semiconductor device must process increases, there is a trend toward increasing the size of the semiconductor device to a larger area; however, this increase in the size of the semiconductor device becomes a problem that lowers the yield of the semiconductor device. Therefore, there is a trend toward dividing the size or functional part of the semiconductor device pattern to place chiplets on the circuit board and embedding a connecting member (680) within the circuit board that has the function of electrically connecting them. However, the connecting member (680) is not limited to this and may also connect semiconductor devices with other functions, such as memory.

[0176] The connecting member (680) may be placed within an insulating layer adjacent to the protective layer (610) in the build-up structure (600). In this case, the signal transmission distance between the second and third semiconductor elements (670, 675) and the connecting member (680) can be reduced, which is advantageous for preventing signal loss. That is, the connecting member (680) electrically connects multiple semiconductor elements placed on a circuit board, and thus, being adjacent to multiple semiconductor elements and reducing the signal transmission distance may be advantageous for reducing signal transmission loss.

[0177] Additionally, a third connecting member (690) is disposed on the lower surface of the second and third pad portions (602, 603). The third connecting member (690) may be solder, but is not limited thereto. The connecting member (680) has a pad portion, and the pad portion of the connecting member (680) is electrically connected to the second and third pad portions (602, 603) through the third connecting member (690).

[0178] The connecting member (680) can function to electrically connect the second and third semiconductor devices (670, 675). In this case, the connecting member (680) may be a bridge die. For example, the connecting member (680) partially overlaps the second and third semiconductor devices (670, 675) in a vertical direction. Additionally, the connecting member (680) electrically connects parts of the terminals of the second and third semiconductor devices (670, 675) to each other. The connecting member (680) may be provided with a material such as silicon, which is the same as the semiconductor device, or may be provided with an organic material such as a photosensitive resin or a thermosetting resin. Chiplet units separated according to function and / or pitch, or multiple semiconductor devices having different functions such as a CPU and a GPU, or a GPU and an HBM, may be mounted on a circuit board, and the connecting member (680) can function to electrically connect them horizontally.

[0179] The connecting member (680) may be an organic bridge capable of smoothly supplying power from the lower side to the upper side while minimizing the loss of supplied power. In this case, in the case of an inorganic bridge including a silicon substrate, power supply is possible through a TSV (Through Silicon Via), but there are problems such as increased process costs for TSV processing and reduced product yield. Therefore, it is preferable that the connecting member (680) of the embodiment be an organic bridge.

[0180] According to the embodiment of FIG. 7, the circuit board described above can be used as an interposer (700) provided between the semiconductor package substrate and the semiconductor device of a semiconductor package.

[0181] That is, as the terminal density of the semiconductor device increases, the wiring becomes more complex, and consequently, the thickness of the circuit board increases. However, as the thickness increases, a problem may arise in which the yield of the circuit board decreases. Therefore, the circuit board can be divided into an interposer (700) and a semiconductor package board (720) for use. The circuit board described above can be used not only as a semiconductor package board (720) but also as an interposer (700).

[0182] A semiconductor package substrate (720) is placed on the lower surface of the interposer (700). The semiconductor package substrate (720) can electrically connect the main board of the electronic device and the interposer.

[0183] At this time, a fourth connecting member (710) may be disposed between the interposer and the semiconductor package substrate (720), thereby electrically connecting the interposer and the semiconductor package substrate (720).

[0184] In the foregoing, although all components constituting an embodiment of the present invention have been described as being combined or operating in combination, the present invention is not necessarily limited to such embodiments. That is, within the scope of the purpose of the present invention, all components may be selectively combined in one or more ways. Furthermore, terms such as "include," "constitute," or "have" described above, unless specifically stated otherwise, mean that the relevant component may be inherent; thus, they should be interpreted as allowing for the inclusion of additional components rather than excluding other components. All terms, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains, unless otherwise defined. Terms commonly used, such as those defined in advance, should be interpreted in accordance with their meaning in the context of the relevant technology and should not be interpreted in an ideal or overly formal sense unless explicitly defined in the present invention.

[0185] The foregoing description is merely an illustrative explanation of the technical concept of the present invention, and those skilled in the art to which the present invention pertains will be able to make various modifications and variations within the scope of the essential characteristics of the present invention. Accordingly, the embodiments disclosed in the present invention are intended to explain, not limit, the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by such embodiments. The scope of protection of the present invention shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention.

[0186] Meanwhile, when a circuit board having the features of the invention described above is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the invention performs a semiconductor package function, it can safely protect the semiconductor chip from external moisture or contaminants, and can resolve issues such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. In addition, when it is responsible for signal transmission, it can resolve noise issues. Through this, the circuit board having the features of the invention described above enables the stable operation of IT devices or home appliances, thereby allowing the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability.

[0187] When a circuit board having the features of the invention described above is used in a transportation device such as a vehicle, it can resolve the problem of signal distortion transmitted to the transportation device, or safely protect a semiconductor chip controlling the transportation device from the outside, and further improve the stability of the transportation device by resolving problems such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

Claims

1. A build-up structure including a plurality of insulating layers stacked along a vertical direction; A protective layer disposed on the above-mentioned build-up structure; and It includes a plurality of insulating members spaced apart from each other and disposed on the above protective layer, The above insulating member includes a side, and A circuit board in which at least a portion of the above-mentioned side is a curved surface.

2. In Paragraph 1, The side of the above insulating member includes a corner surface connecting a plurality of mutually perpendicular surfaces, and The above curved surface is a circuit board placed on the above corner surface.

3. In Paragraph 2, The above curved surface is a circuit board having a predetermined curvature to roundly connect the plurality of surfaces.

4. In Paragraph 1, The above plurality of insulating members are circuit boards provided with the same material as the protective layer.

5. In Paragraph 1, The above-mentioned build-up structure includes a pad portion disposed on the upper surface, and The plurality of insulating members are circuit boards spaced apart from each other in the peripheral region of the pad portion on the protective layer.

6. In Paragraph 5, The above protective layer has a through hole that exposes the pad portion from the protective layer, and The above plurality of insulating members are circuit boards spaced apart from each other in the area surrounding the through hole.

7. In Paragraph 6, The inner wall of the above-mentioned through hole is a circuit board including a curved surface having a predetermined curvature.

8. In Paragraph 7, The above-mentioned curved surface is a circuit board positioned between two regions that are mutually perpendicular or inclined at a predetermined angle.

9. In Paragraph 7, The above-mentioned curved portions are provided in plurality, and the circuit board is arranged along the inner wall perimeter of the through hole.

10. A build-up structure including a plurality of insulating layers stacked along a vertical direction; A protective layer disposed on the above-mentioned build-up structure; A plurality of insulating members spaced apart from each other and disposed on the above protective layer; and It includes electronic elements disposed on the plurality of insulating members, and The above insulating member includes a side, and A semiconductor package in which at least a portion of the above-mentioned side is a curved surface.

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