Display device and electronic device

Abstract

This display device comprises: a pixel electrode and a common electrode spaced apart from each other and disposed over a substrate; a first reflective layer and a second reflective layer separated from each other and disposed respectively on the pixel electrode and the common electrode; and a light-emitting element disposed above the first reflective layer and the second reflective layer and electrically connected between the pixel electrode and the common electrode.

Description

Display devices and electronic devices

[0001] Embodiments of the present invention relate to a display device and an electronic device capable of displaying an image.

[0002] As the information society develops, the demand for display devices and electronic devices capable of displaying images is increasing in various forms. Accordingly, various types of display devices and electronic devices containing pixels for displaying images are being developed. Display devices may be provided independently or integrated into electronic devices to be used as the display screen of the electronic device.

[0003] The problem that the present invention aims to solve is to provide a display device and an electronic device capable of improving light efficiency.

[0004] The problems of the present invention are not limited to the technical problems mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below.

[0005] A display device according to one embodiment may include: a pixel electrode and a common electrode spaced apart from each other and disposed on a substrate; a first reflective layer and a second reflective layer separated from each other and disposed on the pixel electrode and the common electrode, respectively; and a light-emitting element disposed on the first reflective layer and the second reflective layer and electrically connected between the pixel electrode and the common electrode.

[0006] In one embodiment, the first reflective layer is disposed on a portion of the pixel electrode including an end portion that overlaps with the light-emitting element, and may expose another portion of the pixel electrode.

[0007] In one embodiment, the second reflective layer is disposed on a portion of the common electrode including an end adjacent to the pixel electrode that overlaps with the light-emitting element, and may expose another portion of the common electrode.

[0008] In one embodiment, the first reflective layer may cover the side of the pixel electrode on a part of the pixel electrode, and the second reflective layer may cover the side of the common electrode on a part of the common electrode.

[0009] In one embodiment, the first reflective layer may have a width greater than the width of the pixel electrode in a first direction in which one end of the pixel electrode facing the common electrode is extended, covering the one end of the pixel electrode, and may have a length shorter than the length of the pixel electrode in a second direction different from the first direction, exposing the other end of the pixel electrode.

[0010] In one embodiment, the first reflective layer and the second reflective layer may be symmetrical with respect to the light-emitting element.

[0011] In one embodiment, the first reflective layer covers the end of the pixel electrode including the side of the pixel electrode, and the second reflective layer can cover the end of the common electrode including the side of the common electrode.

[0012] In one embodiment, the first reflective layer may cover the pixel electrode entirely, and the second reflective layer may cover the common electrode entirely.

[0013] In one embodiment, the first reflective layer may be opened in a portion that does not overlap with the light-emitting element to expose a portion of the upper surface of the pixel electrode, and the second reflective layer may be opened in a portion that does not overlap with the light-emitting element to expose a portion of the upper surface of the common electrode.

[0014] In one embodiment, the display device may further include: an adhesive layer disposed below the light-emitting element, covering a portion of the first reflective layer and the second reflective layer including a portion overlapping with the light-emitting element; a first connecting electrode disposed on the adhesive layer and connecting the pixel electrode or the first reflective layer and the light-emitting element; and a second connecting electrode disposed on the adhesive layer and connecting the common electrode or the second reflective layer and the light-emitting element.

[0015] In one embodiment, the first connecting electrode may contact the light-emitting element on the part of the first reflective layer and the adhesive layer, and may contact the first reflective layer on another part of the first reflective layer. The second connecting electrode may contact the light-emitting element on the part of the second reflective layer and the adhesive layer, and may contact the second reflective layer on another part of the second reflective layer.

[0016] In one embodiment, the first reflective layer and the second reflective layer are each opened to expose a portion of the upper surface of the pixel electrode and the common electrode, and the first connecting electrode contacts the pixel electrode in the portion where the first reflective layer is opened, and the second connecting electrode contacts the common electrode in the portion where the second reflective layer is opened.

[0017] In one embodiment, the light-emitting element may include: a semiconductor stack disposed on the adhesive layer; a first contact electrode disposed on at least one side of the semiconductor stack and in contact with the first connecting electrode on the first reflective layer; and a second contact electrode disposed on at least one side of the semiconductor stack and in contact with the second connecting electrode on the second reflective layer.

[0018] In one embodiment, the display device may further include a power bus line including a wiring layer extending from the common electrode and electrically connected to the common electrode.

[0019] In one embodiment, the second reflective layer may extend into an area where the power bus line is placed and cover the wiring layer.

[0020] An electronic device according to one embodiment may include a display module including a display panel; a memory for storing an image data signal or an input control signal; and a processor for transmitting the image data signal or the input control signal stored in the memory to the display module. The display panel may include a pixel electrode and a common electrode spaced apart from each other and disposed on a substrate; a first reflective layer and a second reflective layer separated from each other and disposed on the pixel electrode and the common electrode, respectively; and a light-emitting element disposed on the first reflective layer and the second reflective layer and electrically connected between the pixel electrode and the common electrode.

[0021] In one embodiment, the first reflective layer is disposed on a portion of the pixel electrode including an end that overlaps with the light-emitting element and exposes another portion of the pixel electrode, and the second reflective layer is disposed on a portion of the common electrode including an end that overlaps with the light-emitting element and is adjacent to the pixel electrode and exposes another portion of the common electrode.

[0022] In one embodiment, the first reflective layer covers the end of the pixel electrode including the side of the pixel electrode, and the second reflective layer can cover the end of the common electrode including the side of the common electrode.

[0023] In one embodiment, the first reflective layer may cover the pixel electrode entirely, and the second reflective layer may cover the common electrode entirely.

[0024] In one embodiment, the first reflective layer may be opened in a portion that does not overlap with the light-emitting element to expose a portion of the upper surface of the pixel electrode, and the second reflective layer may be opened in a portion that does not overlap with the light-emitting element to expose a portion of the upper surface of the common electrode.

[0025] Specific details of other embodiments are included in the detailed description and drawings.

[0026] The display device and electronic device according to the embodiments may include a light-emitting element and a reflective layer disposed below the light-emitting element. Accordingly, the light efficiency of the display device and electronic device can be improved.

[0027] In some embodiments, the reflective layer can cover the end of the pixel electrode layer to protect the pixel electrode layer. Accordingly, the reliability of the display device and the electronic device can be ensured.

[0028] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification.

[0029] FIG. 1 is a perspective view showing a display device according to one embodiment.

[0030] FIG. 2 is a plan view showing a display panel according to one embodiment.

[0031] FIG. 3 is a block diagram showing a display device according to one embodiment.

[0032] FIG. 4 is an equivalent circuit diagram showing a subpixel according to one embodiment.

[0033] FIG. 5 is a waveform diagram showing driving signals of a subpixel according to one embodiment.

[0034] FIG. 6 is a plan view showing a display panel according to one embodiment.

[0035] FIG. 7 is a plan view showing a display panel according to one embodiment.

[0036] FIG. 8 is a plan view showing a display panel according to one embodiment.

[0037] FIG. 9 is a cross-sectional view showing a display panel according to one embodiment.

[0038] FIG. 10 is a cross-sectional view showing the A1 region of FIG. 9 in detail.

[0039] FIG. 11 is a plan view showing a display panel according to one embodiment.

[0040] FIG. 12 is a cross-sectional view showing a display panel according to one embodiment.

[0041] FIG. 13 is a plan view showing a display panel according to one embodiment.

[0042] FIG. 14 is a cross-sectional view showing a display panel according to one embodiment.

[0043] FIG. 15 is a cross-sectional view showing a power bus line according to one embodiment.

[0044] FIG. 16 is a cross-sectional view showing a power bus line according to one embodiment.

[0045] FIG. 17 is a block diagram of an electronic device according to one embodiment.

[0046] FIG. 18 is a schematic diagram of an electronic device according to various embodiments.

[0047] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0048] When elements or layers are referred to as being "on" another element or layer, this includes cases where another layer or element is interposed directly on or in the middle of another element. Throughout the specification, the same reference numerals refer to the same components. Shapes, sizes, ratios, angles, numbers, etc., disclosed in the drawings for describing embodiments are exemplary and therefore the invention is not limited to the depicted details.

[0049] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0050] Specific embodiments will be described below with reference to the attached drawings.

[0051] FIG. 1 is a perspective view showing a display device according to one embodiment.

[0052] Referring to FIG. 1, the display device (1) may be a device capable of providing images such as video or still images. For example, the display device (1) may be a device capable of displaying images by including a display module including a display panel (100). As an example, the display device (1) may refer to any electronic device that provides a display screen capable of displaying images or includes a display module for displaying images. The display device (1) may be included in an electronic device that provides a display screen and may form the display screen of said electronic device.

[0053] For example, the display device (1) can be used as a display screen in various electronic devices such as mobile phones, smartphones, tablet personal computers, smart watches, watch phones, mobile communication terminals, electronic notebooks, e-books, PMPs (portable multimedia players), navigation systems, UMPCs (Ultra Mobile PCs), as well as in televisions, laptops, monitors, billboards, and the Internet of Things (IOT). Additionally, the display device (1) can be used to display images in other electronic devices such as virtual reality (VR) devices or augmented reality (AR) devices.

[0054] FIG. 1 illustrates a display module, which is a major component of a display device (1). In one embodiment, the display device (1) (or an electronic device including a display module) may include additional components. For example, the display device (1) may further include a housing or case, etc., for housing the display module of FIG. 1.

[0055] In one embodiment, the display device (1) may be a light-emitting display device such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a micro light-emitting display device using a micro or nano light-emitting diode (micro LED or nano LED). Hereinafter, as an example of a display device (1) to which the embodiments can be applied, a micro light-emitting display device including a micro light-emitting diode is disclosed. However, the embodiments are not limited thereto. For example, the type of light-emitting element included in the display device (1) is not limited to a micro light-emitting diode, and the display device (1) may include other types and / or forms of light-emitting elements. Furthermore, the display device (1) according to the embodiments is not limited to a light-emitting display device, and the type and / or form of the display device (1) may be varied according to the embodiments.

[0056] The display device (1) may include a display panel (100), a display driving circuit (250), a circuit board (300), and a power supply (500). The display panel (100), the display driving circuit (250), the circuit board (300), and the power supply (500) may be included in a display module of the display device (1).

[0057] In one embodiment, the display panel (100) may have a roughly rectangular planar shape. For example, the display panel (100) may have a roughly rectangular shape on a plane defined by a first direction (DR1) and a second direction (DR2) that intersect each other. The corners of the display panel (100) may be rounded or formed at right angles. The planar shape of the display panel (100) is not limited to a rectangular shape and may be formed in other polygonal shapes, circular shapes, or elliptical shapes. The display panel (100) may be substantially flat, but is not limited thereto. For example, the display panel (100) may include a curved surface at least in a portion (e.g., left and right ends). In one embodiment, the display panel (100) may be formed flexibly so that it can be bent, curved, folded, or rolled.

[0058] The display panel (100) may include a main area (MA) where an image is displayed. In one embodiment, the display panel (100) may further include a sub-area (SBA).

[0059] The main area (MA) may include a display area (DA) for displaying an image and a non-display area (NDA) which is a surrounding area of ​​the display area (DA). The display area (DA) may include pixels to display an image. Each pixel may include a plurality of subpixels. For example, each pixel may include a first subpixel emitting light of a first color, a second subpixel emitting light of a second color, and a third subpixel emitting light of a third color, but the embodiments are not limited thereto.

[0060] A sub-region (SBA) may protrude from one side of a main region (MA) in a second direction (DR2) (e.g., vertical direction). Although FIG. 1 illustrates a state in which the sub-region (SBA) is unfolded, the sub-region (SBA) may be bent. When the sub-region (SBA) is bent, it may be placed on the lower surface of the display panel (100) while overlapping with the main region (MA) in a third direction (DR3), which is the thickness direction of the display panel (100). A display driving circuit (250) may be placed in the sub-region (SBA).

[0061] The display driving circuit (250) can generate signals and voltages (for example, driving signals and driving voltages of the display panel (100)) for driving the display panel (100). The display driving circuit (250) may be formed as an integrated circuit (IC) and attached to the display panel (100) using a COG (chip on glass) method, a COP (chip on plastic) method, or an ultrasonic bonding method, but is not limited thereto. For example, the display driving circuit (250) may be attached to the circuit board (300) using a COF (chip on film) method.

[0062] A circuit board (300) is attached to one end of a sub-region (SBA) of a display panel (100) and can be electrically connected to the display panel (100) and the display driving circuit (250). The display panel (100) and the display driving circuit (250) can receive digital video data, timing signals, and driving voltages through the circuit board (300). The circuit board (300) may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip-on-film.

[0063] The power supply unit (500) can generate panel driving voltages according to the power voltage supplied from the outside. The power supply unit (500) can be formed as an integrated circuit (IC) and attached to the circuit board (300) in a COF manner.

[0064] FIG. 2 is a plan view showing a display panel according to one embodiment. FIG. 2 shows a state in which a sub-region (SBA) is unfolded.

[0065] Referring to FIGS. 1 and FIGS. 2, the display panel (100) may include a main area (MA) and a sub-area (SBA).

[0066] The main area (MA) may include a display area (DA) and a non-display area (NDA). The display area (DA) may occupy most of the main area (MA).

[0067] A display area (DA) may include pixels (PX) for displaying an image. Each pixel (PX) may include a plurality of subpixels (SPX). A pixel (PX) may be defined as a group of subpixels of the smallest unit capable of expressing a white gradation. For example, a pixel (PX) may include three subpixels (SPX) that emit light of different colors. However, the number, type, and / or ratio of subpixels (SPX) included in each pixel (PX) may vary depending on the embodiments.

[0068] A non-display area (NDA) may be placed adjacent to a display area (DA). For example, the non-display area (NDA) may surround the display area (DA). The non-display area (NDA) may be an edge area of ​​the display panel (100).

[0069] In one embodiment, a first scan driver (SDC1) and a second scan driver (SDC2) may be disposed in a non-display area (NDA). The first scan driver (SDC1) and the second scan driver (SDC2) may be disposed on different sides of a display area (DA). Each of the first scan driver (SDC1) and the second scan driver (SDC2) may be electrically connected to a display driver circuit (250) through a plurality of wires. Each of the first scan driver (SDC1) and the second scan driver (SDC2) may receive a scan control signal from the display driver circuit (250), generate scan signals according to the scan control signal, and output them to scan lines.

[0070] In FIG. 2, an embodiment is disclosed in which a display device (1) (for example, a display panel (100)) includes a first scan drive unit (SDC1) and a second scan drive unit (SDC2), but the embodiments are not limited thereto. For example, the number or location of the scan drive units included in the display device (1) may vary depending on the embodiments.

[0071] A sub-region (SBA) may protrude from one side of a main region (MA) in a second direction (DR2) (e.g., vertical direction). The length of the second direction (DR2) of the sub-region (SBA) may be shorter than the length of the second direction (DR2) of the main region (MA). The length of the first direction (DR1) of the sub-region (SBA) may be less than or equal to the length of the first direction (DR1) of the main region (MA). The sub-region (SBA) may be bent, so that at least a portion of the sub-region (SBA) may overlap with the main region (MA) in a third direction (DR3). For example, a portion of the sub-region (SBA) may be positioned below the main region (MA).

[0072] The sub-region (SBA) may include a connection region (CA), a pad region (PA), and a bending region (BA).

[0073] The connection area (CA) may be an area protruding in a second direction (DR2) from one side of the main area (MA). One side of the connection area (CA) is in contact with the non-display area (NDA) of the main area (MA), and the other side of the connection area (CA) may be in contact with the bending area (BA).

[0074] The pad area (PA) may be an area where pads (PDs) and a display driving circuit (250) are placed. The display driving circuit (250) may be attached to the driving pads of the pad area (PA) using a conductive adhesive member such as an anisotropic conductive film. The circuit board (300) may be attached to the pads (PDs) of the pad area (PA) using a conductive adhesive member such as an anisotropic conductive film. One side of the pad area (PA) may be in contact with a bending area (BA).

[0075] The bending area (BA) may be a bending area. When the display panel (100) is bent in the bending area (BA), the pad area (PA) may be positioned below the connection area (CA) and below the main area (MA). The bending area (BA) may be positioned between the connection area (CA) and the pad area (PA). One side of the bending area (BA) may be in contact with the connection area (CA), and the other side of the bending area (BA) may be in contact with the pad area (PA).

[0076] FIG. 3 is a block diagram showing a display device according to one embodiment.

[0077] Referring to FIG. 3, the display area (DA) may include pixels (PX), scan lines (SL), light emission control lines (EL), and data lines (DL).

[0078] Pixels (PX) can be arranged in a first direction (DR1) and a second direction (DR2). For example, pixels (PX) can be arranged in a matrix form in the first direction (DR1) and the second direction (DR2). Scan lines (SL) and light emission control lines (EL) can be extended in the first direction (DR1) and arranged in the second direction (DR2). Data lines (DL) can be extended in the second direction (DR2) and arranged in the first direction (DR1). Scan lines (SL) may include write scan lines (GWL), initialization scan lines (GIL), control scan lines (GCL), and bias scan lines (GBL). The configuration of scan lines (SL) may vary depending on the structure or driving method of the pixels (PX).

[0079] Each of the pixels (PX) may include a plurality of subpixels (SPX). For example, each of the pixels (PX) may include a first subpixel (SPX1), a second subpixel (SPX2), and a third subpixel (SPX3). The first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) may each emit light of a first color, light of a second color, and light of a third color. The light of the first color, the light of the second color, and the light of the third color may each be red light (for example, light in the red wavelength band with a main peak wavelength of approximately 600 nm to 750 nm), green light (for example, light in the green wavelength band with a main peak wavelength of approximately 480 nm to 560 nm), and blue light (for example, light in the blue wavelength band with a main peak wavelength of approximately 370 nm to 460 nm), but are not limited thereto. In one embodiment, the first subpixel (SPX1), second subpixel (SPX2), and third subpixel (SPX3) of each of the pixels (PX) may be arranged in a first direction (DR1). The number, type, arrangement structure, and / or emission wavelength of the subpixels (SPX) included in each of the pixels (PX) may be varied according to the embodiments.

[0080] Each of the plurality of subpixels (SPX) may be connected to any one of the write scan lines (GWL), any one of the initialization scan lines (GIL), any one of the control scan lines (GCL), any one of the bias scan lines (GBL), any one of the light emission control lines (EL), and any one of the data lines (DL). In describing the embodiments, the term “connection” may include the meaning of “physical connection” and / or “electrical connection”.

[0081] Each of the plurality of subpixels (SPX) can receive a data voltage of a data line (DL) according to a write scan signal of a write scan line (GWL). Each of the plurality of subpixels (SPX) may include a light-emitting element that emits light with a brightness corresponding to the data voltage. The plurality of subpixels (SPX) included in each pixel (PX) may be connected to different data lines (DL). For example, a first subpixel (SPX1), a second subpixel (SPX2), and a third subpixel (SPX3) may be connected to a first data line (DLr), a second data line (DLg), and a third data line (DLb), respectively. Accordingly, the light-emitting brightness of each of the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) can be controlled individually.

[0082] In one embodiment, each pixel (PX) is connected to two or more light emission control lines (EL), and the light emission period (or on-duty ratio) of at least two subpixels (SPX) among a plurality of subpixels (SPX) included in each pixel (PX) can be controlled independently and / or individually by different light emission control signals supplied to different light emission control lines (EL). For example, in each horizontal line (e.g., each pixel row) of a display area (DA), a first light emission control line (EL1) and a second light emission control line (EL2) connected to different subpixels (SPX) among the subpixels (SPX) included in the pixels (PX) placed on the corresponding horizontal line may be disposed. For example, a first light-emitting control line (EL1) may be connected to first subpixels (SPX1) of pixels (PX) arranged on the horizontal line, and a second light-emitting control line (EL2) may be connected to second subpixels (SPX2) and third subpixels (SPX3) included in pixels (PX) of the horizontal line.

[0083] The first subpixel (SPX1) can emit light during a first light emission period in response to a first light emission control signal supplied through the first light emission control line (EL1). The first light emission period may be a period during which a driving current can flow through the first subpixel (SPX1) by the first light emission control signal. The second subpixel (SPX2) and the third subpixel (SPX3) can emit light during a second light emission period in response to a second light emission control signal supplied through the second light emission control line (EL2). The second light emission period may be a period during which a driving current can flow through the second subpixel (SPX2) and the third subpixel (SPX3) by the second light emission control signal. The first light emission period and the second light emission period may be controlled independently or individually.

[0084] In one embodiment, the duration of the first light emission period and the duration of the second light emission period may be different. For example, the duration of the first light emission period may correspond to an on-duty ratio adjusted so that the first subpixel (SPX1) emits light at a target brightness, in accordance with a driving current optimized for the light emission efficiency of the first subpixel (SPX1) (for example, a driving current that falls within the range in which the light-emitting element of the first subpixel (SPX1) exhibits optimal consumption efficiency). The duration of the second light emission period may correspond to an on-duty ratio adjusted so that the second subpixel (SPX2) and the third subpixel (SPX3) emit light at a target brightness, in accordance with a driving current optimized for the light emission efficiency of the second subpixel (SPX2) and the third subpixel (SPX3) (for example, a driving current that falls within the range in which the light-emitting elements of the second subpixel (SPX2) and the third subpixel (SPX3) exhibit optimal consumption efficiency). In this case, the light emission control signal output unit (615) included in the first scan drive unit (SDC1) and the second scan drive unit (SDC2) can output light emission control signals having different pulse widths to the first light emission control line (EL1) and the second light emission control line (EL2).

[0085] However, the embodiments are not limited thereto. For example, in other embodiments, a first sub-pixel (SPX1), a second sub-pixel (SPX2), and a third sub-pixel (SPX3) included in a single pixel (PX) may be commonly connected to a single light emission control line (EL). For example, a single light emission control line (EL) may be arranged on a single horizontal line, and the sub-pixels (SPX) arranged on the single horizontal line may be commonly connected to the single light emission control line (EL). In this case, the light emission periods of the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3) may be controlled by a light emission control signal supplied to the single light emission control line (EL).

[0086] A first scan drive unit (SDC1), a second scan drive unit (SDC2), and a display drive circuit (250) may be disposed in the non-display area (NDA).

[0087] Each of the first scan driver (SDC1) and the second scan driver (SDC2) can be electrically connected to pixels (PX) through scan lines (SL) and light emission control lines (EL). For example, each of the first scan driver (SDC1) and the second scan driver (SDC2) can be electrically connected to subpixels (SPX) of each pixel (PX) through write scan lines (GWL), initialization scan lines (GIL), control scan lines (GCL), bias scan lines (GBL), and light emission control lines (EL).

[0088] Each of the first scan driving unit (SDC1) and the second scan driving unit (SDC2) may include a write scan signal output unit (611), an initialization scan signal output unit (612), a control scan signal output unit (613), a bias scan signal output unit (614), and a light emission control signal output unit (615). Each of the write scan signal output unit (611), the initialization scan signal output unit (612), the control scan signal output unit (613), the bias scan signal output unit (614), and the light emission control signal output unit (615) may receive a scan timing control signal (SCS) from the timing control unit (251).

[0089] The write scan signal output unit (611) can generate write scan signals according to the scan timing control signal (SCS) and output them sequentially to the write scan lines (GWL).

[0090] The initialization scan signal output unit (612) can generate initialization scan signals according to the scan timing control signal (SCS) and output them sequentially to the initialization scan lines (GIL).

[0091] The control scan signal output unit (613) can generate control scan signals according to the scan timing control signal (SCS) and output them sequentially to the control scan lines (GCL).

[0092] The bias scan signal output unit (614) can generate bias scan signals according to the scan timing control signal (SCS) and output them sequentially to the bias scan lines (GBL).

[0093] The light emission control signal output unit (615) can generate light emission control signals according to the scan timing control signal (SCS) and output them sequentially to the light emission control lines (EL). In one embodiment, when the subpixels (SPX) of each horizontal line are divided and connected to a plurality of light emission control lines (EL) (for example, a first light emission control line (EL1) and a second light emission control line (EL2) of each horizontal line), the light emission control signal output unit (615) can output each light emission control signal to the plurality of light emission control lines (EL) for each horizontal period.

[0094] The display driving circuit (250) may include a timing control unit (251) and a data driving unit (252).

[0095] The data driver (252) can be electrically connected to pixels (PX) through data lines (DL). For example, the data driver (252) can be electrically connected to subpixels (SPX) of each pixel (PX) through a first data line (DLr), a second data line (DLg), and a third data line (DLb).

[0096] The data driver (252) can receive digital video data (DATA) and a data timing control signal (DCS) from the timing control unit (251). The data driver (252) converts the digital video data (DATA) into analog data voltages according to the data timing control signal (DCS) and outputs them to the data lines (DL). Subpixels (SPX) are selected by the write scan signals of the first scan driver (SDC1) and the second scan driver (SDC2), and data voltages can be supplied to the selected subpixels (SPX).

[0097] The timing control unit (251) can receive digital video data (DATA) and timing signals from the outside. The timing control unit (251) can generate a scan timing control signal (SCS) and a data timing control signal (DCS) to control the display panel (100) according to the timing signals. The timing control unit (251) can output the scan timing control signal (SCS) to the first scan driving unit (SDC1) and the second scan driving unit (SDC2). The timing control unit (251) can output the digital video data (DATA) and the data timing control signal (DCS) to the data driving unit (252).

[0098] The power supply unit (500) can generate panel driving voltages according to the power voltage supplied from the outside. For example, the power supply unit (500) can generate a first driving voltage (VDD), a second driving voltage (VSS), a third driving voltage (VINT), a fourth driving voltage (VAINT), and a fifth driving voltage (VOBS) and supply them to the display panel (100). The first driving voltage (VDD), the second driving voltage (VSS), the third driving voltage (VINT), the fourth driving voltage (VAINT), and the fifth driving voltage (VOBS) can be supplied to the subpixels (SPX) through respective power lines connected between the power supply unit (500) and the subpixels (SPX), and can be used to drive the subpixels (SPX). Depending on the structure or operation method of the subpixels (SPX), the number and / or type of panel driving voltages output from the power supply unit (500) may be changed.

[0099] FIG. 4 is an equivalent circuit diagram showing a subpixel according to one embodiment. For example, FIG. 4 may be an equivalent circuit diagram showing one of the subpixels (SPX) of FIG. 2 and FIG. 3. For example, the subpixel (SPX) of FIG. 4 may be the first subpixel (SPX1), the second subpixel (SPX2), or the third subpixel (SPX3) of FIG. 3. In one embodiment, the circuit configuration of the plurality of subpixels (SPX) forming each pixel (PX) may be substantially identical to one another.

[0100] FIG. 5 is a waveform diagram showing driving signals of a subpixel according to one embodiment. For example, FIG. 5 shows a write scan signal (GW), a control scan signal (GC), an initialization scan signal (GI), a bias scan signal (GB), and a light emission control signal (EM) supplied to the scan lines (SL) and light emission control line (EL) of FIG. 4.

[0101] Referring to FIGS. 4 and FIGS. 5 in addition to FIGS. 1 to 3, each of the subpixels (SPX) may include a pixel circuit (PXC) and a light-emitting element (LE) electrically connected to the pixel circuit (PXC).

[0102] A subpixel (SPX) can be connected to at least one scan driver through scan lines (SL) and a light emission control line (EL). For example, the subpixel (SPX) can be connected to a first scan driver (SDC1) and a second scan driver (SDC2) through a write scan line (GWL), an initial scan line (GIL), a control scan line (GCL), a bias scan line (GBL), and a light emission control line (EL). The first scan driver (SDC1) and the second scan driver (SDC2) can output a write scan signal (GW), an initial scan signal (GI), a control scan signal (GC), a bias scan signal (GB), and a light emission control signal (EM), respectively, through the write scan line (GWL), the initial scan line (GIL), the control scan line (GCL), the bias scan line (GBL), and the light emission control line (EL).

[0103] When the subpixel (SPX) is the first subpixel (SPX1), the subpixel (SPX) is connected to the first light emission control line (EL1) placed on the corresponding horizontal line and can receive a light emission control signal (EM) (also referred to as the "first light emission control signal") from the first light emission control line (EL1). When the subpixel (SPX) is the second subpixel (SPX2) or the third subpixel (SPX3), the subpixel (SPX) is connected to the second light emission control line (EL2) placed on the corresponding horizontal line and can receive a light emission control signal (EM) (also referred to as the "second light emission control signal") from the second light emission control line (EL2).

[0104] The subpixel (SPX) can be connected to the data driver (252) via the data line (DL). The data driver (252) can output a data voltage (Vdata) corresponding to the image data of each frame via the data line (DL).

[0105] If the subpixel (SPX) is the first subpixel (SPX1), the subpixel (SPX) may be connected to the first data line (DLr) placed in the corresponding pixel column. If the subpixel (SPX) is the second subpixel (SPX2), the subpixel (SPX) may be connected to the second data line (DLg) placed in the corresponding pixel column. If the subpixel (SPX) is the third subpixel (SPX3), the subpixel (SPX) may be connected to the third data line (DLb) placed in the corresponding pixel column.

[0106] A subpixel (SPX) can be connected to a power supply unit (500) via power lines (PL). For example, the subpixel (SPX) can be connected to a power supply unit (500) via a first power line (VDL), a second power line (VSL), a third power line (VIL), a fourth power line (VAIL), and a fifth power line (VOBL). The power supply unit (500) can supply a first driving voltage (VDD), a second driving voltage (VSS), a third driving voltage (VINT), a fourth driving voltage (VAINT), and a fifth driving voltage (VOBS), respectively, to the first power line (VDL), the second power line (VSL), the third power line (VIL), the fourth power line (VAIL), and the fifth power line (VOBL). In one embodiment, the first driving voltage (VDD), the second driving voltage (VSS), the third driving voltage (VINT), the fourth driving voltage (VAINT), and the fifth driving voltage (VOBS) may each be a high-potential pixel voltage (e.g., anode voltage), a low-potential pixel voltage (e.g., cathode voltage or common voltage), a first initialization voltage (e.g., gate initialization voltage), a second initialization voltage (e.g., anode initialization voltage), and a bias voltage.

[0107] The pixel circuit (PXC) can control the driving current (Ids) supplied to the light-emitting element (LE) in response to driving signals supplied to the subpixel (SPX) (e.g., write scan signal (GW), initialization scan signal (GI), control scan signal (GC), bias scan signal (GB), light emission control signal (EM), and data voltage (Vdata)). The pixel circuit (PXC) can control the light emission timing and brightness of the light-emitting element (LE).

[0108] The pixel circuit (PXC) may include pixel transistors (PXT) and a storage capacitor (Cst). In one embodiment, the pixel circuit (PXC) may further include a boosting capacitor (Cbst).

[0109] In one embodiment, the pixel transistors (PXT) may include first to eighth transistors (T1 to T8). The first transistor (T1) may be a driving transistor of a subpixel (SPX). The second to eighth transistors (T2 to T8) may be switching transistors of a subpixel (SPX).

[0110] In one embodiment, the subpixel (SPX) may include heterogeneous pixel transistors (PXT). For example, the first, second, fifth, sixth, seventh, and eighth transistors (T1, T2, T5, T6, T7, T8) may be P-type transistors (e.g., P-type polycrystalline silicon transistors including each active layer formed of polycrystalline silicon), and the third and fourth transistors (T3, T4) may be N-type transistors (e.g., N-type oxide transistors including each active layer formed of an oxide semiconductor). In one embodiment, the active layers of the P-type transistors (e.g., active layers formed of polycrystalline silicon) and the active layers of the N-type transistors (e.g., active layers formed of an oxide semiconductor) may be disposed on different layers within the display panel (100) (e.g., the backplane layer of the display panel (100)).

[0111] The first transistor (T1) can be connected between the fifth transistor (T5) and the sixth transistor (T6). The first transistor (T1) can be connected to the first power line (VDL) via the fifth transistor (T5) and to the light-emitting element (LE) via the sixth transistor (T6). The gate electrode of the first transistor (T1) can be connected to the first node (N1). The first transistor (T1) can control the driving current (Ids) flowing to the subpixel (SPX) according to the voltage of the first node (N1) applied to the gate electrode (for example, a voltage corresponding to the data voltage (Vdata)).

[0112] The second transistor (T2) may be connected between the data line (DL) and the first electrode of the first transistor (T1) (for example, the source electrode of the first transistor (T1) connected to the fifth transistor (T5)). The gate electrode of the second transistor (T2) may be connected to the write scan line (GWL). The second transistor (T2) may be turned on by a write scan signal (GW) of a gate-on voltage supplied from the write scan line (GWL) (for example, a low-level voltage at which the second transistor (T2) can be turned on). When the second transistor (T2) is turned on, a data voltage (Vdata) supplied from the data line (DL) may be delivered to the first electrode (for example, the source electrode) of the first transistor (T1).

[0113] The third transistor (T3) can be connected between the second electrode of the first transistor (T1) (for example, the drain electrode of the first transistor (T1) connected to the sixth transistor (T6)) and the first node (N1). The gate electrode of the third transistor (T3) can be connected to a control scan line (GCL). The third transistor (T3) can be turned on by a control scan signal (GC) of a gate-on voltage supplied from the control scan line (GCL) (for example, a high-level voltage at which the third transistor (T3) can be turned on) to connect the gate electrode of the first transistor (T1) and the second electrode. When the third transistor (T3) is turned on, the first transistor (T1) can be driven as a diode, and a voltage corresponding to a data voltage (Vdata) can be applied to the first node (N1).

[0114] The fourth transistor (T4) can be connected between the first node (N1) and the third power line (VIL). The gate electrode of the fourth transistor (T4) can be connected to the initialization scan line (GIL). The fourth transistor (T4) can be turned on by an initialization scan signal (GI) of a gate-on voltage supplied from the initialization scan line (GIL) (for example, a high-level voltage at which the fourth transistor (T4) can be turned on) to connect the first node (N1) to the third power line (VIL). When the fourth transistor (T4) is turned on, the voltage of the first node (N1) can be initialized to the third driving voltage (VINT) of the third power line (VIL).

[0115] The fifth transistor (T5) can be connected between the first power line (VDL) and the first electrode of the first transistor (T1). The gate electrode of the fifth transistor (T5) can be connected to a light emission control line (EL) (for example, the first light emission control line (EL1) or the second light emission control line (EL2) of FIG. 3). The fifth transistor (T5) can be turned on by a light emission control signal (EM) of a gate-on voltage supplied from the light emission control line (EL) (for example, a low-level voltage at which the fifth transistor (T5) can be turned on) to connect the first electrode of the first transistor (T1) to the first power line (VDL). When the fifth transistor (T5) is turned on, the first power line (VDL) can be connected to the first electrode of the first transistor (T1).

[0116] The sixth transistor (T6) can be connected between the second electrode of the first transistor (T1) and the light-emitting element (LE). The gate electrode of the sixth transistor (T6) can be connected to the light-emitting control line (EL). The sixth transistor (T6) can be turned on by a light-emitting control signal (EM) of a gate-on voltage supplied from the light-emitting control line (EL) (for example, a low-level voltage at which the sixth transistor (T6) can be turned on) to connect the second electrode of the first transistor (T1) to the light-emitting element (LE).

[0117] The seventh transistor (T7) can be connected between the first electrode of the light-emitting element (LE) (for example, the anode electrode connected to the sixth transistor (T6)) and the fourth power line (VAIL). The gate electrode of the seventh transistor (T7) can be connected to the bias scan line (GBL). The seventh transistor (T7) can be turned on by a bias scan signal (GB) of a gate-on voltage supplied from the bias scan line (GBL) (for example, a low-level voltage at which the seventh transistor (T7) can be turned on) to connect the first electrode of the light-emitting element (LE) to the fourth power line (VAIL). When the seventh transistor (T7) is turned on, the voltage of the first electrode of the light-emitting element (LE) can be initialized to the fourth driving voltage (VAINT) of the fourth power line (VAIL).

[0118] The eighth transistor (T8) can be connected between the fifth power line (VOBL) and the first electrode of the first transistor (T1). The gate electrode of the eighth transistor (T8) can be connected to the bias scan line (GBL). The eighth transistor (T8) can be turned on by a bias scan signal (GB) of a gate-on voltage supplied from the bias scan line (GBL) to connect the first electrode of the first transistor (T1) to the fifth power line (VOBL). When the eighth transistor (T8) is turned on, the voltage of the first electrode of the first transistor (T1) can be initialized to the fifth driving voltage (VOBS) of the fifth power line (VOBL). In one embodiment, the fifth driving voltage (VOBS) may be a bias voltage having a voltage level suitable for compensating for the hysteresis characteristics of the first transistor (T1).

[0119] A storage capacitor (Cst) can be connected between a first node (N1) and a first power line (VDL). The storage capacitor (Cst) can be charged to a voltage corresponding to a data voltage (Vdata) applied to the first node (N1).

[0120] A boosting capacitor (Cbst) can be connected between the first node (N1) and the write scan line (GWL). By stabilizing the voltage of the first node (N1) through the coupling action of the boosting capacitor (Cbst), the operation of the first transistor (T1) can be stabilized. The boosting capacitor (Cbst) may be formed by a parasitic capacitance formed between the first node (N1) and the write scan line (GWL), or it may be designed separately.

[0121] A subpixel (SPX) can emit light for a portion of the frame period corresponding to the on-duty ratio and can be non-emitting for the remainder of the frame period. The emission and non-emitting periods of the subpixel (SPX) can be controlled by an emission control signal (EM).

[0122] The period during which the fifth transistor (T5) and the sixth transistor (T6) are turned off (for example, the period during which a high-level light emission control signal (EM) is supplied to the subpixel (SPX)) may be a non-luminous period of the subpixel (SPX). The non-luminous period of the subpixel (SPX) may include an initialization period for initializing the voltage of a specific node of the subpixel (SPX) (for example, the first node (N1), etc.), and a data writing and storage period for charging a storage capacitor (Cst) with a voltage corresponding to the data voltage (Vdata). In one embodiment, an initialization scan signal (GI), a control scan signal (GC), a write scan signal (GW), and a bias scan signal (GB) of the gate-on voltage may be supplied during the non-luminous period of the subpixel (SPX). In one embodiment, the initialization scan signal (GI), the control scan signal (GC), and the bias scan signal (GB) of the gate-on voltage may be supplied sequentially during the non-luminous period of the subpixel (SPX). The periods during which the initialization scan signal (GI) and the control scan signal (GC) of the gate-on voltage are supplied may overlap, but are not limited thereto. During the period during which the control scan signal (GC) of the gate-on voltage is supplied, the write scan signal (GW) of the gate-on voltage may be supplied.

[0123] The period during which the fifth transistor (T5) and the sixth transistor (T6) are turned on (for example, the period during which a low-level light emission control signal (EM) is supplied to the subpixel (SPX)) may be the light emission period of the subpixel (SPX). During the light emission period of the subpixel (SPX), the first transistor (T1) may supply a driving current (Ids) corresponding to the voltage of the first node (N1) to the light-emitting element (LE).

[0124] The light-emitting element (LE) can be connected between the pixel circuit (PXC) and the second power line (VSL). For example, the first electrode of the light-emitting element (LE) (e.g., an anode electrode or a pixel electrode) can be connected to a node between the sixth transistor (T6) and the seventh transistor (T7), and the second electrode of the light-emitting element (LE) (e.g., a cathode electrode or a common electrode) can be connected to the second power line (VSL). The light-emitting element (LE) can emit light in response to a driving current (Ids) supplied from the pixel circuit (PXC).

[0125] In one embodiment, the subpixel (SPX) may include a single light-emitting element (LE), but is not limited thereto. For example, the subpixel (SPX) may include a plurality of light-emitting elements (LE).

[0126] In one embodiment, the light-emitting element (LE) may be a micro light-emitting diode containing an inorganic compound such as a nitride-based or phosphide-based semiconductor material, but is not limited thereto. For example, the light-emitting element (LE) may be an organic light-emitting element, a quantum dot light-emitting element, or other types of light-emitting elements. Additionally, the size or shape of the light-emitting element (LE) may vary depending on the embodiments.

[0127] FIG. 6 is a plan view showing a display panel according to one embodiment. For example, FIG. 6 shows a part of a display area (DA) in which two pixels (PX) are sequentially arranged in a second direction (DR2), and a part of a non-display area (NDA) adjacent to the part of the display area (DA) in which a power bus line (BLI) is arranged.

[0128] FIG. 6 shows an embodiment of a light-emitting element layer including light-emitting elements (LE) of subpixels (SPX). The display panel (100) may further include a backplane layer including circuit elements of subpixels (SPX) (for example, circuit elements included in each of the pixel circuits (PXC) of subpixels (SPX)).

[0129] Referring to FIG. 6, each of the subpixels (SPX) may include a pixel electrode (PXE) and a light-emitting element (LE) disposed on the pixel electrode (PXE). In one embodiment, where the light-emitting element (LE) is a flip-chip type or lateral type micro LED, each of the subpixels (SPX) may further include a common electrode (CE) disposed on one side (e.g., a bottom surface or a top surface) of the light-emitting element (LE) together with the pixel electrode (PXE). In another embodiment, where the light-emitting element (LE) is a vertical type micro LED, the light-emitting element (LE) of each of the subpixels (SPX) may be disposed on the pixel electrode (PXE), and the common electrode (CE) (e.g., a common electrode disposed across the entire display area (DA) in the form of a common layer) may be disposed on the light-emitting elements (LE) of the subpixels (SPX). FIG. 6 shows a display panel (100) including flip-chip type light-emitting elements (LE). The pixel electrode (PXE) is referred to as the anode electrode or the first electrode, and the common electrode (CE) may also be referred to as the cathode electrode or the second electrode.

[0130] In one embodiment, subpixels (SPX) of each pixel (PX) may be arranged in a first direction (DR1) and may share a common electrode (CE). For example, the common electrode (CE) extends in the first direction (DR1) from each pixel row (or horizontal line) of the display area (DA), and the subpixels (SPX) of the pixels (PX) placed in that pixel row may share a common electrode (CE).

[0131] A first subpixel (SPX1) may include a first pixel electrode (PXE1) and a common electrode (CE) (or a part of the common electrode (CE)) spaced apart from each other, and a first light-emitting element (LE1) disposed on the first pixel electrode (PXE1) and the common electrode (CE). The first light-emitting element (LE1) may refer to a light-emitting element (LE) of the first subpixel (SPX1). The first light-emitting element (LE1) may be electrically connected between the first pixel electrode (PXE1) and the common electrode (CE).

[0132] The second subpixel (SPX2) may include a second pixel electrode (PXE2) and a common electrode (CE) spaced apart from each other, and a second light-emitting element (LE2) disposed on the second pixel electrode (PXE2) and the common electrode (CE). The second light-emitting element (LE2) may refer to the light-emitting element (LE) of the second subpixel (SPX2). The second light-emitting element (LE2) may be electrically connected between the second pixel electrode (PXE2) and the common electrode (CE).

[0133] The third subpixel (SPX3) may include a third pixel electrode (PXE3) and a common electrode (CE) spaced apart from each other, and a third light-emitting element (LE3) disposed on the third pixel electrode (PXE3) and the common electrode (CE). The third light-emitting element (LE3) may refer to the light-emitting element (LE) of the third subpixel (SPX3). The third light-emitting element (LE3) may be electrically connected between the third pixel electrode (PXE3) and the common electrode (CE).

[0134] In one embodiment, the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3) of each pixel (PX) may be arranged in a first direction (DR1) and spaced apart from the common electrode (CE) in a second direction (DR2). For example, in each pixel (PX), the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3) may be arranged sequentially along the first direction (DR1). Additionally, the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3) may face different parts of the common electrode (CE) in the second direction (DR2). In another embodiment, when the subpixels (SPX) include vertical type micro LEDs, the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3) may face the common electrode (CE) in the third direction (DR3).

[0135] The pixel electrode (PXE) and pixel circuit (PXC in FIG. 4) of each of the subpixels (SPX) can be electrically connected to each other through an anode contact hole (ANH). For example, the first pixel electrode (PXE1) of the first subpixel (SPX1) can be electrically connected to at least one circuit element (e.g., the 6th and 7th transistors (T6, T7) in FIG. 4) included in the pixel circuit (PXC) of the first subpixel (SPX1) through a first anode contact hole (ANH1) and / or at least one connection pattern. Similarly, the second pixel electrode (PXE2) of the second subpixel (SPX2) may be electrically connected to at least one circuit element included in the pixel circuit (PXC) of the second subpixel (SPX2) through the second anode contact hole (ANH2) and / or at least one connection pattern, and the third pixel electrode (PXE3) of the third subpixel (SPX3) may be electrically connected to at least one circuit element included in the pixel circuit (PXC) of the third subpixel (SPX3) through the third anode contact hole (ANH3) and / or at least one connection pattern.

[0136] Light-emitting elements (LE) may be placed between each pixel electrode (PXE) and a common electrode (CE). For example, a first light-emitting element (LE1) may be placed on the first pixel electrode (PXE1) and the common electrode (CE), and a part of the first light-emitting element (LE1) may overlap with the first pixel electrode (PXE1) and another part of the first light-emitting element (LE1) may overlap with the common electrode (CE). A second light-emitting element (LE2) may be placed on the second pixel electrode (PXE2) and the common electrode (CE), and a part of the second light-emitting element (LE2) may overlap with the second pixel electrode (PXE2) and another part of the second light-emitting element (LE2) may overlap with the common electrode (CE). The third light-emitting element (LE3) is placed on the third pixel electrode (PXE3) and the common electrode (CE), and a part of the third light-emitting element (LE3) overlaps with the third pixel electrode (PXE3) and another part of the third light-emitting element (LE3) overlaps with the common electrode (CE).

[0137] Each of the light-emitting elements (LE) can emit light of a specific color (e.g., red light, green light, blue light, or white light). In one embodiment, the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) can emit light of different colors. For example, the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) can each emit light of a first color (e.g., red light), light of a second color (e.g., green light), and light of a third color (e.g., blue light).

[0138] In one embodiment, the light-emitting elements (LE) of at least two subpixels (SPX) may have different sizes. For example, the size of the first light-emitting element (LE1) may be larger than the size of the second light-emitting element (LE2) and the third light-emitting element (LE3), respectively. The sizes of the second light-emitting element (LE2) and the third light-emitting element (LE3) may be the same or different from each other.

[0139] In one embodiment, the light-emitting elements (LE) may have a differentiated or optimized size depending on the light-emitting efficiency of the light-emitting elements (LE). For example, depending on the light-emitting efficiency of each of the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3), at least two of the light-emitting elements (LE) among the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) may have different sizes. For example, based on the same size and shape, if the light-emitting efficiency of the first light-emitting element (LE1) is lower than the light-emitting efficiency of the second light-emitting element (LE2) and the third light-emitting element (LE3), the size of the first light-emitting element (LE1) may be larger than the size of the second light-emitting element (LE2) and the third light-emitting element (LE3). Accordingly, the light-emitting efficiency of the first light-emitting element (LE1) can be improved, and the difference in light-emitting efficiency between the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) can be reduced or prevented.

[0140] In another embodiment, the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) may emit light of the same color. In this case, on at least one light-emitting element (LE) among the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3), at least one of a light conversion layer (e.g., a light conversion layer including wavelength conversion particles such as quantum dots) and a color filter may be disposed to convert the light emitted from the light-emitting element (LE) of the corresponding subpixel (SPX) into light corresponding to the light emission color of the corresponding subpixel (SPX). When the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) emit light of the same color, the sizes of the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) may be the same or different from each other. For example, depending on the light conversion efficiency of the light conversion layer, at least one of the size of the light-emitting elements (LE) of the subpixels (SPX) and the area of ​​the light-emitting regions (EA) of the subpixels (SPX) may be differentiated.

[0141] A common electrode (CE) may be electrically connected to a power bus line (BLI) (e.g., a cathode bus line) to which a second driving voltage (VSS) is applied. In one embodiment, the common electrode (CE) may extend to a non-display area (NDA) around a display area (DA) and may be electrically connected to the power bus line (BLI) in the non-display area (NDA). The common electrode (CE) may be electrically connected to the power bus line (BLI) through at least one contact hole and / or connecting wiring, etc., or may be formed integrally with at least a portion of the power bus line (BLI). For example, the power bus line (BLI) may be composed of a plurality of wiring layers, and one of the wiring layers and the common electrode (CE) may be formed substantially as one pattern.

[0142] In one embodiment, a second power line (VSL in FIG. 4) to which a second driving voltage (VSS) is applied may also be disposed within the display area (DA). For example, a second power line (VSL) that intersects or overlaps with the common electrode (CE) may be disposed within a backplane layer disposed below the common electrode (CE). In this case, the common electrode (CE) may be electrically connected to the second power line (VSL) through at least one contact hole and / or connecting wiring, etc., within the display area (DA).

[0143] The power bus line (BLI) may be placed in a non-display area (NDA) and may be placed on at least one side of the display area (DA). For example, the power bus line (BLI) may be placed on the left and right sides of the display area (DA), and may be optionally placed on at least one of the upper and lower sides of the display area (DA). In FIG. 6, a portion of the power bus line (BLI) placed on the left side of the display area (DA) is shown.

[0144] The power bus line (BLI) can be electrically connected to the power supply unit (500 in FIG. 3). For example, the power bus line (BLI) can be electrically connected to the power supply unit (500) through at least one connection wire and / or at least one pad (PD), etc., placed in the non-display area (NDA) and / or sub-area (SBA) of the main area (MA). Accordingly, a second driving voltage (VSS) output from the power supply unit (500) can be applied to the power bus line (BLI). The power bus line (BLI) can form a part of a second power line (VSL) that is electrically connected between the power supply unit (500) and the sub-pixels (SPX). In addition to the embodiments described above, the connection structure between the common electrode (CE) and the second power line (VSL) can be varied.

[0145] In one embodiment, the power bus line (BLI) may be composed of multiple layers including a first wiring layer (BLI1) and a second wiring layer (BLI2). The first wiring layer (BLI1) and the second wiring layer (BLI2) may be electrically connected to each other.

[0146] The first wiring layer (BLI1) may be disposed on the same layer as the pixel electrodes (PXE) and the common electrode (CE), and may include a conductive material contained in the pixel electrodes (PXE) and the common electrode (CE). In one embodiment, the first wiring layer (BLI1) may be formed integrally with the common electrode (CE). For example, at least one end of the common electrode (CE) may extend to a non-display area (NDA) and lead to the first wiring layer (BLI1) of the power bus line (BLI).

[0147] The second wiring layer (BLI2) may overlap with at least a portion of the first wiring layer (BLI1). In one embodiment, the second wiring layer (BLI2) may be positioned below the first wiring layer (BLI1) and may come into contact with the first wiring layer (BLI1). For example, at least one insulating layer covering the end of the second wiring layer (BLI2) may be disposed between the first wiring layer (BLI1) and the second wiring layer (BLI2), and the at least one insulating layer may be open in the area where the first wiring layer (BLI1) and the second wiring layer (BLI2) overlap. The first wiring layer (BLI1) and the second wiring layer (BLI2) may come into contact and be electrically connected to each other in the area where the at least one insulating layer is open.

[0148] In one embodiment, the second wiring layer (BLI2) may have a wider width than the first wiring layer (BLI1) in the first direction (DR1). For example, the second wiring layer (BLI2) may extend further toward the outer edge of the display panel (100) from the portion overlapping with the first wiring layer (BLI1) to form a shield layer covering the scan drive unit (for example, the first scan drive unit (SDC1) and the second scan drive unit (SDC2) of FIG. 2 and FIG. 3). In one embodiment, the second wiring layer (BLI2) may be formed to include a plurality of openings (OPN). Accordingly, gas generated by outgassing inside the display panel (100) can be properly discharged.

[0149] In one embodiment, dummy patterns (DMP) may be further disposed in the non-display area (NDA). For example, the dummy patterns (DMP) may have a shape and / or size corresponding to the pixel electrodes (PXE) and may be disposed around the pixel electrodes (PXE) located at the outermost edge of the display area (DA). In one embodiment, dummy pixel circuits connected to each dummy pattern (DMP) through respective dummy holes may be disposed below the dummy patterns (DMP). The dummy patterns (DMP) and / or dummy pixel circuits may be omitted.

[0150] FIG. 7 is a plan view showing a display panel according to one embodiment. Compared to FIG. 6, FIG. 7 shows a display panel (100) further including connecting electrodes (BE). In describing the following embodiments, the same reference numerals are used for configurations that are substantially identical or similar to at least one embodiment described above, and redundant descriptions are omitted.

[0151] Referring to FIGS. 6 and 7, the display panel (100) may further include connecting electrodes (BE) disposed on subpixels (SPX). For example, each subpixel (SPX) may include a first connecting electrode (BE1) disposed on a pixel electrode (PXE) and a second connecting electrode (BE2) disposed on a common electrode (CE).

[0152] The first connecting electrode (BE1) can connect the pixel electrode (PXE) and the light-emitting element (LE). For example, in each sub-pixel (SPX), the first connecting electrode (BE1) can be electrically connected to the pixel electrode (PXE) through the first connecting hole (BH1). The first connecting hole (BH1) may be an opening formed in an insulating layer or an adhesive layer disposed between the pixel electrode (PXE) and the light-emitting element (LE). Additionally, the first connecting electrode (BE1) can be electrically connected to the light-emitting element (LE) by contacting a part of the light-emitting element (LE) disposed on the pixel electrode (PXE) (for example, the side on which the first contact electrode of the light-emitting element (LE) is disposed). As shown in FIG. 7, the first connecting electrode (BE1) may be in contact only with a part of the side of the light-emitting element (LE), but the embodiments are not limited thereto. For example, in another embodiment, the first connecting electrode (BE1) may also be disposed on a part of the upper surface of the light-emitting element (LE).

[0153] The second connecting electrode (BE2) can connect the common electrode (CE) and the light-emitting element (LE). For example, in each subpixel (SPX), the second connecting electrode (BE2) can be electrically connected to the common electrode (CE) through a second connecting hole (BH2). The second connecting hole (BH2) may be an opening formed in an insulating layer or an adhesive layer disposed between the common electrode (CE) and the light-emitting element (LE). Additionally, the second connecting electrode (BE2) can be electrically connected to the light-emitting element (LE) by contacting another part of the light-emitting element (LE) disposed on the common electrode (CE) (for example, the side on which the second contact electrode of the light-emitting element (LE) is disposed). As shown in FIG. 7, the second connecting electrode (BE2) may be in contact only with a part of the side of the light-emitting element (LE), but the embodiments are not limited thereto. For example, in another embodiment, the second connecting electrode (BE2) may also be disposed on a part of the upper surface of the light-emitting element (LE). However, the first connecting electrode (BE1) and the second connecting electrode (BE2) may be separated from each other. In one embodiment, the second connecting electrodes (BE2) of a pixel (PX) or subpixels (SPX) arranged in a single horizontal line may be formed integrally to substantially form a single pattern, but the embodiments are not limited thereto.

[0154] FIG. 7 discloses an embodiment in which the first connecting electrode (BE1) and the pixel electrode (PXE) are electrically connected through the first connecting hole (BH1), and the second connecting electrode (BE2) and the common electrode (CE) are electrically connected through the second connecting hole (BH2), but the embodiments are not limited thereto. For example, in other embodiments, the insulating layer or adhesive layer on the pixel electrode (PXE) and the common electrode (CE) may partially cover the pixel electrode (PXE) and the common electrode (CE) only below the light-emitting element (LE) and / or immediately around the light-emitting element (LE), and may not be placed on other parts of the pixel electrode (PXE) and the common electrode (CE). In this case, the first connecting hole (BH1) and the second connecting hole (BH2) may be omitted, and the first connecting electrode (BE1) and the second connecting electrode (BE2) may be placed directly on other parts of the pixel electrode (PXE) and the common electrode (CE), respectively.

[0155] FIG. 8 is a plan view showing a display panel according to one embodiment. Compared to FIG. 7, FIG. 8 shows a display panel (100) further comprising a reflective layer (RFL).

[0156] Referring to FIGS. 6 through 8, the display panel (100) may further include a reflective layer (RFL) disposed on subpixels (SPX). The reflective layer (RFL) may cover at least a portion of each of the pixel electrode (PXE) and the common electrode (CE). For example, the reflective layer (RFL) may include a first reflective layer (RFL1) and a second reflective layer (RFL2) disposed on the pixel electrode (PXE) and the common electrode (CE) of each of the subpixels (SPX).

[0157] The first reflective layer (RFL1) may cover at least a portion of the pixel electrode (PXE). For example, the first reflective layer (RFL1) may be disposed on a portion of the pixel electrode (PXE) including an end that overlaps with the light-emitting element (LE).

[0158] The second reflective layer (RFL2) may cover at least a portion of the common electrode (CE). For example, the second reflective layer (RFL2) may be disposed on a portion of the common electrode (CE) including an end that overlaps with the light-emitting element (LE). The end of the common electrode (CE) that overlaps with the light-emitting element (LE) may be an end adjacent to the pixel electrode (PXE). The end of the first reflective layer (RFL1) that overlaps with the light-emitting element (LE) and the end of the second reflective layer (RFL2) that overlaps with the light-emitting element (LE) may face each other.

[0159] Each light-emitting element (LE) of the subpixels (SPX) may be disposed on a first reflective layer (RFL1) and a second reflective layer (RFL2). For example, one part of the light-emitting element (LE) may be disposed on the first reflective layer (RFL1), and another part of the light-emitting element (LE) may be disposed on the second reflective layer (RFL2). In one embodiment, a first connecting electrode (BE1) and a second connecting electrode (BE2) may be disposed on the first reflective layer (RFL1) and the second reflective layer (RFL2), respectively. The first connecting electrode (BE1) connects the pixel electrode (PXE) or the first reflective layer (RFL1) to a part of the light-emitting element (LE) (for example, the first contact electrode (CTE1) of FIG. 10), and the second connecting electrode (BE2) connects the common electrode (CE) or the second reflective layer (RFL2) to another part of the light-emitting element (LE) (for example, the second contact electrode (CTE2) of FIG. 10).

[0160] In one embodiment, the first reflective layer (RFL1) and the second reflective layer (RFL2) may each be a single layer or a multilayer conductive layer containing a conductive material. Additionally, the first reflective layer (RFL1) and the second reflective layer (RFL2) may be separated from each other. A pixel electrode (PXE) may be electrically connected to a part of the light-emitting element (LE) through the first reflective layer (RFL1) and the first connecting electrode (BE1), and a common electrode (CE) may be electrically connected to another part of the light-emitting element (LE) through the second reflective layer (RFL2) and the second connecting electrode (BE2). If the first reflective layer (RFL1) and the second reflective layer (RFL2) are conductive, the first reflective layer (RFL1) may also be referred to as the "first reflective electrode," and the second reflective layer (RFL2) may also be referred to as the "second reflective electrode."

[0161] The first reflective layer (RFL1) and the second reflective layer (RFL2) may include a material with high reflectivity for light emitted from a light-emitting element (LE). For example, the first reflective layer (RFL1) and the second reflective layer (RFL2) may include silver (Ag) or aluminum (Al), or other metals with high light reflectivity. In one embodiment, the first reflective layer (RFL1) and the second reflective layer (RFL2) may be formed as a three-layer structure (ITO / Ag / ITO) of indium tin oxide (ITO), silver (Ag), and indium tin oxide (ITO), but the embodiments are not limited thereto. Additionally, the first reflective layer (RFL1) and the second reflective layer (RFL2) may each be formed as a single layer or a multilayer.

[0162] In one embodiment, the first reflective layer (RFL1) and the second reflective layer (RFL2) of each subpixel (SPX) may have corresponding shapes and / or sizes. For example, the first reflective layer (RFL1) and the second reflective layer (RFL2) of each subpixel (SPX) may have substantially the same shape and / or size and may be formed symmetrically with respect to each other. In describing the embodiments, the phrase "substantially identical" includes the meaning of "completely identical," as well as the meaning of "similar to each other to the extent that they have a fine deviation within an allowable tolerance range including process margins."

[0163] For example, with respect to the light-emitting element (LE) of each subpixel (SPX), or with respect to a symmetry axis extending in a first direction (DR1) passing through the center between the pixel electrode (PXE) and the common electrode (CE), the first reflective layer (RFL1) and the second reflective layer (RFL2) may have a substantially symmetrical shape (for example, a vertically symmetrical shape as in the plan view of FIG. 8). As the first reflective layer (RFL1) and the second reflective layer (RFL2) are formed symmetrically, the light emission characteristics of the subpixel (SPX) can be improved. For example, light emitted from the light-emitting element (LE) can be reflected more uniformly and / or efficiently by the mutually symmetrical first reflective layer (RFL1) and second reflective layer (RFL2) and emitted to the upper part of the subpixel (SPX).

[0164] In one embodiment, the first reflective layer (RFL1) may have a width (W2) (hereinafter referred to as "second width (W2)") greater than the width (W1) of the pixel electrode (PXE) in the first direction (DR1) (hereinafter referred to as "first width (W1)"), and may cover one end of the pixel electrode (PXE) facing the common electrode (CE). In one embodiment, the first direction (DR1) may be a direction in which one end of the pixel electrode (PXE) facing the common electrode (CE) and one end of the common electrode (CE) facing the pixel electrode (PXE) extend. For example, the first reflective layer (RFL1) may appropriately cover the upper surface and the side surface of the pixel electrode (PXE) in the portion overlapping with the light-emitting element (LE) and around it. In one embodiment, the second reflective layer (RFL2) may have a width (W3) (hereinafter referred to as "third width (W3)") corresponding to the second width (W2) of the first reflective layer (RFL1) in the first direction (DR1). For example, the second width (W2) of the first reflective layer (RFL1) and the third width (W3) of the second reflective layer (RFL2) may be substantially the same. The second reflective layer (RFL2) may cover one end of the common electrode (CE) facing the pixel electrode (PXE). For example, the second reflective layer (RFL2) may appropriately cover the upper surface and side surface (for example, the side surface facing the pixel electrode (PXE)) of the common electrode (CE) in the portion overlapping with the light-emitting element (LE) and around it. Accordingly, the light reflectance by the first reflective layer (RFL1) and the second reflective layer (RFL2) can be increased, and the light efficiency of the subpixel (SPX) can be improved.

[0165] In one embodiment, the pixel electrode (PXE) extends to an area where each anode contact hole (ANH) is located, so as to reliably cover each anode contact hole (ANH). Accordingly, the length (L1) of the pixel electrode (PXE) extending in the second direction (DR2) (hereinafter referred to as the "first length (L1)") may be greater than or equal to the length (L2) of the common electrode (CE) extending in the second direction (DR2) (hereinafter referred to as the "second length (L2)"). For example, the first length (L1) may be greater than the second length (L2).

[0166] In one embodiment, a light-emitting element region (e.g., a light-emitting element bonding region) on which a light-emitting element (LE) is placed may be arranged or configured vertically symmetrically with respect to each pixel electrode (PXE) and common electrode (CE). For example, the shape and / or size of the region where the light-emitting element (LE) and the pixel electrode (PXE) overlap may be substantially the same as the shape and / or size of the region where the light-emitting element (LE) and the common electrode (CE) overlap. Accordingly, the light-emitting element (LE) can be stably placed on the pixel electrode (PXE) and the common electrode (CE).

[0167] According to one embodiment, when the first reflective layer (RFL1) and the second reflective layer (RFL2) have an up-and-down symmetrical shape, each of the first reflective layer (RFL1) and the second reflective layer (RFL2) may be extended by substantially the same margin length (Lm) in a second direction (DR2) (for example, up and down from the light-emitting element region) toward the outer edge of the subpixel (SPX) from the light-emitting element region. Accordingly, the length (L3) (hereinafter referred to as "third length (L3)") of the first reflective layer (RFL1) extending in the second direction (DR2) may be less than or equal to the first length (L1). For example, the third length (L3) may be smaller than the first length (L1), and the pixel electrode (PXE) may not be covered by the first reflective layer (RFL1) at the end far from the region where the light-emitting element (LE) is placed. In one embodiment, the common electrode (CE) may not be covered by the second reflective layer (RFL2) at the end far from the area where the light-emitting element (LE) is placed. When the second length (L2) is smaller than the first length (L1), the size of the portion of the common electrode (CE) not covered by the second reflective layer (RFL2) may be smaller than the size of the portion of the pixel electrode (PXE) not covered by the first reflective layer (RFL1).

[0168] In one embodiment, the reflective layer (RFL) may not be disposed in the non-display area (NDA). For example, the reflective layer (RFL) may be disposed only within the display area (DA) where the light-emitting elements (LE) are disposed, and may not be disposed in the non-display area (NDA).

[0169] FIG. 9 is a cross-sectional view showing a display panel according to one embodiment. For example, FIG. 9 shows an example of a cross-sectional view of a part of a display panel (100) corresponding to the line X1-X1' of FIG. 8.

[0170] FIG. 10 is a cross-sectional view showing the A1 region of FIG. 9 in detail. For example, FIG. 10 shows in detail an example of a first light-emitting element (LE1) included in a first subpixel (SPX1). In one embodiment, the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) of the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) may have substantially the same or similar cross-sectional structures.

[0171] Referring to FIGS. 9 and FIGS. 10 in addition to FIGS. 1 to 8, a display panel (100) may include a substrate (110), a backplane layer (120) and a light-emitting element layer (130) disposed on the substrate (110). In one embodiment, the display panel (100) may further include an optical layer (140) disposed on the light-emitting element layer (130). The backplane layer (120), the light-emitting element layer (130), and the optical layer (140) may be sequentially disposed on the substrate (110) along a third direction (DR3).

[0172] The substrate (110) may be made of an insulating material such as glass or a polymer resin. If the substrate (110) is made of a polymer resin, it may be a stretchable flexible substrate.

[0173] The substrate (110) may include a display area (DA) and a non-display area (NDA). The display area (DA) may include light-emitting areas (EA) of subpixels (SPX). Each light-emitting area (EA) may include a light-emitting element area where a light-emitting element (LE) of each subpixel (SPX) is placed.

[0174] The backplane layer (120) may include circuit elements included in the pixel circuits (PXC) of the subpixels (SPX) and wiring connected to the subpixels (SPX). In one embodiment, the backplane layer (120) may be formed entirely on one side of the substrate (110).

[0175] The backplane layer (120) may include at least one semiconductor layer, conductive layers, and insulating layers. In one embodiment, when the pixel circuits (PXC) include at least two types of pixel transistors (PXT) formed of different materials, the backplane layer (120) may include a plurality of semiconductor layers.

[0176] For example, the backplane layer (120) is sequentially arranged on the substrate (110) along a third direction (DR3) and comprises a lower conductive layer (BCDL), a barrier layer (121) (or buffer layer), a first semiconductor layer (SCL1) (in one example, a polycrystalline silicon semiconductor layer), a first insulating layer (122) (in one example, a first inorganic insulating layer), a first gate conductive layer (GCDL1) (or a first conductive layer), a second insulating layer (123) (in one example, a second inorganic insulating layer), a second gate conductive layer (GCDL2) (or a second conductive layer), a third insulating layer (124) (in one example, a third inorganic insulating layer), a second semiconductor layer (SCL2) (in one example, an oxide semiconductor layer), a fourth insulating layer (125) (in one example, a fourth inorganic insulating layer), a third gate conductive layer (GCDL3) (or a third conductive layer), a fifth insulating layer (126) (in one example, a fifth inorganic insulating layer), and a first source-drain layer. It may include a conductive layer (SCDL1) (or a fourth conductive layer), a sixth insulating layer (127) (for example, a first organic insulating layer), a second source-drain conductive layer (SCDL2) (or a fifth conductive layer) and a seventh insulating layer (128) (for example, a second organic insulating layer).

[0177] The lower conductive layer (BCDL) may include a lower conductive pattern (BML) disposed below the first transistor (T1). The lower conductive pattern (BML) may cover the lower surface of the first active layer (ACT1) included in the first transistor (T1) wholly or partially. For example, the lower conductive pattern (BML) may be disposed below the first active layer (ACT1) to overlap with the channel region of the first active layer (ACT1) (for example, a part of the first active layer (ACT1) that overlaps with the first gate electrode (GE1)). In one embodiment, the lower conductive layer (BCDL) may include a light-blocking material. For example, the lower conductive layer (BCDL) may include a metal, and the lower conductive pattern (BML) may be formed as a lower metal pattern. Accordingly, light incident on the channel region of the first active layer (ACT1) from below the first active layer (ACT1) can be blocked, and the operating characteristics of the first transistor (T1) can be stabilized.

[0178] A barrier layer (121) may be disposed on a lower conductive layer (BCDL). The barrier layer (121) can protect circuit elements of the backplane layer (120) and light-emitting elements (LE) on the backplane layer (120) from moisture penetrating through a substrate (110) that is susceptible to moisture permeability. In one embodiment, the barrier layer (121) may be composed of a plurality of inorganic insulating layers.

[0179] Circuit elements of the backplane layer (120) may be disposed on the barrier layer (121). For example, pixel transistors (PXT), storage capacitors (Cst), and boosting capacitors (Cbst) included in the pixel circuits (PXC) of each subpixel (SPX) may be disposed on the barrier layer (121). Additionally, wiring of the backplane layer (120) may be disposed on the barrier layer (121). For example, signal lines and power lines electrically connected to the subpixels (SPX) may be disposed on the barrier layer (121).

[0180] FIG. 9 shows, as an example of circuit elements included in the backplane layer (120), a first transistor (T1), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a storage capacitor (Cst), and a boosting capacitor (Cbst) included in the first subpixel (SPX1). FIG. 9 also shows, as an example of wiring included in the backplane layer (120), a write scan line (GWL), first and second light emission control lines (EL1, EL2), a first power line (VDL), and a third power line (VIL). Each of the other wirings includes at least one wiring layer included in at least one conductive layer included in the backplane layer (120), and each may be formed as a single layer or a multilayer wiring.

[0181] In one embodiment, each pixel circuit (PXC) may include first type transistors and second type transistors. The first type transistors and second type transistors may be placed on different layers within the backplane layer (120). For example, as shown in FIG. 4, each pixel circuit (PXC) may include first, second, fifth, sixth, seventh, and eighth P-type transistors (T1, T2, T5, T6, T7, T8) and third and fourth N-type transistors (T3, T4). The active layers included in the first, second, fifth, sixth, seventh, and eighth transistors (T1, T2, T5, T6, T7, T8) and the active layers included in the third and fourth transistors (T3, T4) may be formed with patterns of different semiconductor layers. In addition, the gate electrodes included in the first, second, fifth, sixth, seventh, and eighth transistors (T1, T2, T5, T6, T7, T8) and the gate electrodes included in the third and fourth transistors (T3, T4) can be formed with patterns of different conductive layers.

[0182] A first semiconductor layer (SCL1) (also referred to as the "first semiconductor pattern layer") may be disposed on the barrier layer (121). The first semiconductor layer (SCL1) may include an active layer for each of the first type of transistors. For example, the first semiconductor layer (SCL1) may include a first active layer (ACT1) included in the first transistor (T1), a fifth active layer (ACT5) included in the fifth transistor (T5), and second, sixth, seventh, and eighth active layers (not shown) included in the second, sixth, seventh, and eighth transistors (T2, T6, T7, T8). In one embodiment, the patterns of the first semiconductor layer (SCL1) included in one subpixel (SPX) (for example, the first and fifth active layers (ACT1, ACT5) and the second, sixth, seventh, and eighth active layers of each subpixel (SPX)) may be formed integrally, but are not limited thereto.

[0183] The patterns of the first semiconductor layer (SCL1) may include a first semiconductor material. In one embodiment, the first semiconductor material may be polycrystalline silicon (e.g., low-temperature polycrystalline silicon), but is not limited thereto. For example, the first semiconductor material may be an oxide semiconductor (e.g., at least one of zinc oxide (ZnO), zinc-tin oxide (ZTO), indium-zinc oxide (IZO), indium oxide (InO), titanium oxide (TiO), indium-gallium oxide (IGO), indium-gallium-zinc oxide (IGZO), indium-gallium-tin oxide (IGTO), indium-zinc-tin oxide (IZTO), indium-tin-gallium-zinc oxide (ITGZO), or other oxide semiconductors) or single-crystal silicon.

[0184] A first insulating layer (122) may be disposed on the first semiconductor layer (SCL1). The first insulating layer (122) may comprise at least one insulating material (e.g., silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), titanium oxide (TiOx), aluminum oxide (AlOx), or other inorganic insulating material) and may be composed of a single layer or multiple layers.

[0185] A first gate conductive layer (GCDL1) may be disposed on the first insulating layer (122). The first gate conductive layer (GCDL1) may include the gate electrodes of each of the first type of transistors. For example, the first gate conductive layer (GCDL1) may include a first gate electrode (GE1) included in the first transistor (T1), a fifth gate electrode (GE5) included in the fifth transistor (T5), and second, sixth, seventh, and eighth gate electrodes (not shown) included in the second, sixth, seventh, and eighth transistors (T2, T6, T7, T8).

[0186] The first gate conductive layer (GCDL1) may further include at least one conductive pattern and / or wiring. For example, the first gate conductive layer (GCDL1) may further include a first capacitor electrode (SCE1) of a storage capacitor (Cst), a first electrode (BCE1) of a boosting capacitor (Cbst), and a write scan line (GWL), etc. In one embodiment, the first gate electrode (GE1) of each pixel circuit (PXC) and the first capacitor electrode (SCE1) of the storage capacitor (Cst) are formed integrally, and the first electrode (BCE1) of the boosting capacitor (Cbst) of each pixel circuit (PXC) and the write scan line (GWL) connected to the pixel circuit (PXC) may be formed integrally. In one embodiment, the first gate conductive layer (GCDL1) may further include the bias scan line (GBL) of FIG. 4.

[0187] A second insulating layer (123) may be disposed on the first gate conductive layer (GCDL1). The second insulating layer (123) may comprise at least one insulating material (e.g., an inorganic insulating material) and may be composed of a single layer or multiple layers.

[0188] A second gate conductive layer (GCDL2) may be disposed on the second insulating layer (123). The second gate conductive layer (GCDL2) may include a second capacitor electrode (SCE2) of a storage capacitor (Cst). The first capacitor electrode (SCE1) and the second capacitor electrode (SCE2) of the storage capacitor (Cst) may overlap with the second insulating layer (123) in between.

[0189] The second gate conductive layer (GCDL2) may further include at least one conductive pattern and / or wiring. For example, the second gate conductive layer (GCDL2) may further include a first light-blocking pattern (LBP1) and a second light-blocking pattern (LBP2). The first light-blocking pattern (LBP1) and the second light-blocking pattern (LBP2) may each be disposed below a channel region of the third active layer (ACT3) (for example, a part of the third active layer (ACT3) that overlaps with the third gate electrode (GE3)) and a channel region of the fourth active layer (ACT4) (for example, a part of the fourth active layer (ACT4) that overlaps with the fourth gate electrode (GE4)). Accordingly, light incident on the channel regions of the third active layer (ACT3) and the fourth active layer (ACT4) is blocked from below the third active layer (ACT3) and the fourth active layer (ACT4), and the operating characteristics of the third transistor (T3) and the fourth transistor (T4) can be stabilized. In one embodiment, the second gate conductive layer (GCDL2) may further include the fourth power line (VAIL) of FIG. 4.

[0190] A third insulating layer (124) may be disposed on the second gate conductive layer (GCDL2). The third insulating layer (124) may comprise at least one insulating material (e.g., an inorganic insulating material) and may be composed of a single layer or multiple layers.

[0191] A second semiconductor layer (SCL2) (also referred to as the "second semiconductor pattern layer") may be disposed on the third insulating layer (124). The second semiconductor layer (SCL2) may include an active layer for each of the second type of transistors. For example, the second semiconductor layer (SCL2) may include a third active layer (ACT3) included in the third transistor (T3) and a fourth active layer (ACT4) included in the fourth transistor (T4). In one embodiment, the patterns of the second semiconductor layer (SCL2) included in one subpixel (SPX) (for example, the third and fourth active layers (ACT3, ACT4) of each subpixel (SPX) may be formed integrally, but are not limited thereto. In one embodiment, the second semiconductor layer (SCL2) further includes a second electrode (BCE2) of a boosting capacitor (Cbst), and the second electrode (BCE2) of the boosting capacitor (Cbst) may be formed integrally with the third and fourth active layers (ACT3, ACT4).

[0192] The patterns of the second semiconductor layer (SCL2) may include a second semiconductor material. In one embodiment, the second semiconductor material may be an oxide semiconductor, but is not limited thereto. For example, the second semiconductor material may be polycrystalline silicon or single-crystal silicon.

[0193] A fourth insulating layer (125) may be disposed on the second semiconductor layer (SCL2). The fourth insulating layer (125) may comprise at least one insulating material (e.g., an inorganic insulating material) and may be composed of a single layer or multiple layers.

[0194] A third gate conductive layer (GCDL3) may be disposed on the fourth insulating layer (125). The third gate conductive layer (GCDL3) may include the gate electrodes of each of the second type of transistors. For example, the third gate conductive layer (GCDL3) may include a third gate electrode (GE3) included in the third transistor (T3) and a fourth gate electrode (GE4) included in the fourth transistor (T4). The third gate conductive layer (GCDL3) may further include at least one conductive pattern and / or wiring. For example, the third gate conductive layer (GCDL3) may further include at least one of an initialization scan line (GIL), a control scan line (GCL), and a fifth power line (VOBL).

[0195] A fifth insulating layer (126) may be disposed on the third gate conductive layer (GCDL3). The fifth insulating layer (126) may comprise at least one insulating material (e.g., an inorganic insulating material) and may be composed of a single layer or multiple layers.

[0196] A first source-drain conductive layer (SCDL1) may be disposed on the fifth insulating layer (126). The first source-drain conductive layer (SCDL1) may include at least one electrode, a conductive pattern and / or wiring. For example, the first source-drain conductive layer (SCDL1) may include first, second, and third connection patterns (CNE1, CNE2, CNE3), first and second light emission control lines (EL1, EL2), and a third power line (VIL).

[0197] A first connection pattern (CNE1) may be electrically connected to a fifth active layer (ACT5), a second capacitor electrode (SCE2) of a storage capacitor (Cst), and a first power line (VDL) through at least one contact hole or via hole. A second connection pattern (CNE2) may be electrically connected to a first active layer (ACT1) and a third active layer (ACT3) through at least one contact hole. A third connection pattern (CNE3) may be electrically connected to a third active layer (ACT3) and a fourth active layer (ACT4) through at least one contact hole. A third connection pattern (CNE3) may be electrically connected to a first gate electrode (GE1) and a first capacitor electrode (SCE1) of a storage capacitor (Cst) through at least one contact hole in an area not illustrated. In one embodiment, a first source-drain conductive layer (SCDL1) may further include additional connection patterns for appropriately connecting circuit elements of each subpixel (SPX).

[0198] The first light emission control line (EL1) may be electrically connected to the fifth gate electrode (GE5) and the sixth gate electrode (not shown) of the first subpixel (SPX1) through at least one contact hole in an unillustrated area. The second light emission control line (EL2) may be electrically connected to the fifth and sixth gate electrodes (not shown) of the second and third subpixels (SPX2, SPX3) through at least one contact hole in an unillustrated area. The third power line (VIL) may be electrically connected to the fourth active layer (ACT4) through at least one contact hole.

[0199] A sixth insulating layer (127) may be disposed on the first source-drain conductive layer (SCDL1). The sixth insulating layer (127) may comprise at least one insulating material (e.g., acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or other organic insulating material) and may be composed of a single layer or multiple layers.

[0200] A second source-drain conductive layer (SCDL2) may be disposed on the sixth insulating layer (127). The second source-drain conductive layer (SCDL2) may include at least one electrode, a conductive pattern, and / or wiring. For example, the second source-drain conductive layer (SCDL2) may include a first power line (VDL).

[0201] In one embodiment, the first power line (VDL) may extend substantially in the second direction (DR2), etc., from the display area (DA) and may be commonly connected to subpixels (SPX) arranged continuously and / or sequentially in the second direction (DR2). The first power line (VDL), which is shown separated into two patterns in FIG. 9, may be a single, substantially integral wire. The first power line (VDL) may be electrically connected to the first connection pattern (CNE1) through a first via hole (VH1) (or contact hole). The first via hole (VH1) may be a type of contact hole, which is an opening formed in the sixth insulating layer (127) for contact between the first connection pattern (CNE1) and the first power line (VDL). In one embodiment, the first power line (VDL) may overlap with the channel areas of the first active layer (ACT1), the third active layer (ACT3), and the fourth active layer (ACT4). Accordingly, light incident on the channel regions of the first active layer (ACT1), the third active layer (ACT3), and the fourth active layer (ACT4) is blocked from the top of the first active layer (ACT1), the third active layer (ACT3), and the fourth active layer (ACT4), and the operating characteristics of the first transistor (T1), the third transistor (T3), and the fourth transistor (T4) can be stabilized.

[0202] In one embodiment, the second source-drain conductive layer (SCDL2) may further include an anode connection pattern (not shown) connected to a pixel electrode (PXE) of each subpixel (SPX), and data lines (DL) of FIGS. 3 and 4. The anode connection pattern of each subpixel (SPX) may be electrically connected between the pixel circuit (PXC) of the subpixel (SPX) and the pixel electrode (PXE). For example, the anode connection pattern of each subpixel (SPX) may be electrically connected to the sixth and seventh active layers of the subpixel (SPX) through at least one contact hole and / or at least one connection pattern, and electrically connected to the pixel electrode (PXE) of the subpixel (SPX) through the anode contact hole (ANH) of FIG. 8.

[0203] A seventh insulating layer (128) may be disposed on the second source-drain conductive layer (SCDL2). The seventh insulating layer (128) may comprise at least one insulating material (e.g., an organic insulating material) and may be a single layer or multiple layers.

[0204] Patterns included in each of the conductive layers of the backplane layer (120) may include at least one conductive material. For example, electrodes, conductive patterns, and / or wiring included in each of the lower conductive layer (BCDL), the first gate conductive layer (GCDL1), the second gate conductive layer (GCDL2), the third gate conductive layer (GCDL3), the first source-drain conductive layer (SCDL1), and the second source-drain conductive layer (SCDL2) may include at least one of copper (Cu), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), tantalum (Ta), tungsten (W), magnesium (Mg), and other metals, alloys thereof, or other conductive materials. In one embodiment, electrodes, conductive patterns, and / or wiring disposed in the same conductive layer may be formed simultaneously using the same conductive material. At least two of the conductive layers of the backplane layer (120) may contain the same conductive material or different conductive materials.

[0205] In one embodiment, the patterns included in each of the conductive layers of the backplane layer (120) may have a single-layer or multi-layer structure. For example, each of the electrodes, conductive patterns, and / or wiring included in each of the lower conductive layer (BCDL), the first gate conductive layer (GCDL1), the second gate conductive layer (GCDL2), the third gate conductive layer (GCDL3), the first source-drain conductive layer (SCDL1), and the second source-drain conductive layer (SCDL2) may have a single-layer or multi-layer structure. At least two of the conductive layers of the backplane layer (120) may have the same cross-sectional structure or different cross-sectional structures.

[0206] In one embodiment, the patterns of the second source-drain conductive layer (SCDL2) may comprise a metal (e.g., at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and other metals, or an alloy thereof) and may have a single-layer or multi-layer structure. For example, the electrodes, conductive patterns, and / or wiring included in the second source-drain conductive layer (SCDL2) may be low-resistance patterns formed of a three-layer structure (Ti / Al / Ti) of titanium (Ti), aluminum (Al), and titanium (Ti). Alternatively, the patterns of the second source-drain conductive layer (SCDL2) may comprise other low-resistance materials and / or structures. When the resistance of the patterns included in the second source-drain conductive layer (SCDL2) is reduced, the resistance of the conductive patterns and / or wiring placed on the current path through which the driving current of each subpixel (SPX) flows may be reduced. Accordingly, the image quality of the display device (1) can be standardized and power consumption improved.

[0207] A light-emitting element layer (130) may be disposed on the seventh insulating layer (128). The light-emitting element layer (130) may include pixel electrodes (PXE), light-emitting elements (LE), and a common electrode (CE) included in subpixels (SPX). Additionally, the light-emitting element layer (130) may further include insulating layers. In one embodiment, the insulating layers of the light-emitting element layer (130) may include eighth and ninth insulating layers (132, 134) and a first capping layer (136).

[0208] A pixel electrode layer (PCDL) including pixel electrodes (PXE) of subpixels (SPX) may be disposed on the seventh insulating layer (128). For example, the pixel electrode layer (PCDL) may include a first pixel electrode (PXE1), a second pixel electrode (PXE2), and a third pixel electrode (PXE3). In one embodiment, the light-emitting element (LE) may be a flip-chip type micro LED. A flip-chip type micro LED refers to an LED having first and second contact electrodes (CTE1, CTE2) formed on one side (e.g., the bottom side) of the light-emitting element (LE). When the light-emitting element (LE) is a flip-chip type micro LED, the pixel electrode layer (PCDL) may further include a common electrode (CE). For example, the pixel electrodes (PXE) of subpixels (SPX) and the common electrode (CE) may be disposed on the same layer and may be formed simultaneously using the same conductive material. Figure 9 shows the first pixel electrode (PXE1) and the common electrode (CE) of the first subpixel (SPX1) among the patterns of the pixel electrode layer (PCDL).

[0209] The first pixel electrode (PXE1) of the first subpixel (SPX1) can be electrically connected to the pixel circuit (PXC) of the first subpixel (SPX1) through the first anode contact hole (ANH1) of FIG. 8. The second pixel electrode (PXE2) of the second subpixel (SPX2) can be electrically connected to the pixel circuit (PXC) of the second subpixel (SPX2) through the second anode contact hole (ANH2) of FIG. 8. The third pixel electrode (PXE3) of the third subpixel (SPX3) can be electrically connected to the pixel circuit (PXC) of the third subpixel (SPX3) through the third anode contact hole (ANH3) of FIG. 8. The pixel circuits (PXC) of the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) can control the voltage applied to the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3), respectively.

[0210] In one embodiment, the patterns of the pixel electrode layer (PCDL) (e.g., pixel electrodes (PXE) and common electrode (CE)) may comprise the same conductive material. In one embodiment, the patterns of the pixel electrode layer (PCDL) may comprise a metal (e.g., at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and other metals, or an alloy thereof) and may have a single-layer or multi-layer structure. For example, the patterns of the pixel electrode layer (PCDL) may be low-resistance patterns formed of a three-layer structure (Ti / Al / Ti) of titanium (Ti), aluminum (Al), and titanium (Ti). Alternatively, the patterns of the pixel electrode layer (PCDL) may comprise other low-resistance materials (e.g., copper (Cu)) and / or structures. When the resistance of the patterns included in the pixel electrode layer (PCDL) is reduced or minimized, the first driving voltage (VDD) and the second driving voltage (VSS) can be stably transmitted to the light-emitting elements (LE) of the subpixels (SPX).

[0211] A reflective layer (RFL) may be disposed on the pixel electrode layer (PCDL). For example, a first reflective layer (RFL1) may be disposed on each pixel electrode (PXE), and a second reflective layer (RFL2) may be disposed on the common electrode (CE).

[0212] In one embodiment, the reflective layer (RFL) may be disposed directly on the pixel electrode layer (PCDL). For example, the first reflective layer (RFL1) may be disposed directly on the pixel electrode (PXE) and in contact with the pixel electrode (PXE), and the second reflective layer (RFL2) may be disposed directly on the common electrode (CE) and in contact with the common electrode (CE). However, the embodiments are not limited thereto. For example, at least one insulating layer (e.g., an organic insulating layer) and / or at least one conductive layer (e.g., a metal layer) may be disposed between the reflective layer (RFL) and the pixel electrode layer (PCDL).

[0213] The reflective layer (RFL) may include a material with high reflectivity to light emitted from the light-emitting element (LE). For example, as previously exemplified, the reflective layer (RFL) may include silver (Ag) or aluminum (Al), or other metals with high light reflectivity.

[0214] In one embodiment, the first reflective layer (RFL1) and the second reflective layer (RFL2) may be formed with an appropriate material, structure, and / or thickness, taking into account the light reflectance of the first reflective layer (RFL1) and the second reflective layer (RFL2), the conductivity and reliability of the first reflective layer (RFL1) and the second reflective layer (RFL2), etc. As an example, the first reflective layer (RFL1) and the second reflective layer (RFL2) may each be formed with a three-layer structure (ITO / Ag / ITO) of indium-tin oxide (ITO), silver (Ag), and indium-tin oxide (ITO). Accordingly, the light reflectance, conductivity, and reliability of the first reflective layer (RFL1) and the second reflective layer (RFL2) can be appropriately secured.

[0215] An eighth insulating layer (132) may be disposed on the pixel electrode layer (PCDL) and the reflective layer (RFL). The eighth insulating layer (132) may be an adhesive layer that temporarily fixes or adheres the light-emitting elements (LE) to prevent the light-emitting elements (LE) from tilting or falling over during the process of transferring the light-emitting elements (LE) to the display panel (100). For example, the eighth insulating layer (132) may be a film for temporarily adhering the light-emitting elements (LE) to each pixel electrode (PXE) and common electrode (CE). To facilitate temporary adhesion, the thickness of the eighth insulating layer (132) may be greater than the thickness of each pixel electrode (PXE) and common electrode (CE), and greater than the thickness of each of the first and second contact electrodes (CTE1, CTE2) of the light-emitting elements (LE). The eighth insulating layer (132) may also be referred to as an "adhesive layer."

[0216] The eighth insulating layer (132) may cover a portion of the first reflective layer (RFL1) and the second reflective layer (RFL2) below the light-emitting element (LE) and expose other portions of the first reflective layer (RFL1) and the second reflective layer (RFL2). For example, the eighth insulating layer (132) may cover a portion of the first reflective layer (RFL1) and the second reflective layer (RFL2) that overlaps with the light-emitting element (LE), and may be open at portions corresponding to the first connection hole (BH1) and the second connection hole (BH2) to expose a portion of the upper surface of the first reflective layer (RFL1) and the second reflective layer (RFL2).

[0217] Although FIG. 9 illustrates the eighth insulating layer (132) being disposed over the entire display area (DA) or subpixel area, embodiments are not limited thereto. For example, the eighth insulating layer (132) may be disposed only on a portion of the first reflective layer (RFL1) and the second reflective layer (RFL2) that overlap with the light-emitting elements (LE), while exposing other portions of the first reflective layer (RFL1) and the second reflective layer (RFL2). Alternatively, the eighth insulating layer (132) may be disposed separately on each of the subpixels (SPX). The eighth insulating layer (132) may not be disposed in the non-display area (NDA).

[0218] The eighth insulating layer (132) may include at least one insulating material, for example, an organic insulating material. For example, the eighth insulating layer (132) may be a photosensitive organic layer such as photoresist. Alternatively, the eighth insulating layer (132) may be formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0219] Although FIG. 9 illustrates that the eighth insulating layer (132) is arranged with a uniform thickness or height, the embodiments are not limited thereto. For example, the eighth insulating layer (132) may have a lower height than other parts in the portion where the light-emitting elements (LE) are placed. For example, the height or thickness of the eighth insulating layer (132) may be partially reduced as the eighth insulating layer (132) is pressed by pressure applied during the process of placing the light-emitting elements (LE) on the eighth insulating layer (132).

[0220] Light-emitting elements (LE) may be disposed on the eighth insulating layer (132). A first light-emitting element (LE1) may be disposed on the first pixel electrode (PXE1) and the common electrode (CE) of the first subpixel (SPX1). A second light-emitting element (LE2) may be disposed on the second pixel electrode (PXE2) and the common electrode (CE) of the second subpixel (SPX2). A third light-emitting element (LE3) may be disposed on the third pixel electrode (PXE3) and the common electrode (CE) of the third subpixel (SPX3).

[0221] In one embodiment, each of the light-emitting elements (LE) may be a micro LED comprising an inorganic material. For example, each of the light-emitting elements (LE) may be formed of an inorganic material such as gallium nitride (GaN), and the length of the first direction (DR1), the length of the second direction (DR2), and the length of the third direction (DR3) of each of the light-emitting elements (LE) may each be several μm to several hundred μm. For example, the length of the first direction (DR1), the length of the second direction (DR2), and the length of the third direction (DR3) of each of the light-emitting elements (LE) may each be approximately 100 μm or less.

[0222] Light-emitting elements (LE) can be formed by growing on a semiconductor substrate, such as a silicon substrate or a sapphire substrate. Light-emitting elements (LE) can be transferred directly from the semiconductor substrate onto the pixel electrodes (PXE) and common electrode (CE) of the display panel (100). Alternatively, light-emitting elements (LE) can be transferred onto the pixel electrodes (PXE) and common electrode (CE) of the display panel (100) via an electrostatic method using an electrostatic head or a stamping method using an elastic polymer material, such as PDMS or silicon, as a transfer substrate.

[0223] A light-emitting element (LE) may include a conductive layer (E1), a semiconductor stack (STC), first and second contact electrodes (CTE1, CTE2), and a protective film (PRL). The semiconductor stack (STC) may include a first semiconductor layer (SEM1), an active layer (MQW) (e.g., a light-emitting layer), and a second semiconductor layer (SEM2) arranged sequentially in a third direction (DR3). In one embodiment, the semiconductor stack (STC) may further include a third semiconductor layer (SEM3) arranged on the second semiconductor layer (SEM2).

[0224] A conductive layer (E1) may be disposed on the lower surface of the first semiconductor layer (SEM1). Although FIG. 10 illustrates that the conductive layer (E1) covers the entire lower surface of the first semiconductor layer (SEM1), the embodiments are not limited thereto. As an example, the conductive layer (E1) may be disposed on a part of the lower surface of the first semiconductor layer (SEM1). The conductive layer (E1) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or a transparent conductive material such as a metal oxide.

[0225] The first semiconductor layer (SEM1) can be placed on the conductive layer (E1). The first semiconductor layer (SEM1) may be made of a semiconductor material layer doped with a first conductive type dopant such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), etc., for example, gallium nitride (GaN).

[0226] An active layer (MQW) may be disposed on a first semiconductor layer (SEM1). The active layer (MQW) may include the same semiconductor material as the first semiconductor layer (SEM1) and the second semiconductor layer (SEM2). For example, if the first semiconductor layer (SEM1) and the second semiconductor layer (SEM2) include gallium nitride (GaN), the active layer (MQW) may also include gallium nitride (GaN). For example, the active layer (MQW) may include at least one of gallium nitride (GaN), indium gallium nitride (InGaN), and aluminum gallium nitride (AlGaN). The active layer (MQW) may emit light by the recombination of electron-hole pairs according to an electric signal applied through the first semiconductor layer (SEM1) and the second semiconductor layer (SEM2).

[0227] The active layer (MQW) may include a material having a single or multiple quantum well structure. When the active layer (MQW) includes a material having a multiple quantum well structure, it may have a structure in which multiple well layers and barrier layers are alternately stacked. In this case, the well layers may be formed of InGaN, and the barrier layers may be formed of GaN or AlGaN, but are not limited thereto. Alternatively, the active layer (MQW) may have a structure in which semiconductor materials with large band gap energy and semiconductor materials with small band gap energy are alternately stacked, or it may include different Group 3 to Group 5 semiconductor materials depending on the wavelength of the emitted light.

[0228] When the active layer (MQW) contains indium gallium nitride (InGaN), the color of the emitted light may vary depending on the indium (In) content. For example, as the indium (In) content increases, the wavelength band of the light emitted by the active layer (MQW) shifts toward the red wavelength band, and as the indium (In) content decreases, the wavelength band of the light emitted by the active layer (MQW) may shift toward the blue wavelength band.

[0229] The second semiconductor layer (SEM2) can be disposed on the active layer (MQW). The second semiconductor layer (SEM2) may be a semiconductor material layer doped with a second conductivity type dopant, such as silicon (Si), germanium (Ge), tin (Sn), etc., for example, gallium nitride (GaN).

[0230] A third semiconductor layer (SEM3) may be disposed on a second semiconductor layer (SEM2). The third semiconductor layer (SEM3) is a semiconductor material layer in which the n-type dopant is lower than a predetermined threshold value and may be referred to as an un-doped semiconductor layer. For example, the third semiconductor layer (SEM3) may be indium aluminum gallium nitride (InAlGaN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), or indium nitride (InN), in which the n-type dopant is lower than a predetermined threshold value.

[0231] An electron blocking layer may be placed between the first semiconductor layer (SEM1) and the active layer (MQW). The electron blocking layer may be a layer designed to suppress or prevent too many electrons from flowing into the active layer (MQW). For example, the electron blocking layer may be AlGaN or p-AlGaN doped with p-type Mg. The electron blocking layer may be omitted.

[0232] A superlattice layer may be disposed between the active layer (MQW) and the second semiconductor layer (SEM2). The superlattice layer may be a layer for relieving stress between the second semiconductor layer (SEM2) and the active layer (MQW). For example, the superlattice layer may be formed of InGaN or GaN. The superlattice layer may be omitted.

[0233] A protective film (PRL) may be disposed on the side of the first semiconductor layer (SEM1), the side of the active layer (MQW), and the side of the second semiconductor layer (SEM2). The protective film (PRL) may be a film for protecting the side of the light-emitting element (LE). The protective film (PRL) may be formed of an inorganic material, for example, silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), titanium oxide (TiOx), aluminum oxide (AlOx), or other inorganic insulating material.

[0234] In one embodiment, the protective film (PRL) is disposed on the sides of the first semiconductor layer (SEM1), the sides of the active layer (MQW), and the sides of the second semiconductor layer (SEM2) of the semiconductor stack (STC), and may not be disposed on the sides of the third semiconductor layer (SEM3), but the embodiments are not limited thereto. As an example, as illustrated in FIGS. 9 and 10, the protective film (PRL) may be disposed on the sides of the first semiconductor layer (SEM1), the sides of the active layer (MQW), the sides of the second semiconductor layer (SEM2), and the sides of the third semiconductor layer (SEM3) of the semiconductor stack (STC).

[0235] A hole (LEH) can be formed that penetrates the conductive layer (E1), the first semiconductor layer (SEM1), and the active layer (MQW) of the light-emitting element (LE) to expose the second semiconductor layer (SEM2). The hole (LEH) may have a circular planar shape, but the shape of the hole (LEH) is not limited thereto. For example, the hole (LEH) may have a polygonal planar shape such as an ellipse or a square.

[0236] A protective film (PRL) may be disposed on the sidewall of the conductive layer (E1) exposed in the hole (LEH), the sidewall of the first semiconductor layer (SEM1), and the sidewall of the active layer (MQW). The protective film (PRL) may not cover the second semiconductor layer (SEM2) in the hole (LEH). Accordingly, the second semiconductor layer (SEM2) may be exposed without being covered by the protective film (PRL).

[0237] The first contact electrode (CTE1) may be disposed on at least one side of the semiconductor stack (STC) and on at least one side of the conductive layer (E1) and on the lower surface. The first contact electrode (CTE1) may be disposed on the lower surface of the conductive layer (E1) that is exposed and not covered by a protective film (PRL). Therefore, the first contact electrode (CTE1) may be electrically connected to the conductive layer (E1).

[0238] The second contact electrode (CTE2) may be disposed on at least one side of the semiconductor stack (STC), at least one side of the conductive layer (E1), and on the lower surface. In this case, while the first contact electrode (CTE1) is disposed on the first side of the semiconductor stack (STC) and the first side of the conductive layer (E1), the second contact electrode (CTE2) may be disposed on the second side of the semiconductor stack (STC) and the second side of the conductive layer (E1).

[0239] The second contact electrode (CTE2) can be placed on a protective film (PRL) placed in the hole (LEH) and on a second semiconductor layer (SEM2) exposed in the hole (LEH) without being covered by the protective film (PRL). Therefore, the second contact electrode (CTE2) can be electrically connected to the second semiconductor layer (SEM2) in the hole (LEH).

[0240] FIGS. 9 and 10 illustrate that the first contact electrode (CTE1) and the second contact electrode (CTE2) of each of the light-emitting elements (LE) are disposed on the eighth insulating layer (132), but the embodiments are not limited thereto. In one example, the eighth insulating layer (132) may be disposed on the lower surface and part of the side of the first contact electrode (CTE1) of each of the light-emitting elements (LE) and on the lower surface and part of the side of the second contact electrode (CTE2). Alternatively, the eighth insulating layer (132) may be disposed on the sides of the conductive layer (E1) of each of the light-emitting elements (LE). Alternatively, the eighth insulating layer (132) may be disposed on the sides of the first semiconductor layer (SEM1), the sides of the active layer (MQW), and the sides of the second semiconductor layer (SEM2) of each of the light-emitting elements (LE). In this case, the eighth insulating layer (132) may be disposed on a part of each of the sides of the second semiconductor layer (SEM2).

[0241] In one embodiment, the first contact electrode (CTE1) and the second contact electrode (CTE2) may each be placed on three sides of the semiconductor stack (STC). For example, if the semiconductor stack (STC) includes first to fourth sides, the first contact electrode (CTE1) may be placed on the first side, the second side, and the third side, and the second contact electrode (CTE2) may be placed on the second side, the third side, and the fourth side.

[0242] Each of the first contact electrode (CTE1) and the second contact electrode (CTE2) may include at least one conductive material, for example, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). In one embodiment, the first contact electrode (CTE1) and the second contact electrode (CTE2) may be formed with a two-layer structure of chromium (Cr) and gold (Au) (Cr / Au), a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti) (Ti / Al / Ti), or a three-layer structure of indium-tin oxide (ITO), silver (Ag), and indium-tin oxide (ITO) (ITO / Ag / ITO) to increase reflectivity.

[0243] When the first contact electrode (CTE1) and the second contact electrode (CTE2) are each formed of a metal with high reflectivity, light emitted from the active layer (MQW) of the light-emitting element (LE) that travels in the lateral direction of the light-emitting element (LE) can be reflected by the first contact electrode (CTE1) and the second contact electrode (CTE2) and emitted to the upper surface of the light-emitting element (LE). Therefore, since the loss of light from the light-emitting element (LE) can be reduced, the light efficiency of the light-emitting element (LE) can be increased. To increase the light efficiency of the light-emitting element (LE), the first contact electrode (CTE1) and the second contact electrode (CTE2) can be arranged to cover most of the side of the semiconductor stack (STC).

[0244] The first contact electrode (CTE1) can be in contact with the first connecting electrode (BE1) on the first reflective layer (RFL1). The second contact electrode (CTE2) can be in contact with the second connecting electrode (BE2) on the second reflective layer (RFL2).

[0245] The first connecting electrode (BE1) and the second connecting electrode (BE2) can be placed on the eighth insulating layer (132).

[0246] The first connecting electrode (BE1) connects the first contact electrode (CTE1) of the light-emitting element (LE) and the pixel electrode (PXE). For example, the first connecting electrode (BE1) of the first sub-pixel (SPX1) can connect the first contact electrode (CTE1) of the first light-emitting element (LE1) and the first pixel electrode (PXE1). The first connecting electrode (BE1) of the second sub-pixel (SPX2) can connect the first contact electrode (CTE1) of the second light-emitting element (LE2) and the second pixel electrode (PXE2). The first connecting electrode (BE1) of the third sub-pixel (SPX3) can connect the first contact electrode (CTE1) of the third light-emitting element (LE3) and the third pixel electrode (PXE3).

[0247] In one embodiment, the first connecting electrode (BE1) may contact the light-emitting element (LE) on a portion of the first reflective layer (RFL1) and the eighth insulating layer (132), and may contact the first reflective layer (RFL1) on another portion of the first reflective layer (RFL1). For example, the first connecting electrode (BE1) may contact and / or be connected to the first reflective layer (RFL1) through a first connecting hole (BH1) penetrating the eighth insulating layer (132), and may be electrically connected to each pixel electrode (PXE) through the first reflective layer (RFL1). In another embodiment, if the eighth insulating layer (132) is placed only on a portion of the first reflective layer (RFL1) that overlaps with the light-emitting element (LE), the first connecting hole (BH1) may be unnecessary. For example, the first connecting electrode (BE1) may be placed directly on the first reflective layer (RFL1) (or pixel electrode (PXE)) exposed around the light-emitting element (LE).

[0248] The second connecting electrode (BE2) connects the second contact electrode (CTE2) of the light-emitting element (LE) to the common electrode (CE). For example, the second connecting electrode (BE2) of the first subpixel (SPX1) can connect the second contact electrode (CTE2) of the first light-emitting element (LE1) to the common electrode (CE). The second connecting electrode (BE2) of the second subpixel (SPX2) can connect the second contact electrode (CTE2) of the second light-emitting element (LE2) to the common electrode (CE). The second connecting electrode (BE2) of the third subpixel (SPX3) can connect the second contact electrode (CTE2) of the third light-emitting element (LE3) to the common electrode (CE).

[0249] In one embodiment, the second connecting electrode (BE2) may contact the light-emitting element (LE) on a portion of the second reflective layer (RFL2) and the eighth insulating layer (132), and may contact the second reflective layer (RFL2) on another portion of the second reflective layer (RFL2). For example, the second connecting electrode (BE2) may contact and / or be connected to the second reflective layer (RFL2) through a second connecting hole (BH2) penetrating the eighth insulating layer (132), and may be electrically connected to the common electrode (CE) through the second reflective layer (RFL2). In another embodiment, if the eighth insulating layer (132) is placed only on a portion of the second reflective layer (RFL2) that overlaps with the light-emitting element (LE), the second connecting hole (BH2) may be unnecessary. For example, the second connecting electrode (BE2) may be placed directly on the second reflective layer (RFL2) (or common electrode (CE)) exposed around the light-emitting element (LE).

[0250] Each of the first connecting electrode (BE1) and the second connecting electrode (BE2) may comprise at least one conductive material, for example, any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, each of the first connecting electrode (BE1) and the second connecting electrode (BE2) may be made of a transparent conductive material (for example, transparent conductive oxide (TCO)), such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0251] The conductive layer (E1) of the light-emitting element (LE) is in contact with and / or connected to a first contact electrode (CTE1) and can be electrically connected to a first connecting electrode (BE1) through the first contact electrode (CTE1). The second semiconductor layer (SEM2) of the light-emitting element (LE) is in contact with and / or connected to a second contact electrode (CTE2) formed in a hole (LEH) and can be electrically connected to a second connecting electrode (BE2) through the second contact electrode (CTE2).

[0252] The ninth insulating layer (134) may be disposed on the eighth insulating layer (132). In one embodiment, the ninth insulating layer (134) may be formed to a height less than or equal to the height of the light-emitting elements (LE) so as to partially or entirely cover the sides of the light-emitting elements (LE). The upper surface of each of the light-emitting elements (LE) may be exposed and not covered by the ninth insulating layer (134).

[0253] Additionally, the ninth insulating layer (134) may cover at least a portion of the first and second connecting electrodes (BE1, BE2). For example, as shown in FIG. 9, the ninth insulating layer (134) may be formed to a height greater than the maximum height of the first and second connecting electrodes (BE1, BE2) to completely cover the first and second connecting electrodes (BE1, BE2), but embodiments are not limited thereto.

[0254] The ninth insulating layer (134) may include at least one insulating material, for example, an organic insulating material. For example, the ninth insulating layer (134) may be formed of an organic insulating layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. The ninth insulating layer (134) may be formed as a single layer or a multilayer. The ninth insulating layer (134) may flatten the step caused by the light-emitting elements (LE).

[0255] The first capping layer (136) may be disposed on the light-emitting elements (LE) and the ninth insulating layer (134). The first capping layer (136) may include at least one insulating material, for example, an inorganic insulating material.

[0256] An optical layer (140) may be disposed on the first capping layer (136). The optical layer (140) may include a light-transmitting layer (TPL) disposed in the light-emitting regions (EA) of the subpixels (SPX), a light-blocking layer (BM) disposed in the non-light-emitting region (NEA) surrounding the light-emitting regions (EA) of the subpixels (SPX), and color filters corresponding to the light-emitting color of each of the subpixels (SPX) (for example, first, second, and third color filters (CF1, CF2, CF3)).

[0257] FIG. 9 illustrates a structure in which a light-blocking layer (BM), a second capping layer (142), and a reflective film (RF) are disposed on a first capping layer (136), and a light-transmitting layer (TPL) and a third capping layer (144) are disposed on the second capping layer (142) and the reflective film (RF), but the embodiments are not limited thereto. For example, the arrangement order and / or shape of the light-blocking layer (BM), the reflective film (RF), and the light-transmitting layer (TPL), etc., may be varied according to the embodiments.

[0258] A light-blocking layer (BM) may be disposed on the first capping layer (136). The light-blocking layer (BM) may separate the light-emitting region (EA) and the non-light-emitting region (NEA). The light-blocking layer (BM) may include a light-blocking material such as an inorganic black pigment, such as carbon black, or an organic black pigment. The light-blocking layer (BM) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin, but is not limited thereto.

[0259] The second capping layer (142) may be disposed on the first capping layer (136) and the light-blocking layer (BM). The second capping layer (142) may include at least one insulating material, for example, an inorganic insulating material.

[0260] A reflective film (RF) may be placed on a light-blocking layer (BM). For example, the reflective film (RF) may be placed on a portion of a second capping layer (142) covering the side of the light-blocking layer (BM). The reflective film (RF) may reflect light traveling laterally from the light-transmitting layer (TPL). The reflective film (RF) may include a material with high light reflectivity, for example, a metal such as aluminum (Al). Alternatively, the reflective film (RF) may consist of inorganic films having different refractive indices that are alternately arranged (for example, silicon nitride (SiN2)). x ), silicon nitride oxide (SiON), silicon oxide (SiO x ), titanium oxide (TiO₂) x ), or aluminum oxide (AlO x It may also be formed as a dispersed Bragg reflector including )).

[0261] A light-transmitting layer (TPL) may be placed in each light-emitting region (EA) and surrounded by a light-blocking layer (BM). In one embodiment, the light-transmitting layer (TPL) may comprise a substantially transparent organic material. For example, the light-transmitting layer (TPL) may be a light-transmitting organic film comprising an epoxy resin, an acrylic resin, a cardo resin, or an imide resin.

[0262] In one embodiment, a light-emitting element (LE) emits light of a color corresponding to the light-emitting color of each subpixel (SPX), and a light-transmitting layer (TPL) can transmit the light emitted from the light-emitting element (LE). When subpixels (SPX) include light-emitting elements (LE) that emit light corresponding to each light-emitting color, the light emitted from the light-emitting elements (LE) can be utilized more efficiently. For example, a decrease in the light efficiency of subpixels (SPX) due to light conversion can be prevented. In addition, the color purity of the light emitted from subpixels (SPX) can be increased, and the color reproduction rate of subpixels (SPX) can be increased.

[0263] In another embodiment, a light-emitting element (LE) of at least one subpixel (SPX) emits light of a color different from the light-emitting color of the subpixel (SPX), and a wavelength conversion layer including wavelength conversion particles may be disposed on the light-emitting element (LE) of the at least one subpixel (SPX). In one embodiment, the wavelength conversion layer may include a base resin made of a light-transmitting layer (TPL) and wavelength conversion particles (e.g., quantum dots, quantum rods, fluorescent materials, or phosphorescent materials) dispersed within the light-transmitting layer (TPL). The wavelength conversion layer may convert light emitted from the light-emitting element (LE) of the subpixel (SPX) into light of a different color. For example, if the first light-emitting element (LE1) emits blue light and the first subpixel (SPX1) is a red subpixel that emits red light, a wavelength conversion layer including wavelength conversion particles that convert blue light into red light may be disposed on the first light-emitting element (LE1). If the subpixels (SPX) include light-emitting elements (LE) that emit light of the same color, the manufacturing efficiency of the light-emitting element layer (130) and the display panel (100) including it can be increased and the manufacturing cost reduced.

[0264] A third capping layer (144) may be disposed on the second capping layer (142) and the light-transmitting layer (TPL). The third capping layer (144) may include at least one insulating material, for example, an inorganic insulating material.

[0265] A first overcoat layer (146) may be disposed on the third capping layer (144). In one embodiment, the first overcoat layer (146) comprises a transparent organic material (e.g., acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin), and the upper surface of the first overcoat layer (146) may be substantially flat. However, the embodiments are not limited thereto. For example, the first overcoat layer (146) may be an inorganic layer comprising an inorganic material, and the first overcoat layer (146) may be formed with a sufficient thickness to include a substantially flat upper surface or may be flattened through a separate flattening process. Accordingly, the upper surface of the first overcoat layer (146) may be substantially flat.

[0266] Color filters of subpixels (SPX) may be disposed on the first overcoat layer (146). In the light-emitting region (EA) of each subpixel (SPX), a color filter that selectively transmits light corresponding to a color (or wavelength) corresponding to the light-emitting color of the subpixel (SPX) may be disposed. For example, a first color filter (CF1) that selectively transmits light of a first color may be disposed in the light-emitting region (EA) of the first subpixel (SPX1). In one embodiment, the color filters of the subpixels (SPX) may be disposed to overlap each other in the non-light-emitting region (NEA) to form a light-blocking pattern. For example, the first color filter (CF1), the second color filter (CF2), and the third color filter (CF3) disposed in the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3), respectively, may overlap each other in the non-light-emitting region (NEA). The second color filter (CF2) can selectively transmit light of the second color corresponding to the light emission color of the second subpixel (SPX2), and the third color filter (CF3) can selectively transmit light of the third color corresponding to the light emission color of the third subpixel (SPX3).

[0267] A second overcoat layer (148) may be disposed on the first color filter (CF1), the second color filter (CF2), and the third color filter (CF3). In one embodiment, the second overcoat layer (148) may include a light-transmitting organic material, and the upper surface of the second overcoat layer (148) may be substantially flat. However, the embodiments are not limited thereto. For example, the second overcoat layer (148) may be an inorganic layer including an inorganic material, and the second overcoat layer (148) may be formed with a sufficient thickness to include a substantially flat upper surface, or may be flattened through a separate flattening process. Accordingly, the upper surface of the second overcoat layer (148) may be substantially flat.

[0268] As described above, in the embodiments, a reflective layer (RFL) may be disposed below the light-emitting element (LE) of each subpixel (SPX). For example, a first reflective layer (RFL1) and a second reflective layer (RFL2) may be disposed on the pixel electrode (PXE) and the common electrode (CE) of each subpixel (SPX), overlapping with different parts of the light-emitting element (LE).

[0269] According to the embodiments, the reflectance of light emitted from the light-emitting element (LE) can be increased and the light efficiency of the subpixel (SPX) can be improved. For example, among the light emitted from the light-emitting element (LE), light traveling downward toward the first reflective layer (RFL1) and the second reflective layer (RFL2) is reflected by the first reflective layer (RFL1) and the second reflective layer (RFL2) toward the upper direction of the subpixel (SPX) (for example, the front direction of the display panel (100)), thereby increasing the amount of light emitted from the subpixel (SPX) and increasing the brightness of the subpixel (SPX). Accordingly, the light efficiency of the subpixels (SPX) and the display device (1) including them can be improved.

[0270] FIG. 11 is a plan view showing a display panel according to one embodiment. FIG. 12 is a cross-sectional view showing a display panel according to one embodiment. For example, FIG. 12 shows one embodiment of a cross-section of a portion of a display panel (100) corresponding to the line X2-X2' of FIG. 11. Compared to FIG. 8 and FIG. 9, FIG. 11 and FIG. 12 show different embodiments of a reflective layer (RFL).

[0271] Referring to FIGS. 11 and 12, a reflective layer (RFL) can completely cover the pixel electrode (PXE) and the common electrode (CE) of each of the subpixels (SPX). For example, a first reflective layer (RFL1) can completely cover the pixel electrode (PXE), and a second reflective layer (RFL2) can completely cover the common electrode (CE). As an example, the first reflective layer (RFL1) can completely cover the top surface and the side surface of the pixel electrode (PXE), including the end where the side surface of the pixel electrode (PXE) is located. Additionally, the second reflective layer (RFL2) can completely cover the top surface and the side surface of the common electrode (CE), including the end where the side surface of the common electrode (CE) is located.

[0272] According to the above-described embodiment, the reliability of the display device (1) can be improved by preventing damage to the pixel electrodes (PXE) and the common electrode (CE). For example, by forming a reflective layer (RFL) to completely cover the pixel electrodes (PXE) and the common electrode (CE), the pixel electrodes (PXE) and the common electrode (CE) can be prevented from being exposed to the etching solution during the process of forming the reflective layer (RFL). For example, while an etching process of the conductive film is performed after the conductive film for forming the reflective layer (RFL) is deposited (for example, an etching process to pattern the conductive film into a first reflective layer (RFL1) and a second reflective layer (RFL2)), the pixel electrodes (PXE) and the common electrode (CE) may be completely covered by the conductive film (or the first reflective layer (RFL1) and the second reflective layer (RFL2)). Accordingly, the conductive film, or the first reflective layer (RFL1) and the second reflective layer (RFL2) formed from the conductive film, also function as capping layers that protect the pixel electrodes (PXE) and the common electrode (CE), and can prevent damage to the pixel electrodes (PXE) and the common electrode (CE) during the formation process of the reflective layer (RFL) or subsequent processes. For example, even if the pixel electrodes (PXE) and the common electrode (CE) are each formed with a three-layer structure (Ti / Al / Ti) of titanium (Ti), aluminum (Al), and titanium (Ti), the pixel electrodes (PXE) and the common electrode (CE) are not exposed to the etching solution during the etching process to form the reflective layer (RFL). Therefore, titanium tips (e.g., titanium tips that occur in the form of titanium (Ti) protruding as aluminum (Al) is consumed by the etching solution at the ends (e.g., sides) of the pixel electrodes (PXE) and the common electrode (CE)) or voids caused by the difference in etching rates between titanium (Ti) and aluminum (Al) may not occur. Accordingly, the reliability of the subpixels (SPX) and the display device (1) including them can be improved.

[0273] In one embodiment, the reflective layer (RFL) may also be placed in the non-display area (NDA). For example, the second reflective layer (RFL2) may extend into the non-display area (NDA) and cover the first wiring layer (BLI1) of the power bus line (BLI). Accordingly, the power bus line (BLI) can be properly protected during the process of forming the reflective layer (RFL), and the reliability of the display device (1) can be increased. In one embodiment, a portion of the second reflective layer (RFL2) covering the first wiring layer (BLI1) may form one of the wiring layers included in the power bus line (BLI) (for example, the fourth wiring layer (BLI4) of FIG. 16).

[0274] FIG. 13 is a plan view showing a display panel according to one embodiment. FIG. 14 is a cross-sectional view showing a display panel according to one embodiment. For example, FIG. 14 shows one embodiment of a cross-section of a portion of a display panel (100) corresponding to the line X3-X3' of FIG. 13. Compared to FIG. 11 and FIG. 12, FIG. 13 and FIG. 14 show different embodiments of a reflective layer (RFL).

[0275] Referring to FIGS. 13 and 14, the reflective layer (RFL) may cover the ends of the pixel electrode (PXE) and the common electrode (CE) of each sub-pixel (SPX), but may not cover a portion of the upper surface of the pixel electrode (PXE) and the common electrode (CE). For example, the first reflective layer (RFL1) and the second reflective layer (RFL2) may be open in a portion that does not overlap with the light-emitting element (LE), thereby exposing a portion of the upper surface of the pixel electrode (PXE) and a portion of the upper surface of the common electrode (CE), respectively. As an example, the first reflective layer (RFL1) may be open in the area where the first connection hole (BH1) is located and around it, and the second reflective layer (RFL2) may be open in the area where the second connection hole (BH2) is located and around it.

[0276] The first connecting electrode (BE1) may contact the pixel electrode (PXE) in the part where the first reflective layer (RFL1) is open, and the second connecting electrode (BE2) may contact the common electrode (CE) in the part where the second reflective layer (RFL2) is open. For example, in the area corresponding to the first connecting hole (BH1) (for example, inside the first connecting hole (BH1)), the first connecting electrode (BE1) may directly contact and / or be connected to the pixel electrode (PXE), and in the area corresponding to the second connecting hole (BH2) (for example, inside the second connecting hole (BH2)), the second connecting electrode (BE2) may directly contact and / or be connected to the common electrode (CE). By directly connecting the first connecting electrode (BE1) and the second connecting electrode (BE2) to the pixel electrode (PXE) and the common electrode (CE), respectively, the contact resistance between the first connecting electrode (BE1) and the pixel electrode (PXE), and the contact resistance between the second connecting electrode (BE2) and the common electrode (CE) can be reduced. Accordingly, the quality of contact between the first connecting electrode (BE1) and the pixel electrode (PXE), and the quality of contact between the second connecting electrode (BE2) and the common electrode (CE) can be improved.

[0277] In addition, according to the above-described embodiment, the first reflective layer (RFL1) and the second reflective layer (RFL2) can appropriately cover the ends, including the sides of the pixel electrode (PXE) and the common electrode (CE). Accordingly, during an etching process for forming the first reflective layer (RFL1) and the second reflective layer (RFL2), the ends of the pixel electrode (PXE) and the common electrode (CE) can be covered and protected by a conductive film for forming the first reflective layer (RFL1) and the second reflective layer (RFL2), or by the first reflective layer (RFL1) and the second reflective layer (RFL2) formed from said conductive film, thereby preventing exposure to the etching solution. Accordingly, damage to the pixel electrodes (PXE) and the common electrode (CE) during the process of forming the reflective layer (RFL) or subsequent processes can be prevented, and the reliability of the subpixels (SPX) and the display device (1) including them can be improved.

[0278] FIG. 15 is a cross-sectional view showing a power bus line according to one embodiment. For example, FIG. 15 shows an example of a cross-sectional view of a portion of the power bus line (BLI) illustrated in FIG. 6 to 8.

[0279] Referring to FIG. 15 in addition to FIG. 6 to 8, the power bus line (BLI) may include a first wiring layer (BLI1) and a second wiring layer (BLI2). In one embodiment, the power bus line (BLI) may further include a third wiring layer (BLI3).

[0280] The first wiring layer (BLI1) may extend from the common electrode (CE). For example, the first wiring layer (BLI1) may be formed with a three-layer structure (Ti / Al / Ti) of titanium (Ti), aluminum (Al), and titanium (Ti), and the first wiring layer (BLI1) and the common electrode (CE) may be formed integrally.

[0281] A second wiring layer (BLI2) may be disposed between a first wiring layer (BLI1) and a third wiring layer (BLI3). For example, the second wiring layer (BLI2) may be disposed on a seventh insulating layer (128) in a non-display area (NDA) and may be in contact with and / or connected to the first wiring layer (BLI1) immediately below the first wiring layer (BLI1).

[0282] The seventh insulating layer (128) may be opened to expose a portion of the third wiring layer (BLI3). For example, the seventh insulating layer (128) may cover one end of the third wiring layer (BLI3) and expose another portion of the third wiring layer (BLI3). At the portion where the seventh insulating layer (128) is opened, the second wiring layer (BLI2) and the third wiring layer (BLI3) may come into contact and / or be connected.

[0283] In one embodiment, the second wiring layer (BLI2) may include a material suitable for protecting the third wiring layer (BLI3) during the formation process of the first wiring layer (BLI1). For example, the first wiring layer (BLI1) and the third wiring layer (BLI3) may each be formed with a three-layer structure (Ti / Al / Ti) of titanium (Ti), aluminum (Al), and titanium (Ti), and the second wiring layer (BLI2) may include a transparent conductive oxide such as indium-tin oxide (ITO).

[0284] The third wiring layer (BLI3) may be formed as a pattern of at least one conductive layer included in the backplane layer (120). For example, the third wiring layer (BLI3) may be formed as a pattern of a second source-drain conductive layer (SCDL2) disposed on the sixth insulating layer (127) and may include a low-resistance material.

[0285] As in the above-described embodiment, by forming the power bus line (BLI) in multiple layers, the resistance of the power bus line (BLI) can be lowered. Accordingly, the second driving voltage (VSS) can be stably transmitted to the subpixels (SPX) of the display area (DA).

[0286] FIG. 16 is a cross-sectional view showing a power bus line according to one embodiment. For example, FIG. 16 shows an example of a cross-sectional view of a portion of the power bus line (BLI) shown in FIG. 11 and FIG. 13.

[0287] Referring to FIG. 16 in addition to FIG. 11 to 15, the power bus line (BLI) may further include a fourth wiring layer (BLI4) extending from a second reflective layer (RFL2). For example, the fourth wiring layer (BLI4) may be formed with a three-layer structure (ITO / Ag / ITO) of indium-tin oxide (ITO), silver (Ag), and indium-tin oxide (ITO), and the fourth wiring layer (BLI4) and the second reflective layer (RFL2) may be formed integrally.

[0288] A fourth wiring layer (BLI4) may be disposed on a first wiring layer (BLI1). For example, the fourth wiring layer (BLI4) may be disposed directly above the first wiring layer (BLI1) in a non-display area (NDA) and may be in contact with and / or connected to the first wiring layer (BLI1). The fourth wiring layer (BLI4) may cover an end of the first wiring layer (BLI1) to protect the first wiring layer (BLI1). For example, the fourth wiring layer (BLI4) may completely cover the first wiring layer (BLI1).

[0289] As described above, a subpixel (SPX) of a display device (1) according to the embodiments may include a reflective layer (RFL) disposed below a light-emitting element (LE). For example, the subpixel (SPX) may include a pixel electrode (PXE) and a common electrode (CE) formed by patterns of a pixel electrode layer (PCDL) and spaced apart from each other, a first reflective layer (RFL1) and a second reflective layer (RFL2) formed by patterns of a reflective layer (RFL) and disposed on the pixel electrode (PXE) and the common electrode (CE), respectively, and a light-emitting element (LE) disposed on the first reflective layer (RFL1) and the second reflective layer (RFL2). Accordingly, the light efficiency of the subpixel (SPX) and the display device (1) (or electronic device) including the same can be improved.

[0290] In another embodiment, when the light-emitting element (LE) of the subpixel (SPX) is a vertical type light-emitting element (e.g., a vertical type micro LED), the patterns of the pixel electrode layer (PCDL) include pixel electrodes (PXE), and a common electrode (CE) may be disposed on the light-emitting elements (LE) placed on the pixel electrodes (PXE) (e.g., disposed across the entire surface in the form of a common layer). In this case, by sequentially disposing of a reflective layer (RFL) (e.g., a first reflective layer (RFL1)), a light-emitting element (LE), and a common electrode (CE) on top of each of the pixel electrodes (PXE), the light efficiency of the subpixel (SPX) and the display device (1) including it can be improved.

[0291] In some embodiments, the reflective layer (RFL) can cover the end of the pixel electrode layer (PCDL) to protect the pixel electrode layer (PCDL). For example, the first reflective layer (RFL1) can cover the end of the pixel electrode (PXE), and the second reflective layer (RFL2) can cover the end of the common electrode (CE). Accordingly, damage to the pixel electrode (PXE) and the common electrode (CE) can be prevented, and the reliability of the display device (1) (or electronic device) can be ensured or improved.

[0292] A display device (1) according to at least one of the embodiments described above may be applied to various electronic devices. An electronic device according to one embodiment may include the display device (1) described above (or a display module including a display panel (100) according to at least one embodiment), and may further include a module or device having additional functions other than the display device (1).

[0293] FIG. 17 is a block diagram of an electronic device according to one embodiment. Referring to FIG. 17, an electronic device (10) according to one embodiment may include a display module (11), a processor (12), a memory (13), and a power module (14).

[0294] The electronic device (10) can output various information in the form of an image through the display module (11). For example, when the processor (12) executes an application stored in memory (13), the image information provided by the application can be provided to the user through the display module (11).

[0295] The display module (11) may include a display panel (100) for displaying an image. For example, the display module (11) may include a display panel (100) according to at least one of the embodiments described above.

[0296] The processor (12) may include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0297] The memory (15) may store data information necessary for the operation of the processor (12) or the display module (11). For example, the memory (15) may store image data signals and / or input control signals.

[0298] The processor (12) can control the display module (11) using information stored in the memory (15). The processor (12) can transmit video data signals and / or input control signals stored in the memory (15) to the display module (11). For example, when the processor (12) executes an application stored in the memory (15), video data signals and / or input control signals are transmitted to the display module (11), and the display module (11) can process the received signals and output video information through a display screen.

[0299] The power module (14) may include a power supply module, such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate power necessary for the operation of the electronic device (10).

[0300] At least one of each component of the electronic device (10) described above may be included in the display device (1) according to the embodiments described above. Additionally, some of the individual modules functionally included in one module may be included in the display device (1), while others may be provided separately from the display device (1). For example, the display device (1) may include a display module (11), and the processor (12), memory (13), and power module (14) may be provided in the form of other devices within the electronic device (10) other than the display device (1).

[0301] FIG. 18 is a schematic diagram of an electronic device according to various embodiments.

[0302] Referring to FIG. 18, various electronic devices to which the display device (1) according to the embodiments is applied may include not only image display electronic devices such as a smartphone (10_1a), tablet PC (10_1b), laptop (10_1c), TV (10_1d), and desk monitor (10_1e), but also wearable electronic devices including display modules such as smart glasses (10_2a), head-mounted display (10_2b), and smart watch (10_2c), and automotive electronic devices (10_3) including display modules such as a CID (Center Information Display) and room mirror display placed on the instrument panel, center fascia, and dashboard of a car.

[0303] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims

1. Pixel electrodes and a common electrode spaced apart from each other on a substrate; A first reflective layer and a second reflective layer separated from each other and disposed on the pixel electrode and the common electrode, respectively; and A display device comprising a light-emitting element disposed on the first reflective layer and the second reflective layer and electrically connected between the pixel electrode and the common electrode.

2. In Paragraph 1, A display device wherein the first reflective layer is disposed on a portion of the pixel electrode including an end portion overlapping with the light-emitting element and exposing another portion of the pixel electrode.

3. In Paragraph 2, A display device wherein the second reflective layer overlaps with the light-emitting element and is disposed on a portion of the common electrode including an end adjacent to the pixel electrode, and exposes another portion of the common electrode.

4. In Paragraph 3, The first reflective layer covers the side of the pixel electrode on a part of the pixel electrode, and A display device in which the second reflective layer covers the side of the common electrode on a part of the common electrode.

5. In Paragraph 2, A display device in which the first reflective layer has a width greater than the width of the pixel electrode in a first direction in which one end of the pixel electrode facing the common electrode is extended and covers the one end of the pixel electrode, and has a length shorter than the length of the pixel electrode in a second direction different from the first direction and exposes the other end of the pixel electrode.

6. In Paragraph 5, A display device in which the first reflective layer and the second reflective layer are symmetrical to each other with respect to the light-emitting element.

7. In Paragraph 1, The first reflective layer covers the end of the pixel electrode, including the side of the pixel electrode, and A display device in which the second reflective layer covers the end of the common electrode, including the side of the common electrode.

8. In Paragraph 7, The first reflective layer covers the entire pixel electrode, and The above second reflective layer is a display device that covers the common electrode entirely.

9. In Paragraph 7, The first reflective layer is opened in a portion that does not overlap with the light-emitting element to expose a portion of the upper surface of the pixel electrode, and A display device in which the second reflective layer is opened in a portion that does not overlap with the light-emitting element to expose a portion of the upper surface of the common electrode.

10. In Paragraph 1, An adhesive layer disposed below the light-emitting element, covering a portion of the first reflective layer and a portion of the second reflective layer that overlaps with the light-emitting element; A first connecting electrode disposed on the adhesive layer and connecting the pixel electrode or the first reflective layer and the light-emitting element; and A display device comprising a second connecting electrode disposed on the adhesive layer and connecting the common electrode or the second reflective layer and the light-emitting element.

11. In Paragraph 10, The first connecting electrode contacts the light-emitting element on the part of the first reflective layer and the adhesive layer, and contacts the first reflective layer on another part of the first reflective layer. A display device wherein the second connecting electrode contacts the light-emitting element on the part of the second reflective layer and the adhesive layer, and contacts the second reflective layer on the other part of the second reflective layer.

12. In Paragraph 10, The first reflective layer and the second reflective layer are each opened to expose a portion of the upper surface of the pixel electrode and the common electrode, and The first connecting electrode above contacts the pixel electrode at the portion where the first reflective layer is opened, and A display device in which the second connecting electrode contacts the common electrode at the portion where the second reflective layer is opened.

13. In Paragraph 10, The above light-emitting element is, A semiconductor stack disposed on the adhesive layer above; A first contact electrode disposed on at least one side of the semiconductor stack and in contact with the first connecting electrode on the first reflective layer; and A display device comprising a second contact electrode disposed on at least one side of the semiconductor stack and in contact with the second connecting electrode on the second reflective layer.

14. In Paragraph 1, A display device further comprising a power bus line electrically connected to the common electrode and including a wiring layer extending from the common electrode.

15. In Paragraph 14, A display device in which the second reflective layer extends into an area where the power bus line is arranged and covers the wiring layer.

16. Display module including a display panel; A memory for storing video data signals or input control signals; and It includes a processor that transmits an image data signal or an input control signal stored in the memory to the display module, The above display panel is, Pixel electrodes and a common electrode spaced apart from each other on a substrate; A first reflective layer and a second reflective layer separated from each other and disposed on the pixel electrode and the common electrode, respectively; and An electronic device comprising a light-emitting element disposed on the first reflective layer and the second reflective layer and electrically connected between the pixel electrode and the common electrode.

17. In Paragraph 16, The first reflective layer is disposed on a portion of the pixel electrode including an end portion that overlaps with the light-emitting element, and exposes another portion of the pixel electrode, and An electronic device in which the second reflective layer overlaps with the light-emitting element and is disposed on a portion of the common electrode including an end adjacent to the pixel electrode, and exposes another portion of the common electrode.

18. In Paragraph 16, The first reflective layer covers the end of the pixel electrode, including the side of the pixel electrode, and The electronic device, wherein the second reflective layer covers the end of the common electrode, including the side of the common electrode.

19. In Paragraph 18, The first reflective layer covers the entire pixel electrode, and The above second reflective layer is an electronic device that covers the common electrode entirely.

20. In Paragraph 18, The first reflective layer is opened in a portion that does not overlap with the light-emitting element to expose a portion of the upper surface of the pixel electrode, and An electronic device in which the second reflective layer is opened in a portion that does not overlap with the light-emitting element to expose a portion of the upper surface of the common electrode.

Images