Display device, electronic device, and method for manufacturing display device

Abstract

This display device comprises: a pixel electrode and a common electrode; an insulating layer disposed on one portion of the pixel electrode and the common electrode; a light-emitting element, which is disposed on the insulating layer and includes a semiconductor stack and first and second contact electrodes on a side portion of the semiconductor stack; a first connection electrode, which is disposed on a first side portion of the light-emitting element including the first contact electrode and on the insulating layer and connects the first contact electrode and the pixel electrode; a second connection electrode, which is disposed on a second side portion of the light-emitting element including the second contact electrode and on the insulating layer and connects the second contact electrode and the common electrode; and a first pattern and a second pattern encompassing the first side portion and the second side portion, respectively, on the first connection electrode and the second connection electrode.

Description

Display device and electronic device, and method of manufacturing a display device

[0001] Embodiments of the present invention relate to a display device capable of displaying an image, an electronic device, and a method for manufacturing a display device.

[0002] As the information society develops, the demand for display devices and electronic devices capable of displaying images is increasing in various forms. Accordingly, various types of display devices and electronic devices containing pixels for displaying images are being developed. Display devices may be provided independently or integrated into electronic devices to be used as the display screen of the electronic device.

[0003] The problem that the present invention aims to solve is to provide a display device, an electronic device, and a method for manufacturing a display device that can prevent short circuit defects and improve light efficiency.

[0004] The problems of the present invention are not limited to the technical problems mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below.

[0005] A display device according to one embodiment may include: a pixel electrode and a common electrode disposed on a substrate; an insulating layer disposed on a portion of the pixel electrode and the common electrode; a light-emitting element disposed on the insulating layer and including a first contact electrode and a second contact electrode disposed on a semiconductor stack and a side of the semiconductor stack; a first connecting electrode disposed on the insulating layer and including the first contact electrode among the side portions of the light-emitting element and the first contact electrode and the pixel electrode; a second connecting electrode disposed on the insulating layer and including the second contact electrode among the side portions of the light-emitting element and the second contact electrode and the common electrode; a first pattern disposed on the first connecting electrode and surrounding the first side portion of the light-emitting element; and a second pattern disposed on the second connecting electrode, surrounding the second side portion of the light-emitting element and spaced apart from the first pattern.

[0006] In one embodiment, the first pattern and the second pattern include a negative type photoresist material and may include a side with an inverse taper shape.

[0007] In one embodiment, the display device may further include: a first reflective film disposed on the side of the first pattern and surrounding the first side portion of the light-emitting element; and a second reflective film disposed on the side of the second pattern and surrounding the second side portion of the light-emitting element.

[0008] In one embodiment, the angle formed between at least one part of the first reflective film and the pixel electrode may be 100° to 120°, and the angle formed between at least one part of the second reflective film and the common electrode may be 100° to 120°.

[0009] In one embodiment, the first pattern and the second pattern may include a transparent organic material through which light emitted from the light-emitting element can pass.

[0010] In one embodiment, the height of the first pattern may be greater than or equal to the height of the first connecting electrode, and the height of the second pattern may be greater than or equal to the height of the second connecting electrode.

[0011] In one embodiment, the first pattern may have a shape and size corresponding to the first connecting electrode when viewed from above, and the second pattern may have a shape and size corresponding to the second connecting electrode when viewed from above.

[0012] In one embodiment, the side of the light-emitting element further includes a third side portion between the first side portion and the second side portion, and the first connecting electrode and the second connecting electrode may be spaced apart from each other with the third side portion of the light-emitting element in between.

[0013] In one embodiment, the first pattern and the second pattern may be spaced apart from each other with the third side portion of the light-emitting element in between.

[0014] In one embodiment, the display device further includes a light-blocking layer disposed on the side of the first pattern and the second pattern, and the light-blocking layer may surround at least one part of the light-emitting element including the first side portion and the second side portion.

[0015] An electronic device according to one embodiment may include a display module including a display panel; and a processor that transmits an image data signal to the display module. The display panel may include: a pixel electrode and a common electrode disposed on a substrate; an insulating layer disposed on a portion of the pixel electrode and the common electrode; a light-emitting element disposed on the insulating layer and including a semiconductor stack and a first contact electrode and a second contact electrode disposed on a side of the semiconductor stack; a first connecting electrode disposed on a first side portion of the side of the light-emitting element including the first contact electrode and on the insulating layer, and connecting the first contact electrode and the pixel electrode; a second connecting electrode disposed on a second side portion of the side of the light-emitting element including the second contact electrode and on the insulating layer, and connecting the second contact electrode and the common electrode; a first pattern disposed on the first connecting electrode and surrounding the first side portion of the light-emitting element; and a second pattern disposed on the second connecting electrode, surrounding the second side portion of the light-emitting element and spaced apart from the first pattern.

[0016] In one embodiment, the first pattern and the second pattern include a negative type photoresist material and may include a side with an inverse taper shape.

[0017] In one embodiment, the display panel may further include: a first reflective film disposed on the side of the first pattern and surrounding the first side portion of the light-emitting element; and a second reflective film disposed on the side of the second pattern and surrounding the second side portion of the light-emitting element.

[0018] In one embodiment, the angle formed between at least one part of the first reflective film and the pixel electrode may be 100° to 120°, and the angle formed between at least one part of the second reflective film and the common electrode may be 100° to 120°.

[0019] In one embodiment, the first pattern may have a shape and size corresponding to the first connecting electrode when viewed from above, and the second pattern may have a shape and size corresponding to the second connecting electrode when viewed from above.

[0020] In one embodiment, the display panel further includes a light-blocking layer disposed on the side of the first pattern and the second pattern, and the light-blocking layer may surround at least one part of the light-emitting element including the first side portion and the second side portion.

[0021] A method for manufacturing a display device according to one embodiment may include: forming a pixel electrode and a common electrode on a substrate; forming an insulating layer covering a portion of the pixel electrode and the common electrode; placing a light-emitting element on the insulating layer, the light-emitting element including a semiconductor stack and a first contact electrode and a second contact electrode disposed on a side of the semiconductor stack; forming a conductive film on the pixel electrode, the common electrode, the insulating layer, and the light-emitting element; forming a first pattern surrounding a first side portion including the first contact electrode among the side portions of the light-emitting element and a second pattern surrounding a second side portion including the second contact electrode among the side portions of the light-emitting element on the conductive film; and forming a first connecting electrode surrounding the first side portion of the light-emitting element and connecting the first contact electrode and the pixel electrode, and a second connecting electrode surrounding the second side portion of the light-emitting element and connecting the second contact electrode and the common electrode, by etching the conductive film using the first pattern and the second pattern as a mask.

[0022] In one embodiment, in the step of forming the first pattern and the second pattern, a negative type photoresist material may be used to form the first pattern and the second pattern in a shape including a reverse taper-shaped side.

[0023] In one embodiment, the method for manufacturing the display device may further include the step of forming a first reflective film and a second reflective film on the side of the first pattern and the side of the second pattern, respectively.

[0024] In one embodiment, the method for manufacturing a display device may further include the step of forming a light-blocking layer on the sides of the first pattern and the second pattern, surrounding at least one portion of the light-emitting element including the first side portion and the second side portion.

[0025] Specific details of other embodiments are included in the detailed description and drawings.

[0026] The display device and electronic device according to the embodiments may include a first connecting electrode connecting a part of a light-emitting element and a pixel electrode, a second connecting electrode connecting another part of a light-emitting element and a common electrode, a first pattern disposed on the first connecting electrode, and a second pattern disposed on the second connecting electrode and spaced apart from the first pattern. In some embodiments, the first connecting electrode and the second connecting electrode may be formed below the first pattern and the second pattern, respectively, by utilizing the first pattern and the second pattern. According to the display device and electronic device and the method for manufacturing the display device according to the embodiments, the first connecting electrode and the second connecting electrode can be stably separated to prevent short circuit defects between the pixel electrode and the common electrode.

[0027] In some embodiments, the first pattern and the second pattern surround different side portions of the light-emitting element and may include sides in the shape of an inverse taper. Additionally, the display device and the electronic device may further include a first reflective film and a second reflective film disposed on the sides of the first pattern and the second pattern and inclined at a shape or angle corresponding to the sides of the first pattern and the second pattern. According to the display device and the electronic device and the method for manufacturing the display device according to the embodiments, the reflectance of side light directed toward the first reflective film and the second reflective film can be increased, and the light efficiency of the display device and the electronic device can be improved.

[0028] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification.

[0029] FIG. 1 is a perspective view showing a display device according to one embodiment.

[0030] FIG. 2 is a plan view showing a display panel according to one embodiment.

[0031] FIG. 3 is a block diagram showing a display device according to one embodiment.

[0032] FIG. 4 is an equivalent circuit diagram showing a subpixel according to one embodiment.

[0033] FIG. 5 is a plan view showing a display panel according to one embodiment.

[0034] FIG. 6 is a plan view showing a display panel according to one embodiment.

[0035] FIG. 7 is a cross-sectional view showing a display panel according to one embodiment.

[0036] Figure 8 is a cross-sectional view showing the A1 region of Figure 7 in detail.

[0037] FIGS. 9 to 19 are cross-sectional views showing a method for manufacturing a display device according to one embodiment.

[0038] FIG. 20 is a block diagram of an electronic device according to one embodiment.

[0039] FIG. 21 is a schematic diagram of an electronic device according to various embodiments.

[0040] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0041] When elements or layers are referred to as being "on" another element or layer, this includes cases where another layer or element is interposed directly on or in the middle of another element. Throughout the specification, the same reference numerals refer to the same components. Shapes, sizes, ratios, angles, numbers, etc., disclosed in the drawings for describing embodiments are exemplary and therefore the invention is not limited to the depicted details.

[0042] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0043] Specific embodiments will be described below with reference to the attached drawings.

[0044] FIG. 1 is a perspective view showing a display device according to one embodiment.

[0045] Referring to FIG. 1, the display device (1) may be a device capable of providing images such as video or still images. For example, the display device (1) may be a device capable of displaying images by including a display module including a display panel (100). As an example, the display device (1) may refer to any electronic device that provides a display screen on which an image can be displayed, or includes a display module for displaying an image. The display device (1) may be included in an electronic device that provides a display screen and may form the display screen of said electronic device.

[0046] For example, the display device (1) can be used as a display screen in various electronic devices such as mobile phones, smartphones, tablet personal computers, smart watches, watch phones, mobile communication terminals, electronic notebooks, e-books, PMPs (portable multimedia players), navigation systems, UMPCs (Ultra Mobile PCs), as well as in televisions, laptops, monitors, billboards, and the Internet of Things (IOT). Additionally, the display device (1) can be used to display images in other electronic devices such as virtual reality (VR) devices or augmented reality (AR) devices.

[0047] FIG. 1 illustrates a display module, which is a major component of a display device (1). In one embodiment, the display device (1) (or an electronic device including a display module) may include additional components. For example, the display device (1) may further include a housing or case, etc., for housing the display module of FIG. 1.

[0048] In one embodiment, the display device (1) may be a light-emitting display device such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a micro light-emitting display device using a micro or nano light-emitting diode (micro LED or nano LED). Hereinafter, as an example of a display device (1) to which the embodiments can be applied, a micro light-emitting display device including a micro light-emitting diode is disclosed. However, the embodiments are not limited thereto. For example, the type of light-emitting element included in the display device (1) is not limited to a micro light-emitting diode, and the display device (1) may include other types and / or forms of light-emitting elements. Furthermore, the display device (1) according to the embodiments is not limited to a light-emitting display device, and the type and / or form of the display device (1) may be varied according to the embodiments.

[0049] The display device (1) may include a display panel (100), a display driving circuit (250), a circuit board (300), and a power supply (500). The display panel (100), the display driving circuit (250), the circuit board (300), and the power supply (500) may be included in a display module of the display device (1).

[0050] In one embodiment, the display panel (100) may have a roughly rectangular planar shape. For example, the display panel (100) may have a roughly rectangular shape on a plane defined by a first direction (DR1) and a second direction (DR2) that intersect each other. The corners of the display panel (100) may be rounded or formed at right angles. The planar shape of the display panel (100) is not limited to a rectangular shape and may be formed in other polygonal shapes, circular shapes, or elliptical shapes. The display panel (100) may be substantially flat, but is not limited thereto. For example, the display panel (100) may include a curved surface at least in a portion (e.g., left and right ends). In one embodiment, the display panel (100) may be formed flexibly so that it can be bent, curved, folded, or rolled.

[0051] The display panel (100) may include a main area (MA) where an image is displayed. In one embodiment, the display panel (100) may further include a sub-area (SBA).

[0052] The main area (MA) may include a display area (DA) for displaying an image and a non-display area (NDA) which is a surrounding area of ​​the display area (DA). The display area (DA) may include pixels to display an image. Each pixel may include a plurality of subpixels. For example, each pixel may include a first subpixel emitting light of a first color, a second subpixel emitting light of a second color, and a third subpixel emitting light of a third color, but the embodiments are not limited thereto.

[0053] A sub-region (SBA) may protrude from one side of a main region (MA) in a second direction (DR2) (e.g., vertical direction). Although FIG. 1 illustrates a state in which the sub-region (SBA) is unfolded, the sub-region (SBA) may be bent. When the sub-region (SBA) is bent, it may be placed on the lower surface of the display panel (100) while overlapping with the main region (MA) in a third direction (DR3), which is the thickness direction of the display panel (100). A display driving circuit (250) may be placed in the sub-region (SBA).

[0054] The display driving circuit (250) can generate signals and voltages (for example, driving signals and driving voltages of the display panel (100)) for driving the display panel (100). The display driving circuit (250) may be formed as an integrated circuit (IC) and attached to the display panel (100) using a COG (chip on glass) method, a COP (chip on plastic) method, or an ultrasonic bonding method, but is not limited thereto. For example, the display driving circuit (250) may be attached to the circuit board (300) using a COF (chip on film) method.

[0055] A circuit board (300) is attached to one end of a sub-region (SBA) of a display panel (100) and can be electrically connected to the display panel (100) and the display driving circuit (250). The display panel (100) and the display driving circuit (250) can receive digital video data, timing signals, and driving voltages through the circuit board (300). The circuit board (300) may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip-on-film.

[0056] The power supply unit (500) can generate panel driving voltages according to the power voltage supplied from the outside. The power supply unit (500) can be formed as an integrated circuit (IC) and attached to the circuit board (300) in a COF manner.

[0057] FIG. 2 is a plan view showing a display panel according to one embodiment. FIG. 2 shows a state in which a sub-region (SBA) is unfolded.

[0058] Referring to FIGS. 1 and FIGS. 2, the display panel (100) may include a main area (MA) and a sub-area (SBA).

[0059] The main area (MA) may include a display area (DA) and a non-display area (NDA). The display area (DA) may occupy most of the main area (MA).

[0060] A display area (DA) may include pixels (PX) for displaying an image. Each pixel (PX) may include a plurality of subpixels (SPX). A pixel (PX) may be defined as a group of subpixels of the smallest unit capable of expressing a white gradation. For example, a pixel (PX) may include three subpixels (SPX) that emit light of different colors. However, the number, type, and / or ratio of subpixels (SPX) included in each pixel (PX) may vary depending on the embodiments.

[0061] A non-display area (NDA) may be placed adjacent to a display area (DA). For example, the non-display area (NDA) may surround the display area (DA). The non-display area (NDA) may be an edge area of ​​the display panel (100).

[0062] In one embodiment, a first scan driver (SDC1) and a second scan driver (SDC2) may be disposed in a non-display area (NDA). The first scan driver (SDC1) and the second scan driver (SDC2) may be disposed on different sides of a display area (DA). Each of the first scan driver (SDC1) and the second scan driver (SDC2) may be electrically connected to a display driver circuit (250) through a plurality of wires. Each of the first scan driver (SDC1) and the second scan driver (SDC2) may receive a scan control signal from the display driver circuit (250), generate scan signals according to the scan control signal, and output them to scan lines.

[0063] In FIG. 2, an embodiment is disclosed in which a display device (1) (for example, a display panel (100)) includes a first scan drive unit (SDC1) and a second scan drive unit (SDC2), but the embodiments are not limited thereto. For example, the number or location of the scan drive units included in the display device (1) may vary depending on the embodiments.

[0064] A sub-region (SBA) may protrude from one side of a main region (MA) in a second direction (DR2) (e.g., vertical direction). The length of the second direction (DR2) of the sub-region (SBA) may be shorter than the length of the second direction (DR2) of the main region (MA). The length of the first direction (DR1) of the sub-region (SBA) may be less than or equal to the length of the first direction (DR1) of the main region (MA). The sub-region (SBA) may be bent, so that at least a portion of the sub-region (SBA) may overlap with the main region (MA) in a third direction (DR3). For example, a portion of the sub-region (SBA) may be positioned below the main region (MA).

[0065] The sub-region (SBA) may include a connection region (CA), a pad region (PA), and a bending region (BA).

[0066] The connection area (CA) may be an area protruding in a second direction (DR2) from one side of the main area (MA). One side of the connection area (CA) is in contact with the non-display area (NDA) of the main area (MA), and the other side of the connection area (CA) may be in contact with the bending area (BA).

[0067] The pad area (PA) may be an area where pads (PDs) and a display driving circuit (250) are placed. The display driving circuit (250) may be attached to the driving pads of the pad area (PA) using a conductive adhesive member such as an anisotropic conductive film. The circuit board (300) may be attached to the pads (PDs) of the pad area (PA) using a conductive adhesive member such as an anisotropic conductive film. One side of the pad area (PA) may be in contact with a bending area (BA).

[0068] The bending area (BA) may be a bending area. When the display panel (100) is bent in the bending area (BA), the pad area (PA) may be positioned below the connection area (CA) and below the main area (MA). The bending area (BA) may be positioned between the connection area (CA) and the pad area (PA). One side of the bending area (BA) may be in contact with the connection area (CA), and the other side of the bending area (BA) may be in contact with the pad area (PA).

[0069] FIG. 3 is a block diagram showing a display device according to one embodiment.

[0070] Referring to FIG. 3, the display area (DA) may include pixels (PX), scan lines (SL), light emission control lines (EL), and data lines (DL).

[0071] Pixels (PX) can be arranged in a first direction (DR1) and a second direction (DR2). For example, pixels (PX) can be arranged in a matrix form in the first direction (DR1) and the second direction (DR2). Scan lines (SL) and light emission control lines (EL) can be extended in the first direction (DR1) and arranged in the second direction (DR2). Data lines (DL) can be extended in the second direction (DR2) and arranged in the first direction (DR1). Scan lines (SL) may include write scan lines (GWL), initialization scan lines (GIL), control scan lines (GCL), and bias scan lines (GBL). The configuration of scan lines (SL) may vary depending on the structure or driving method of the pixels (PX).

[0072] Each of the pixels (PX) may include a plurality of subpixels (SPX). For example, each of the pixels (PX) may include a first subpixel (SPX1), a second subpixel (SPX2), and a third subpixel (SPX3). The first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) may each emit light of a first color, light of a second color, and light of a third color. The light of the first color, the light of the second color, and the light of the third color may each be red light (for example, light in the red wavelength band with a main peak wavelength of approximately 600 nm to 750 nm), green light (for example, light in the green wavelength band with a main peak wavelength of approximately 480 nm to 560 nm), and blue light (for example, light in the blue wavelength band with a main peak wavelength of approximately 370 nm to 460 nm), but are not limited thereto. In one embodiment, the first subpixel (SPX1), second subpixel (SPX2), and third subpixel (SPX3) of each of the pixels (PX) may be arranged in a first direction (DR1). The number, type, arrangement structure, and / or emission wavelength of the subpixels (SPX) included in each of the pixels (PX) may be varied according to the embodiments.

[0073] Each of the plurality of subpixels (SPX) may be connected to any one of the write scan lines (GWL), any one of the initialization scan lines (GIL), any one of the control scan lines (GCL), any one of the bias scan lines (GBL), any one of the light emission control lines (EL), and any one of the data lines (DL). In describing the embodiments, the term “connection” may include the meaning of “physical connection” and / or “electrical connection”.

[0074] Each of the plurality of subpixels (SPX) can receive a data voltage of a data line (DL) according to a write scan signal of a write scan line (GWL). Each of the plurality of subpixels (SPX) may include a light-emitting element that emits light with a brightness corresponding to the data voltage. The plurality of subpixels (SPX) included in each pixel (PX) may be connected to different data lines (DL). For example, a first subpixel (SPX1), a second subpixel (SPX2), and a third subpixel (SPX3) may be connected to a first data line (DLr), a second data line (DLg), and a third data line (DLb), respectively. Accordingly, the light-emitting brightness of each of the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) can be controlled individually.

[0075] In one embodiment, each pixel (PX) is connected to two or more light emission control lines (EL), and the light emission period (or on-duty ratio) of at least two subpixels (SPX) among a plurality of subpixels (SPX) included in each pixel (PX) can be controlled independently and / or individually by different light emission control signals supplied to different light emission control lines (EL). For example, in each horizontal line (e.g., each pixel row) of a display area (DA), a first light emission control line (EL1) and a second light emission control line (EL2) connected to different subpixels (SPX) among the subpixels (SPX) included in the pixels (PX) placed on the corresponding horizontal line may be disposed. For example, a first light-emitting control line (EL1) may be connected to first subpixels (SPX1) of pixels (PX) arranged on the horizontal line, and a second light-emitting control line (EL2) may be connected to second subpixels (SPX2) and third subpixels (SPX3) included in pixels (PX) of the horizontal line.

[0076] The first subpixel (SPX1) can emit light during a first light emission period in response to a first light emission control signal supplied through the first light emission control line (EL1). The first light emission period may be a period during which a driving current can flow through the first subpixel (SPX1) by the first light emission control signal. The second subpixel (SPX2) and the third subpixel (SPX3) can emit light during a second light emission period in response to a second light emission control signal supplied through the second light emission control line (EL2). The second light emission period may be a period during which a driving current can flow through the second subpixel (SPX2) and the third subpixel (SPX3) by the second light emission control signal. The first light emission period and the second light emission period may be controlled independently or individually.

[0077] In one embodiment, the duration of the first light emission period and the duration of the second light emission period may be different. For example, the duration of the first light emission period may correspond to an on-duty ratio adjusted so that the first subpixel (SPX1) emits light at a target brightness, in accordance with a driving current optimized for the light emission efficiency of the first subpixel (SPX1) (for example, a driving current that falls within the range in which the light-emitting element of the first subpixel (SPX1) exhibits optimal consumption efficiency). The duration of the second light emission period may correspond to an on-duty ratio adjusted so that the second subpixel (SPX2) and the third subpixel (SPX3) emit light at a target brightness, in accordance with a driving current optimized for the light emission efficiency of the second subpixel (SPX2) and the third subpixel (SPX3) (for example, a driving current that falls within the range in which the light-emitting elements of the second subpixel (SPX2) and the third subpixel (SPX3) exhibit optimal consumption efficiency). In this case, the light emission control signal output unit (615) included in the first scan drive unit (SDC1) and the second scan drive unit (SDC2) can output light emission control signals having different pulse widths to the first light emission control line (EL1) and the second light emission control line (EL2).

[0078] However, the embodiments are not limited thereto. For example, in other embodiments, a first sub-pixel (SPX1), a second sub-pixel (SPX2), and a third sub-pixel (SPX3) included in a single pixel (PX) may be commonly connected to a single light emission control line (EL). For example, a single light emission control line (EL) may be arranged on a single horizontal line, and the sub-pixels (SPX) arranged on the single horizontal line may be commonly connected to the single light emission control line (EL). In this case, the light emission periods of the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3) may be controlled by a light emission control signal supplied to the single light emission control line (EL).

[0079] A first scan drive unit (SDC1), a second scan drive unit (SDC2), and a display drive circuit (250) may be disposed in the non-display area (NDA) and the sub-area (SBA in FIG. 2).

[0080] Each of the first scan driver (SDC1) and the second scan driver (SDC2) can be electrically connected to pixels (PX) through scan lines (SL) and light emission control lines (EL). For example, each of the first scan driver (SDC1) and the second scan driver (SDC2) can be electrically connected to subpixels (SPX) of each pixel (PX) through write scan lines (GWL), initialization scan lines (GIL), control scan lines (GCL), bias scan lines (GBL), and light emission control lines (EL).

[0081] Each of the first scan driving unit (SDC1) and the second scan driving unit (SDC2) may include a write scan signal output unit (611), an initialization scan signal output unit (612), a control scan signal output unit (613), a bias scan signal output unit (614), and a light emission control signal output unit (615). Each of the write scan signal output unit (611), the initialization scan signal output unit (612), the control scan signal output unit (613), the bias scan signal output unit (614), and the light emission control signal output unit (615) may receive a scan timing control signal (SCS) from the timing control unit (251).

[0082] The write scan signal output unit (611) can generate write scan signals according to the scan timing control signal (SCS) and output them sequentially to the write scan lines (GWL).

[0083] The initialization scan signal output unit (612) can generate initialization scan signals according to the scan timing control signal (SCS) and output them sequentially to the initialization scan lines (GIL).

[0084] The control scan signal output unit (613) can generate control scan signals according to the scan timing control signal (SCS) and output them sequentially to the control scan lines (GCL).

[0085] The bias scan signal output unit (614) can generate bias scan signals according to the scan timing control signal (SCS) and output them sequentially to the bias scan lines (GBL).

[0086] The light emission control signal output unit (615) can generate light emission control signals according to the scan timing control signal (SCS) and output them sequentially to the light emission control lines (EL). In one embodiment, when the subpixels (SPX) of each horizontal line are divided and connected to a plurality of light emission control lines (EL) (for example, a first light emission control line (EL1) and a second light emission control line (EL2) of each horizontal line), the light emission control signal output unit (615) can output each light emission control signal to the plurality of light emission control lines (EL) for each horizontal period.

[0087] The display driving circuit (250) may include a timing control unit (251) and a data driving unit (252).

[0088] The data driver (252) can be electrically connected to pixels (PX) through data lines (DL). For example, the data driver (252) can be electrically connected to subpixels (SPX) of each pixel (PX) through a first data line (DLr), a second data line (DLg), and a third data line (DLb).

[0089] The data driver (252) can receive digital video data (DATA) and a data timing control signal (DCS) from the timing control unit (251). The data driver (252) converts the digital video data (DATA) into analog data voltages according to the data timing control signal (DCS) and outputs them to the data lines (DL). Subpixels (SPX) are selected by the write scan signals of the first scan driver (SDC1) and the second scan driver (SDC2), and data voltages can be supplied to the selected subpixels (SPX).

[0090] The timing control unit (251) can receive digital video data (DATA) and timing signals from the outside. The timing control unit (251) can generate a scan timing control signal (SCS) and a data timing control signal (DCS) to control the display panel (100) according to the timing signals. The timing control unit (251) can output the scan timing control signal (SCS) to the first scan driving unit (SDC1) and the second scan driving unit (SDC2). The timing control unit (251) can output the digital video data (DATA) and the data timing control signal (DCS) to the data driving unit (252).

[0091] The power supply unit (500) can generate panel driving voltages according to the power voltage supplied from the outside. For example, the power supply unit (500) can generate a first driving voltage (VDD), a second driving voltage (VSS), a third driving voltage (VINT), a fourth driving voltage (VAINT), and a fifth driving voltage (VOBS) and supply them to the display panel (100). The first driving voltage (VDD), the second driving voltage (VSS), the third driving voltage (VINT), the fourth driving voltage (VAINT), and the fifth driving voltage (VOBS) can be supplied to the subpixels (SPX) through respective power lines connected between the power supply unit (500) and the subpixels (SPX), and can be used to drive the subpixels (SPX). Depending on the structure or operation method of the subpixels (SPX), the number and / or type of panel driving voltages output from the power supply unit (500) may be changed.

[0092] FIG. 4 is an equivalent circuit diagram showing a subpixel according to one embodiment. For example, FIG. 4 may be an equivalent circuit diagram showing one of the subpixels (SPX) of FIG. 2 and FIG. 3. For example, the subpixel (SPX) of FIG. 4 may be the first subpixel (SPX1), the second subpixel (SPX2), or the third subpixel (SPX3) of FIG. 3. In one embodiment, the circuit configuration of the plurality of subpixels (SPX) forming each pixel (PX) may be substantially identical to one another.

[0093] Referring to FIG. 4 in addition to FIG. 1 to 3, each of the subpixels (SPX) may include a pixel circuit (PXC) and a light-emitting element (LE) electrically connected to the pixel circuit (PXC).

[0094] A subpixel (SPX) can be connected to at least one scan driver through scan lines (SL) and a light emission control line (EL). For example, the subpixel (SPX) can be connected to a first scan driver (SDC1) and a second scan driver (SDC2) through a write scan line (GWL), an initial scan line (GIL), a control scan line (GCL), a bias scan line (GBL), and a light emission control line (EL). The first scan driver (SDC1) and the second scan driver (SDC2) can output a write scan signal (GW), an initial scan signal (GI), a control scan signal (GC), a bias scan signal (GB), and a light emission control signal (EM), respectively, through the write scan line (GWL), the initial scan line (GIL), the control scan line (GCL), the bias scan line (GBL), and the light emission control line (EL).

[0095] When the subpixel (SPX) is the first subpixel (SPX1), the subpixel (SPX) is connected to the first light emission control line (EL1) placed on the corresponding horizontal line and can receive a light emission control signal (EM) (also referred to as the "first light emission control signal") from the first light emission control line (EL1). When the subpixel (SPX) is the second subpixel (SPX2) or the third subpixel (SPX3), the subpixel (SPX) is connected to the second light emission control line (EL2) placed on the corresponding horizontal line and can receive a light emission control signal (EM) (also referred to as the "second light emission control signal") from the second light emission control line (EL2).

[0096] The subpixel (SPX) can be connected to the data driver (252) via the data line (DL). The data driver (252) can output a data voltage (Vdata) corresponding to the image data of each frame via the data line (DL).

[0097] If the subpixel (SPX) is the first subpixel (SPX1), the subpixel (SPX) may be connected to the first data line (DLr) placed in the corresponding pixel column. If the subpixel (SPX) is the second subpixel (SPX2), the subpixel (SPX) may be connected to the second data line (DLg) placed in the corresponding pixel column. If the subpixel (SPX) is the third subpixel (SPX3), the subpixel (SPX) may be connected to the third data line (DLb) placed in the corresponding pixel column.

[0098] A subpixel (SPX) can be connected to a power supply unit (500) via power lines (PL). For example, the subpixel (SPX) can be connected to a power supply unit (500) via a first power line (VDL), a second power line (VSL), a third power line (VIL), a fourth power line (VAIL), and a fifth power line (VOBL). The power supply unit (500) can supply a first driving voltage (VDD), a second driving voltage (VSS), a third driving voltage (VINT), a fourth driving voltage (VAINT), and a fifth driving voltage (VOBS), respectively, to the first power line (VDL), the second power line (VSL), the third power line (VIL), the fourth power line (VAIL), and the fifth power line (VOBL). In one embodiment, the first driving voltage (VDD), the second driving voltage (VSS), the third driving voltage (VINT), the fourth driving voltage (VAINT), and the fifth driving voltage (VOBS) may each be a high-potential pixel voltage (e.g., anode voltage), a low-potential pixel voltage (e.g., cathode voltage or common voltage), a first initialization voltage (e.g., gate initialization voltage), a second initialization voltage (e.g., anode initialization voltage), and a bias voltage.

[0099] The pixel circuit (PXC) can control the driving current (Ids) supplied to the light-emitting element (LE) in response to driving signals supplied to the subpixel (SPX) (e.g., write scan signal (GW), initialization scan signal (GI), control scan signal (GC), bias scan signal (GB), light emission control signal (EM), and data voltage (Vdata)). The pixel circuit (PXC) can control the light emission timing and brightness of the light-emitting element (LE).

[0100] The pixel circuit (PXC) may include pixel transistors (PXT) and a storage capacitor (Cst). In one embodiment, the pixel circuit (PXC) may further include a boosting capacitor (Cbst).

[0101] In one embodiment, the pixel transistors (PXT) may include first to eighth transistors (T1 to T8). The first transistor (T1) may be a driving transistor of a subpixel (SPX). The second to eighth transistors (T2 to T8) may be switching transistors of a subpixel (SPX).

[0102] In one embodiment, the subpixel (SPX) may include heterogeneous pixel transistors (PXT). For example, the first, second, fifth, sixth, seventh, and eighth transistors (T1, T2, T5, T6, T7, T8) may be P-type transistors (e.g., P-type polycrystalline silicon transistors including each active layer formed of polycrystalline silicon), and the third and fourth transistors (T3, T4) may be N-type transistors (e.g., N-type oxide transistors including each active layer formed of an oxide semiconductor). In one embodiment, the active layers of the P-type transistors (e.g., active layers formed of polycrystalline silicon) and the active layers of the N-type transistors (e.g., active layers formed of an oxide semiconductor) may be disposed on different layers within the display panel (100) (e.g., the backplane layer of the display panel (100)). However, the embodiments are not limited thereto. For example, pixel transistors (PXT) according to another embodiment may include active layers containing the same semiconductor material and may be formed of transistors of the same type.

[0103] The first transistor (T1) can be connected between the fifth transistor (T5) and the sixth transistor (T6). The first transistor (T1) can be connected to the first power line (VDL) via the fifth transistor (T5) and to the light-emitting element (LE) via the sixth transistor (T6). The gate electrode of the first transistor (T1) can be connected to the first node (N1). The first transistor (T1) can control the driving current (Ids) flowing to the subpixel (SPX) according to the voltage of the first node (N1) applied to the gate electrode (for example, a voltage corresponding to the data voltage (Vdata)).

[0104] The second transistor (T2) may be connected between the data line (DL) and the first electrode of the first transistor (T1) (for example, the source electrode of the first transistor (T1) connected to the fifth transistor (T5)). The gate electrode of the second transistor (T2) may be connected to the write scan line (GWL). The second transistor (T2) may be turned on by a write scan signal (GW) of a gate-on voltage supplied from the write scan line (GWL) (for example, a low-level voltage at which the second transistor (T2) can be turned on). When the second transistor (T2) is turned on, a data voltage (Vdata) supplied from the data line (DL) may be delivered to the first electrode (for example, the source electrode) of the first transistor (T1).

[0105] The third transistor (T3) can be connected between the second electrode of the first transistor (T1) (for example, the drain electrode of the first transistor (T1) connected to the sixth transistor (T6)) and the first node (N1). The gate electrode of the third transistor (T3) can be connected to a control scan line (GCL). The third transistor (T3) can be turned on by a control scan signal (GC) of a gate-on voltage supplied from the control scan line (GCL) (for example, a high-level voltage at which the third transistor (T3) can be turned on) to connect the gate electrode of the first transistor (T1) and the second electrode. When the third transistor (T3) is turned on, the first transistor (T1) can be driven as a diode, and a voltage corresponding to a data voltage (Vdata) can be applied to the first node (N1).

[0106] The fourth transistor (T4) can be connected between the first node (N1) and the third power line (VIL). The gate electrode of the fourth transistor (T4) can be connected to the initialization scan line (GIL). The fourth transistor (T4) can be turned on by an initialization scan signal (GI) of a gate-on voltage supplied from the initialization scan line (GIL) (for example, a high-level voltage at which the fourth transistor (T4) can be turned on) to connect the first node (N1) to the third power line (VIL). When the fourth transistor (T4) is turned on, the voltage of the first node (N1) can be initialized to the third driving voltage (VINT) of the third power line (VIL).

[0107] The fifth transistor (T5) can be connected between the first power line (VDL) and the first electrode of the first transistor (T1). The gate electrode of the fifth transistor (T5) can be connected to a light emission control line (EL) (for example, the first light emission control line (EL1) or the second light emission control line (EL2) of FIG. 3). The fifth transistor (T5) can be turned on by a light emission control signal (EM) of a gate-on voltage supplied from the light emission control line (EL) (for example, a low-level voltage at which the fifth transistor (T5) can be turned on) to connect the first electrode of the first transistor (T1) to the first power line (VDL). When the fifth transistor (T5) is turned on, the first power line (VDL) can be connected to the first electrode of the first transistor (T1).

[0108] The sixth transistor (T6) can be connected between the second electrode of the first transistor (T1) and the light-emitting element (LE). The gate electrode of the sixth transistor (T6) can be connected to the light-emitting control line (EL). The sixth transistor (T6) can be turned on by a light-emitting control signal (EM) of a gate-on voltage supplied from the light-emitting control line (EL) (for example, a low-level voltage at which the sixth transistor (T6) can be turned on) to connect the second electrode of the first transistor (T1) to the light-emitting element (LE).

[0109] The seventh transistor (T7) can be connected between the first electrode of the light-emitting element (LE) (for example, the anode electrode connected to the sixth transistor (T6)) and the fourth power line (VAIL). The gate electrode of the seventh transistor (T7) can be connected to the bias scan line (GBL). The seventh transistor (T7) can be turned on by a bias scan signal (GB) of a gate-on voltage supplied from the bias scan line (GBL) (for example, a low-level voltage at which the seventh transistor (T7) can be turned on) to connect the first electrode of the light-emitting element (LE) to the fourth power line (VAIL). When the seventh transistor (T7) is turned on, the voltage of the first electrode of the light-emitting element (LE) can be initialized to the fourth driving voltage (VAINT) of the fourth power line (VAIL).

[0110] The eighth transistor (T8) can be connected between the fifth power line (VOBL) and the first electrode of the first transistor (T1). The gate electrode of the eighth transistor (T8) can be connected to the bias scan line (GBL). The eighth transistor (T8) can be turned on by a bias scan signal (GB) of a gate-on voltage supplied from the bias scan line (GBL) to connect the first electrode of the first transistor (T1) to the fifth power line (VOBL). When the eighth transistor (T8) is turned on, the voltage of the first electrode of the first transistor (T1) can be initialized to the fifth driving voltage (VOBS) of the fifth power line (VOBL). In one embodiment, the fifth driving voltage (VOBS) may be a bias voltage having a voltage level suitable for compensating for the hysteresis characteristics of the first transistor (T1).

[0111] A storage capacitor (Cst) can be connected between a first node (N1) and a first power line (VDL). The storage capacitor (Cst) can be charged to a voltage corresponding to a data voltage (Vdata) applied to the first node (N1).

[0112] A boosting capacitor (Cbst) can be connected between the first node (N1) and the write scan line (GWL). By stabilizing the voltage of the first node (N1) through the coupling action of the boosting capacitor (Cbst), the operation of the first transistor (T1) can be stabilized. The boosting capacitor (Cbst) may be formed by a parasitic capacitance formed between the first node (N1) and the write scan line (GWL), or it may be designed separately.

[0113] A subpixel (SPX) can emit light for a portion of the frame period corresponding to the on-duty ratio and can be non-emitting for the remainder of the frame period. The emission and non-emitting periods of the subpixel (SPX) can be controlled by an emission control signal (EM).

[0114] The period during which the fifth transistor (T5) and the sixth transistor (T6) are turned off (for example, the period during which a high-level light emission control signal (EM) is supplied to the subpixel (SPX)) may be a non-luminous period of the subpixel (SPX). The non-luminous period of the subpixel (SPX) may include an initialization period for initializing the voltage of a specific node of the subpixel (SPX) (for example, the first node (N1), etc.), and a data writing and storage period for charging a voltage corresponding to the data voltage (Vdata) to the storage capacitor (Cst).

[0115] In one embodiment, an initial scan signal (GI), a control scan signal (GC), a write scan signal (GW), and a bias scan signal (GB) of the gate-on voltage may be supplied during the non-luminous period of the subpixel (SPX). In one embodiment, the initial scan signal (GI), the control scan signal (GC), and the bias scan signal (GB) of the gate-on voltage may be supplied sequentially during the non-luminous period of the subpixel (SPX). The periods during which the initial scan signal (GI) and the control scan signal (GC) of the gate-on voltage are supplied may overlap, but are not limited thereto. The write scan signal (GW) of the gate-on voltage may be supplied during the period during which the control scan signal (GC) of the gate-on voltage is supplied.

[0116] The period during which the fifth transistor (T5) and the sixth transistor (T6) are turned on (for example, the period during which a low-level light emission control signal (EM) is supplied to the subpixel (SPX)) may be the light emission period of the subpixel (SPX). During the light emission period of the subpixel (SPX), the first transistor (T1) may supply a driving current (Ids) corresponding to the voltage of the first node (N1) to the light-emitting element (LE).

[0117] The light-emitting element (LE) can be connected between the pixel circuit (PXC) and the second power line (VSL). For example, the first electrode of the light-emitting element (LE) (e.g., an anode electrode or a pixel electrode) can be connected to a node between the sixth transistor (T6) and the seventh transistor (T7), and the second electrode of the light-emitting element (LE) (e.g., a cathode electrode or a common electrode) can be connected to the second power line (VSL). The light-emitting element (LE) can emit light in response to a driving current (Ids) supplied from the pixel circuit (PXC).

[0118] In one embodiment, the subpixel (SPX) may include a single light-emitting element (LE), but is not limited thereto. For example, the subpixel (SPX) may include a plurality of light-emitting elements (LE).

[0119] In one embodiment, the light-emitting element (LE) may be a micro light-emitting diode containing an inorganic compound such as a nitride-based or phosphide-based semiconductor material, but is not limited thereto. For example, the light-emitting element (LE) may be an organic light-emitting element, a quantum dot light-emitting element, or other types of light-emitting elements. Additionally, the size or shape of the light-emitting element (LE) may vary depending on the embodiments.

[0120] FIG. 5 is a plan view showing a display panel according to one embodiment. For example, FIG. 5 shows a part of a display area (DA) in which two pixels (PX) are sequentially arranged in a second direction (DR2), and a part of a non-display area (NDA) adjacent to the display area (DA) in which a power bus line (BLI) is arranged.

[0121] FIG. 5 shows an embodiment of the layout structure of a light-emitting element layer including light-emitting elements (LE) of subpixels (SPX). The display panel (100) may further include a backplane layer including circuit elements of subpixels (SPX) (for example, circuit elements included in each of the pixel circuits (PXC) of subpixels (SPX)).

[0122] Referring to FIG. 5, each of the subpixels (SPX) may include a pixel electrode (PXE) and a light-emitting element (LE) disposed on the pixel electrode (PXE). In one embodiment, where the light-emitting element (LE) is a flip-chip type or lateral type micro LED, each of the subpixels (SPX) may further include a common electrode (CE) disposed on one side (e.g., a bottom surface or a top surface) of the light-emitting element (LE) together with the pixel electrode (PXE). In another embodiment, where the light-emitting element (LE) is a vertical type micro LED, the light-emitting element (LE) of each of the subpixels (SPX) may be disposed on the pixel electrode (PXE), and the common electrode (CE) (e.g., a common electrode disposed across the entire display area (DA) in the form of a common layer) may be disposed on the light-emitting elements (LE) of the subpixels (SPX). FIG. 5 shows a display panel (100) including flip-chip type light-emitting elements (LE). The pixel electrode (PXE) may also be referred to as an anode electrode or a first electrode, and the common electrode (CE) may also be referred to as a cathode electrode or a second electrode.

[0123] In one embodiment, subpixels (SPX) of each pixel (PX) may be arranged in a first direction (DR1) and may share a common electrode (CE). For example, the common electrode (CE) extends in the first direction (DR1) from each pixel row (or horizontal line) of the display area (DA), and the subpixels (SPX) of the pixels (PX) placed in that pixel row may share a common electrode (CE).

[0124] In one embodiment, subpixels (SPX) of a display area (DA) may be arranged in a stripe shape. For example, in each pixel column containing pixels (PX) arranged in a second direction (DR2) in the display area (DA), first subpixels (SPX1) may be arranged sequentially or continuously in the second direction (DR2). Additionally, second subpixels (SPX2) included in each pixel column may be arranged sequentially or continuously in the second direction (DR2), and third subpixels (SPX3) included in each pixel column may be arranged sequentially or continuously in the second direction (DR2). However, the arrangement of pixels (PX) and / or subpixels (SPX) may vary depending on the embodiments.

[0125] A first subpixel (SPX1) may include a first pixel electrode (PXE1) and a common electrode (CE) (or a part of the common electrode (CE)) spaced apart from each other, and a first light-emitting element (LE1) disposed on the first pixel electrode (PXE1) and the common electrode (CE). The first pixel electrode (PXE1) may refer to the pixel electrode (PXE) of the first subpixel (SPX1), and the first light-emitting element (LE1) may refer to the light-emitting element (LE) of the first subpixel (SPX1). The first light-emitting element (LE1) may be electrically connected between the first pixel electrode (PXE1) and the common electrode (CE).

[0126] The second subpixel (SPX2) may include a second pixel electrode (PXE2) and a common electrode (CE) spaced apart from each other, and a second light-emitting element (LE2) disposed on the second pixel electrode (PXE2) and the common electrode (CE). The second pixel electrode (PXE2) may refer to the pixel electrode (PXE) of the second subpixel (SPX2), and the second light-emitting element (LE2) may refer to the light-emitting element (LE) of the second subpixel (SPX2). The second light-emitting element (LE2) may be electrically connected between the second pixel electrode (PXE2) and the common electrode (CE).

[0127] The third subpixel (SPX3) may include a third pixel electrode (PXE3) and a common electrode (CE) spaced apart from each other, and a third light-emitting element (LE3) disposed on the third pixel electrode (PXE3) and the common electrode (CE). The third pixel electrode (PXE3) may refer to the pixel electrode (PXE) of the third subpixel (SPX3), and the third light-emitting element (LE3) may refer to the light-emitting element (LE) of the third subpixel (SPX3). The third light-emitting element (LE3) may be electrically connected between the third pixel electrode (PXE3) and the common electrode (CE).

[0128] In one embodiment, the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3) of each pixel (PX) are arranged sequentially along a first direction (DR1) and may be spaced apart from the common electrode (CE) in a second direction (DR2). The first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3) may face different parts of the common electrode (CE) in the second direction (DR2). In another embodiment, when the subpixels (SPX) include vertical type micro LEDs, the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3) may face the common electrode (CE) in a third direction (DR3).

[0129] The pixel electrode (PXE) and pixel circuit (PXC in FIG. 4) of each of the subpixels (SPX) can be electrically connected to each other through an anode contact hole (ANH) (or a first contact hole). For example, the first pixel electrode (PXE1) of the first subpixel (SPX1) can be electrically connected to at least one circuit element (e.g., the sixth and seventh transistors (T6, T7) in FIG. 4) included in the pixel circuit (PXC) of the first subpixel (SPX1) through the first anode contact hole (ANH1) and / or at least one connection pattern. Similarly, the second pixel electrode (PXE2) of the second subpixel (SPX2) may be electrically connected to at least one circuit element included in the pixel circuit (PXC) of the second subpixel (SPX2) through the second anode contact hole (ANH2) and / or at least one connection pattern, and the third pixel electrode (PXE3) of the third subpixel (SPX3) may be electrically connected to at least one circuit element included in the pixel circuit (PXC) of the third subpixel (SPX3) through the third anode contact hole (ANH3) and / or at least one connection pattern.

[0130] Light-emitting elements (LE) may be placed between each pixel electrode (PXE) and a common electrode (CE). For example, a first light-emitting element (LE1) may be placed on the first pixel electrode (PXE1) and the common electrode (CE), and a part of the first light-emitting element (LE1) may overlap with the first pixel electrode (PXE1) and another part of the first light-emitting element (LE1) may overlap with the common electrode (CE). A second light-emitting element (LE2) may be placed on the second pixel electrode (PXE2) and the common electrode (CE), and a part of the second light-emitting element (LE2) may overlap with the second pixel electrode (PXE2) and another part of the second light-emitting element (LE2) may overlap with the common electrode (CE). The third light-emitting element (LE3) is placed on the third pixel electrode (PXE3) and the common electrode (CE), and a part of the third light-emitting element (LE3) overlaps with the third pixel electrode (PXE3) and another part of the third light-emitting element (LE3) overlaps with the common electrode (CE).

[0131] Each of the light-emitting elements (LE) can emit light of a specific color (e.g., red light, green light, blue light, or white light). In one embodiment, the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) can emit light of different colors. For example, the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) can each emit light of a first color (e.g., red light), light of a second color (e.g., green light), and light of a third color (e.g., blue light).

[0132] In another embodiment, the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) may emit light of the same color. In this case, on at least one light-emitting element (LE) among the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3), at least one of a light conversion layer (e.g., a light conversion layer including wavelength conversion particles such as quantum dots) and a color filter may be disposed to convert the light emitted from the light-emitting element (LE) of the corresponding subpixel (SPX) into light corresponding to the light emission color of the corresponding subpixel (SPX).

[0133] The first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) may have substantially the same size as each other, but are not limited thereto. For example, depending on the light efficiency of the light-emitting elements (LE) and / or subpixels (SPX), at least two of the light-emitting elements (LE) among the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) may have different sizes.

[0134] A common electrode (CE) may be electrically connected to a power bus line (BLI) (e.g., a cathode bus line) to which a second driving voltage (VSS) is applied. In one embodiment, the common electrode (CE) may extend to a non-display area (NDA) around a display area (DA) and may be electrically connected to the power bus line (BLI) in the non-display area (NDA). The common electrode (CE) may be electrically connected to the power bus line (BLI) through at least one contact hole and / or connecting wiring, etc., or may be formed integrally with at least a portion of the power bus line (BLI). For example, the power bus line (BLI) may be composed of a plurality of wiring layers, and one of the wiring layers and the common electrode (CE) may be formed substantially as one pattern.

[0135] In one embodiment, a second power line (VSL in FIG. 4) to which a second driving voltage (VSS) is applied may also be disposed within the display area (DA). For example, a second power line (VSL) that intersects or overlaps with the common electrode (CE) may be disposed within a backplane layer disposed below the common electrode (CE). In this case, the common electrode (CE) may be electrically connected to the second power line (VSL) through at least one contact hole and / or connecting wiring, etc., within the display area (DA).

[0136] The power bus line (BLI) may be placed in a non-display area (NDA) and may be placed on at least one side of the display area (DA). For example, the power bus line (BLI) may be placed on the left and right sides of the display area (DA), and may be optionally placed on at least one of the upper and lower sides of the display area (DA). In FIG. 5, a portion of the power bus line (BLI) placed on the left side of the display area (DA) is shown.

[0137] The power bus line (BLI) can be electrically connected to the power supply unit (500 in FIG. 3). For example, the power bus line (BLI) can be electrically connected to the power supply unit (500) through at least one connection wire and / or at least one pad (PD), etc., placed in the non-display area (NDA) and / or sub-area (SBA) of the main area (MA). Accordingly, a second driving voltage (VSS) output from the power supply unit (500) can be applied to the power bus line (BLI). The power bus line (BLI) can form a part of a second power line (VSL) that is electrically connected between the power supply unit (500) and the sub-pixels (SPX). In addition, the connection structure between the common electrode (CE) and the second power line (VSL) can be varied according to the embodiments.

[0138] In one embodiment, the power bus line (BLI) may be composed of multiple layers including a first wiring layer (BLI1) and a second wiring layer (BLI2). The first wiring layer (BLI1) and the second wiring layer (BLI2) may be electrically connected to each other.

[0139] The first wiring layer (BLI1) may be disposed on the same layer as the pixel electrodes (PXE) and the common electrode (CE), and may include a conductive material contained in the pixel electrodes (PXE) and the common electrode (CE). In one embodiment, the first wiring layer (BLI1) may be formed integrally with the common electrode (CE). For example, at least one end of the common electrode (CE) may extend to a non-display area (NDA) and lead to the first wiring layer (BLI1) of the power bus line (BLI).

[0140] The second wiring layer (BLI2) may overlap with at least a portion of the first wiring layer (BLI1). In one embodiment, the second wiring layer (BLI2) may be positioned below the first wiring layer (BLI1) and may be in contact with and / or connected to the first wiring layer (BLI1).

[0141] In one embodiment, the second wiring layer (BLI2) may have a wider width than the first wiring layer (BLI1) in the first direction (DR1). For example, the second wiring layer (BLI2) may extend further toward the outer edge of the display panel (100) from the portion overlapping with the first wiring layer (BLI1) to cover the scan drive unit (for example, the first scan drive unit (SDC1) and the second scan drive unit (SDC2) of FIG. 2 and FIG. 3). In one embodiment, the second wiring layer (BLI2) may be formed to include a plurality of openings (OPN). Accordingly, gas generated by outgassing inside the display panel (100) can be properly discharged.

[0142] In one embodiment, the power bus line (BLI) may further include at least one wiring layer disposed within the backplane layer of the display panel (100). For example, the power bus line (BLI) may further include a third wiring layer disposed below the second wiring layer (BLI2) and included in one of the conductive layers of the backplane layer (for example, the second source-drain conductive layer (SCDL2) of FIG. 7). The end of the third wiring layer may be covered with at least one insulating layer. The at least one insulating layer may be open in the area where the second wiring layer (BLI2) (or the first wiring layer (BLI1)) and the third wiring layer overlap, so that the second wiring layer (BLI2) and the third wiring layer may be in contact and / or connected. If the power bus line (BLI) does not include the second wiring layer (BLI2), the third wiring layer may be in direct contact and / or connected to the first wiring layer (BLI1).

[0143] FIG. 6 is a plan view showing a display panel according to one embodiment. Compared to FIG. 5, FIG. 6 further shows connecting electrodes (BE), light-transmitting patterns (OC), and reflective films (RF) surrounding light-emitting elements (LE). In describing the following embodiments, the same reference numerals are used for configurations that are substantially identical or similar to at least one embodiment described above, and redundant descriptions are omitted.

[0144] Referring to FIGS. 5 and 6, the display panel (100) may further include connecting electrodes (BE) and light-transmitting patterns (OC) (or barrier patterns) disposed in subpixels (SPX). In one embodiment, the display panel (100) may additionally include reflective films (RF).

[0145] The connecting electrodes (BE) may include first connecting electrodes (BE1) and second connecting electrodes (BE2) spaced apart from each other. The first connecting electrodes (BE1) may be placed on the pixel electrodes (PXE) of the subpixels (SPX), and the second connecting electrodes (BE2) may be placed on the common electrode (CE) of the subpixels (SPX).

[0146] The first connecting electrodes (BE1) can connect the pixel electrode (PXE) of each subpixel (SPX) to the light-emitting element (LE). For example, in each subpixel (SPX), the first connecting electrode (BE1) can electrically connect the pixel electrode (PXE) to a part of the light-emitting element (LE) (for example, a part including the first contact electrode (CTE1) of FIG. 8). A part of the first connecting electrode (BE1) may be directly in contact with or connected to a part of the light-emitting element (LE), or electrically connected to a part of the light-emitting element (LE) through at least one other electrode or connection pattern. Additionally, another part of the first connecting electrode (BE1) may be directly in contact with or connected to a part of the pixel electrode (PXE), or electrically connected to the pixel electrode (PXE) through at least one other electrode or connection pattern.

[0147] The second connecting electrodes (BE2) can connect the common electrode (CE) of each subpixel (SPX) to the light-emitting element (LE). For example, in each subpixel (SPX), the second connecting electrode (BE2) can electrically connect the common electrode (CE) to another part of the light-emitting element (LE) (for example, a part including the second contact electrode (CTE2) of FIG. 8). A part of the second connecting electrode (BE2) may be in direct contact or connected to another part of the light-emitting element (LE), or electrically connected to another part of the light-emitting element (LE) through at least one other electrode or connection pattern. Additionally, another part of the second connecting electrode (BE2) may be in direct contact or connected to a part of the common electrode (CE), or electrically connected to the common electrode (CE) through at least one other electrode or connection pattern.

[0148] The light-emitting patterns (OC) may include first patterns (OC1) and second patterns (OC2) spaced apart from each other. The first patterns (OC1) may be placed overlapping with first connecting electrodes (BE1) on the pixel electrodes (PXE) of subpixels (SPX), and the second patterns (OC2) may be placed overlapping with second connecting electrodes (BE2) on the common electrode (CE) of subpixels (SPX). Each of the first patterns (OC1) may also be referred to as a "first light-emitting pattern" or "first barrier," and each of the second patterns (OC2) may also be referred to as a "second light-emitting pattern" or "second barrier."

[0149] The reflective films (RF) may include first reflective films (RF1) and second reflective films (RF2) spaced apart from each other. The first reflective films (RF1) may surround the first connecting electrodes (BE1) and first patterns (OC1) of the subpixels (SPX), and the second reflective films (RF2) may surround the second connecting electrodes (BE2) and second patterns (OC2) of the subpixels (SPX).

[0150] For example, each subpixel (SPX) may include a first connecting electrode (BE1) and a first pattern (OC1) disposed on a pixel electrode (PXE), a first reflective film (RF1) surrounding the sides of the first connecting electrode (BE1) and the first pattern (OC1), a second connecting electrode (BE2) and a second pattern (OC2) disposed on a common electrode (CE), and a second reflective film (RF2) surrounding the sides of the second connecting electrode (BE2) and the second pattern (OC2).

[0151] The first connecting electrode (BE1) and the first pattern (OC1) may overlap each other in the third direction (DR3) and have corresponding shapes. Additionally, the first connecting electrode (BE1) and the first pattern (OC1) may have a shape that surrounds a portion of the light-emitting element (LE) placed on the pixel electrode (PXE).

[0152] For example, the first connecting electrode (BE1) may be placed on a portion of the pixel electrode (PXE) to contact a portion of the side of the light-emitting element (LE) that is placed on the pixel electrode (PXE) and to surround a portion of the side of the light-emitting element (LE). The first pattern (OC1) is placed on the first connecting electrode (BE1) and may have a shape and size corresponding to the first connecting electrode (BE1) when viewed from above. For example, the first connecting electrode (BE1) and the first pattern (OC1) may be placed sequentially on the pixel electrode (PXE) and may have substantially the same planar shape and / or size.

[0153] The first reflective film (RF1) can be placed on the side of the first pattern (OC1). Accordingly, the first reflective film (RF1) can surround a portion of the side of the light-emitting element (LE) surrounded by the first pattern (OC1).

[0154] The second connecting electrode (BE2) and the second pattern (OC2) overlap each other in the third direction (DR3) and may have corresponding shapes. Additionally, the second connecting electrode (BE2) and the second pattern (OC2) may have shapes that surround another part of the light-emitting element (LE) placed on the common electrode (CE).

[0155] For example, the second connecting electrode (BE2) may be placed on a portion of the common electrode (CE) to contact a portion of the side of the light-emitting element (LE) that is placed on the common electrode (CE) and to surround a portion of the side of the light-emitting element (LE). The second pattern (OC2) is placed on the second connecting electrode (BE2) and may have a shape and size corresponding to the second connecting electrode (BE2) when viewed from above. For example, the second connecting electrode (BE2) and the second pattern (OC2) may be placed sequentially on the common electrode (CE) and may have substantially the same planar shape and / or size.

[0156] The second reflective film (RF2) can be placed on the side of the second pattern (OC2). Accordingly, the second reflective film (RF2) can surround a portion of the side of the light-emitting element (LE) surrounded by the second pattern (OC2).

[0157] In describing the embodiments, a portion of the side of the light-emitting element (LE) surrounded by a first connecting electrode (BE1), a first pattern (OC1), and / or a first reflective film (RF1) is referred to as the "first side portion," and another portion of the side of the light-emitting element (LE) surrounded by a second connecting electrode (BE2), a second pattern (OC2), and / or a second reflective film (RF2) is referred to as the "second side portion." Additionally, a portion of the side of the light-emitting element (LE) excluding the first side portion and the second side portion (for example, a side portion exposed and not surrounded by the first connecting electrode (BE1), the first pattern (OC1), the first reflective film (RF1), the second connecting electrode (BE2), the second pattern (OC2), and / or the second reflective film (RF2), etc.) is referred to as the "third side portion."

[0158] The first connecting electrode (BE1) and the second connecting electrode (BE2) of each sub-pixel (SPX) may be spaced apart from each other. For example, the first connecting electrode (BE1) and the second connecting electrode (BE2) may not be placed in the area between the pixel electrode (PXE) and the common electrode (CE), and may be spaced apart from each other in the second direction (DR2). In this case, the first connecting electrode (BE1) and the second connecting electrode (BE2) may not be placed on a part of the light-emitting element (LE) that is placed in the area between the pixel electrode (PXE) and the common electrode (CE), for example, a part of the light-emitting element (LE) including a third side portion. For example, the first connecting electrode (BE1) and the second connecting electrode (BE2) may be spaced apart from each other with the third side portion of the light-emitting element (LE) in between.

[0159] Similarly, the first pattern (OC1) and the second pattern (OC2) of each subpixel (SPX) may be spaced apart from each other. For example, the first pattern (OC1) and the second pattern (OC2) may not be placed in the area between the pixel electrode (PXE) and the common electrode (CE), and may be spaced apart from each other in the second direction (DR2). In this case, the first pattern (OC1) and the second pattern (OC2) may not be placed on a part of the light-emitting element (LE) including a third side portion. For example, the first pattern (OC1) and the second pattern (OC2) may be spaced apart from each other with the third side portion of the light-emitting element (LE) in between.

[0160] Additionally, the first reflective film (RF1) and the second reflective film (RF2) may not be placed on a portion of the light-emitting element (LE) where the first pattern (OC1) and the second pattern (OC2) are not placed. For example, the first reflective film (RF1) and the second reflective film (RF2) may not be placed in the region between the pixel electrode (PXE) and the common electrode (CE), and may be spaced apart from each other in the second direction (DR2). For example, the first reflective film (RF1) and the second reflective film (RF2) may be spaced apart from each other with the third side portion of the light-emitting element (LE) in between.

[0161] In one embodiment, the light-emitting element (LE) may have a planar shape that is approximately rectangular when viewed from above, and may include four sides that meet the four corners of each of the top surface and the bottom surface. For example, the light-emitting element (LE) may include a first side (an upper side located at one end of the light-emitting element (LE) in the second direction (DR2) and positioned on the pixel electrode (PXE)) that is positioned on the pixel electrode (PXE) and extends in the first direction (DR1), a second side (an lower side located at the other end of the light-emitting element (LE) in the second direction (DR2) and positioned on the common electrode (CE)) that is positioned on the common electrode (CE), a third side (a left side located at one end of the light-emitting element (LE) in the second direction (DR2) that connects one end of the first side and one end of the second side, and extends in the second direction (DR2) (an example, a left side located at one end of the light-emitting element (LE) in the first direction (DR1)), and a fourth side (an right side located at the other end of the light-emitting element (LE) in the second direction (DR2) that connects the other end of the first side and the other end of the second side.

[0162] In this case, the first side portion of the light-emitting element (LE) may include the first side of the light-emitting element (LE), a portion of the third side (for example, a portion of the third side disposed on the pixel electrode (PXE)), and a portion of the fourth side (for example, a portion of the fourth side disposed on the pixel electrode (PXE)). The second side portion of the light-emitting element (LE) may include the second side of the light-emitting element (LE), another portion of the third side (for example, a portion of the third side disposed on the common electrode (CE)), and another portion of the fourth side (for example, a portion of the fourth side disposed on the common electrode (CE)). A third side portion of the light-emitting element (LE) may include the remainder of the third side of the light-emitting element (LE) (for example, a central portion disposed in the area between the pixel electrode (PXE) and the common electrode (CE) of the third side), and the remainder of the fourth side (for example, a central portion disposed in the area between the pixel electrode (PXE) and the common electrode (CE) of the fourth side).

[0163] In one embodiment, the display panel (100) may further include additional electrodes or configurations disposed on the light-emitting element layer. For example, the display panel (100) may further include reflective electrodes (RFL of FIG. 7) disposed below the light-emitting elements (LE).

[0164] FIG. 7 is a cross-sectional view showing a display panel according to one embodiment. For example, FIG. 7 shows an example of a cross-sectional view of a part of a display panel (100) corresponding to the line X1-X1' of FIG. 6.

[0165] FIG. 8 is a cross-sectional view showing the A1 region of FIG. 7 in detail. For example, FIG. 8 shows in detail an example of a first light-emitting element (LE1) included in a first subpixel (SPX1). In one embodiment, the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) of the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) may have substantially the same or similar cross-sectional structures.

[0166] Referring to FIGS. 7 and FIGS. 8 in addition to FIGS. 1 to 6, a display panel (100) may include a substrate (110), a backplane layer (120) and a light-emitting element layer (130) disposed on the substrate (110). In one embodiment, the display panel (100) may further include an optical layer (140) disposed on the light-emitting element layer (130).

[0167] The substrate (110) may be made of an insulating material such as glass or a polymer resin. If the substrate (110) is made of a polymer resin, it may be a stretchable flexible substrate.

[0168] The substrate (110) may include a display area (DA) and a non-display area (NDA). The display area (DA) may include light-emitting areas (EA) of subpixels (SPX). Each light-emitting area (EA) may include a light-emitting element area where a light-emitting element (LE) of each subpixel (SPX) is placed. The display area (DA) may further include a non-light-emitting area (NEA) placed around the light-emitting areas (EA). The non-light-emitting area (NEA) may surround the light-emitting areas (EA).

[0169] The backplane layer (120) may include circuit elements included in the pixel circuits (PXC) of the subpixels (SPX) and wiring connected to the subpixels (SPX). In one embodiment, the backplane layer (120) may be formed entirely on one side of the substrate (110).

[0170] The backplane layer (120) may include at least one semiconductor layer, conductive layers, and insulating layers. In one embodiment, when the pixel circuits (PXC) include at least two types of pixel transistors (PXT) formed of different materials, the backplane layer (120) may include a plurality of semiconductor layers.

[0171] For example, the backplane layer (120) is sequentially arranged on the substrate (110) along a third direction (DR3) and comprises a lower conductive layer (BCDL), a barrier layer (121) (or buffer layer), a first semiconductor layer (SCL1) (in one example, a polycrystalline silicon semiconductor layer), a first insulating layer (122) (in one example, a first inorganic insulating layer), a first gate conductive layer (GCDL1) (or a first conductive layer), a second insulating layer (123) (in one example, a second inorganic insulating layer), a second gate conductive layer (GCDL2) (or a second conductive layer), a third insulating layer (124) (in one example, a third inorganic insulating layer), a second semiconductor layer (SCL2) (in one example, an oxide semiconductor layer), a fourth insulating layer (125) (in one example, a fourth inorganic insulating layer), a third gate conductive layer (GCDL3) (or a third conductive layer), a fifth insulating layer (126) (in one example, a fifth inorganic insulating layer), and a first source-drain layer. It may include a conductive layer (SCDL1) (or a fourth conductive layer), a sixth insulating layer (127) (for example, a first organic insulating layer), a second source-drain conductive layer (SCDL2) (or a fifth conductive layer) and a seventh insulating layer (128) (for example, a second organic insulating layer).

[0172] The lower conductive layer (BCDL) may include a lower conductive pattern (BML) disposed below the first transistor (T1). The lower conductive pattern (BML) may cover the lower surface of the first active layer (ACT1) included in the first transistor (T1) wholly or partially. For example, the lower conductive pattern (BML) may be disposed below the first active layer (ACT1) to overlap with the channel region of the first active layer (ACT1) (for example, a part of the first active layer (ACT1) that overlaps with the first gate electrode (GE1)). In one embodiment, the lower conductive layer (BCDL) may include a light-blocking material such as a metal. Accordingly, light incident on the channel region of the first active layer (ACT1) from below the first active layer (ACT1) can be blocked, and the operating characteristics of the first transistor (T1) can be stabilized.

[0173] A barrier layer (121) may be disposed on a lower conductive layer (BCDL). The barrier layer (121) can protect circuit elements of the backplane layer (120) and light-emitting elements (LE) on the backplane layer (120) from moisture penetrating through a substrate (110) that is susceptible to moisture permeability. In one embodiment, the barrier layer (121) may be composed of a plurality of inorganic insulating layers.

[0174] Circuit elements of the backplane layer (120) may be disposed on the barrier layer (121). For example, pixel transistors (PXT), storage capacitors (Cst), and boosting capacitors (Cbst) included in the pixel circuits (PXC) of each subpixel (SPX) may be disposed on the barrier layer (121). Additionally, wiring of the backplane layer (120) may be disposed on the barrier layer (121). For example, signal lines and power lines electrically connected to the subpixels (SPX) may be disposed on the barrier layer (121).

[0175] FIG. 7 shows, as an example of circuit elements included in the backplane layer (120), a first transistor (T1), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a storage capacitor (Cst), and a boosting capacitor (Cbst) included in the first subpixel (SPX1). FIG. 7 also shows, as an example of wiring included in the backplane layer (120), a write scan line (GWL), first and second light emission control lines (EL1, EL2), a first power line (VDL), and a third power line (VIL). Each of the other wirings includes at least one wiring layer included in at least one conductive layer included in the backplane layer (120), and each may be formed as a single layer or a multilayer wiring.

[0176] In one embodiment, each pixel circuit (PXC) may include first type transistors and second type transistors. The first type transistors and second type transistors may be placed on different layers within the backplane layer (120). For example, as shown in FIG. 4, each pixel circuit (PXC) may include first, second, fifth, sixth, seventh, and eighth P-type transistors (T1, T2, T5, T6, T7, T8) and third and fourth N-type transistors (T3, T4). The active layers included in the first, second, fifth, sixth, seventh, and eighth transistors (T1, T2, T5, T6, T7, T8) and the active layers included in the third and fourth transistors (T3, T4) may be formed with patterns of different semiconductor layers. In addition, the gate electrodes included in the first, second, fifth, sixth, seventh, and eighth transistors (T1, T2, T5, T6, T7, T8) and the gate electrodes included in the third and fourth transistors (T3, T4) can be formed with patterns of different conductive layers.

[0177] A first semiconductor layer (SCL1) (also referred to as the "first semiconductor pattern layer") may be disposed on the barrier layer (121). The first semiconductor layer (SCL1) may include an active layer for each of the first type of transistors. For example, the first semiconductor layer (SCL1) may include a first active layer (ACT1) included in the first transistor (T1), a fifth active layer (ACT5) included in the fifth transistor (T5), and second, sixth, seventh, and eighth active layers (not shown) included in the second, sixth, seventh, and eighth transistors (T2, T6, T7, T8). In one embodiment, the patterns of the first semiconductor layer (SCL1) included in one subpixel (SPX) (for example, the first and fifth active layers (ACT1, ACT5) and the second, sixth, seventh, and eighth active layers of each subpixel (SPX)) may be formed integrally, but are not limited thereto.

[0178] The patterns of the first semiconductor layer (SCL1) may include a first semiconductor material. In one embodiment, the first semiconductor material may be polycrystalline silicon (e.g., low-temperature polycrystalline silicon), but is not limited thereto. For example, the first semiconductor material may be an oxide semiconductor (e.g., at least one of zinc oxide (ZnO), zinc-tin oxide (ZTO), indium-zinc oxide (IZO), indium oxide (InO), titanium oxide (TiO), indium-gallium oxide (IGO), indium-gallium-zinc oxide (IGZO), indium-gallium-tin oxide (IGTO), indium-zinc-tin oxide (IZTO), indium-tin-gallium-zinc oxide (ITGZO), or other oxide semiconductors) or single-crystal silicon.

[0179] A first insulating layer (122) may be disposed on the first semiconductor layer (SCL1). The first insulating layer (122) may comprise at least one insulating material (e.g., silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), titanium oxide (TiOx), aluminum oxide (AlOx), or other inorganic insulating material) and may be composed of a single layer or multiple layers.

[0180] A first gate conductive layer (GCDL1) may be disposed on the first insulating layer (122). The first gate conductive layer (GCDL1) may include the gate electrodes of each of the first type of transistors. For example, the first gate conductive layer (GCDL1) may include a first gate electrode (GE1) included in the first transistor (T1), a fifth gate electrode (GE5) included in the fifth transistor (T5), and second, sixth, seventh, and eighth gate electrodes (not shown) included in the second, sixth, seventh, and eighth transistors (T2, T6, T7, T8).

[0181] The first gate conductive layer (GCDL1) may further include at least one conductive pattern and / or wiring. For example, the first gate conductive layer (GCDL1) may further include a first capacitor electrode (SCE1) of a storage capacitor (Cst), a first electrode (BCE1) of a boosting capacitor (Cbst), and a write scan line (GWL), etc. In one embodiment, the first gate electrode (GE1) of each pixel circuit (PXC) and the first capacitor electrode (SCE1) of the storage capacitor (Cst) are formed integrally, and the first electrode (BCE1) of the boosting capacitor (Cbst) of each pixel circuit (PXC) and the write scan line (GWL) connected to the pixel circuit (PXC) may be formed integrally.

[0182] A second insulating layer (123) may be disposed on the first gate conductive layer (GCDL1). The second insulating layer (123) may comprise at least one insulating material (e.g., an inorganic insulating material) and may be composed of a single layer or multiple layers.

[0183] A second gate conductive layer (GCDL2) may be disposed on the second insulating layer (123). The second gate conductive layer (GCDL2) may include a second capacitor electrode (SCE2) of a storage capacitor (Cst). The first capacitor electrode (SCE1) and the second capacitor electrode (SCE2) of the storage capacitor (Cst) may overlap with the second insulating layer (123) in between.

[0184] The second gate conductive layer (GCDL2) may further include at least one conductive pattern and / or wiring. For example, the second gate conductive layer (GCDL2) may further include a first light-blocking pattern (LBP1) and a second light-blocking pattern (LBP2). The first light-blocking pattern (LBP1) and the second light-blocking pattern (LBP2) may each be disposed below a channel region of the third active layer (ACT3) (for example, a part of the third active layer (ACT3) that overlaps with the third gate electrode (GE3)) and a channel region of the fourth active layer (ACT4) (for example, a part of the fourth active layer (ACT4) that overlaps with the fourth gate electrode (GE4)). Accordingly, light incident on the channel regions of the third active layer (ACT3) and the fourth active layer (ACT4) is blocked from below the third active layer (ACT3) and the fourth active layer (ACT4), and the operating characteristics of the third transistor (T3) and the fourth transistor (T4) can be stabilized.

[0185] A third insulating layer (124) may be disposed on the second gate conductive layer (GCDL2). The third insulating layer (124) may comprise at least one insulating material (e.g., an inorganic insulating material) and may be composed of a single layer or multiple layers.

[0186] A second semiconductor layer (SCL2) (also referred to as the "second semiconductor pattern layer") may be disposed on the third insulating layer (124). The second semiconductor layer (SCL2) may include an active layer for each of the second type of transistors. For example, the second semiconductor layer (SCL2) may include a third active layer (ACT3) included in the third transistor (T3) and a fourth active layer (ACT4) included in the fourth transistor (T4). In one embodiment, the patterns of the second semiconductor layer (SCL2) included in one subpixel (SPX) (for example, the third and fourth active layers (ACT3, ACT4) of each subpixel (SPX) may be formed integrally, but are not limited thereto. In one embodiment, the second semiconductor layer (SCL2) further includes a second electrode (BCE2) of a boosting capacitor (Cbst), and the second electrode (BCE2) of the boosting capacitor (Cbst) may be formed integrally with the third and fourth active layers (ACT3, ACT4).

[0187] The patterns of the second semiconductor layer (SCL2) may include a second semiconductor material. In one embodiment, the second semiconductor material may be an oxide semiconductor, but is not limited thereto. For example, the second semiconductor material may be polycrystalline silicon or single-crystal silicon.

[0188] A fourth insulating layer (125) may be disposed on the second semiconductor layer (SCL2). The fourth insulating layer (125) may comprise at least one insulating material (e.g., an inorganic insulating material) and may be composed of a single layer or multiple layers.

[0189] A third gate conductive layer (GCDL3) may be disposed on the fourth insulating layer (125). The third gate conductive layer (GCDL3) may include the gate electrodes of each of the second type of transistors. For example, the third gate conductive layer (GCDL3) may include a third gate electrode (GE3) included in the third transistor (T3) and a fourth gate electrode (GE4) included in the fourth transistor (T4).

[0190] A fifth insulating layer (126) may be disposed on the third gate conductive layer (GCDL3). The fifth insulating layer (126) may comprise at least one insulating material (e.g., an inorganic insulating material) and may be composed of a single layer or multiple layers.

[0191] A first source-drain conductive layer (SCDL1) may be disposed on the fifth insulating layer (126). The first source-drain conductive layer (SCDL1) may include at least one electrode, a conductive pattern and / or wiring. For example, the first source-drain conductive layer (SCDL1) may include first, second, and third connection patterns (CNE1, CNE2, CNE3), first and second light emission control lines (EL1, EL2), and a third power line (VIL).

[0192] A first connection pattern (CNE1) may be electrically connected to a fifth active layer (ACT5), a second capacitor electrode (SCE2) of a storage capacitor (Cst), and a first power line (VDL) through at least one contact hole or via hole. A second connection pattern (CNE2) may be electrically connected to a first active layer (ACT1) and a third active layer (ACT3) through at least one contact hole. A third connection pattern (CNE3) may be electrically connected to a third active layer (ACT3) and a fourth active layer (ACT4) through at least one contact hole. A third connection pattern (CNE3) may be electrically connected to a first gate electrode (GE1) and a first capacitor electrode (SCE1) of a storage capacitor (Cst) through at least one contact hole in an area not illustrated. In one embodiment, a first source-drain conductive layer (SCDL1) may further include additional connection patterns for appropriately connecting circuit elements of each subpixel (SPX).

[0193] The first light emission control line (EL1) may be electrically connected to the fifth gate electrode (GE5) and the sixth gate electrode (not shown) of the first subpixel (SPX1) through at least one contact hole in an unillustrated area. The second light emission control line (EL2) may be electrically connected to the fifth and sixth gate electrodes (not shown) of the second and third subpixels (SPX2, SPX3) through at least one contact hole in an unillustrated area. The third power line (VIL) may be electrically connected to the fourth active layer (ACT4) through at least one contact hole.

[0194] A sixth insulating layer (127) may be disposed on the first source-drain conductive layer (SCDL1). The sixth insulating layer (127) may comprise at least one insulating material (e.g., acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or other organic insulating material) and may be a single layer or a multilayer.

[0195] A second source-drain conductive layer (SCDL2) may be disposed on the sixth insulating layer (127). The second source-drain conductive layer (SCDL2) may include at least one electrode, a conductive pattern, and / or wiring. For example, the second source-drain conductive layer (SCDL2) may include a first power line (VDL).

[0196] In one embodiment, the first power line (VDL) may extend substantially into the second direction (DR2) or the like from the display area (DA) and may be commonly connected to subpixels (SPX) arranged continuously and / or sequentially in the second direction (DR2). The first power line (VDL), which is shown separated into two patterns in FIG. 7, may be a single, substantially integral wire. The first power line (VDL) may be electrically connected to the first connection pattern (CNE1) through a first via hole (VH1) (or contact hole). The first via hole (VH1) may be a type of contact hole, which is an opening formed in the sixth insulating layer (127) for contact between the first connection pattern (CNE1) and the first power line (VDL). In one embodiment, the first power line (VDL) may overlap with the channel areas of the first active layer (ACT1), the third active layer (ACT3), and the fourth active layer (ACT4). Accordingly, light incident on the channel regions of the first active layer (ACT1), the third active layer (ACT3), and the fourth active layer (ACT4) is blocked from the top of the first active layer (ACT1), the third active layer (ACT3), and the fourth active layer (ACT4), and the operating characteristics of the first transistor (T1), the third transistor (T3), and the fourth transistor (T4) can be stabilized.

[0197] In one embodiment, the second source-drain conductive layer (SCDL2) may further include an anode connection pattern (not shown) connected to a pixel electrode (PXE) of each subpixel (SPX), and data lines (DL) of FIGS. 3 and 4. The anode connection pattern of each subpixel (SPX) may be electrically connected between the pixel circuit (PXC) of the corresponding subpixel (SPX) and the pixel electrode (PXE). For example, the anode connection pattern of each subpixel (SPX) may be electrically connected to the sixth and seventh active layers of the corresponding subpixel (SPX) through at least one contact hole and / or at least one connection pattern, and may be electrically connected to the pixel electrode (PXE) of the corresponding subpixel (SPX) through the anode contact hole (ANH) of FIG. 6.

[0198] A seventh insulating layer (128) may be disposed on the second source-drain conductive layer (SCDL2). The seventh insulating layer (128) may comprise at least one insulating material (e.g., an organic insulating material) and may be a single layer or multiple layers.

[0199] Patterns included in each of the conductive layers of the backplane layer (120) may include at least one conductive material. For example, electrodes, conductive patterns, and / or wiring included in each of the lower conductive layer (BCDL), the first gate conductive layer (GCDL1), the second gate conductive layer (GCDL2), the third gate conductive layer (GCDL3), the first source-drain conductive layer (SCDL1), and the second source-drain conductive layer (SCDL2) may include at least one of copper (Cu), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), tantalum (Ta), tungsten (W), magnesium (Mg), and other metals, alloys thereof, or other conductive materials. In one embodiment, electrodes, conductive patterns, and / or wiring disposed in the same conductive layer may be formed simultaneously using the same conductive material. The patterns included in each of the conductive layers of the backplane layer (120) may have a single layer or a multilayer structure.

[0200] A light-emitting element layer (130) may be disposed on the seventh insulating layer (128). The light-emitting element layer (130) may include pixel electrodes (PXE), a common electrode (CE), light-emitting elements (LE), first connecting electrodes (BE1), and second connecting electrodes (BE2) included in subpixels (SPX). In one embodiment, the light-emitting element layer (130) may further include at least one of reflective electrodes (RFL), light-transmitting patterns (OC), reflective films (RF), and a light-blocking layer (BM).

[0201] Additionally, the light-emitting element layer (130) may further include a plurality of insulating layers. In one embodiment, the insulating layers of the light-emitting element layer (130) may include an eighth insulating layer (132), a ninth insulating layer (134), and a first overcoat layer (136).

[0202] Specifically, a pixel electrode layer (PCDL) including pixel electrodes (PXE) of subpixels (SPX) may be disposed on the seventh insulating layer (128). For example, the pixel electrode layer (PCDL) may include a first pixel electrode (PXE1), a second pixel electrode (PXE2), and a third pixel electrode (PXE3). In one embodiment, the light-emitting element (LE) may be a flip-chip type micro LED. A flip-chip type micro LED refers to an LED having first and second contact electrodes (CTE1, CTE2) formed on one side (e.g., the bottom side) of the light-emitting element (LE). When the light-emitting element (LE) is a flip-chip type micro LED, the pixel electrode layer (PCDL) may further include a common electrode (CE). For example, the pixel electrodes (PXE) of subpixels (SPX) and the common electrode (CE) may be disposed on the same layer and may be formed simultaneously using the same conductive material. Figure 7 shows the first pixel electrode (PXE1) and the common electrode (CE) of the first subpixel (SPX1) among the patterns of the pixel electrode layer (PCDL).

[0203] The first pixel electrode (PXE1) of the first subpixel (SPX1) can be electrically connected to the pixel circuit (PXC) of the first subpixel (SPX1) through the first anode contact hole (ANH1) of FIG. 6. The second pixel electrode (PXE2) of the second subpixel (SPX2) can be electrically connected to the pixel circuit (PXC) of the second subpixel (SPX2) through the second anode contact hole (ANH2) of FIG. 6. The third pixel electrode (PXE3) of the third subpixel (SPX3) can be electrically connected to the pixel circuit (PXC) of the third subpixel (SPX3) through the third anode contact hole (ANH3) of FIG. 6.

[0204] Patterns of the pixel electrode layer (PCDL), for example, pixel electrodes (PXE) and common electrode (CE), may comprise at least one conductive material and may be composed of a single layer or multiple layers. In one embodiment, the patterns of the pixel electrode layer (PCDL) may comprise a metal (for example, at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and other metals, or an alloy thereof) and may have a single layer or multiple layer structure. For example, the patterns of the pixel electrode layer (PCDL) may be low-resistance patterns formed of a three-layer structure (Ti / Al / Ti) of titanium (Ti), aluminum (Al), and titanium (Ti). Alternatively, the patterns of the pixel electrode layer (PCDL) may comprise other low-resistance materials (for example, copper (Cu)) and / or structures. When the resistance of the patterns included in the pixel electrode layer (PCDL) is reduced or minimized, the first driving voltage (VDD) and the second driving voltage (VSS) can be stably transmitted to the light-emitting elements (LE) of the subpixels (SPX).

[0205] In one embodiment, reflective electrodes (RFL) may be disposed on the pixel electrode layer (PCDL). For example, each subpixel (SPX) may include a first reflective electrode (RFL1) disposed on the pixel electrode (PXE) and a second reflective electrode (RFL2) disposed on the common electrode (CE).

[0206] The first reflective electrode (RFL1) may cover at least a portion of the pixel electrode (PXE). For example, the first reflective electrode (RFL1) may be placed on a portion of the pixel electrode (PXE) including an end that overlaps with the light-emitting element (LE).

[0207] The second reflective electrode (RFL2) may cover at least a portion of the common electrode (CE). For example, the second reflective electrode (RFL2) may be placed on a portion of the common electrode (CE) including an end that overlaps with the light-emitting element (LE).

[0208] Reflective electrodes (RFLs) may include a material with high reflectivity to light emitted from a light-emitting element (LE). In one embodiment, each of the reflective electrodes (RFLs) may be a single-layer or multi-layer conductive pattern containing a conductive material. For example, the reflective electrodes (RFLs) may include silver (Ag) or aluminum (Al), or other metals with high light reflectivity. As an example, the reflective electrodes (RFLs) may be formed as a three-layer structure (ITO / Ag / ITO) of indium-tin oxide (ITO), silver (Ag), and indium-tin oxide (ITO).

[0209] When the first reflective electrode (RFL1) and the second reflective electrode (RFL2) are conductive, the pixel electrode (PXE) can be electrically connected to a part of the light-emitting element (LE) through the first reflective electrode (RFL1) and the first connecting electrode (BE1), and the common electrode (CE) can be electrically connected to another part of the light-emitting element (LE) through the second reflective electrode (RFL2) and the second connecting electrode (BE2).

[0210] In FIG. 7, the pixel electrode (PXE), common electrode (CE), first reflective electrode (RFL1), and second reflective electrode (RFL2) are each shown separately, but the embodiments are not limited thereto. For example, the first reflective electrode (RFL1) may be part of the pixel electrode (PXE), and the second reflective electrode (RFL2) may be part of the common electrode (CE). For example, the pixel electrode (PXE) may be formed as a single-layer or multi-layer electrode including the first reflective electrode (RFL1), and the common electrode (CE) may be formed as a single-layer or multi-layer electrode including the second reflective electrode (RFL2). Alternatively, the display panel (100) may not include the first reflective electrode (RFL1) and the second reflective electrode (RFL2) of FIG. 7, and the eighth insulating layer (132), the first connecting electrode (BE1), and the second connecting electrode (BE2) may be disposed directly on the pixel electrode layer (PCDL). In one embodiment, the display panel (100) does not include separate first reflective electrode (RFL1) and second reflective electrode (RFL2), and the pixel electrode (PXE) and common electrode (CE) each include a material with high reflectivity so that they can also function as reflective layers.

[0211] An eighth insulating layer (132) may be disposed on the pixel electrode layer (PCDL) and the reflective electrodes (RFL). The eighth insulating layer (132) may be an adhesive layer that temporarily fixes or adheres the light-emitting elements (LE) to prevent the light-emitting elements (LE) from tilting or falling over during the process of transferring the light-emitting elements (LE) to the display panel (100). For example, the eighth insulating layer (132) may be a film for temporarily adhering the light-emitting elements (LE) to each pixel electrode (PXE) and common electrode (CE). To facilitate temporary adhesion, the thickness of the eighth insulating layer (132) may be greater than the thickness of each pixel electrode (PXE) and common electrode (CE), and greater than the thickness of each of the first and second contact electrodes (CTE1, CTE2) of the light-emitting elements (LE). The eighth insulating layer (132) may also be referred to as an "adhesive layer" or a "bonding layer."

[0212] The eighth insulating layer (132) may cover a portion of the pixel electrode (PXE), common electrode (CE), first reflective electrode (RFL1), and second reflective electrode (RFL2) below the light-emitting element (LE). In one embodiment, the eighth insulating layer (132) may be placed only in a portion of the light-emitting region (EA) including the area where each light-emitting element (LE) is placed. For example, the eighth insulating layer (132) may be placed individually within the light-emitting region (EA) of each sub-pixel (SPX). However, the embodiments are not limited thereto. For example, in another embodiment, the eighth insulating layer (132) may be placed across the entire display area (DA) or each sub-pixel area or light-emitting region (EA). In this case, the eighth insulating layer (132) has connection holes formed therein that expose a portion of the upper surface of each of the first reflective electrode (RFL1) and the second reflective electrode (RFL2) (or a portion of the upper surface of each of the pixel electrode (PXE) and the common electrode (CE)), and through the connection holes, the first connecting electrode (BE1) and the second connecting electrode (BE2) may be in contact with and / or connected to the first reflective electrode (RFL1) and the second reflective electrode (RFL2) (or the pixel electrode (PXE) and the common electrode (CE)), respectively.

[0213] The eighth insulating layer (132) may include at least one insulating material, for example, an organic insulating material. For example, the eighth insulating layer (132) may be a photosensitive organic layer such as photoresist. Alternatively, the eighth insulating layer (132) may be formed from acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, etc.

[0214] In FIG. 7, the eighth insulating layer (132) is depicted as having a generally uniform thickness or height and being substantially flat below and around the light-emitting element (LE), but embodiments are not limited thereto. For example, the height of the eighth insulating layer (132) may be partially reduced in the portion where each light-emitting element (LE) is placed, as the eighth insulating layer (132) is pressed by pressure applied during the process of placing the light-emitting elements (LE) on the eighth insulating layer (132).

[0215] The light-emitting elements (LE) may be disposed on the eighth insulating layer (132). In one embodiment, each of the light-emitting elements (LE) may be a micro LED comprising an inorganic material. For example, each of the light-emitting elements (LE) may be formed of an inorganic material such as gallium nitride (GaN), and the length of the first direction (DR1), the length of the second direction (DR2), and the length of the third direction (DR3) of each of the light-emitting elements (LE) may each be several μm to several hundred μm. For example, the length of the first direction (DR1), the length of the second direction (DR2), and the length of the third direction (DR3) of each of the light-emitting elements (LE) may each be approximately 100 μm or less.

[0216] Light-emitting elements (LE) can be formed by growing on a semiconductor substrate, such as a silicon substrate or a sapphire substrate. Light-emitting elements (LE) can be transferred directly from the semiconductor substrate onto the pixel electrodes (PXE) and common electrode (CE) of the display panel (100). Alternatively, light-emitting elements (LE) can be transferred onto the pixel electrodes (PXE) and common electrode (CE) of the display panel (100) via an electrostatic method using an electrostatic head or a stamping method using an elastic polymer material, such as PDMS or silicon, as a transfer substrate.

[0217] The light-emitting element (LE) may include a conductive layer (E1), a semiconductor stack (STC), first and second contact electrodes (CTE1, CTE2), and a protective film (PRL). The semiconductor stack (STC) may include a first semiconductor layer (SEM1), an active layer (MQW) (e.g., a light-emitting layer), and a second semiconductor layer (SEM2) arranged sequentially in a third direction (DR3). In one embodiment, the semiconductor stack (STC) may optionally further include a third semiconductor layer (SEM3) arranged on the second semiconductor layer (SEM2).

[0218] A conductive layer (E1) may be disposed on the lower surface of the first semiconductor layer (SEM1). Although FIG. 8 illustrates a case where the conductive layer (E1) covers the entire lower surface of the first semiconductor layer (SEM1), the embodiments are not limited thereto. As an example, the conductive layer (E1) may be disposed on a portion of the lower surface of the first semiconductor layer (SEM1). The conductive layer (E1) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or a transparent conductive material such as a metal oxide.

[0219] The first semiconductor layer (SEM1) can be placed on the conductive layer (E1). The first semiconductor layer (SEM1) may be made of a semiconductor material layer doped with a first conductive type dopant such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), etc., for example, gallium nitride (GaN).

[0220] An active layer (MQW) may be disposed on a first semiconductor layer (SEM1). The active layer (MQW) may include the same semiconductor material as the first semiconductor layer (SEM1) and the second semiconductor layer (SEM2). For example, if the first semiconductor layer (SEM1) and the second semiconductor layer (SEM2) include gallium nitride (GaN), the active layer (MQW) may also include gallium nitride (GaN). For example, the active layer (MQW) may include at least one of gallium nitride (GaN), indium gallium nitride (InGaN), and aluminum gallium nitride (AlGaN). The active layer (MQW) may emit light by the recombination of electron-hole pairs according to an electric signal applied through the first semiconductor layer (SEM1) and the second semiconductor layer (SEM2).

[0221] The active layer (MQW) may include a material having a single or multiple quantum well structure. When the active layer (MQW) includes a material having a multiple quantum well structure, it may have a structure in which multiple well layers and barrier layers are alternately stacked. In this case, the well layers may be formed of InGaN, and the barrier layers may be formed of GaN or AlGaN, but are not limited thereto. Alternatively, the active layer (MQW) may have a structure in which semiconductor materials with large band gap energy and semiconductor materials with small band gap energy are alternately stacked, or it may include different Group 3 to Group 5 semiconductor materials depending on the wavelength of the emitted light.

[0222] When the active layer (MQW) contains indium gallium nitride (InGaN), the color of the emitted light may vary depending on the indium (In) content. For example, as the indium (In) content increases, the wavelength band of the light emitted by the active layer (MQW) shifts toward the red wavelength band, and as the indium (In) content decreases, the wavelength band of the light emitted by the active layer (MQW) may shift toward the blue wavelength band.

[0223] The second semiconductor layer (SEM2) can be disposed on the active layer (MQW). The second semiconductor layer (SEM2) may be a semiconductor material layer doped with a second conductivity type dopant, such as silicon (Si), germanium (Ge), tin (Sn), etc., for example, gallium nitride (GaN).

[0224] A third semiconductor layer (SEM3) may be disposed on the second semiconductor layer (SEM2). The third semiconductor layer (SEM3) is a semiconductor material layer in which the n-type dopant is lower than a predetermined threshold value and may be referred to as an un-doped semiconductor layer. For example, the third semiconductor layer (SEM3) may be indium aluminum gallium nitride (InAlGaN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), or indium nitride (InN), in which the n-type dopant is lower than a predetermined threshold value. The third semiconductor layer (SEM3) may be omitted.

[0225] An electron blocking layer may be placed between the first semiconductor layer (SEM1) and the active layer (MQW). The electron blocking layer may be a layer designed to suppress or prevent too many electrons from flowing into the active layer (MQW). For example, the electron blocking layer may be AlGaN or p-AlGaN doped with p-type Mg. The electron blocking layer may be omitted.

[0226] A superlattice layer may be disposed between the active layer (MQW) and the second semiconductor layer (SEM2). The superlattice layer may be a layer for relieving stress between the second semiconductor layer (SEM2) and the active layer (MQW). For example, the superlattice layer may be formed of InGaN or GaN. The superlattice layer may be omitted.

[0227] A protective film (PRL) may be disposed on the side of the conductive layer (E1) and the semiconductor stack (STC). The protective film (PRL) may comprise an inorganic material, for example, silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), titanium oxide (TiOx), aluminum oxide (AlOx), or other inorganic insulating materials.

[0228] A hole (LEH) can be formed that penetrates the conductive layer (E1), the first semiconductor layer (SEM1), and the active layer (MQW) of the light-emitting element (LE) to expose the second semiconductor layer (SEM2). The hole (LEH) may have a circular planar shape, but the shape of the hole (LEH) is not limited thereto. For example, the hole (LEH) may have a polygonal planar shape such as an ellipse or a square.

[0229] A protective film (PRL) may be disposed on the sidewall of the conductive layer (E1) exposed in the hole (LEH), the sidewall of the first semiconductor layer (SEM1), and the sidewall of the active layer (MQW). The protective film (PRL) may not cover the second semiconductor layer (SEM2) in the hole (LEH).

[0230] The first contact electrode (CTE1) may be disposed on at least one side of the semiconductor stack (STC) and on at least one side and bottom surface of the conductive layer (E1). For example, the first contact electrode (CTE1) may be disposed on a first side portion and a bottom portion of the light-emitting element (LE). For example, the first contact electrode (CTE1) may be disposed on the first side, a portion of the third side, and a portion of the fourth side of the semiconductor stack (STC) and the conductive layer (E1), respectively, and on a bottom portion of the conductive layer (E1). The first contact electrode (CTE1) may not be disposed on the second side portion and the third side portion of the light-emitting element (LE).

[0231] The lower surface of the conductive layer (E1) may include a portion that is exposed and not covered by a protective film (PRL) in a portion that overlaps with the first contact electrode (CTE1). The first contact electrode (CTE1) may be placed on a portion of the lower surface of the conductive layer (E1) that is not covered by the protective film (PRL) and may be electrically connected to the conductive layer (E1).

[0232] The second contact electrode (CTE2) may be disposed on at least one side of the semiconductor stack (STC), and on at least one side and bottom surface of the conductive layer (E1). For example, the second contact electrode (CTE2) may be disposed on a second side portion and another bottom portion of the light-emitting element (LE). As an example, the second contact electrode (CTE2) may be disposed on the second side of the semiconductor stack (STC) and the conductive layer (E1), another portion of the third side and another portion of the fourth side, and another portion of the bottom surface of the conductive layer (E1), respectively. The second contact electrode (CTE2) may not be disposed on the first side portion and the third side portion of the light-emitting element (LE).

[0233] The second contact electrode (CTE2) can be placed on a protective film (PRL) placed in the hole (LEH) and on a second semiconductor layer (SEM2) exposed in the hole (LEH) without being covered by the protective film (PRL). The second contact electrode (CTE2) can be electrically connected to the second semiconductor layer (SEM2) in the hole (LEH).

[0234] Each of the first contact electrode (CTE1) and the second contact electrode (CTE2) may include at least one conductive material, for example, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). In one embodiment, the first contact electrode (CTE1) and the second contact electrode (CTE2) may be formed with a two-layer structure of chromium (Cr) and gold (Au) (Cr / Au), a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti) (Ti / Al / Ti), or a three-layer structure of indium-tin oxide (ITO), silver (Ag), and indium-tin oxide (ITO) (ITO / Ag / ITO) to increase reflectivity.

[0235] When the first contact electrode (CTE1) and the second contact electrode (CTE2) are each formed of a metal with high reflectivity, light traveling in the lateral direction of the light-emitting element (LE) among the light emitted from the active layer (MQW) of the light-emitting element (LE) can be reflected by the first contact electrode (CTE1) and the second contact electrode (CTE2) and emitted to the upper surface of the light-emitting element (LE). Therefore, light loss of the light-emitting element (LE) can be reduced, and the light efficiency of the light-emitting element (LE) can be increased. To increase the light efficiency of the light-emitting element (LE), the first contact electrode (CTE1) and the second contact electrode (CTE2) can be arranged to cover at least the side of the active layer (MQW).

[0236] In one embodiment, the light-emitting element (LE) may include light extraction patterns (LEP) formed on one surface from which light is emitted. For example, the light-emitting element (LE) may include light extraction patterns (LEP) formed on the upper surface of a semiconductor stack (STC) (for example, the upper surface of a third semiconductor layer (SEM3)). The light extraction patterns (LEP) may have a shape suitable for diffusing and / or scattering light on the upper surface of the light-emitting element (LE). For example, the upper surface of the light-emitting element (LE) may be formed non-flat so that the upper surface of the light-emitting element (LE) has a shape suitable for light scattering. Accordingly, the light efficiency of the light-emitting element (LE) (for example, the light emission rate of light generated from the light-emitting element (LE)) can be increased.

[0237] In one embodiment, the light-emitting element (LE) may include sides with an inverse taper shape. For example, the light-emitting element (LE) may have a shape in which the width and / or area gradually increases from the bottom to the top. Accordingly, the amount of light emitted from the top surface of the light-emitting element (LE) can be increased, thereby further increasing the light efficiency of the light-emitting element (LE).

[0238] Connecting electrodes (BE) may be disposed on the eighth insulating layer (132). For example, the first connecting electrode (BE1) and the second connecting electrode (BE2) may be disposed on different parts of the eighth insulating layer (132). The first connecting electrode (BE1) and the second connecting electrode (BE2) may be spaced apart from each other with a light-emitting element (LE) in between.

[0239] The first connecting electrode (BE1) connects the first contact electrode (CTE1) of the light-emitting element (LE) and the pixel electrode (PXE). For example, the first connecting electrode (BE1) of the first sub-pixel (SPX1) can electrically connect the first contact electrode (CTE1) of the first light-emitting element (LE1) and the first pixel electrode (PXE1). The first connecting electrode (BE1) of the second sub-pixel (SPX2) can electrically connect the first contact electrode (CTE1) of the second light-emitting element (LE2) and the second pixel electrode (PXE2). The first connecting electrode (BE1) of the third sub-pixel (SPX3) can electrically connect the first contact electrode (CTE1) of the third light-emitting element (LE3) and the third pixel electrode (PXE3).

[0240] In one embodiment, the first connecting electrode (BE1) may contact the first contact electrode (CTE1) of the light-emitting element (LE) on the eighth insulating layer (132). For example, a portion of the first connecting electrode (BE1) (for example, one end of the first connecting electrode (BE1) disposed on the eighth insulating layer (132)) may be directly disposed on the first side portion of the light-emitting element (LE) including the first contact electrode (CTE1). Accordingly, the first connecting electrode (BE1) may be electrically connected to the first contact electrode (CTE1) of the light-emitting element (LE). The first connecting electrode (BE1) may have a shape and / or inclination corresponding to the first side portion of the light-emitting element (LE) on the first side portion of the light-emitting element (LE).

[0241] Additionally, the first connecting electrode (BE1) may come into contact with the first reflective electrode (RFL1) on the pixel electrode (PXE). For example, another part of the first connecting electrode (BE1) (for example, the other end of the first connecting electrode (BE1) placed on a part of the pixel electrode (PXE) not covered by the eighth insulating layer (132)) may be placed directly on a part of the first reflective electrode (RFL1) not covered by the eighth insulating layer (132). Accordingly, the first connecting electrode (BE1) may be electrically connected to the first reflective electrode (RFL1) and may be electrically connected to the pixel electrode (PXE) through the first reflective electrode (RFL1). In another embodiment, when the subpixel (SPX) does not include the first reflective electrode (RFL1) or the pixel electrode (PXE) and the first reflective electrode (RFL1) are integrated, the first connecting electrode (BE1) may be electrically connected to the pixel electrode (PXE) by contacting the pixel electrode (PXE) on a part of the pixel electrode (PXE) that is not covered by the eighth insulating layer (132).

[0242] The second connecting electrode (BE2) connects the second contact electrode (CTE2) of the light-emitting element (LE) to the common electrode (CE). For example, the second connecting electrode (BE2) of the first subpixel (SPX1) can electrically connect the second contact electrode (CTE2) of the first light-emitting element (LE1) to the common electrode (CE). The second connecting electrode (BE2) of the second subpixel (SPX2) can electrically connect the second contact electrode (CTE2) of the second light-emitting element (LE2) to the common electrode (CE). The second connecting electrode (BE2) of the third subpixel (SPX3) can electrically connect the second contact electrode (CTE2) of the third light-emitting element (LE3) to the common electrode (CE).

[0243] In one embodiment, the second connecting electrode (BE2) may contact the second contact electrode (CTE2) of the light-emitting element (LE) on the eighth insulating layer (132). For example, a portion of the second connecting electrode (BE2) (for example, one end of the second connecting electrode (BE2) disposed on the eighth insulating layer (132)) may be directly disposed on the second side portion of the light-emitting element (LE) including the second contact electrode (CTE2). Accordingly, the second connecting electrode (BE2) may be electrically connected to the second contact electrode (CTE2) of the light-emitting element (LE). The second connecting electrode (BE2) may have a shape and / or inclination corresponding to the second side portion of the light-emitting element (LE) on the second side portion of the light-emitting element (LE).

[0244] Additionally, the second connecting electrode (BE2) may come into contact with the second reflective electrode (RFL2) on the common electrode (CE). For example, another part of the second connecting electrode (BE2) (for example, the other end of the second connecting electrode (BE2) placed on a part of the common electrode (CE) not covered by the eighth insulating layer (132)) may be placed directly on a part of the second reflective electrode (RFL2) not covered by the eighth insulating layer (132). Accordingly, the second connecting electrode (BE2) may be electrically connected to the second reflective electrode (RFL2) and may be electrically connected to the common electrode (CE) through the second reflective electrode (RFL2). In another embodiment, when the subpixel (SPX) does not include the second reflective electrode (RFL2) or the common electrode (CE) and the second reflective electrode (RFL2) are integrated, the second connecting electrode (BE2) may be electrically connected to the common electrode (CE) by contacting the common electrode (CE) on a part of the common electrode (CE) that is not covered by the eighth insulating layer (132).

[0245] Each of the first connecting electrode (BE1) and the second connecting electrode (BE2) may comprise at least one conductive material, such as a transparent conductive material (e.g., Transparent Conductive Oxide (TCO)) such as indium-tin oxide (ITO) or indium-zinc oxide (IZO). Alternatively, each of the first connecting electrode (BE1) and the second connecting electrode (BE2) may comprise any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0246] The conductive layer (E1) of the light-emitting element (LE) is in contact with and / or connected to a first contact electrode (CTE1) and can be electrically connected to a first connecting electrode (BE1) through the first contact electrode (CTE1). The second semiconductor layer (SEM2) of the light-emitting element (LE) is in contact with and / or connected to a second contact electrode (CTE2) formed in a hole (LEH) and can be electrically connected to a second connecting electrode (BE2) through the second contact electrode (CTE2).

[0247] Light-transmitting patterns (OC) may be placed on connecting electrodes (BE). For example, a first pattern (OC1) (e.g., a first light-transmitting pattern or a first barrier) may be placed on a first connecting electrode (BE1), and a second pattern (OC2) (e.g., a second light-transmitting pattern or a second barrier) may be placed on a second connecting electrode (BE2). The first pattern (OC1) has a planar shape corresponding to the first connecting electrode (BE1) and may cover the first connecting electrode (BE1). The second pattern (OC2) has a planar shape corresponding to the second connecting electrode (BE2) and may cover the second connecting electrode (BE2).

[0248] The first pattern (OC1) and the second pattern (OC2) may surround different parts of the light-emitting element (LE) and may be spaced apart from each other with the light-emitting element (LE) in between. For example, as illustrated in FIGS. 6 and 7, the first pattern (OC1) may surround a first side portion of the light-emitting element (LE) (for example, a side portion of the light-emitting element (LE) placed on a pixel electrode (PXE)), and the second pattern (OC2) may surround a second side portion of the light-emitting element (LE) (for example, a side portion of the light-emitting element (LE) placed on a common electrode (CE). Additionally, the first pattern (OC1) and the second pattern (OC2) may not be placed on a third side portion of the light-emitting element (LE), including a side portion that does not overlap with the pixel electrode (PXE) and the common electrode (CE), and may be spaced apart from each other with the third side portion of the light-emitting element (LE) in between.

[0249] In one embodiment, the light-transmitting patterns (OC) may include sides with an inverse taper shape. For example, each of the first pattern (OC1) and the second pattern (OC2) may include sides with an inverse taper shape at a portion located opposite the light-emitting element (LE). For example, each of the first pattern (OC1) and the second pattern (OC2) may have a shape in which the width gradually increases toward the top from the outer portion of the light-emitting region (EA) (for example, the boundary between the light-emitting region (EA) and the non-light-emitting region (NEA)).

[0250] In one embodiment, the light-transmitting patterns (OC) may include a negative-type photoresist material and may include a side with an inverse taper shape. Additionally, the light-transmitting patterns (OC) may include a light-transmitting organic material and may include a surface with a smooth shape. For example, among the negative-type photoresist materials, a light-transmitting organic material that allows light emitted from a light-emitting element (LE) to pass through may be used to form a first pattern (OC1) and a second pattern (OC2). Accordingly, each of the first pattern (OC1) and the second pattern (OC2) may be formed as a smooth pattern having an overall inverse taper shape and may be formed as a light-transmitting pattern that allows light emitted from the light-emitting element (LE) to pass through. In one embodiment, the light-transmitting patterns (OC) may include a light-transmitting organic material such as an epoxy resin, an acrylic resin, or an imide resin, but is not limited thereto.

[0251] In one embodiment, the angle range in which the sides of the light-emitting patterns (OC) are tilted can be appropriately adjusted or changed by controlling process conditions applied to the process of forming the light-emitting patterns (OC). For example, the first pattern (OC1) and the second pattern (OC2) can be formed such that the sides of the first pattern (OC1) and the second pattern (OC2), which are placed in the outer part of the light-emitting region (EA), each have an angle in the range of approximately and / or generally 100° to 120° with respect to the pixel electrode (PXE) and the common electrode (CE).

[0252] The side of the light-emitting patterns (OC) that contacts each connecting electrode (BE) may have a shape and / or slope corresponding to the connecting electrode (BE). For example, the inner surface of the first pattern (OC1) that contacts the first connecting electrode (BE1) on the first side portion of the light-emitting element (LE) may have a shape and / or slope corresponding to the shape and / or slope of the first side portion of the light-emitting element (LE) and the first connecting electrode (BE1). Additionally, the inner surface of the second pattern (OC2) that contacts the second connecting electrode (BE2) on the second side portion of the light-emitting element (LE) may have a shape and / or slope corresponding to the shape and / or slope of the second side portion of the light-emitting element (LE) and the second connecting electrode (BE2).

[0253] In one embodiment, the light-transmitting patterns (OC) may be formed with a thickness and height suitable for eliminating or mitigating the step caused by the light-emitting elements (LE). For example, the light-transmitting patterns (OC) may be formed with a height similar to that of the light-emitting elements (LE) to surround the sides of the light-emitting elements (LE). The step caused by the light-transmitting patterns (OC) can be mitigated.

[0254] In one embodiment, the light-transmitting patterns (OC) can be used as a mask to form the connecting electrodes (BE), and accordingly, can be formed in a shape corresponding to the shape of the connecting electrodes (BE). For example, the light-transmitting patterns (OC) and the connecting electrodes (BE) may have substantially the same or similar shapes when viewed in a planar view, and may have substantially the same or similar areas.

[0255] In one embodiment, when connecting electrodes (BE) are formed using light-transmitting patterns (OC) as a mask, the portion of the conductive film for forming the connecting electrodes (BE) that is covered by the light-transmitting patterns (OC) may remain and become each connecting electrode (BE). In this case, the connecting electrodes (BE) may be placed at a height less than or equal to the height of the light-transmitting patterns (OC), and the upper surface of the connecting electrodes (BE) may be generally covered by the light-transmitting patterns (OC). For example, the first pattern (OC1) may be formed at a height greater than the height of the first connecting electrode (BE1) to cover the first connecting electrode (BE1), and the second pattern (OC2) may be formed at a height greater than the height of the second connecting electrode (BE2) to cover the second connecting electrode (BE2). In one embodiment, one end of each of the first connecting electrode (BE1) and the second connecting electrode (BE2) that contacts the upper surface of the light-emitting element (LE) may not be covered by the first pattern (OC1) and the second pattern (OC2).

[0256] A ninth insulating layer (134) may be disposed on the light-emitting elements (LE) and light-transmitting patterns (OC). For example, the ninth insulating layer (134) may cover the pixel electrodes (PXE), common electrode (CE), reflective electrodes (RFL), light-emitting elements (LE), and light-transmitting patterns (OC) in their entirety.

[0257] The ninth insulating layer (134) may include at least one insulating material. For example, the ninth insulating layer (134) may include an inorganic insulating material (e.g., silicon oxynitride (SiON), etc.) suitable for protecting pixel electrodes (PXE), a common electrode (CE), reflective electrodes (RFL), light-emitting elements (LE), and light-transmitting patterns (OC).

[0258] Reflective films (RF) may be disposed on the ninth insulating layer (134). The reflective films (RF) may be disposed on the sides of the light-transmitting patterns (OC). For example, a first reflective film (RF1) may be disposed on the side of a first pattern (OC1) located in the outer part of the light-emitting region (EA) and on a part of the ninth insulating layer (134) covering the side of the first pattern (OC1), and a second reflective film (RF2) may be disposed on the side of a second pattern (OC2) located in the outer part of the light-emitting region (EA) and on a part of the ninth insulating layer (134) covering the side of the second pattern (OC2). The first reflective film (RF1) and the second reflective film (RF2) may face each other with the light-emitting element (LE), the first connecting electrode (BE1) and the second connecting electrode (BE2), and the first pattern (OC1) and the second pattern (OC2) in between.

[0259] The reflective films (RF) may include a material with high reflectivity to light emitted from the light-emitting element (LE). For example, the reflective films (RF) may include aluminum (Al) or other metals with high light reflectivity. However, the embodiments are not limited thereto. In one example, in another embodiment, the reflective films (RF) may consist of inorganic films having different refractive indices and arranged alternately (for example, silicon nitride (SiN2)). x ), silicon nitride oxide (SiON), silicon oxide (SiO x ), titanium oxide (TiO₂) x ), or aluminum oxide (AlO x It may also be formed as a dispersed Bragg reflector including )).

[0260] Reflective films (RF) can reflect light (e.g., side light) that travels in a lateral direction by passing through light transmission patterns (OC) among the light emitted from the light-emitting element (LE). Accordingly, the amount of light emitted in an upward direction from each subpixel (SPX) can be increased, thereby improving the light efficiency of the subpixel (SPX).

[0261] Reflective films (RF) may have a shape and / or slope corresponding to the side shape of the light-transmitting patterns (OC). For example, a first reflective film (RF1) may have a shape and / or slope corresponding to the side shape of the first pattern (OC1) and may surround a first side portion of the light-emitting element (LE). A second reflective film (RF2) may have a shape and / or slope corresponding to the side shape of the second pattern (OC2) and may surround a second side portion of the light-emitting element (LE).

[0262] In one embodiment, the first pattern (OC1) includes an inverted tapered side having an angle of approximately 100° to 120° with respect to the pixel electrode (PXE), and the first reflective film (RF1) may be inclined at an angle (θ1) of approximately 100° to 120° with respect to the pixel electrode (PXE). For example, the first reflective film (RF1) may move away from the central portion of the light-emitting region (EA) as it extends from the lower portion adjacent to the backplane layer (120) to the upper portion adjacent to the optical layer (140). Additionally, the angle formed between at least one portion of the first reflective film (RF1) and the pixel electrode (PXE) may be 100° to 120°. The second pattern (OC2) includes an inverted tapered side having an angle of approximately 100° to 120° with respect to the common electrode (CE), and the second reflective film (RF2) may be inclined at an angle (θ2) of approximately 100° to 120° with respect to the common electrode (CE). For example, the second reflective film (RF2) may move away from the central portion of the light-emitting region (EA) as it moves from the lower portion adjacent to the backplane layer (120) to the upper portion adjacent to the optical layer (140). Additionally, the angle formed by at least one portion of the second reflective film (RF2) and the common electrode (CE) may be 100° to 120°.

[0263] As in the embodiments, when the first reflective film (RF1) and the second reflective film (RF2) are tilted at an angle (θ1, θ2) of approximately 100° to 120° with respect to the pixel electrode (PXE) and the common electrode (CE), the light reflectance by the reflective films (RF) can be effectively improved (e.g., increased or optimized). On the other hand, when the angle formed by the pixel electrode (PXE) and the common electrode (CE) and the reflective films (RF) is less than 100°, the effect of improving the light efficiency of the subpixel (SPX) by the light reflected by the reflective films (RF) is reduced, making it difficult to obtain a significant effect. In addition, if the angle formed by the pixel electrode (PXE), the common electrode (CE), and the reflective films (RF) is greater than 120°, the process of forming the first pattern (OC1) and the second pattern (OC2) in a corresponding shape may become difficult, and as the width of the upper surface of the first pattern (OC1) and the second pattern (OC2) increases, the distance between the upper part of the first reflective film (RF1) and the second reflective film (RF2) and the light-emitting element (LE) increases, and the effect of improving the light efficiency of the subpixel (SPX) by the reflective films (RF) may be reduced.

[0264] In one embodiment, the angle (θ1) formed by the first reflective film (RF1) and the pixel electrode (PXE) may be the same as the angle (θ2) formed by the second reflective film (RF2) and the common electrode (CE), but is not limited thereto. In one embodiment, the angle (θ1) formed by the first reflective film (RF1) and the pixel electrode (PXE) and the angle (θ2) formed by the second reflective film (RF2) and the common electrode (CE) may be approximately 110°, thereby maximizing the light efficiency improvement effect by the first reflective film (RF1) and the second reflective film (RF2). However, the embodiments are not limited thereto. For example, an angle range in which the light efficiency improvement effect by the first reflective film (RF1) and the second reflective film (RF2) can be optimized in each display panel (100) may be derived, and light-transmitting patterns (OC) and reflective films (RF) may be formed in a corresponding form.

[0265] A light-blocking layer (BM) may be disposed on the ninth insulating layer (134) and the reflective films (RF). The light-blocking layer (BM) may be disposed in a non-emissive region (NEA) and may surround an emissive region (EA) in which a light-emitting element (LE) is disposed. For example, the light-blocking layer (BM) may be disposed on at least the side of the first pattern (OC1) and the first reflective film (RF1), and on the side of the second pattern (OC2) and the second reflective film (RF2). Accordingly, the light-blocking layer (BM) may surround at least one part of the light-emitting element (LE), including the first side portion and the second side portion.

[0266] The light-blocking layer (BM) may include a light-blocking material such as an inorganic black pigment, such as carbon black, or an organic black pigment. The light-blocking layer (BM) may include organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin, but is not limited thereto. In one embodiment, the display panel (100) may further include a capping layer (e.g., an inorganic film) disposed on the light-blocking layer (BM).

[0267] A first overcoat layer (136) may be formed on the ninth insulating layer (134) and the light-blocking layer (BM). The first overcoat layer (136) may include a light-transmitting organic material (e.g., acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin), but is not limited thereto. The upper surface of the first overcoat layer (136) may be substantially flat.

[0268] An optical layer (140) may be disposed on the first overcoat layer (136). The optical layer (140) may include color filters corresponding to the emission color of each of the subpixels (SPX) (for example, first, second, and third color filters (CF1, CF2, CF3)), and a second overcoat layer (142) covering the color filters.

[0269] In one embodiment, a light-emitting element (LE) emits light of a color corresponding to the light-emitting color of each subpixel (SPX), and a color filter that selectively transmits light of a color corresponding to the light-emitting color of the light-emitting element (LE) may be disposed on each light-emitting element (LE). For example, a first color filter (CF1) that selectively transmits light of a first color emitted from the first light-emitting element (LE1) may be disposed on the first light-emitting element (LE1) of the first subpixel (SPX1).

[0270] In another embodiment, a light-emitting element (LE) of at least one subpixel (SPX) emits light of a color different from the light-emitting color of the said subpixel (SPX), and a light-converting layer (e.g., a wavelength-converting layer) including wavelength-converting particles may be disposed on the light-emitting element (LE) of the said at least one subpixel (SPX). For example, the optical layer (140) may further include a light-converting layer disposed between the light-emitting element (LE) of the said subpixel (SPX) and a color filter, which converts the light emitted from the light-emitting element (LE) into light corresponding to the light-emitting color of the said subpixel (SPX).

[0271] FIG. 7 illustrates an embodiment in which the optical layer (140) includes color filters and does not include a light conversion layer.

[0272] Specifically, color filters of subpixels (SPX) may be disposed on the first overcoat layer (136). For example, a first color filter (CF1) that selectively transmits light of a first color may be disposed in the light-emitting region (EA) of the first subpixel (SPX1). A second color filter (CF2) that selectively transmits light of a second color may be disposed in the light-emitting region (EA) of the second subpixel (SPX2), and a third color filter (CF3) that selectively transmits light of a third color may be disposed in the light-emitting region (EA) of the third subpixel (SPX3).

[0273] In one embodiment, the color filters of the subpixels (SPX) may be arranged to overlap each other in the non-emissive region (NEA) to form a light-blocking pattern. For example, the first color filter (CF1), the second color filter (CF2), and the third color filter (CF3), which are arranged in the emissive region (EA) of the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3), respectively, may overlap each other in the non-emissive region (NEA). The second color filter (CF2) may selectively transmit light of a second color corresponding to the emitted color of the second subpixel (SPX2), and the third color filter (CF3) may selectively transmit light of a third color corresponding to the emitted color of the third subpixel (SPX3).

[0274] A second overcoat layer (142) may be disposed on the first color filter (CF1), the second color filter (CF2), and the third color filter (CF3). In one embodiment, the second overcoat layer (142) may include a light-transmitting organic material, but is not limited thereto. The upper surface of the second overcoat layer (142) may be substantially flat.

[0275] FIGS. 9 to 19 are cross-sectional views showing a method for manufacturing a display device according to one embodiment. For example, FIGS. 9 to 19 sequentially show manufacturing steps for forming a light-emitting element layer (130) among manufacturing steps for manufacturing a display panel (100) according to the embodiment of FIG. 7.

[0276] Referring to FIG. 9 in addition to FIG. 1 to 8, a pixel electrode layer (PCDL) can be formed on a substrate (110). For example, a backplane layer (120) can be formed on the substrate (110), and a pixel electrode (PXE) and a common electrode (CE) for each of the subpixels (SPX) can be formed on the backplane layer (120).

[0277] Patterns of the pixel electrode layer (PCDL) can be formed as single-layer or multi-layer patterns using at least one conductive material. For example, after forming a single-layer or multi-layer conductive film on the backplane layer (120) using at least one conductive material suitable for forming pixel electrodes (PXE) and a common electrode (CE) (e.g., formed over the entire surface), a patterning process including an etching process of the conductive film can be performed to form the conductive film into patterns of the pixel electrode layer (PCDL).

[0278] Referring to FIG. 10, reflective electrodes (RFL) can be formed on a pixel electrode layer (PCDL). For example, a first reflective electrode (RFL1) can be formed on a portion of each pixel electrode (PXE), and a second reflective electrode (RFL2) can be formed on a portion of a common electrode (CE). In one embodiment, the reflective electrodes (RFL) can be formed using a conductive material such as a metal. For example, reflective electrodes (RFL) can be formed on the pixel electrode layer (PCDL) by performing a film deposition process and a patterning process of a conductive film using at least one conductive material including a metal with high reflectivity.

[0279] Referring to FIG. 11, an eighth insulating layer (132) (e.g., an adhesive layer or a bonding layer) can be formed on the pixel electrode layer (PCDL) and the reflective electrodes (RFL). For example, the eighth insulating layer (132) can be formed on a portion of the light-emitting region (EA) including the light-emitting region where each light-emitting element (LE) is to be placed, using an organic insulating material having adhesive properties. The eighth insulating layer (132) can cover a portion of each pixel electrode (PXE) and the common electrode (CE). When the display panel (100) includes a first reflective electrode (RFL1) and a second reflective electrode (RFL2) placed below the light-emitting element (LE), the eighth insulating layer (132) can cover a portion of the first reflective electrode (RFL1) and the second reflective electrode (RFL2).

[0280] Referring to FIG. 12, each light-emitting element (LE) of each subpixel (SPX) can be placed on the eighth insulating layer (132). In one embodiment, the light-emitting elements (LE) can be formed by growing on a semiconductor substrate such as a silicon substrate or a sapphire substrate, and then transferred onto the pixel electrodes (PXE) and common electrode (CE) of the display panel (100). Each light-emitting element (LE) can be placed in each light-emitting element region (LEA) and can be supported by the eighth insulating layer (132). In one embodiment, each light-emitting element (LE) may be a flip-chip type light-emitting element comprising a semiconductor stack (STC) as shown in FIG. 8, and a first contact electrode (CTE1) and a second contact electrode (CTE2) placed on the side of the semiconductor stack (STC).

[0281] Referring to FIG. 13, a conductive film (CDL) can be formed on pixel electrodes (PXE), a common electrode (CE), reflective electrodes (RFL), an eighth insulating layer (132), and light-emitting elements (LE). The conductive film (CDL) is intended to form connecting electrodes (BE) and can be formed using at least one conductive material previously exemplified as the material of the connecting electrodes (BE). For example, the conductive film (CDL) can be formed by depositing a transparent conductive oxide, such as indium-zinc oxide (IZO), or other conductive material, over the entire display area (DA) where the light-emitting elements (LE) are placed. In one embodiment, the conductive film (CDL) can be formed by a sputtering method, but the material or method of forming the conductive film (CDL) is not limited thereto.

[0282] Referring to FIG. 14, light-transmitting patterns (OC) including a first pattern (OC1) and a second pattern (OC2) can be formed on a conductive film (CDL). The first pattern (OC1) can be formed to surround a first side portion of a light-emitting element (LE) including a first contact electrode (CTE1). For example, the first pattern (OC1) can be formed around the first side portion of the light-emitting element (LE) and on a portion of the first reflective electrode (RFL1) (or pixel electrode (PXE)) that is not covered by the eighth insulating layer (132). The second pattern (OC2) can be formed to surround a second side portion of the light-emitting element (LE) including a second contact electrode (CTE2). For example, the second pattern (OC2) may be formed around the perimeter of the second side portion of the light-emitting element (LE) and on a portion of the second reflective electrode (RFL2) (or common electrode (CE)) that is not covered by the eighth insulating layer (132). The light-transmitting patterns (OC) may be formed with a thickness and height suitable for mitigating the step difference caused by the light-emitting element (LE) of each subpixel (SPX).

[0283] In one embodiment, a first pattern (OC1) and a second pattern (OC2) can be formed by a photolithography process using a negative-type photoresist material (for example, a transparent organic material among negative-type photoresist materials). Accordingly, each of the first pattern (OC1) and the second pattern (OC2) can be formed to include a side with an inverted taper shape.

[0284] By using a negative-type photoresist material to form light-transmitting patterns (OC), each light-transmitting pattern (OC) can be properly formed at a target location, and the photoresist material can be stably removed from other areas. For example, after forming a photoresist film by applying the photoresist material over the entire surface of a conductive film (CDL), light can be irradiated onto the photoresist film only at the locations where the first connecting electrode (BE1) and the second connecting electrode (BE2) are to be formed, respectively. Accordingly, the first pattern (OC1) and the second pattern (OC2) can be formed at the locations where the first connecting electrode (BE1) and the second connecting electrode (BE2) are to be formed, respectively.

[0285] When light-transmitting patterns (OC) are formed using a negative-type photoresist material, light may not be irradiated onto the photoresist film in locations where connecting electrodes (BE) are not formed, such as around the third side portion of the light-emitting element (LE). Accordingly, the photoresist film covering the third side portion of the light-emitting element (LE) is properly removed during the development process, thereby preventing residue of the photoresist film from remaining on the third side portion of the light-emitting element (LE).

[0286] In one embodiment, the shape of the first pattern (OC1) and the second pattern (OC2) can be controlled by controlling the formation process of the first pattern (OC1) and the second pattern (OC2). For example, the side shape of the first pattern (OC1) and the second pattern (OC2) can be controlled by controlling the conditions of the photolithography process for forming the first pattern (OC1) and the second pattern (OC2). In one embodiment, the first pattern (OC1) and the second pattern (OC2) may each be formed in a shape including a side angle tilted at an angle of approximately and / or generally in the range of 100° to 120° with respect to the pixel electrode (PXE) and the common electrode (CE).

[0287] Referring to FIG. 15, connecting electrodes (BE) can be formed below light-transmitting patterns (OC). For example, by etching a conductive film (CDL) using light-transmitting patterns (OC) as a mask, connecting electrodes (BE) of a shape and size corresponding to the shape of the light-transmitting patterns (OC) can be formed below each of the light-transmitting patterns (OC). As an example, the conductive film (CDL) can be patterned into a first connecting electrode (BE1) and a second connecting electrode (BE2) by performing a wet etching process using a first pattern (OC1) and a second pattern (OC2) placed in each light-emitting region (EA) as a mask. Accordingly, a first connecting electrode (BE1) can be formed below the first pattern (OC1), and a second connecting electrode (BE2) can be formed below the second pattern (OC2).

[0288] Accordingly, the first connecting electrode (BE1) may be formed to surround a first side portion of the light-emitting element (LE) including a first contact electrode (CTE1). For example, the first connecting electrode (BE1) may be formed around the first side portion of the light-emitting element (LE) and on a portion of the first reflective electrode (RFL1) (or pixel electrode (PXE)) that is not covered by the eighth insulating layer (132). The first connecting electrode (BE1) may connect the first contact electrode (CTE1) of the light-emitting element (LE) and the pixel electrode (PXE). For example, the first connecting electrode (BE1) may be electrically connected between the first reflective electrode (RFL1) connected to the pixel electrode (PXE) and the first contact electrode (CTE1) of the light-emitting element (LE).

[0289] The second connecting electrode (BE2) may be formed to surround a second side portion of the light-emitting element (LE) including a second contact electrode (CTE2). For example, the second connecting electrode (BE2) may be formed around the perimeter of the second side portion of the light-emitting element (LE) and on a portion of the second reflective electrode (RFL2) (or common electrode (CE)) that is not covered by the eighth insulating layer (132). The second connecting electrode (BE2) may connect the second contact electrode (CTE2) of the light-emitting element (LE) and the common electrode (CE). For example, the second connecting electrode (BE2) may be electrically connected between the second reflective electrode (RFL2) connected to the common electrode (CE) and the second contact electrode (CTE2) of the light-emitting element (LE).

[0290] In the process of forming the light-transmitting patterns (OC) performed above, by using a negative-type photoresist material to form the light-transmitting patterns (OC), no residue of the photoresist film may remain on the third side portion of the light-emitting element (LE). Accordingly, the conductive film (CDL) is properly removed from the portion covering the third side portion of the light-emitting element (LE), thereby allowing the first connecting electrode (BE1) and the second connecting electrode (BE2) to be stably separated. Accordingly, electrical stability (e.g., insulation) between the first connecting electrode (BE1) and the second connecting electrode (BE2) can be secured.

[0291] On the other hand, if light-transmitting patterns (OC) are formed using a positive-type photoresist material and the light-transmitting patterns (OC) are utilized as a mask to form connecting electrodes (BE), or if the connecting electrodes (BE) are formed using a separate mask pattern formed from a positive-type photoresist material, there is a risk of a short circuit defect occurring between the first connecting electrode (BE1) and the second connecting electrode (BE2). For example, when etching a conductive film (CDL) using patterns containing a positive-type photoresist material as a mask, a residue of the photoresist film may remain on the third side portion of the light-emitting element (LE). Consequently, there is a risk that the first connecting electrode (BE1) and the second connecting electrode (BE2) may not be properly separated and a short circuit defect may occur.

[0292] Referring to FIG. 16, a ninth insulating layer (134) can be formed on light-emitting elements (LE) and light-transmitting patterns (OC). For example, the ninth insulating layer (134) can be formed over the pixel electrodes (PXE), common electrode (CE), reflective electrodes (RFL), light-emitting elements (LE), and light-transmitting patterns (OC).

[0293] The ninth insulating layer (134) may be formed with a material and thickness suitable for protecting electrodes, patterns and / or light-emitting elements (LE) disposed on the light-emitting element layer (130). In one embodiment, the ninth insulating layer (134) may be formed as a thin film using at least one inorganic insulating material (e.g., silicon oxynitride (SiON), etc.).

[0294] Referring to FIG. 17, reflective films (RF) can be formed on the sides of light-transmitting patterns (OC). For example, a first reflective film (RF1) can be formed on a portion of the ninth insulating layer (134) covering the side of the first pattern (OC1), and a second reflective film (RF2) can be formed on another portion of the ninth insulating layer (134) covering the side of the second pattern (OC2). The first reflective film (RF1) and the second reflective film (RF2) can be formed using the material previously exemplified as the material for the reflective films (RF).

[0295] The first reflective film (RF1) and the second reflective film (RF2) may each have a shape and / or inclination corresponding to the side shape of the first pattern (OC1) and the second pattern (OC2). For example, the first reflective film (RF1) may be tilted at an angle of approximately 100° to 120° (θ1 in FIG. 7) with respect to the pixel electrode (PXE), and the second reflective film (RF2) may be tilted at an angle of approximately 100° to 120° (θ2 in FIG. 7) with respect to the common electrode (CE).

[0296] Referring to FIG. 18, a light-blocking layer (BM) can be formed in a non-emissive region (NEA). For example, a light-blocking layer (BM) can be formed on the sides of light-transmitting patterns (OC) and reflective films (RF). The light-blocking layer (BM) can surround at least one portion of the light-emitting element (LE). For example, the light-blocking layer (BM) can surround a first side portion and a second side portion of the light-emitting element (LE). In one embodiment, the light-blocking layer (BM) may also be placed on both sides of a third side portion of the light-emitting element (LE), but is not limited thereto. The light-blocking layer (BM) can be formed using the material previously exemplified as the material of the light-blocking layer (BM).

[0297] Referring to FIG. 19, a first overcoat layer (136) can be formed on the ninth insulating layer (134) and the light-blocking layer (BM). The first overcoat layer (136) can be formed using a light-transmitting material (e.g., a light-transmitting organic material) as previously illustrated, and the upper surface of the first overcoat layer (136) can be substantially flat.

[0298] With reference to FIGS. 9 to 19, a light-emitting element layer (130) of a display panel (100) according to one embodiment can be formed by the process described above. Subsequently, an optical layer (140) of FIG. 7 can be formed on the light-emitting element layer (130). Accordingly, a display panel (100) according to the embodiment of FIG. 7 can be manufactured.

[0299] As described above, the display device (1) according to the embodiments may include a first connecting electrode (BE1) connecting a part of the light-emitting element (LE) (e.g., a first contact electrode (CTE1)) and a pixel electrode (PXE), a second connecting electrode (BE2) connecting a different part of the light-emitting element (LE) (e.g., a second contact electrode (CTE2)) and a common electrode (CE), a first pattern (OC1) disposed on the first connecting electrode (BE1), and a second pattern (OC2) disposed on the second connecting electrode (BE2) and spaced apart from the first pattern (OC1). In some embodiments, the first connecting electrode (BE1) and the second connecting electrode (BE2) may be formed below the first pattern (OC1) and the second pattern (OC2), respectively, by utilizing the first pattern (OC1) and the second pattern (OC2). According to the display device (1) and the method of manufacturing the same according to the embodiments, the first connecting electrode (BE1) and the second connecting electrode (BE2) can be stably separated to prevent short circuit defects between the pixel electrode (PXE) and the common electrode (CE), and the reliability of the display device (1) can be secured.

[0300] In some embodiments, the first pattern (OC1) and the second pattern (OC2) surround different side portions of the light-emitting element (LE) and may include sides with an inverse taper shape. In some embodiments, by forming the first pattern (OC1) and the second pattern (OC2) using a negative type photoresist material, the first pattern (OC1) and the second pattern (OC2) can be formed appropriately and / or easily in a desired shape, and the first pattern (OC1) and the second pattern (OC2) can be reliably separated.

[0301] In some embodiments, the display device (1) may further include a first reflective film (RF1) disposed on the side of a first pattern (OC1) and a second reflective film (RF2) disposed on the side of a second pattern (OC2). The first reflective film (RF1) and the second reflective film (RF2) may be tilted in a shape or angle corresponding to the side of the first pattern (OC1) and the second pattern (OC2), respectively, with respect to the pixel electrode (PXE) and the common electrode (CE). For example, the first reflective film (RF1) and the second reflective film (RF2) may be tilted at an angle greater than 90° with respect to the pixel electrode (PXE) and the common electrode (CE), for example, in the range of 100° to 120°. By doing so, light traveling in a lateral direction toward the first reflective film (RF1) and the second reflective film (RF2) can be effectively reflected, and the light emission rate of the subpixel (SPX) can be increased. According to the display device (1) and the method of manufacturing the same according to the embodiments, the light efficiency of the display device (1) can be improved.

[0302] A display device (1) according to at least one of the embodiments described above may be applied to various electronic devices. An electronic device according to one embodiment may include the display device (1) described above (or a display module including a display panel (100) according to at least one embodiment), and may further include a module or device having additional functions other than the display device (1).

[0303] For example, the electronic device may include a display panel (100) including a first pattern (OC1) and a second pattern (OC2) according to the embodiments. Accordingly, short circuit defects between the pixel electrode (PXE) and the common electrode (CE) can be prevented, and the reliability of the electronic device can be ensured. In some embodiments, the electronic device may further include a first reflective film (RF1) and a second reflective film (RF2) according to the embodiments. Accordingly, the light efficiency of the electronic device can be improved.

[0304] FIG. 20 is a block diagram of an electronic device according to one embodiment. Referring to FIG. 20, an electronic device (10) according to one embodiment may include a display module (11), a processor (12), a memory (13), and a power module (14).

[0305] The electronic device (10) can output various information in the form of an image through the display module (11). For example, when the processor (12) executes an application stored in memory (13), the image information provided by the application can be provided to the user through the display module (11).

[0306] The display module (11) may include a display panel (100) for displaying an image. For example, the display module (11) may include a display panel (100) according to at least one of the embodiments described above.

[0307] The processor (12) may include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0308] The memory (15) may store data information necessary for the operation of the processor (12) or the display module (11). For example, the memory (15) may store image data signals and / or input control signals.

[0309] The processor (12) can control the display module (11) using information stored in the memory (15). The processor (12) can transmit video data signals and / or input control signals stored in the memory (15) to the display module (11). For example, when the processor (12) executes an application stored in the memory (15), video data signals and / or input control signals are transmitted to the display module (11), and the display module (11) can process the received signals and output video information through a display screen.

[0310] The power module (14) may include a power supply module, such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate power necessary for the operation of the electronic device (10).

[0311] At least one of each component of the electronic device (10) described above may be included in the display device (1) according to the embodiments described above. Additionally, some of the individual modules functionally included in one module may be included in the display device (1), while others may be provided separately from the display device (1). For example, the display device (1) may include a display module (11), and the processor (12), memory (13), and power module (14) may be provided in the form of other devices within the electronic device (10) other than the display device (1).

[0312] FIG. 21 is a schematic diagram of an electronic device according to various embodiments.

[0313] Referring to FIG. 21, various electronic devices to which the display device (1) according to the embodiments is applied may include not only image display electronic devices such as a smartphone (10_1a), tablet PC (10_1b), laptop (10_1c), TV (10_1d), and desk monitor (10_1e), but also wearable electronic devices including display modules such as smart glasses (10_2a), head-mounted display (10_2b), and smart watch (10_2c), and automotive electronic devices (10_3) including display modules such as a CID (Center Information Display) and room mirror display placed on the instrument panel, center fascia, and dashboard of a car.

[0314] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims

1. Pixel electrodes and a common electrode disposed on a substrate; An insulating layer disposed on a portion of each of the pixel electrode and the common electrode; A light-emitting element disposed on the insulating layer and comprising a semiconductor stack and a first contact electrode and a second contact electrode disposed on the side of the semiconductor stack; A first connecting electrode disposed on a first side portion including the first contact electrode among the sides of the light-emitting element and on the insulating layer, and connecting the first contact electrode and the pixel electrode; A second connecting electrode disposed on a second side portion including the second contact electrode among the sides of the light-emitting element and on the insulating layer, and connecting the second contact electrode and the common electrode; A first pattern disposed on the first connecting electrode and surrounding the first side portion of the light-emitting element; and A display device comprising a second pattern spaced apart from the first pattern, which is disposed on the second connecting electrode and surrounds the second side portion of the light-emitting element.

2. In Paragraph 1, A display device comprising the first pattern and the second pattern, the first pattern and the second pattern, respectively, a negative type photoresist material and a side with an inverse taper shape.

3. In Paragraph 2, A first reflective film disposed on the side of the first pattern and surrounding the first side portion of the light-emitting element; and A display device further comprising a second reflective film disposed on the side of the second pattern and surrounding the second side portion of the light-emitting element.

4. In Paragraph 3, The angle formed by at least a portion of the first reflective film and the pixel electrode is 100° to 120°, and A display device in which the angle formed by at least a portion of the second reflective film and the common electrode is 100° to 120°.

5. In Paragraph 1, A display device comprising a first pattern and a second pattern, wherein the first pattern and the second pattern include a transparent organic material through which light emitted from the light-emitting element can pass.

6. In Paragraph 1, The height of the first pattern is greater than or equal to the height of the first connecting electrode, and A display device in which the height of the second pattern is greater than or equal to the height of the second connecting electrode.

7. In Paragraph 1, The first pattern above has a shape and size corresponding to the first connecting electrode when viewed from above, The above second pattern is a display device having a shape and size corresponding to the second connecting electrode when viewed from above.

8. In Paragraph 1, The side of the light-emitting element further includes a third side portion between the first side portion and the second side portion, and A display device in which the first connecting electrode and the second connecting electrode are spaced apart from each other with the third side portion of the light-emitting element in between.

9. In Paragraph 8, A display device in which the first pattern and the second pattern are spaced apart from each other with the third side portion of the light-emitting element in between.

10. In Paragraph 1, It further includes a light-blocking layer disposed on the side of the first pattern and the second pattern, A display device in which the light-blocking layer surrounds at least one portion of the light-emitting element, including the first side portion and the second side portion.

11. A display module including a display panel; and It includes a processor that transmits an image data signal to the above-mentioned display module, The above display panel is, Pixel electrodes and common electrodes disposed on a substrate; An insulating layer disposed on a portion of the pixel electrode and the common electrode; A light-emitting element disposed on the insulating layer and comprising a semiconductor stack and a first contact electrode and a second contact electrode disposed on the side of the semiconductor stack; A first connecting electrode disposed on a first side portion including the first contact electrode among the sides of the light-emitting element and on the insulating layer, and connecting the first contact electrode and the pixel electrode; A second connecting electrode disposed on a second side portion including the second contact electrode among the sides of the light-emitting element and on the insulating layer, and connecting the second contact electrode and the common electrode; A first pattern disposed on the first connecting electrode and surrounding the first side portion of the light-emitting element; and An electronic device comprising a second pattern spaced apart from the first pattern, which is disposed on the second connecting electrode and surrounds the second side portion of the light-emitting element.

12. In Paragraph 11, The electronic device, wherein the first pattern and the second pattern include a negative type photoresist material and include a reverse taper-shaped side.

13. In Paragraph 12, The above display panel is, A first reflective film disposed on the side of the first pattern and surrounding the first side portion of the light-emitting element; and An electronic device further comprising a second reflective film disposed on the side of the second pattern and surrounding the second side portion of the light-emitting element.

14. In Paragraph 13, The angle formed by at least a portion of the first reflective film and the pixel electrode is 100° to 120°, and An electronic device in which the angle formed by at least a portion of the second reflective film and the common electrode is 100° to 120°.

15. In Paragraph 11, The first pattern above has a shape and size corresponding to the first connecting electrode when viewed from above, The above second pattern is an electronic device having a shape and size corresponding to the second connecting electrode when viewed from above.

16. In Paragraph 11, The above display panel further includes a light-blocking layer disposed on the side of the first pattern and the second pattern, and The above light-blocking layer surrounds at least one portion of the light-emitting element, including the first side portion and the second side portion, in an electronic device.

17. A step of forming pixel electrodes and a common electrode on a substrate; A step of forming an insulating layer covering a portion of the pixel electrode and the common electrode; A step of placing a light-emitting element including a semiconductor stack and a first contact electrode and a second contact electrode disposed on the side of the semiconductor stack on the insulating layer; A step of forming a conductive film on the pixel electrode, the common electrode, the insulating layer, and the light-emitting element; A step of forming on the conductive film a first pattern surrounding a first side portion including the first contact electrode among the sides of the light-emitting element, and a second pattern surrounding a second side portion including the second contact electrode among the sides of the light-emitting element; and A method for manufacturing a display device, comprising the step of forming a first connecting electrode that surrounds the first side portion of the light-emitting element and connects the first contact electrode and the pixel electrode, and a second connecting electrode that surrounds the second side portion of the light-emitting element and connects the second contact electrode and the common electrode, by etching the conductive film using the first pattern and the second pattern as a mask.

18. In Paragraph 17, A method for manufacturing a display device, wherein, in the step of forming the first pattern and the second pattern, a negative type photoresist material is used to form the first pattern and the second pattern in a shape including a reverse taper side.

19. In Paragraph 17, A method for manufacturing a display device, further comprising the step of forming a first reflective film and a second reflective film on the side of the first pattern and the side of the second pattern, respectively.

20. In Paragraph 17, A method for manufacturing a display device, further comprising the step of forming a light-blocking layer on the sides of the first pattern and the second pattern, the light-emitting element including the first side portion and the second side portion, and surrounding at least one portion of the light-emitting element.

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