Metal dielectric stack structure of vertical transistor, using heat treatment, and manufacturing method therefor

Abstract

The present invention relates to a metal dielectric stack structure of a vertical transistor, using heat treatment, and a manufacturing method therefor, and, more specifically, to a metal dielectric stack structure and a manufacturing method therefor, which use a method of forming a dielectric layer by oxidizing a metal electrode through heat treatment without depositing a separate dielectric material for forming the dielectric layer of a vertical transistor. When a vertical transistor is manufactured, a dielectric layer is formed on a gate metal by using oxidation of a metal through heat treatment, and thus a thin dielectric layer can be formed without a separate dielectric material for forming a dielectric layer, and a dielectric layer deposition process can be omitted. Particularly, the metal dielectric stack structure and the manufacturing method therefor can be provided, in which, even when a gate dielectric layer is formed on the inner sidewall of a hole in the center of a vertical transistor, use of heat treatment instead of deposition enables a reduction in investment costs for expensive equipment during the manufacturing process of a vertical transistor, simplification of the process, and an increase in film uniformity.

Description

Metal insulating film stacking structure of a vertical structure transistor using heat treatment and method for manufacturing the same

[0001] The present invention relates to a metal insulating film stacking structure of a vertical structure transistor using heat treatment and a method for manufacturing the same. More specifically, the invention relates to a metal insulating film stacking structure that forms an insulating film by oxidizing a metal electrode through heat treatment without depositing a separate insulating material for the formation of an insulating film of a vertical structure transistor, and a method for manufacturing the same.

[0002] While the advancement of the electronics industry and integrated circuits is leading to the sophistication of the electronics industry, power consumption increases with the increase in integration density and operating speed. Currently, thin-film transistors, which are widely used mainly in displays, are used in applications such as wearables and biosensor platforms, and various materials such as amorphous silicon, polysilicon, and oxides are being utilized and researched and developed as semiconductor materials for transistors.

[0003] Insulating films are important for these transistors, and these insulating films are mainly deposited by vacuum deposition methods. Various methods are used in addition to PECVD (plasma enhanced chemical vapor deposition), CVD (chemical vapor deposition), and ALD (atomic layer deposition). The vacuum equipment required to implement these methods is expensive, which increases investment costs and maintenance costs, contributing to the rise in production costs.

[0004] In a vertical NAND flash memory, transistors are formed in a vertical structure and an insulating film is deposited between gate metals and on the inner sidewalls of vertical holes. The present invention provides a method to eliminate such insulating film deposition process.

[0005] The present invention was devised to solve such problems, and aims to enable a thin insulating film without requiring a separate insulating material for forming the insulating film by forming an insulating film on the gate metal using metal oxidation through heat treatment when manufacturing a vertical structure transistor, and also to allow the deposition process of the insulating film to be omitted.

[0006] Another objective is to provide a metal insulating film stacked structure and a method for manufacturing the same, which can reduce investment costs for expensive equipment, simplify the process, and improve film uniformity in the manufacturing process of vertical transistors by using heat treatment instead of deposition, especially when forming a gate insulating film on the inner sidewall of the central hole of a vertical transistor.

[0007] To achieve the above objective, a method for manufacturing a metal insulating film stacked structure of a vertical structure transistor using heat treatment according to the present invention (hereinafter referred to as the "method for manufacturing a metal insulating film stacked structure") comprises: (a) a step of depositing a gate metal on a substrate; (b) a step of forming an insulating film on the surface of the gate metal; (c) a step of forming a gate metal and an insulating film in a vertical direction on the insulating film formed in step (b) in the same manner as in steps (a) and (b) in a predetermined number of layers; (d) a step of forming a vertical hole penetrating the top and bottom of the gate metal and insulating film formed vertically through steps (a) to (c); and (e) a step of forming a gate insulating film on the inner sidewall of the vertical hole through oxidation of the gate metal using heat treatment.

[0008] Each insulating film of steps (b) and (c) above can be formed on each gate metal surface through oxidation using heat treatment.

[0009] The gate metal may be any one of tantalum (Ta), hafnium (Hf), or aluminum (Al).

[0010] The heat treatment of the gate metal surface and the inner sidewall of the vertical hole can be performed in an atmosphere of any one of oxygen, nitrogen, or a mixture of oxygen and nitrogen.

[0011] The above heat treatment temperature may be a range in which no change occurs in either the substrate or the film or metal formed on the substrate.

[0012] The above heat treatment temperature may be a range in which the gate metal is thermally oxidized.

[0013] The heat treatment of the gate metal surface and the gate metal of the inner sidewall of the vertical hole can be performed at 450°C or lower.

[0014] Each insulating film of steps (b) and (c) above can be formed by depositing an insulating film as an insulating material on each gate metal.

[0015] Each insulating film of steps (b) and (c) above can be formed by depositing different first metals and second metals, and then heat-treating the deposited first metals and second metals to convert the first metal into a gate electrode and the second metal into a gate insulating film.

[0016] The above heat treatment temperature may be a range in which no change occurs in either the substrate or the film or metal formed on the substrate.

[0017] The above heat treatment may be a range in which the second metal is thermally oxidized.

[0018] The above heat treatment can be carried out in an atmosphere of any one of oxygen, nitrogen, and a mixture of oxygen and nitrogen.

[0019] The first metal mentioned above may be any one selected from the group consisting of titanium (Ti), molybdenum (Mo), or copper (Cu).

[0020] The second metal may be any one selected from the group consisting of tantalum (Ta), hafnium (Hf), or aluminum (Al).

[0021] According to another aspect of the present invention, a metal insulating film stacking structure of a vertical structure transistor (hereinafter referred to as the "first metal insulating film stacking structure") comprises: a substrate; a plurality of gate metals vertically stacked on the upper portion of the substrate; an insulating film formed on the surface of each of the stacked gate metals; a vertical hole penetrating the upper and lower portions in the central portion of the vertically formed gate metals and the insulating film; and a gate insulating film formed on the inner side wall of the vertical hole, wherein the insulating film is composed of at least one of an oxide film or a nitride film formed by transforming the stacked surface of each of the gate metals by heat treatment, and the gate insulating film is composed of at least one of an oxide film or a nitride film formed by transforming the gate metal surface exposed into the vertical hole by heat treatment.

[0022] According to another aspect of the present invention, a metal insulating film stacking structure of a vertical structure transistor (hereinafter referred to as a "second metal insulating film stacking structure") comprises: a substrate; a plurality of gate metals vertically stacked on the upper portion of the substrate; an insulating film formed on the surface of each of the stacked gate metals; a vertical hole penetrating the upper and lower portions in the central portion of the vertically formed gate metals and the insulating film; and a gate insulating film formed on the inner side wall of the vertical hole, wherein each insulating film is formed by depositing different first metals and second metals, and then heat-treating the deposited first metals and second metals to convert the first metal into a gate electrode and the second metal into an insulating film.

[0023] In the above first metal insulating film stacked structure, the gate metal may be any one of tantalum (Ta), hafnium (Hf), and aluminum (Al).

[0024] In the above second metal insulating film laminated structure, the first metal may be any one selected from the group consisting of titanium (Ti), molybdenum (Mo), or copper (Cu).

[0025] In the above second metal insulating film laminated structure, the second metal may be any one selected from the group consisting of tantalum (Ta), hafnium (Hf), or aluminum (Al).

[0026] According to the present invention, when manufacturing a vertical structure transistor, by using the oxidation of a metal through heat treatment to form an insulating film on the gate metal, a thin insulating film is made possible without requiring a separate insulating material for forming the insulating film, and the deposition process of the insulating film can be omitted.

[0027] In particular, by using heat treatment instead of deposition even when forming a gate insulating film on the inner sidewall of the central hole of a vertical transistor, it is possible to reduce the investment cost of expensive equipment in the manufacturing process of a vertical transistor, simplify the process, and improve the uniformity of the film, thereby providing a metal insulating film stacked structure and a method for manufacturing the same.

[0028] Figure 1 is a drawing showing the metal insulating film stacking structure of a typical vertical structure transistor.

[0029] FIG. 2 is a drawing showing a cross-section of the metal insulating film stacking structure of the vertical structure transistor of the present invention.

[0030] FIG. 3 is a drawing showing a cross-section of a metal insulating film stacking structure of a vertical structure transistor of the present invention, with a vertical hole formed in the center.

[0031] FIG. 4 is a drawing showing a structure in which a gate insulating film is formed on the inner sidewall of a central vertical hole of a metal insulating film stacking structure of a vertical structure transistor of the present invention using heat treatment.

[0032] Figure 5 is a graph showing the thickness of the oxide gate insulating film formed according to temperature when heat treatment is performed for 20 minutes in an oxygen atmosphere.

[0033] Preferred embodiments of the present invention will be described in detail below with reference to the attached drawings. Prior to this, terms and words used in this specification and claims should not be interpreted as being limited to their ordinary or dictionary meanings. Instead, based on the principle that the inventor can appropriately define the concepts of terms to best describe their invention, they should be interpreted in a meaning and concept consistent with the technical spirit of the present invention. Therefore, the embodiments described in this specification and the configurations illustrated in the drawings are merely one preferred embodiment of the present invention and do not represent all aspects of the technical spirit of the present invention. It should be understood that various equivalents and modifications capable of replacing them may exist at the time of filing this application.

[0034]

[0035] Figure 1 is a diagram showing the metal insulating film stacking structure of a typical vertical structure transistor.

[0036] These vertical structure transistors (100) are the basic structure of a 3D NAND flash memory, and multiple such vertical structure transistors (100) are connected to form a 3D NAND flash memory.

[0037] First, the gate metal (110) and the insulating film (120) are alternately stacked and vertically etched to form a vertical hole. 'WL' stands for 'Word Line' and refers to a wire connected to the transistor gate electrode.

[0038] Next, a gate insulating film (140) is deposited on the inner side wall of the vertical hole, and a material to form a transistor channel layer (150) is deposited thereon. As shown in FIG. 1, polysilicon is used as the transistor channel layer (150), and it is more preferable that it be an oxide semiconductor with low leakage current.

[0039]

[0040] FIG. 2 is a cross-section of the metal insulating film stacking structure of the vertical structure transistor of the present invention (hereinafter referred to as the 'metal insulating film stacking structure') before a vertical hole is formed in the center (200.1), FIG. 3 is a cross-section of the metal insulating film stacking structure of the present invention (200.2) with a vertical hole formed in the center, FIG. 4 is a diagram showing a structure (200) in which a gate insulating film (240) is formed on the inner side wall of the central vertical hole (230) of the metal insulating film stacking structure (200.2) of the present invention using heat treatment.

[0041] Structures such as the gate metal (210), insulating film (220), vertical hole (230), and gate insulating film (240) as shown in FIGS. 2 to 4 are formed on the substrate at the bottom. The substrate (10) used here utilizes an insulating material such as glass, a silicon wafer, or plastic. When using a plastic substrate, a buffer layer may be formed for heat treatment stability.

[0042] In the present invention, when forming such a metal insulating film stacked structure (200), the gate metal (210) uses a material capable of forming an insulating film through heat treatment. Various materials such as doped silicon, aluminum, tungsten, Ti, and Hf may be used. An insulating film (220) is formed by applying heat treatment to the gate metal (210).

[0043] As for the material of the gate metal (210), a material with a high dielectric constant of the formed insulating film may be preferred as needed. Such materials may include Ta, Hf, Al, etc., which facilitate the formation of an insulating film by heat treatment at particularly low temperatures, and these materials have a high dielectric constant of the formed insulating film, which helps improve the characteristics of the transistor.

[0044] At this time, the heat treatment atmosphere may use oxygen, nitrogen, or other gases, or a mixture of these gases may be used. In the case of oxygen, an oxide film is formed on the surface of the gate metal (210) as an insulating film (220), and in the case of nitrogen, a nitride film is formed on the surface of the gate metal (210) as an insulating film (220), so the gas can be selected and used according to the purpose.

[0045]

[0046] The first method for forming an insulating film (220) is as follows.

[0047] That is, an insulating film (220) is formed on the surface of the gate metal (210) by heat treatment in this manner, and then the gate metal (210) is stacked again on top of it, and then the insulating film (220) is formed on the surface of the newly stacked gate metal by heat treatment again, and the process is repeated to form a metal-insulating film repeating layer with a vertically stacked structure as shown in FIG. 2.

[0048] The heat treatment process conditions for forming such an insulating film (220) will be described in detail later with reference to FIG. 5.

[0049]

[0050] The second method for forming an insulating film (220) is as follows.

[0051] As described above in the metal insulating film stacking structure, instead of forming an insulating film (220) on the surface of the gate metal (210) by thermal oxidation of the gate metal (210) of each layer, an insulating film (220) can be formed by depositing an insulating film (220) as an insulating material on the gate metal (210).

[0052]

[0053] The third method for forming an insulating film (220) is described as follows.

[0054] A first metal and a second metal are deposited sequentially on a substrate.

[0055] The first metal is a metal to be used as the gate electrode, and titanium (Ti), molybdenum (Mo), copper (Cu), etc., which do not oxidize easily, are deposited.

[0056] The second metal deposited on the first metal is a metal that oxidizes easily due to its low Gibbs-free energy, such as tantalum (Ta), hafnium (Hf), or aluminum (Al). Using materials with high dielectric constants of oxide films, such as tantalum (Ta), hafnium (Hf), or aluminum (Al), increases the dielectric constant of the insulating film, which helps improve the characteristics of the transistor.

[0057] Here, the deposition process of the first metal and the second metal is performed using sputtering or evaporation, which are representative thin film processes, to form an evenly thin layer. At this time, the deposition thickness of the first metal (11) is adjusted to 300 nm or less to optimize the electrode resistance, and the thickness of the second metal (12) can be adjusted to 200 nm or less by considering the thickness of the oxide film to be formed after thermal oxidation.

[0058] Subsequently, when the first metal and the second metal are thermally oxidized by heat treatment, the first metal becomes a gate electrode (210) and the second metal is converted into an insulating film (220). The heat treatment can be performed at a temperature of 300°C to 1000°C for 10 minutes to 2 hours in an atmosphere of oxygen, nitrogen, or mixed gas, and is carried out within a range where the material of the substrate does not change.

[0059] The heat treatment process conditions can be applied in the same way as in the first method for forming an insulating film (220), and will be described in detail later with reference to FIG. 5.

[0060]

[0061] Afterwards, as shown in FIGS. 3 and 4, a hole (230) is formed vertically in the center of the metal insulating film stacked structure (200.1) by etching (200.2).

[0062] Afterward, heat treatment is performed in a gas atmosphere on the gate metal (210) of each layer at the inner side wall of the vertically formed hole (230) to form a gate insulating film (240) as shown in FIG. 4. The heat treatment process conditions for forming the gate insulating film (240) will be described in detail later with reference to FIG. 5.

[0063] When performing heat treatment on the inner side wall of such a vertical hole (230), the heat treatment atmosphere may use oxygen, nitrogen, or other gases, or a mixture of these gases may be used. In the case of oxygen, an oxide film is formed on the surface of the gate metal (210) as a gate insulating film (240), and in the case of nitrogen, a nitride film is formed on the surface of the gate metal (210) as a gate insulating film (240), so the gas can be selected and used according to the purpose.

[0064] In the metal insulating film stacking structure (200) of FIG. 4, a transistor channel layer (not shown) is formed on the gate insulating film (240) formed on the inner side wall of the vertical hole (230), just like in the conventional metal insulating film stacking structure (100) of FIG. 1.

[0065] When heat treatment is performed on the inner side wall of the vertical hole (230) using oxygen, nitrogen, or a mixture of these gases, only the surface of the gate metal (210) is heat-treated. When the gate insulating film (240) is transformed by heat treatment, it undergoes volume expansion and may protrude slightly as shown in FIG. 4. Subsequently, a semiconductor film is deposited inside, and polysilicon or oxide semiconductor materials may be deposited. At this time, if an atomic layer deposition (ALD) device is used, the surface step coverage is good, allowing it to be covered well with a uniform shape.

[0066] The metal insulating film stacking structure (200) formed in this way is also a basic structure of the transistors of the 3D NAND flash memory, and a number of such vertical structure transistors are connected to form the 3D NAND flash memory.

[0067]

[0068] Figure 5 is a graph showing the thickness of the oxide insulating film formed according to temperature when heat treatment is performed for 20 minutes in an oxygen atmosphere.

[0069] The heat treatment process conditions described below apply to both cases where an insulating film (220) is formed on a plane of a vertically stacked gate metal (210) and where a gate insulating film (240) is formed by performing heat treatment on the inner side wall of a vertical hole (230).

[0070] The heat treatment temperature is generally performed in the range of 300°C to 1000°C and can be performed for 10 minutes to 2 hours.

[0071] However, it must be adjusted and performed according to each process, and in particular, within a temperature range that does not alter the substrate material or surrounding materials. The higher the temperature, the faster the rate of formation of the insulating film. Referring to Figure 5, it is clearly shown that the thickness of the Ta oxide film gradually increases as the heat treatment temperature increases.

[0072] The result of heat treatment when the gate metal (210) is Ta is as shown in FIG. 5. Heat treatment was performed for 20 minutes in an oxygen atmosphere at atmospheric pressure, and the oxygen flow rate was 50 sccm (standard cc per minute). The heat treatment temperature was varied from 400 ℃ to 600 ℃. That is, each point on the graph represents the thickness when heat treatment is performed for 20 minutes at the corresponding temperature. In the case of this graph, heat treatment is performed for 20 minutes, but since the thickness varies depending on the time of heat treatment, the thickness can be adjusted by varying the time according to the target characteristics when actually manufacturing the transistor.

[0073] The temperature of the heat treatment is determined by the substrate used, or the film or metal formed on the substrate.

[0074] In the case of a glass substrate, since glass deformation may occur at high temperatures, heat treatment must be performed at a temperature of 450°C or lower. In the case of a silicon substrate, heat treatment at a higher temperature is also possible. However, if there is a material that deforms at high temperatures, such as aluminum, on the surface of the silicon substrate, heat treatment must be performed at a temperature lower than the deformation temperature of such material.

[0075] Heat treatment is performed in a furnace at atmospheric pressure, or at a pressure lower than atmospheric pressure. During heat treatment, gas elements and metals react. At this time, the reaction proceeds more readily for metals with lower Gibbs free energy, and selecting a metal with low Gibbs free energy facilitates oxidation and can lower the oxidation temperature.

[0076] Heat treatment can be performed in a nitrogen atmosphere under process conditions such as temperature, pressure, and time as in an oxygen atmosphere. Since heat treatment in this way produces a nitride film as an insulating film, the composition of the insulating film formed varies depending on the type of gas in the heat treatment atmosphere.

Images