Method for generating design information about circuit comprising plurality of modules

Abstract

The present invention relates to a method, performed by a computer device, for generating design information about a circuit comprising a plurality of modules, wherein: a specification library comprising a plurality of specification elements related to a circuit configuration is identified; a plurality of pieces of specification information about a circuit to be generated, design information about a structure and function of the circuit to be generated, and hierarchical information defining a connection relationship between modules of the circuit to be generated are acquired; and software design information is generated by using an artificial intelligence language model.

Description

Method for generating circuit design information composed of multiple modules

[0001] The present invention relates to a method for a computer device to generate circuit design information, and more specifically, to a method for generating and verifying circuit design information composed of a plurality of modules.

[0002] As the performance and miniaturization of electronic devices have recently advanced, the design of circuits capable of performing complex functions is becoming increasingly important. In particular, circuit designs often require the composition of multiple modules, and the interaction and optimization between these modules are emerging as critical challenges during the design process. To address this, automated design tools and technologies are advancing, and various attempts are being made to reduce design time and improve quality.

[0003] However, current design tools have limitations, such as failing to efficiently handle interactions between multiple modules or provide sufficient design optimization for circuits with complex structures. Furthermore, the frequent need to manually refine designs leads to prolonged design processes and a higher risk of errors.

[0004] Therefore, there is an increasing demand for methods to generate and verify circuit design information composed of multiple modules.

[0005] According to the method for generating circuit design information composed of a plurality of modules of the present invention, the purpose is to immediately verify and modify the connectivity between modules while proceeding with the design of modules with complex hierarchical relationships during the process of generating design information for a complex circuit.

[0006] In addition, according to the method for generating circuit design information composed of a plurality of modules of the present invention, the purpose is to facilitate modification of a plurality of modules even when modifications are identified during or after the design of the circuit.

[0007] The present invention relates to a method for generating circuit design information composed of a plurality of modules, performed by a computer device, comprising: (a) identifying a specification library including a plurality of specification elements related to circuit configuration; (b) obtaining a plurality of specification information for a circuit to be generated, design information regarding the structure and function of the circuit to be generated, and hierarchical information defining the connection relationship between modules of the circuit to be generated, wherein the plurality of specification information corresponds to any one of the plurality of specification elements; (c) using an artificial intelligence language model to generate hardware design information including a plurality of sub-module information and software design information related to the hardware design information based on the design information, wherein the sub-module information includes at least one specification information; (d) generating design information for at least one upper module including at least some of the plurality of sub-module information based on the hierarchical information and verifying the connectivity between the sub-module information included in the upper module; (e) identifying specification information to be modified that requires modification; and (f) identifying design information for the upper module associated with the specification information to be modified, the sub-module information, and the software design information, and performing associated modifications on the identified information.

[0008] In one embodiment of the present invention, the plurality of specification elements may include at least one of interface information, port information, and logic information.

[0009] In one embodiment of the present invention, the step (c) comprises the step of generating prompt information to be provided to the artificial intelligence language model based on the design information, and

[0010] The method may include the step of providing the above prompt information to the above artificial intelligence language model to generate the above hardware design information and the above software design information.

[0011] In one embodiment of the present invention, step (f) may include a step of modifying the prompt information based on the identified information and a step of providing the modified prompt information to the artificial intelligence language model to generate change information that changes the submodule information and the software design information.

[0012] In one embodiment of the present invention, the hardware design information is implemented in a Hardware Description Language (HDL), and the software design information may include at least one of header description information and hardware abstraction layer (HAL) function information.

[0013] In one embodiment of the present invention, the method may further include a step performed after step (c), which uses the artificial intelligence language model to check whether the hardware design information and the software design information satisfy a predetermined consistency criterion according to the layer information.

[0014] In one embodiment of the present invention, the sub-module information may include specification interface information for connecting with another module.

[0015] In one embodiment of the present invention, verifying the connectivity in step (d) may include confirming the validity of the connection between the specification interface information included in each of the plurality of sub-module information that are interconnected based on the layer information.

[0016] In one embodiment of the present invention, the design information for the upper module includes upper interface information that defines the connection relationship of the upper module itself, and the step (d) may further include verifying the connectivity between the upper interface information and the lower module information included in the upper module.

[0017] In one embodiment of the present invention, the method may further include the step of generating design information for a top-level module including a plurality of upper modules and verifying connectivity between the plurality of upper modules.

[0018] In one embodiment of the present invention, step (e) may include verifying the specification information to be modified based on a connection error identified as a result of the connectivity verification of step (d) or a change request received from an external source.

[0019] In one embodiment of the present invention, performing the associated change in step (f) may include updating the connection definition between sub-modules within the design information for the associated upper module.

[0020] In one embodiment of the present invention, step (c) may further include: a step of identifying structural context information in which each of the plurality of modules is located in a circuit to be generated based on the hierarchical information—the structural context information includes vertical hierarchical location information and horizontal connection relationship information—a step of deriving external interface boundary conditions that the sub-module information must comply with based on the structural context information, a step of generating prompt information such that the design range of the sub-module information corresponds to the external interface boundary conditions, and a step of using the artificial intelligence language model based on the prompt information.

[0021] In one embodiment of the present invention, the method may further include the steps of receiving a request for adjustment of the layer information, re-identifying the structural context information based on the adjusted layer information to reflect the changed vertical layer position and horizontal connection relationship of the corresponding submodule, and changing the prompt information so as to reflect external interface boundary conditions according to the re-identified structural context information.

[0022] According to the method for generating circuit design information composed of a plurality of modules of the present invention, there is an advantage in that, while proceeding with the design of modules with complex hierarchical relationships during the process of generating design information for complex circuits, connectivity between modules can be immediately verified and modified.

[0023] In addition, according to the method for generating circuit design information composed of a plurality of modules of the present invention, there is an advantage that modifications to the plurality of modules can be easily performed even when modifications are identified during or after the design of the circuit.

[0024] FIG. 1 is a block diagram of a computer device according to one embodiment of the present invention.

[0025] FIG. 2 is a diagram of the structure of circuit design information generated by a computer device according to one embodiment of the present invention.

[0026] FIG. 3 is a flowchart of a method for a computer device according to an embodiment of the present invention to generate circuit design information composed of a plurality of modules.

[0027] FIG. 4 is a block diagram of an application executed by a computer device according to one embodiment of the present invention.

[0028] Hereinafter, embodiments disclosed in this specification will be described in detail with reference to the attached drawings. Identical or similar components regardless of drawing symbols are assigned the same reference number, and redundant descriptions thereof will be omitted. Furthermore, in describing the embodiments disclosed in this specification, if it is determined that a detailed description of related prior art could obscure the essence of the embodiments disclosed in this specification, such detailed description will be omitted.

[0029] Terms including ordinal numbers, such as first, second, etc., may be used to describe various components, but said components are not limited by said terms. These terms are used solely for the purpose of distinguishing one component from another.

[0030] A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0031] In this application, each step described may be performed regardless of the order listed, except where it must be performed in the order listed by a particular causal relationship.

[0032] In this application, terms such as “comprising” or “having” are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0033]

[0034] The present invention will be described below with reference to the attached drawings.

[0035] FIG. 1 is a block diagram of a computer device according to an embodiment of the present invention. With reference to FIG. 1, the computer device of the present invention will be described.

[0036] The present invention relates to a method for a computer device to generate circuit design information.

[0037] Referring to FIG. 1, the computer device of the present invention may include a memory in which an application program for generating circuit design information is stored, and a processor that executes the application program to generate circuit design information.

[0038] The computer device of the present invention may be connected to another device via a network to receive specification information, design information, and layer information regarding a target circuit to be generated. However, in some cases, the computer device may receive the aforementioned specification information, design information, and layer information through a separate input device without being connected to a separate network.

[0039]

[0040] FIG. 2 is a diagram showing the structure of circuit design information generated by a computer device according to an embodiment of the present invention. With reference to FIG. 2, the circuit design information generated by the computer device of the present invention will be described.

[0041] The circuit design information generated by the computer device of the present invention may be composed of a plurality of modules. In the circuit design information, the modules may form a hierarchical structure. Specifically, in the circuit design information, the plurality of modules may have a hierarchical relationship between lower modules and upper modules.

[0042] A submodule refers to the lowest-level unit of a module that does not contain other modules below it. A submodule may include at least one piece of information regarding circuit design. Specifically, a submodule may include at least one piece of specification information and logic information, etc. At least some of the specification information may correspond to a specification interface that defines an interface for connecting to other modules.

[0043] A higher-level module may include multiple lower-level modules. Multiple lower-level modules included in the higher-level module may form an interconnection relationship. Interfaces connecting the multiple lower-level modules may be defined. If the connection relationship of the interconnected interfaces is valid, the connectivity between the lower-level modules can be validly verified.

[0044] A parent module may include a parent interface that defines the connection relationships of the parent module itself. Although not shown in the drawings, a parent module may be connected to other parent modules, or it may be connected to other modules by belonging to an additional top-level module. The parent interface included in the parent module may be connected to a child module included in that parent module.

[0045] As described above, in the case of modules where circuit design information has complex connection relationships and multiple hierarchical relationships, modification of any one design information may require multiple associated changes to multiple modules. The computer device of the present invention can easily perform such multiple associated changes without individual modification work by the designer.

[0046] FIG. 3 is a flowchart of a method for a computer device according to an embodiment of the present invention to generate circuit design information composed of a plurality of modules. With reference to FIG. 3, a method for a computer device according to the present invention to generate circuit design information composed of a plurality of modules will be described.

[0047] In step (310), the computer device identifies a specification library containing multiple specification elements related to circuit configuration.

[0048] The spec library may be stored in the memory of a computer device or in an external storage device accessible by the computer device. The spec library may include multiple spec elements related to circuit configuration.

[0049] Spec elements may include basic specification information related to conventional circuit design, interface information, port information, logic information, and module configuration information. For example, spec elements may include bus specification information including AXI interfaces, local interfaces, etc., SFR specification information, and bitwidth information of ports.

[0050] The specification library may include specification elements customized according to the characteristics of the user or organization of the computer device. The specification library may be updated by adding new specification elements as needed.

[0051]

[0052] In step (320), the computer device obtains multiple specification information for the circuit to be generated.

[0053] The specification information may be information determined according to the purpose, function, use, size, and production process of the circuit to be generated through the computer device of the present invention. The specification information may correspond to any one of a plurality of specification elements included in a specification library.

[0054]

[0055] In step (330), the computer device obtains design information of the circuit to be generated.

[0056] The design information of the circuit to be generated refers to design information regarding the design, structure, function, etc. of the circuit to be generated through the computer device of the present invention. The design information may be implemented in a form that can be recognized by an artificial intelligence language module in a subsequent step (340). In some cases, the design information may be implemented in a predetermined language or format.

[0057]

[0058] In step (340), the computer device checks hardware design information and software design information based on design information.

[0059] Here, hardware design information may be module or logic information implemented in HDL (Hardware Description Language).

[0060] Specifically, the hardware design information may include multiple sub-module information of the circuit to be generated. The sub-module information may include at least one specification information and logic information. Specifically, the hardware design information may configure the sub-module by referencing multiple specification elements stored in the specification library identified in step (310).

[0061] In some cases, hardware design information may include individual logic information rather than module information containing multiple elements. This individual logic information can be connected to a specification interface and configured as a module as needed.

[0062] Software design information may be software code information related to the execution of hardware design information. Software design information may include at least one header description information and Hardware Abstraction Layer (HAL) function information.

[0063] A computer device can generate hardware design information and software design information using an artificial intelligence language model (LLM). If the computer device includes an artificial intelligence language model, the computer device can directly generate hardware design information and software design information using the artificial intelligence language model. However, the computer device may request the generation of hardware design information and software design information from an external artificial intelligence language model connected via a network, even if it does not include an artificial intelligence language model, and receive the results.

[0064] A computer device can generate prompt information to generate hardware design information and software design information using an artificial intelligence language model. The computer device can generate prompt information based on the design information obtained in step (330). In some cases, the computer device can use the design information obtained in step (330) as prompt information without separate modification.

[0065] The computer device provides the prompt information generated in this way to the artificial intelligence language model and can request the generation of suitable hardware design information and software design information by referring to the specification library verified in step (310).

[0066] Hardware design information and software design information generated using an artificial intelligence language model can be verified through a separate verification step. In the verification step, the hardware design information and software design information may be verified through a verification module implemented separately from the artificial intelligence language model on a computer device, or, in some cases, provided to a user terminal to receive the verification result information.

[0067]

[0068] In step (350), the computer device obtains the hierarchy information of the circuit to be generated.

[0069] The hierarchical information of the circuit to be generated refers to information regarding the creation of connection relationships between multiple sub-modules or individual logic information and the verification of such connectivity. In some cases, a computer device may acquire the hierarchical information of the circuit to be generated along with specification information or design information. In such cases, step (350) may be performed together with step (310) or step (330).

[0070] The computer device (10) can identify structural context information within the target circuit based on the hierarchical information obtained in step (350). Structural context information refers to information that defines the technical position and interrelationships of individual modules within the overall architecture and network of the circuit, rather than the modules existing as isolated units. Structural context information may include vertical hierarchical position information and horizontal connection relationship information.

[0071] Here, the vertical hierarchy position information may include information regarding the design level of the module. Specifically, the vertical hierarchy position information may be information identifying whether the target module belongs directly to the top-level module of the circuit, or whether it is a sub-module of a deep level that is nested and included within a specific upper module. Through the identified vertical hierarchy position information, the computer device (10) can define the range of control signals that the module must receive from the upper level, or the hierarchy of data that must be transmitted to the lower level.

[0072] Here, horizontal connection relationship information may include information regarding interaction paths between adjacent modules existing at the same or different levels. For example, the horizontal connection relationship information may be information identifying the logical connectivity between the target module and the source module and destination module with which it transmits and receives data, and the consistency of interface specifications for signal transmission between modules.

[0073] For example, when the computer device (10) of the present invention designs a communication SoC (System on Chip), the identified vertical hierarchy location information may be information regarding whether the target module is located in a main control block that manages the data flow of the entire system, or in a lower computation area within a baseband block for processing specific communication standards. Additionally, for example, when the computer device (10) of the present invention designs a high-speed interface circuit, the identified horizontal connection relationship information may be information regarding the signal transmission path and bit band compatibility of the connection interface between a module responsible for the physical layer and a controller module responsible for the data protocol.

[0074]

[0075] The computer device (10) can derive external interface boundary conditions that the sub-module information must comply with based on identified structural context information. Here, the external interface boundary conditions refer to technical constraints or interface specifications that the target module must observe in order to exchange data with the entire system of the circuit or other adjacent modules.

[0076] Specifically, the computer device (10) can determine the characteristics of the external connection terminal of the target module by utilizing vertical hierarchical location information among the identified structural context information. For example, if the target module is a location directly connected to the data bus of the upper system, communication protocols conforming to the bus specifications, data transmission speeds, and electrical characteristics of the signal can be derived as boundary conditions.

[0077] Additionally, the computer device (10) can derive boundary conditions to prevent physical and logical conflicts between adjacent modules based on horizontal connection relationship information. Here, the boundary conditions may include constraints on timing constraints in a path sharing signals with adjacent modules, signal synchronization methods, and the structure of data packets.

[0078] For example, when the computer device (10) of the present invention designs a memory controller module within a high-performance graphics processing unit (GPU), the derived external interface boundary condition may be information regarding the data bandwidth specification of the memory interface layer where the module is located (e.g., DDR5 or GDDR6 protocol specification) and the signal transmission delay time limit value with an adjacent memory chip. Additionally, for example, when the computer device (10) designs a processing module that receives data from an external sensor, the external interface boundary condition may be information regarding the voltage level specification of an input port corresponding to the output specification of the sensor and the minimum sampling rate that must be guaranteed for real-time data processing.

[0079]

[0080] The computer device (10) can generate prompt information based on derived external interface boundary conditions so that the design range of the sub-module information aligns with the boundary conditions. Here, the prompt information refers to instruction information that defines the technical limits or essential requirements of the design data to be generated by the artificial intelligence language model, thereby controlling the output of the artificial intelligence language model so that it does not exceed the physical and logical constraints of the entire circuit.

[0081] Specifically, the computer device (10) can analyze the derived boundary conditions, convert them into commands or parameters that an artificial intelligence language model can understand, and include them in prompt information. By limiting the design scope of the sub-module within the framework of external interface boundary conditions, the computer device (10) can induce the hardware and software design information generated by the artificial intelligence language model to strictly comply with predefined input / output specifications and operating conditions.

[0082] For example, when the computer device (10) of the present invention designs an interface module that follows a specific standard communication specification, the generated prompt information may include specific guidelines that instruct an artificial intelligence language model to generate code that must include the essential signal names, data transmission timing, and protocol compliance details of the corresponding communication specification. Additionally, for example, when the computer device (10) designs a circuit for a mobile device with a specific power consumption limit, the prompt information may include constraint parameters that force the design range of the sub-module to have a low-power logic structure optimized within the corresponding power consumption threshold.

[0083]

[0084] A computer device (10) can obtain design information for a circuit to be generated by using an artificial intelligence language model based on generated prompt information. Here, using an artificial intelligence language model means a series of processes in which generated prompt information is provided as input data, and hardware design information and software design information are output from the artificial intelligence language model.

[0085] The computer device (10) can perform operations by directly including an artificial intelligence language model, or request the generation of design information from an external artificial intelligence language model connected via a network and receive the result. At this time, the artificial intelligence language model can generate hardware description language (HDL)-based module information and corresponding software code that satisfy the hierarchical structure and physical constraints of the circuit by reflecting the structural context information and external interface boundary conditions included in the prompt information.

[0086] Specifically, hardware design information generated by an artificial intelligence language model may include multiple sub-module information, and software design information may include header description information related to the execution of the hardware and hardware abstraction layer (HAL) function information.

[0087] For example, when the computer device (10) of the present invention uses an artificial intelligence language model to design a specific cryptographic operation module, the artificial intelligence language model can generate a set of software library functions for controlling operations by accessing the corresponding hardware registers, along with hardware logic optimized for the data processing structure specified in the prompt. Additionally, for example, when designing for a high-speed data interface, the artificial intelligence language model can simultaneously output design information such as hardware code responsible for signal processing of the physical layer as well as software interrupt processing routines for interacting with the upper protocol stack, in a form that corresponds to the layer information.

[0088]

[0089] The computer device (10) may receive a request for adjustment of layer information from a user. A request for adjustment of layer information refers to input from a user who wishes to change the overall structure of the circuit, the arrangement between modules, or the method of connection between modules during the design process or after the design is completed. The user may perform adjustment requests, such as changing the parent module to which a specific module belongs or modifying the signal transmission path between modules, through an interface provided by the computer device (10).

[0090] The computer device (10) can re-identify the structural context information of the corresponding sub-module based on the adjusted hierarchical information. In the re-identification process, the computer device (10) can re-analyze and reflect the vertical hierarchical position and horizontal connection relationship of the sub-module that have been changed according to the adjustment of the hierarchical information. Specifically, the structural context information can be updated by identifying in real-time the hierarchical information that has changed as a specific module moves to another upper module, or the connection path information that has been modified as an adjacent module is replaced.

[0091] The computer device (10) can change prompt information so that external interface boundary conditions are reflected according to re-identified structural context information. This means a process of changing prompt information, which is an existing design guideline, so that an artificial intelligence language model can generate design information that corresponds to the changed circuit structure.

[0092] For example, if a user requests a hierarchical information adjustment to move a specific encryption module from a 'data processing block' to a 'security control block', the computer device (10) can identify the new vertical position of the module and re-identify the new horizontal connection relationship with adjacent modules within the security control block. Additionally, for example, by modifying the prompt information so that an enhanced security protocol or specific interface specification required at the changed position is automatically reflected as an external interface boundary condition, the artificial intelligence language model can be controlled to regenerate hardware and software design information optimized for the changed environment.

[0093] As another example, when the computer device (10) of the present invention receives a request to adjust the data transmission bandwidth of an interface module, the computer device (10) can re-identify the vertical and horizontal connection relationships between the upper layer bus and the lower layer buffer interconnected with the module. At this time, by updating the prompt information to reflect physical constraints, such as the bit width of the input / output signal or the signal transmission timing required to accommodate the expanded bandwidth, as changed external interface boundary conditions, the artificial intelligence language model can collectively change and generate hardware and software design information optimized for the expanded specifications while maintaining data consistency of the entire layered structure.

[0094]

[0095] In step (360), the computer device generates design information for the upper module based on the layer information and verifies the connectivity.

[0096] Specifically, the computer device can select multiple sub-modules to be included in a single upper module based on hierarchical information. Additionally, the computer device can select specification information for connection interfaces to be included in the upper module separately from the sub-modules. Subsequently, the computer device can generate design information for the upper module by connecting the multiple sub-modules and / or specification interfaces selected based on the hierarchical information.

[0097] A computer device can generate design information for a higher-level module and create connection relationships with multiple lower-level modules. Specifically, based on hierarchical information, the computer device can verify specification information of connection interfaces in multiple lower-level modules to be interconnected. After verifying the connectivity between the specification information of connection interfaces, the computer device can define connection information between the connection interfaces to create connection relationships among multiple lower-level modules.

[0098] Any one submodule included in a single upper module may be connected to an additional other submodule or to the connection interface of the upper module itself, in addition to other submodules. The computer device may create a chain of connection relationships within this upper model in step (360).

[0099] Additionally, the computer device can verify the connectivity of these connection relationships in step (360). Specifically, first, when the computer device generates design information for an upper module including a connection interface of a plurality of lower modules and the upper module itself based on hierarchical information, it can verify the connectivity of the generated upper module.

[0100] Although the attached drawing only illustrates the computer device verifying connectivity within the upper module in step (360), the computer device may additionally verify connectivity between multiple upper modules in some cases.

[0101] In addition, the circuit design information may include a top-level module containing multiple upper modules. In such cases, the computer device can verify the connectivity of the connection interfaces of the multiple upper modules included in the top-level module and the top-level module itself.

[0102]

[0103] In step (370), the computer device checks the specification information to be modified.

[0104] After step (360), the computer device can identify the specification information that needs to be modified among the multiple specification information for various reasons.

[0105] For example, the computer device may discover an error in connectivity during the process of verifying connectivity in step (360). In this case, it may be necessary to modify the design of the submodule or the design of the individual logic.

[0106] In another example, the computer device may obtain a request for modification of specification information and design information after step (360). In this case, the computer device may determine whether to re-perform the circuit design from the initial stage according to the modification request, or whether the modification request can be reflected by changing the circuit design information generated so far. If it is determined that the modification request is not a change to a critical element of the circuit and the modification request can be reflected by changing the circuit design information generated so far, the next step (380) may be performed.

[0107] As another example, a computer device may not detect an error regarding the connectivity of a single parent module, but may identify a need for cascading corrections by detecting errors in other parent modules connected to that module. This need for cascading corrections may have been received from other computer devices or other application programs running on the same computer device.

[0108] As described above, if there is a top-level module above a top-level module or a connection relationship between multiple top-level modules, the steps described above (340, 350, 360) may be repeated. That is, after design information for a lower module is generated, the generation of design information for a top-level module and connectivity verification are performed, and additionally, the generation of design information for a top-level module and connectivity verification may be performed again. The number of repetitions of these steps may increase as module layers of the circuit design are added.

[0109]

[0110] In step (380), the computer device performs a change associated with the specification information to be modified.

[0111] The computer device first identifies the upper module, lower module, individual logic information, and software design information associated with the specification information to be modified identified in step (370). Subsequently, it performs changes according to the target requiring individual changes. The aforementioned changes may be performed differently depending on the characteristics of the target requiring changes.

[0112] For example, if a change to a specific submodule is required, the computer device can utilize an artificial intelligence language model that generated the design information of that submodule. That is, the computer device can re-examine the prompt information used when generating the design information of the submodule and modify the prompt information to reflect the changes. Subsequently, the computer device can change the design information of the submodule using the modified prompt information.

[0113] As another example, if a change to the connection interface of the parent model itself is required, the computer device can refer to the specification library to select the specification element to be changed and modify the part regarding the connection interface in the parent model's design information.

[0114]

[0115] According to the method for generating circuit design information composed of a plurality of modules of the present invention, which includes the aforementioned series of steps, there is an advantage in that the connectivity between modules can be immediately verified and modified while proceeding with the design of modules with complex hierarchical relationships during the process of generating design information for a complex circuit. In addition, there is an advantage in that modifications to a plurality of modules can be easily performed even when the need for modification is identified during or after the circuit design is completed.

[0116]

[0117] The technical features disclosed in each embodiment of the present invention are not limited to that embodiment only, and as long as they are not mutually incompatible, the technical features disclosed in each embodiment may be combined and applied to different embodiments.

[0118] Therefore, in each embodiment, the technical features are described primarily, but as long as the technical features are not mutually incompatible, they may be combined and applied together.

[0119] The present invention is not limited to the embodiments described above and the attached drawings, and various modifications and variations may be possible from the perspective of those skilled in the art to which the present invention belongs. Accordingly, the scope of the present invention should be defined not only by the claims of this specification but also by equivalents thereof.

Claims

1. A method for generating circuit design information composed of a plurality of modules, performed by a computer device, (a) A step of identifying a specification library containing multiple specification elements related to circuit configuration; (b) a step of obtaining a plurality of specification information for a circuit to be generated, design information for the structure and function of the circuit to be generated, and hierarchical information defining the connection relationships between modules of the circuit to be generated - the plurality of specification information corresponds to any one of the plurality of specification elements -; (c) A step of generating hardware design information including a plurality of sub-module information and software design information related to the hardware design information, based on the design information, using an artificial intelligence language model - the sub-module information includes at least one specification information -; (d) a step of generating design information for at least one upper module including at least some of the plurality of lower module information based on the above hierarchy information, and verifying the connectivity between the lower module information included in the upper module; (e) a step of identifying specification information to be modified that requires correction; and (f) a step comprising identifying design information for the upper module associated with the specification information to be modified, the lower module information and the software design information associated with the above, and performing associated changes on the identified information, Method for generating circuit design information.

2. In Paragraph 1, The above plurality of specification elements include at least one of interface information, port information, and logic information, Method for generating circuit design information.

3. In Paragraph 1, The above step (c) is, A step of generating prompt information to be provided to the artificial intelligence language model based on the above design information; and A step comprising providing the above prompt information to the above artificial intelligence language model to generate the above hardware design information and the above software design information, Method for generating circuit design information.

4. In Paragraph 3, The above (f) step is, A step of modifying the prompt information based on the identified information; and The method includes the step of providing the modified prompt information to the artificial intelligence language model to generate change information that modifies the sub-module information and the software design information. Method for generating circuit design information.

5. In Paragraph 1, The above hardware design information is implemented in a Hardware Description Language (HDL), and The above software design information includes at least one of header description information and hardware abstraction layer (HAL) function information, Method for generating circuit design information.

6. In Paragraph 1, This is performed after the above (c) step, and A method further comprising the step of using the artificial intelligence language model to verify whether the hardware design information and the software design information satisfy predetermined consistency criteria according to the layer information. Method for generating circuit design information.

7. In Paragraph 1, The above sub-module information includes specification interface information for connecting to other modules, Method for generating circuit design information.

8. In Paragraph 7, Verifying the connectivity in step (d) above is, Includes verifying the validity of the connection between the specification interface information included in each of the multiple sub-module information interconnected based on the above layer information, Method for generating circuit design information.

9. In Paragraph 1, The design information for the above upper module is, It includes upper interface information that defines the connection relationship of the upper module itself, and The above step (d) is, Further including verifying the connectivity between the above-mentioned upper interface information and the above-mentioned lower module information included in the above-mentioned upper module, Method for generating circuit design information.

10. In Paragraph 1, A method further comprising the step of generating design information for a top-level module including a plurality of upper-level modules and verifying connectivity between the plurality of upper-level modules. Method for generating circuit design information.

11. In Paragraph 1, The above step (e) is, The method includes verifying the specification information to be modified based on a connection error identified as a result of the connectivity verification in step (d) above or a change request received from an external source. Method for generating circuit design information.

12. In Paragraph 1, Performing the associated change in step (f) above is, Includes updating the connection definitions between sub-modules within the design information for the associated upper module, Method for generating circuit design information.

13. In Paragraph 1, The above step (c) is, A step of identifying structural context information in which each of the plurality of modules is located in the target circuit for generation, based on the above-mentioned hierarchical information - the structural context information includes vertical hierarchical location information and horizontal connection relationship information -; A step of deriving external interface boundary conditions that the sub-module information must comply with based on the structural context information above; A step of generating prompt information such that the design range of the above sub-module information corresponds to the above external interface boundary condition; and A step further comprising using the artificial intelligence language model based on the above prompt information, Method for generating circuit design information.

14. In Paragraph 13, A step of receiving a request for adjustment regarding the above-mentioned layer information; A step of re-identifying the structural context information based on the above-mentioned adjusted hierarchy information, reflecting the changed vertical hierarchy position and horizontal connection relationship of the corresponding submodule; and A further step of changing the prompt information so that external interface boundary conditions are reflected according to the re-identified structural context information, Method for generating circuit design information.

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