Power amplifier protection circuit with low insertion loss

Abstract

A power amplifier protection circuit with low insertion loss is disclosed. In one aspect, a multipath transmission chain may use a multiplexer to provide a signal from the various paths to a power amplifier. Circuitry within the multiplexer may also be responsive to detected power levels to provide various power-limiting protection, such as a clamp and / or attenuator, to limit an input signal to levels that will not damage the power amplifier. Combining the clamp, attenuator, and multiplexer into a single circuit that reuses transistors reduces an overall insertion loss for the protection circuitry and multiplexer. Further, such reuse may provide space savings.

Description

POWER AMPLIFIER PROTECTION CIRCUIT WITH LOW INSERTION LOSSPRIORITY APPLICATION

[0001] The present application is related to U.S. Provisional Patent Application Serial No. 63 / 748,080, filed on January 22, 2025, and entitled “POWER AMPLIFIER PROJECTION CIRCUIT WITH LOW INSERTION LOSS,” the contents of which are incorporated herein by reference in their entirety.BACKGROUNDI. Field of the Disclosure

[0001] The technology of the disclosure relates generally to power amplifier protection circuits that protect power amplifiers from large input signals.II. Background

[0002] Computing devices abound in modem society, and more particularly, mobile communication devices have become increasingly common. Hie prevalence of these mobile communication devices is partly driven by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from pure communication tools into sophisticated mobile entertainment centers, thus enabling enhanced user experiences. With the advent of the myriad functions available to such devices, there has been increased pressure to make mobile communication paths more robust to accommodate the bandwidth needed to support the data used by the myriad functions. Making robust communication paths within the mobile communication device provides room for innovation.SUMMARY

[0003] Aspects disclosed in the detailed description include a power amplifier protection circuit with low insertion loss. In particular, a multipath transmission chain may use a multiplexer to provide a signal from the various paths to a power amplifier. Circuitry within the multiplexer may also be responsive to detected power levels to provide various power-limiting protection, such as a clamp and / or attenuator, to limit an input signal to levels that will not damage the power amplifier. Combining the clamp,attenuator, and multiplexer into a single circuit that reuses transistor switches reduces an overall insertion loss for the protection circuitry and multiplexer. Further, such reuse may provide space savings.

[0004] In this regard, in one aspect, a power amplifier front-end is disclosed. The power amplifier front-end includes a multiplexer comprising a plurality of input lines, each with a corresponding series switch configured to select one input line to be connected to an output node, and a power detector coupled to the output node and configured to provide a feedback signal indicative of a sensed power level. The power amplifier frontend also includes a clamp formed from at least one series switch, wherein the clamp is configured to clamp a voltage level passing to the output node, and an attenuator comprising the at least one series switch and a first shunt transistor, wherein the clamp and the attenuator are variable and configured to be set responsive to the feedback signal from the power detector.

[0005] In another aspect, a communication device comprising a transmission chain is disclosed. The communication device includes a power amplifier die comprising an output amplifier stage and a power amplifier front-end, the power amplifier front-end comprising a multiplexer comprising a plurality of input lines, each with a corresponding series switch configured to select one input line to be connected to the power amplifier die through an output node and a power detector coupled to the output node and configured to provide a feedback signal indicative of a sensed power level. The power amplifier front-end further includes a clamp formed from at least one series switch, wherein the clamp is configured to clamp a voltage level passing to the output node, and an attenuator comprising the at least one series switch and a first shunt transistor, wherein the clamp and the attenuator are variable and configured to be set responsive to the feedback signal from the power detector.

[0006] In another aspect, a method of protecting a power amplifier die is disclosed. The method includes providing a plurality of signals to a multiplexer-protection circuit, selecting a signal from the plurality of signals using a series switch, clamping a voltage level for the signal using the series switch, and using the scries switch as part of an attenuator.BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram of a conventional protection circuit for a power amplifier in a transmission chain;

[0008] Figure 2 is a block diagram of a protection circuit combined with a multiplexer, which provides low insertion loss for the power amplifier and having a first power detection feedback loop according to aspects of the present disclosure;

[0009] Figure 3 is a block diagram of the protection circuit combined with the multiplexer, which provides low insertion loss for the power amplifier and having a second power detection feedback loop according to aspects of the present disclosure;

[0010] Figure 4 is a block diagram of the protection circuit combined with the multiplexer, which provides low insertion loss for the power amplifier and having a third power detection feedback loop according to aspects of the present disclosure;

[0011] Figure 5 is a block diagram of an alternate switch configuration within the multiplexer-protection circuit, highlighting how series switches may be reused to change a network configuration;

[0012] Figures 6A-6C are block diagrams of alternate multiplexer-protection circuits that include an additional power sensor to assist in managing the protection circuit, the variation lies in the element into which the signal from the additional power sensor is provided;

[0013] Figure 7 is a block diagram providing some additional details about an exemplary attenuator control circuit;

[0014] Figure 8 illustrates additional details about the shunt transistors used to assist in providing attenuation for the combined circuit;

[0015] Figure 9 illustrates additional details about the series switches that may be used for multiplexing and clamping in the combined circuit;

[0016] Figure 10 illustrates a possible additional reuse opportunity where unused series switches may be added to the clamp to raise the maximum possible clamp value;

[0017] Figure 11 is a flowchart illustrating an exemplary process for protecting a power amplifier with a combined multiplexer and protection circuitry; and

[0018] Figure 12 is a block diagram of a mobile communication device, which may include the combined multiplexer-protection circuit according to the present disclosure.DETAILED DESCRIPTION

[0019] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0020] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be teimed a second element, and similarly, a second element could be termed a first element without departing from the scope of the present disclosure. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0021] It will be understood that when an element, such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element, or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, no intervening elements are present. Likewise, it will be understood that when an element, such as a layer, region, or substrate, is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element, or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, no intervening elements are present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another clement, no intervening elements arc present.

[0022] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It willbe understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a," “an,” and “the” are intended to include the plural forms as well unless the context clearly indicates otherwise. It will be further understood that the terms “comprises," “comprising," “includes,” and / or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0024] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0025] In keeping with the above admonition about definitions, the present disclosure uses transceiver in a broad manner. Current industry literature uses “transceiver” in two ways. The first way uses transceiver broadly to refer to a plurality of circuits that send and receive signals. Exemplary circuits may include a baseband processor, an up / down conversion circuit, filters, amplifiers, couplers, and the like coupled to one or more antennas. A second way, used by some authors in the industry literature, refers to a circuit positioned between a baseband processor and a power amplifier circuit as a transceiver. This intermediate circuit may include the up / down conversion circuits, mixers, oscillators, filters, and the like, but generally does not include the power amplifiers. As used herein, the term transceiver is used in the first sense. Where relevant to distinguish between the two definitions, the terms “transceiver chain” and “transceiver circuit” are used respectively.

[0026] Additionally, to the extent that the term “approximately” is used in the claims, it is herein defined to be within five percent (5%).

[0027] Aspects disclosed in the detailed description include a power amplifier protection circuit with low insertion loss. In particular, a multipath transmission chain may use a multiplexer to provide a signal from the various paths to a power amplifier.Circuitry within the multiplexer may also respond to detected power levels to provide various power-limiting protections, such as clamps and / or attenuators, to limit an input signal to levels that will not damage the power amplifier. By combining the clamp, attenuator, and multiplexer into a single circuit that reuses transistors, the overall insertion loss for the protection circuitry and multiplexer is reduced. Further, such reuse may provide space savings.

[0028] Before addressing aspects of the present disclosure, a brief overview of a power amplifier chain and the precursor elements is provided with reference to Figure 1. A discussion of aspects of the present disclosure begins below with reference to Figure 2.

[0029] In thi s regard, Figure 1 illustrates a power amplifier chain 100 that may include a power amplifier front-end 102, a power amplifier die 104, and an output match filter 106. The output match filter 106 may be coupled to an antenna (not shown), and the power amplifier chain 100 may be part of a transmission chain within a mobile communication device. As such, there may be multiple signal paths originating in baseband processors (not shown), application processors (also not shown), or similar components, which may be combined within the power amplifier chain 100 and amplified for transmission.

[0030] To combine the multiple incoming signals on input lines 108(l)-108(N) (where, as shown, N=2), a multiplexer (MUX) 110 is used. The MUX 110 has some measurable insertion loss, as is well understood. The combined signal is then provided to the power amplifier die 104, which may boost the signal with various amplifier stages, such as a driver amplifier stage 112 and an output amplifier stage 114, each having its own respective bias circuit 1 16, 118.

[0031] Modern power amplifier chains are subject to challenging conditions, including input power, supply voltage, load mismatch, process and temperature variations, environmental challenges, and other operating conditions. Accordingly, device manufacturers mandate high-stress tests in an effort to over-engineer the components such that the device continues to operate in all possible operating conditions. The elements of the power amplifier die 104 and the output match filter 106 arc vulnerable to overpower conditions. That is, if these elements handle power levels exceeding certain tolerances, the elements may be damaged, which, in extreme cases, may brick the device. Accordingly, the device manufacturer may insist that the power amplifier chain include both input power limits and reverse power protection loops. Not only must suchprotection circuits be present, but they also need to pass ruggedness tests without compromising main transmission performance metrics.

[0032] Accordingly, the power amplifier front-end 102 may include input line clamps 120(l)-120(N) for respective input lines 108(1)- 108(N). Further, the combined signal may pass through an attenuator 122, which includes a resistive network with variable resistances to attenuate the signal before delivery to the power amplifier die 104. The variable resistances are controlled, for example, by a local overpower loop control circuit 124. This circuit detects power leaving the MUX 110 using a power detector 126 and adjusts the variable resistances based on the detected power.

[0033] While the clamps 120(1 )- 120(N) and the attenuator 122 may provide adequate protection for the power amplifier die 104, the presence of three devices (e.g., clamps, MUX, and attenuator) in the path, each having its own insertion loss, may otherwise compromise performance in an undesirable manner. Accordingly, there remains room for improvement.

[0034] Exemplary aspects of the present disclosure provide a combined multiplexerprotection circuit in a power amplifier front-end that consolidates the insertion loss to a single device yet still provides ample flexibility for mitigating overpower conditions. The power amplifier front-end is well-suited for implementation using field effect transistors (FETs), even if the power amplifier die relies on bipolar technologies. The reduction in insertion loss requires a lower overall gain from the power amplifier, which in turn generates lower power dissipation. The combination is effectuated, in part, through the reuse of switches in the multiplexer to implement analog attenuation and analog signal clamping functions without requiring additional radio frequency (RF) signal path devices.

[0035] In this regard, Figures 2-4 introduce a combined MUX -protection circuit 200 that operates with the power amplifier die 104 and the output match filter 106 in a transmission chain. A power detector 202 (also referred to as Pdetect in the Figures) is coupled to a node 204 between the MUX-protection circuit 200 and the power amplifier die 104 and provides a power limit protection feedback loop 206.

[0036] For the sake of illustration, it is assumed that the combined MUX-protection circuit 200 includes two input lines 208(l)-208(2). The concepts of the present disclosure are applicable to MUX with more than two input lines. The multiplexer function is effectuated by a series switch 210(l)-210(2) coupled to the input lines 208(l)-208(2), respectively. The series switches 210(l)-210(2) are, in an exemplary aspect, transistorsand, more specifically, field effect transistors (FETs). By opening and closing the switches 210(1 )-210(2), one or the other of the input lines 208(l)-208(2) can be coupled to the node 204.

[0037] While FETs are generically considered, it should be appreciated that the power amplifier front-end may be a complementary metal oxide semiconductor (CMOS), silicon on insulator (SOI) semiconductor, or any other process that has FET-type devices (BiCMOS, HEMT, or the like) and is well-suited for use with a bipolar power amplifier die (e.g., GaAs)

[0038] Exemplary aspects of the present disclosure contemplate reusing the series switches 210(1 )-210(2) as a clamp to assist in protecting the power amplifier die 104. Additional transistors are added to form a network that can be used as an attenuator that also assists in protecting the power amplifier die 104. In an exemplary aspect, the network is a Il-network. Thus, a first network is formed from a first shunt transistor 212, the series switch 210(1), and a common shunt transistor 214. The second network is formed from a second shunt transistor 216, the series switch 210(2), and the common shunt transistor 214.

[0039] The transistors that fomr the clamps (i.e., series switches 210( l)-210(2)) may be controlled by a clamp control circuit 218. The transistors that form the attenuators (i.e., transistors 212, 214, and 216) may be controlled by an attenuator control circuit 220. In particular, the control circuits 218, 220 may translate or convert digital control signals from a digital control circuit 222 into analog signals that are provided to the gates of the transistors.

[0040] As explained in greater detail below with reference to Figure 9, the series switches 210(l)-210(2) may actually be a plurality of FETs and is amenable to fine adjustable analog voltage clamping that can be set by the digital control circuit 222 (using signal Pclamp_th) with a dedicated register (not shown) that sets the gate voltage of the series switches 210(l)-210(2) with an analog digital-to-analog converter (DAC, also not shown). In this way, the series switches 210(l)-210(2) of each input line 208(l)-208(2) act as a source follower analog stage instead of a switching digital stage and limit the output voltage to a voltage equal to VDAc(Pclamp_th)-VGs(switch). Process and temperature variations of Vcs(switch) can be compensated for using a matching device in the clamp control DAC side, such that the two VGS voltages cancel each other (see DACs 900, 902 described below).

[0041] As also explained in greater detail below with reference to Figure 8, the shunt transistors 212, 214, 216 are reused as analog control resistors instead of digital switches. As such, a controllable amount of attenuation can be provided. The attenuation value is set by the analog voltage level at the gate of the shunt transistors 212, 214, 216. When the transistors 212, 214, 216 are acting as switches, a full positive supply voltage may be placed on the gates. Alternatively, when operating as an attenuator, an analog voltage between ground and the full supply level can be placed at the gates to vary the resistance provided.

[0042] In Figure 2, the digital control circuit 222 is part of the power limit protection feedback loop 206 and is configured to receive information relating to the power level sensed at the node 204 by the power detector 202. The digital control circuit 222 generates appropriate digital control signals and sends such digital control signals to the clamp control circuit 218 and the attenuator control circuit 220.

[0043] In contrast, in Figure 3, the power limit protection feedback loop 206 is coupled directly to the attenuator control circuit 220, and the digital control circuit 222 provides threshold values (Pclamp_th and Patten_th) to the control circuits 218, 220, respectively. The attenuator control circuit 220 compares the sensed power to the threshold value and generates appropriate analog control signals for the transistors 212, 214, and 216. The series switches 210(1), 210(2) may be operated as a source-follower that limits the input signal voltage to Pclamp_th.

[0044] In further contrast, in Figure 4, the power limit protection feedback loop 206 is coupled directly to the clamp control circuit 218. The digital control circuit 222 still provides the threshold values. The clamp control circuit 218 compares the sensed power to the threshold value and generates appropriate analog control signals for the series switches 210(l)-210(2). The transistors 212, 214, and 216 may combine to put an amount of attenuation dictated by Patten_th.

[0045] In alternate aspects not illustrated, either the clamp control circuit 218 or the attenuator control circuit 220 may be omitted, and a digital signal from the digital control circuit 222 may be provided directly to control relevant transistors. That is, if the clamp control circuit 218 is omitted, a digital control signal may be provided to the series switches 210(l)-210(2). Conversely, if the attenuator control circuit 220 is omitted, a digital control signal may be provided to transistors 212, 214, and 216.

[0046] Also, while a Fl-network is contemplated and illustrated, the present disclosure is not so limited, and different numbers of series and shunt transistors may be used in different configurations (e.g., an L-network, a T-network, or cascaded T and fl networks).

[0047] Note that it may also be possible to reuse a switch from one path in another path. For example, as illustrated in Figure 5, the shunt transistor 214 is omitted, but a FI-network may still be provided by reusing the series switch 210( 1 )-210(2) from an inactive path. Thus, a fl-network for input line 208(1) may be formed with shunt transistors 212, 216 being the two “legs” 500(l)-500(2) and the series switches 210(l)-210(2) being the crossbar 502. In this case, the node 204 couples to the Il-network in the middle of the crossbar 502. As illustrated, the input line 208(2) is not active, and the series switch 210(2) is reused to couple the shunt transistor 216 to the network.

[0048] The above aspects provide a local power sensing feedback loop based on an input power for the power amplifier die 104. The transmit path may also need protection in cases when the output amplifier stage 114 is exposed to large load mismatches. To assist in detecting such conditions, a power detector may be added after the output match filter 106 (e.g., before the antenna). The signal from this power detector may be provided to the MUX-protection circuit 200 in a variety of ways, as illustrated in Figures 6A-6C.

[0049] In this regard, Figures 6A-6C contemplate a power detector 600 coupled to an isolation port of a coupler 602. This configuration will detect large, reflected power levels from the antenna 604. The signal from the power detector 600 may be provided directly to the MUX-protection circuit 200 with the signal from the power detector 202 through an AND circuit 606, as shown in Figure 6A. It should be appreciated that, as described above, this feedback may be provided to the clamp control circuit 218 or the attenuator control circuit 220 (not shown in Figures 6A-6C).

[0050] Alternatively, the signal from the power detector 202 may be provided to the MUX-protection circuit 200, and the signal from the power detector 600 may be provided to the digital control circuit 222, as illustrated in Figure 6B. The digital control circuit 222 may include a time delay circuit 608 and attenuation control circuit 610. Such a digital approach gives high flexibility with programmable memory 612, providing adjustment steps, and the digital values eliminate noise in the detected power signal. Again, the input from the digital control circuit 222 may be to the clamp control circuit 218 or the attenuator control circuit 220 (or both).

[0051] Still another option is illustrated in Figure 6C, where both power detectors 202 and 600 provide the feedback signals to the digital control circuit 222. A single control signal may be provided, eliminating the need for the AND circuit 606. Again, the control signal may be provided to the clamp control circuit 218, the attenuator control circuit 220, or both. This aspect may reduce the risk of ringing between the two feedback loops.

[0052] In an exemplary aspect, on detection of power levels above thresholds, the digital control circuit 222 makes a large step down in input power by clamping and attenuating the signal in the FEM. After a time delay, the digital control circuit may incrementally step up the input power by removing clamping and attenuation until an unadulterated signal is being used with the understanding that the clamping and attenuation may be reapplied during the step-up sequence if the power levels again exceed an acceptable threshold.

[0053] It should be appreciated that a true power detector may require sensing both a voltage and a current, which may be difficult to implement. However, in a controlled impedance domain, the power level corresponds precisely to a voltage level. Accordingly, the power detector 202 may be implemented as a voltage level detector. It should also be appreciated that comparisons are more easily done when comparing currents instead of voltages. Thus, Figure 7 illustrates an exemplary control circuit, which, as illustrated, is an attenuator control circuit 220 that receives voltage signals from the power detector 202 and the digital control circuit 222 and converts both to currents for comparison.

[0054] Specifically, the signal from the digital control circuit 222 is converted to an analog signal by a DAC 700. Voltage to current (V-to-I) converter 702 creates an Iref signal for a comparator 704. Similarly, the analog signal (Pdet) from the power detector 202 is converted to a current signal Idet by a V-to-I converter 706. The comparator 704 generates a Vcomp signal for a Vgate control circuit 708 that controls signals provided to the gates of the transistors 212, 214, 216, and the switches 210(l)-210(2) to provide a desired resistance used to attenuate the signals. Similarly, the clamp control circuit 218 may use a DAC 710 to adjust the gates to provide desired clamping.

[0055] While Figure 7 assumes that the detected power from power detector 202 is provided directly to the attenuator control circuit 220, as shown in Figure 3, it should be appreciated that similar concepts can be applied if the signal is provided to the clamp control circuit 218 or the digital control circuit 222.

[0056] Figure 8 provides additional details about the converters 702, 706, and the comparator 704, as well as additional details about possible structures for the shunt transistors 212, 214, 216. More specifically, Figure 8 illustrates the digital control signal Patten_th being provided as Vref to a reference side transconductance stage V-to-I converter 800 (i.e., converter 702) while the power detected signal (RF_Pdet) is provided to a matched transconductance stage V-to-I converter 802 (i.e., converter 706). A first supply 804 gives headroom for transistors 806, 808, 810, 812, 814 to operate. The transistor 806 is cascoded with the transconductance stage V-to-I converter 802, while the transistor 808 is cascoded with the transconductance stage V-to-I converter 800. The node 816 effectively serves as the comparison point for currents, such that as RF_Pdet increases, the current flows to the supply, raising the voltage at node 818. As RF_Pdet goes down, current goes into the ground through the node 816. The voltage (Vcomp) at node 818 is provided to the gate of a source follower transistor (Mfol) 820. A second supply (typically not equal to the first supply 804) 822 is provided for the transistor 820. The analog voltages for the gates of the shunt transistors 212, 214, 216 (generically shown as transistor 824) are generated by the transistor 820 that processes Vcomp from the comparator 704. Circuit 826 acts as a pull-down circuit for the transistor 820. This circuit 826 allows Vgate_shunt to go to ground when the shunt switches need to be off, but allows it to go to the supply 822 when the shunt devices need to operate as an ON switch and to the analog voltage from transistor 820 when the shunt devices are being used as attenuators.

[0057] While it is possible to implement a shunt transistor as a single transistor if the maximum signal level is lower than the maximum drain-source voltage that the FET can sustain. More likely, the shunt transistor will be implemented with a stacked FET configuration, as illustrated in Figure 8. A four-FET stack is shown, but other numbers of FETs are within the scope of the present disclosure.

[0058] Similarly, the series switches 210(l)-210(2) may be implemented as a plurality of FETs as illustrated in Figure 9. The digital control circuit 222 writes to a register (not shown) representing the Vclamp analog voltage. This value is then provided to Vclamp DACs 900, 902. In turn, this value is provided to the gates of the FETS 904(1)-904(M), 906(1 )-906(M) (where as shown M=4). The DACs 900, 902 may include a matching VGS to offset the VGS of the switch.

[0059] Note that one limitation of using a series switch as an analog clamp is the fact that the strength of the series switch sets a limit on a threshold for the clamp. A relatively small size of the series switch will result in a large VGS drop on the switch, and thus, the analog clamping voltage will be lower, corresponding to a lower power level. To implement a higher value clamping threshold, a larger size series switch is needed. Just increasing the size is not practical. However, given that the multiplexer has at least one other signal path, there are likely to be unused series switches in the inactive paths. When the series switch is a set of FETs as illustrated in Figure 9, there are at least a few FETs in an unused branch that may be used without compromising the isolation of the MUX. By using these inactive FETs, the equivalent size of the active switch may be increased, thereby increasing the maximum possible power clamp level. Figure 10 illustrates a switching network 1000 that enables such reuse. Note that the precise arrangement of such reuse is not central to the present disclosure and may depend on how many input lines are present, as well as how large M is.

[0060] Figure 11 discloses a flowchart of a process 1100 for consolidating MUX functions with power protection functions. In this regard, the process 1100 begins by generating a signal to be transmitted (block 1102), for example, in a baseband processor (not shown). This signal may be transmitted using a known wireless protocol, and a power level may be set at a desired level (block 1104) according to the rules of the wireless protocol. The signal may be upconverted by an intermediate frequency processor and then again upconverted to RF or converted directly to an RF signal, as is well known. This RF signal is passed to the power amplifier front-end module of a transmission chain with power level instructions (block 1106). A bias and a supply voltage for the output amplifier stage 114 are set (block 1108) based on the power level instructions. The supply voltage may be set by a power management integrated circuit (PMIC) or the like.

[0061] With continued reference to Figure 11, the signal passes into the MUX-protection circuit 200 through an input line 208 (block 1110). The power detector 202 senses the power at the node 204 (block 1112). The sensed power level is compared to a threshold (block 1114). Responsive to detecting that the sensed power exceeds the threshold, series switches 210(1 )-210(2) are reused to provide a voltage clamp (block 1116). Additionally, the shunt transistors 212, 214, 216 are used with the series switches 210( 1)-210(2) to provide attenuation (block 1118). Optionally, the clamp and attenuation may be further adjusted based on the second power detector 600 (block 1120).

[0062] The power amplifier protection circuit with low insertion loss, according to aspects disclosed herein, is well-suited for any device that includes a power amplifier in a transmission chain for wireless communication and may be provided in or integrated into any processor-based device. Examples, without limitation, include a set- top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smartphone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smartwatch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter.

[0063] Figure 12 is a schematic diagram of an exemplary mobile communication device 1200, wherein the power amplifier with a protection circuit and low insertion loss, as described above, can be provided. Herein, the communication device 1200 can be any type of communication device, such as those listed above as well as access points, base stations (e.g., eNB or gNB), and any other type of wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, Ultra-wideband (UWB), and near field communications.

[0064] More particularly, the communication device 1200 will generally include a control system 1202, a baseband processor 1204, transmit circuitry 1206, receive circuitry 1208, antenna switching circuitry 1210, multiple antennas 1212, and user interface circuitry 1214. In a non-limiting example, the control system 1202 can be a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), as an example. In this regard, the control system 1202 can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus intcrfacc(s). The receive circuitry 1208 receives radio frequency signals via the antennas 1212 and through the antenna switching circuitry 1210 from one or more base stations. A low noise amplifier and a filter of the receive circuitry 1208 cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signalto an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter(s) (ADC).

[0065] The baseband processor 1204 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations. The baseband processor 1204 is generally implemented in one or more digital signal processors (DSPs) and ASICs.

[0066] For transmission, the baseband processor 1204 receives digitized data, which may represent voice, data, or control information, from the control system 1202 and encodes it for transmission. The encoded data is output to the transmit circuitry 1206, where a digital-to-analog converter(s) (DAC) converts the digitally encoded data into an analog signal, and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission and deliver the modulated carrier signal to the antennas 1212 through the antenna switching circuitry 1210 to the antennas 1212. The multiple antennas 1212 and the replicated transmit and receive circuitries 1206, 1208 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0067] It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in various sequences other than the illustrated ones. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications, as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0068] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosurewill be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

AMENDED CLAIMSreceived by the International Bureau on 20 April 2026 (20.04.2026)

1. (Currently Amended) A power amplifier front-end comprising:a multiplexer comprising a plurality of input lines, each with a corresponding series switch configured to select one input line to be connected to an output node;a power detector coupled to the output node and configured to provide a feedback signal indicative of a sensed power level;a clamp formed from at least one of the corresponding series switches, wherein the clamp is configured to clamp a voltage level passing to the output node; andan attenuator comprising the at least one of the corresponding series switches and a first shunt transistor,wherein the clamp and the attenuator are variable and configured to be set responsive to the feedback signal from the power detector.

2. (Currently Amended) The power amplifier front-end of claim 1,wherein the attenuator comprises a If-network formed from the at least one of the corresponding series switches, the first shunt transistor, and a second shunt transistor.

3. (Original) The power amplifier front-end of claim 1, further comprising a clamp control circuit coupled to the clamp.

4. (Original) The power amplifier front-end of claim 3, wherein the clamp control circuit is configured to receive the feedback signal.

5. (Original) The power amplifier front-end of claim 1, further comprising an attenuator control circuit coupled to the attenuator.

6. (Original) The power amplifier front-end of claim 5, wherein the attenuator control circuit is configured to receive the feedback signal.

7. (Original) The power amplifier front-end of claim 5, further comprising a clamp control circuit coupled to the clamp, wherein the clamp control circuit and the attenuator control circuit are configured to receive digital signals from a digital control circuit, wherein the digital signals are based on the feedback signal.

8. (Currently Amended) The power amplifier front-end of claim 1,wherein the at least one of the corresponding series switches comprises a plurality of transistors.

9. (Original) The power amplifier front-end of claim 1, wherein the first shunt transistor comprises a plurality of stacked transistors.

10. (Original) The power amplifier front-end of claim 5, wherein the attenuator control circuit is configured to use an analog signal to control the attenuator.

11. (Original) The power amplifier front-end of claim 7, wherein the clamp control circuit is configured to use a second analog signal to control the clamp.

12. (Original) The power amplifier front-end of claim 1 integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smartphone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.

13. (Currently Amended) A communication device comprising a transmission chain comprising:a power amplifier die comprising an output amplifier stage;a power amplifier front-end, the power amplifier front-end comprising: a multiplexer comprising a plurality of input lines, each with a corresponding series switch configured to select one input line to be connected to the power amplifier die through an output node;a power detector coupled to the output node and configured to provide a feedback signal indicative of a sensed power level;a clamp formed from at least one of the corresponding series switches, wherein the clamp is configured to clamp a voltage level passing to the output node; andan attenuator comprising the at least one of the corresponding series switches and a first shunt transistor,wherein the clamp and the attenuator are variable and configured to be set responsive to the feedback signal from the power detector.

14. (Original) The communication device of claim 13, further comprising a second power detector coupled to an output of the power amplifierdie, the second power detector configured to provide a second feedback signal.

15. (Original) The communication device of claim 13, further comprising a digital control circuit configured to receive the feedback signal and generate control signals for the clamp and the attenuator.

16. (Original) A method of protecting a power amplifier die, comprising:providing a plurality of signals to a multiplexer-protection circuit; selecting a signal from the plurality of signals using a series switch; clamping a voltage level for the signal using the series switch; and using the series switch as part of an attenuator.

17. (Original) The method of claim 16, further comprising sensing a power level at an output node of the multiplexer-protection circuit.

18. (Original) The method of claim 17, further comprising controlling the attenuator based on the power level.

19. (Original) The method of claim 17, further comprising setting the voltage level with the series switch based on the power level.

20. (Original) The method of claim 16, further comprising receiving a feedback signal from a power detector proximate an antenna and controlling the attenuator at least in part based on the feedback signal.

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