Method for forming non-orthogonal via openings using directional etching

Abstract

A method for forming interconnected features in a semiconductor device comprises forming a first feature on or in a substrate, forming first and second layers over the first feature, and patterning the second layer to form an opening. A directional etch is used to form a via opening in the first layer with a non-orthogonal alignment to the first feature, compensating for any misalignment between the opening in the second layer and the first feature. This approach enables the formation of a second feature in contact with the first feature despite initial misalignment. The directional etch can be configured to improve alignment based on determined overlay errors. The method can be extended to simultaneously form multiple via openings with different non-orthogonal alignments in different directions to connect multiple features on the substrate, allowing for the formation of third and fourth features in contact with respective first and second features.

Description

[0001] METHOD FOR FORMING NON-ORTHOGONAL VIA OPENINGS USING DIRECTIONAL ETCHING

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims priority to US. Ser. No. 63 / 747,519, which is incorporated herein by reference in its entirety.

[0004] TECHNICAL FIELD

[0005] The present disclosure relates to semiconductor device fabrication, and more particularly to methods for forming via openings with non-orthogonal alignment to connect features in different layers of a semiconductor device.

[0006] BACKGROUND OF THE INVENTION

[0007] In semiconductor manufacturing, forming interconnect structures is crucial for enabling electrical connections in integrated circuits. Traditional methods involve creating features on a substrate, depositing dielectric layers, patterning, and etching via openings to connect metal layers. These processes typically use orthogonal etching to create vertical via openings aligned with underlying features.

[0008] Various prior art methods exist for forming via openings in dielectric layers. A common technique, disclosed in US patent application 18 / 965,940, which is incorporated herein by reference in its entirety and uses a mask layer to pattern and transfer via openings into dielectric layers, requiring precise alignment for proper connections.

[0009] Directional etching processes have been explored to modify feature characteristics. See for example, these patent applications and patents: US10535522B1 Angular control of ion beam for vertical surface treatment; US10971368B2 Techniques for processing substrates using directional reactive ion etching; US20190096739A1 Method and equipment for forming gaps in a material layer; US20200117080A1 Techniques for forming angled structures; US20240136197A1 Modifying patterned features using a directional etch; and US20240234161A9 Modifying patterned features using a directional etch. Some methods use tuned etching to direct species horizontally, and dynamic-angle plasma etching changes the plasma flux angle during etching. These offer directional control but haven't fully addressed overlay misalignment by creating non-orthogonal via openings.The challenge is establishing reliable connections between layers with overlay errors, especially with closely spaced features. Extending via openings for better alignment can cause electrical shorts or increased parasitic capacitance, degrading performance and reliability. A solution is needed to address misalignment while maintaining isolation between closely spaced features.

[0010] SUMMARY OF THE INVENTION

[0011] Although illustrative embodiments of one or more aspects are provided herein, the disclosed processes may be implemented using any number of techniques. The disclosure is not limited to the illustrative or specific embodiments, any drawings, and any techniques illustrated herein, including any exemplary designs and embodiments illustrated and described herein, and may be modified within the scope of the appended claims along with their full scope of equivalents.

[0012] The present disclosure relates to methods for improving overlay alignment between layers in semiconductor fabrication while preventing electrical shorting and minimizing undesired capacitance between closely spaced features. The methods selectively extend certain vias / features to improve overlay alignment with underlying features, while preventing extension in cases where underlying features are particularly close to each other.

[0013] FIG. 1 shows the state of the art in overlay correction in which an originally formed via 102 is misaligned to a feature 104. A GCB or other directional etch is used to extend the via to be in better alignment with the underlying feature 104 as an extended via 106 as shown in FIG. 2.

[0014] In one aspect of this disclosure, shown in FIG. 3, a method includes forming a first feature 104 on or in a substrate, forming a first layer 105 over the first feature 104, and forming a second layer (not shown) over the first layer. The method further includes patterning the second layer to form an opening in the second layer, using a directional etch to form a via opening in the first layer, the via opening having a non-orthogonal alignment to the first feature, and forming a second feature 108 in contact with the first feature.

[0015] In one aspect, the method includes determining that the opening in the second layer has an overlay error and misalignment with the first feature in the z-direction, and configuring the directional etch to improve alignment of the opening with the first feature.According to another aspect of the present disclosure, shown in FIG. 4 a method includes forming a first feature 110 on or in a substrate 112, forming a first layer 122 over the first feature 110, and forming a second layer 120 over the first layer 122. The method further includes patterning the second layer 120 to form a first opening in the second layer 120, the opening misaligned from the first feature 110. Using a directional etch (illustrated by arrows) a second opening is formed in the first layer 122, the second opening having a non-orthogonal alignment extending from the misaligned first opening to the first feature 110, and forming a second feature (not shown) in the second opening, the second feature in contact with the first feature.

[0016] According to another aspect of the present disclosure, a method includes forming a first feature and second feature on or in a substrate, forming a first layer over the first and second feature, and forming a second layer over the first layer. The method further includes patterning the second layer to form a first and second opening in the second layer, using a directional etch process to form a first via opening in the first layer having a non-orthogonal alignment to the first feature, and a second via opening in the first layer having a non-orthogonal alignment to the second feature. The method also includes forming a third feature in the first via opening and in contact with the first feature, and forming a fourth feature in the second via opening and in contact with the second feature.

[0017] According to another aspect of the present disclosure, a method includes forming a first feature and second feature on or in a substrate, forming a first layer over the first and second feature, and forming a second layer over the first layer. The method further includes patterning the second layer to form a first and second opening in the second layer, using a directional etch process to form a first via opening in the first layer having a non-orthogonal alignment to the first feature in a first direction, and a second via opening in the first layer having a non-orthogonal alignment to the second feature in a second direction. The method also includes forming a third feature in the first via opening and in contact with the first feature, and forming a fourth feature in the second via opening and in contact with the second feature. Further areas of applicability will become apparent from the description provided herein. It should be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.

[0018] BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows one aspect of the state of the art. FIG. 2 shows one aspect of the state of the art.FIG. 3 shows an aspect of the present disclosure. FIG. 4 shows an aspect of the present disclosure. FIG. 5 shows an aspect of the present disclosure. FIG. 6 shows an aspect of the present disclosure. FIG. 7 A shows an aspect of the present disclosurei n which the opening formed in the first layer is smaller than the underlying first feature. FIG. 7B shows a process where multiple steps with multiple angles of etch create a larger opening, such as an opening as wide as the underlying first feature.

[0019] FIG. 8 shows an aspect of the present disclosure in which layer 120 is kept and then the via is selectively filled using selective deposition on (or growth of) layer 120. This could better re-align top of upper feature with bottom feature while keeping general dimensions of the upper feature more constant. FIGS. 9 and 10 illustrate top-down and side views showing misalignments in multiple directions which may be due to scaling or other issue causing overlay error.

[0020] FIG. 11 shows an aspect of the present disclosure in which the focused directional etch (gas cluster, ion beam, ion ribbon) could be tilted and / or scanned in different directions for different regions. The substrate could be rotated relative to the source if the misalignments are consistent in the "north," "south," "east," and "west" directions.

[0021] FIG. 12 shows an aspect of the present disclosure in which the directional etch source is scanned in a direction while tilted (and / or the substrate could be moved relative to the source).

[0022] FIG. 13 shows an aspect of the present disclosure in which the scan direction is changed (e.g., back and forth) or customized to correct overlay error in different directions in different regions (e.g. bidirectional scan in one region, E-directional scan in another region.

[0023] FIG. 14 shows an aspect of the present disclosure in which the directional etch would remove material under the patterned layer with overlay error to tunnel toward underlying feature. The upper layer could be retained in the stack and the substrate further processed.

[0024] FIG. 15 shows an alternative to FIG 14 in which the mask layer is removed.

[0025] FIG. 16 shows an aspect of the present disclosure in which the vias are filled with conductive material using ALD or other suitable process to complete the via.

[0026] FIGS. 17 and 18 show aspects of the present disclosure in which subsequent patterns formed above the via are adjusted to accommodate the misalignment and correction.FIG. 19 shows an aspect of the present disclosure in which chiplets are locally aligned to top of the slanted feature which may be adjusted from the original design due to the offset.

[0027] FIG. 20 shows an aspect of the present disclosure in which devices and systems are designed to take advantage of slanted vias even in the case of no misalignment. This technique could allow the vias to provide some redistribution / routing.

[0028] FIG.21 shows an aspect of the present disclosure in which two adjusted patterns are bonded. This could be useful in bonded CFET where the first active wafer (e.g., with NFET) has similar overlay error and correction as second active wafer (e.g. with PFET).

[0029] DESCRIPTION EXAMPLE EMBODIMENTS

[0030] In the specification, claims, and accompanying drawings of this application, terms "first”, "second", and so on are intended to distinguish between similar objects but do not necessarily indicate a specific order or sequence. It should be understood that the terms used in such a way are interchangeable in proper circumstances, which is merely a discrimination manner that is used when objects having a same attribute are described in embodiments of this application. In addition, the terms "include", "contain" and any other variants mean to cover the non-exclusive inclusion, so that a process, method, system, product, or device that includes a series of units is not necessarily limited to those units, but may include other units not expressly listed or inherent to such a process, method, product, or device.

[0031] A method is provided for forming features on a substrate with improved alignment capabilities. In the method, a first feature is formed on or in a substrate. This first feature is a conductive line, a via, a contact, or any other semiconductor device component that requires electrical connection.

[0032] After forming the first feature, a first layer is formed over the first feature. The first layer is an insulating layer such as silicon dioxide, silicon nitride, or a low-k dielectric material that provides electrical isolation between conductive elements. The first layer is deposited using techniques such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD) to ensure complete coverage of the first feature.

[0033] Next, a second layer is formed over the first layer. The second layer functions as a mask or as an additional insulating layer and is composed of materials such as silicon nitride, silicon carbide, or silicon oxynitride. The second layer is deposited using similar deposition techniques as the first layer,maintaining consistent thickness across the substrate surface. Alternatively, the layer may be an organic material such as a photoresist.

[0034] The method continues with patterning the second layer to form an opening in the second layer. This patterning process involves applying a photoresist layer over the second layer (if the second layer is not itself a photoresist), exposing the photoresist to a pattern of radiation through a photomask, developing the photoresist to form a pattern, and then etching the second layer through the photoresist pattern. The opening in the second layer defines the initial location for a subsequent via that will connect to the first feature.

[0035] After forming the opening in the second layer, a directional etch is used to form a via opening in the first layer. The directional etch is specifically configured to create a via opening having a non-orthogonal alignment to the first feature. This non-orthogonal alignment means that the via opening is formed at an angle relative to the vertical axis of the substrate, allowing the via to approach the first feature at an angle rather than directly from above. The directional etch can be performed using reactive ion etching (RIE), gas cluster beam (GCB), or other focused beam of etching species with specific gas chemistry and power settings that promote anisotropic etching in the desired direction.

[0036] The method includes determining that the opening in the second layer has an overlay error and misalignment with the first feature in the z-direction. This determination can be made using metrology tools such as scanning electron microscopy (SEM) or optical overlay measurement tools that identify the degree and direction of misalignment between the opening in the second layer and the target connection point on the first feature.

[0037] Based on this determination, the directional etch is configured to improve alignment of the opening with the first feature. The configuration includes adjusting parameters such as the angle of beam bombardment, the etch chemistry, the bias power, and the duration of the etch to direct the via path toward the intended connection point on the first feature. By angling the etch direction, the method compensates for the initial misalignment in the z-direction, allowing the via to reach the target connection point despite the overlay error.

[0038] Finally, a second feature is formed in contact with the first feature. The second feature can be a conductive material such as copper, aluminum, tungsten, ruthenium, cobalt, nickel or other conductive metal or alloy that fills the via opening and establishes electrical contact with the first feature. The formation of the second feature typically involves depositing a barrier layer and a seed layer followed byfilling the via opening with the conductive material using techniques such as electroplating, physical vapor deposition (PVD), or chemical vapor deposition (CVD).

[0039] In an embodiment, the directional etch is adjusted based on the magnitude and direction of the overlay error. For minor misalignments, the etch angle may be adjusted by 5 to 15 degrees from vertical. For more significant misalignments, the etch angle may be increased to 15 to 30 degrees from vertical to ensure proper connection with the first feature. Angles of up to 85 degrees may be possible.

[0040] This method provides significant advantages in semiconductor fabrication by allowing recovery from misalignment errors that would otherwise result in failed connections between features. The non-orthogonal via formation enables electrical connections to be established even when perfect vertical alignment cannot be achieved, improving manufacturing yield and device reliability.

[0041] In an embodiment, a method for forming a semiconductor structure includes forming interconnected features through multiple layers.

[0042] The method comprises:

[0043] SI: Forming a first feature on or in a substrate. The first feature is a conductive element such as a metal line, a via, a contact, or a semiconductor device structure formed within the substrate. The first feature is formed using conventional semiconductor fabrication techniques such as deposition, patterning, and etching processes. In a specific implementation, the first feature is formed by depositing a conductive material into a trench or opening previously formed in the substrate, followed by a planarization process to remove excess material.

[0044] S2: Forming a first layer over the first feature. The first layer is deposited over the substrate and the first feature using techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or spin-on processes. The first layer comprises a dielectric material such as silicon dioxide, silicon nitride, a low-k dielectric, or a combination thereof. The thickness of the first layer ranges from 50 nm to 500 nm, with specific implementations at 100 nm, 250 nm, and 400 nm depending on the device requirements.

[0045] S3: Forming a second layer over the first layer. The second layer is deposited over the first layer using similar deposition techniques as used for the first layer. The second layer comprises a material different from the first layer to provide etch selectivity during subsequent processing steps. For example, if the first layer is silicon dioxide, the second layer is silicon nitride or a different dielectric material. Thesecond layer typically has a thickness ranging from 30 nm to 300 nm, with specific implementations at 50 nm, 150 nm, and 250 nm.

[0046] S4: Patterning the second layer to form a first opening in the second layer, the opening misaligned from the first feature. The patterning process includes applying a photoresist layer over the second layer, exposing the photoresist through a mask, developing the photoresist to form a pattern, and then etching the second layer through the photoresist pattern. The misalignment between the first opening and the first feature may be intentional or unintentional, with the offset distance ranging from 5 nm to 100 nm depending on the specific device requirements. The misalignment may be in any direction relative to the first feature, including lateral displacement, rotational offset, or a combination thereof. S5: Using a directional etch to form a second opening in the first layer, the second opening having a non- orthogonal alignment extending from the first opening to the first feature. The directional etch is performed using an anisotropic etching process such as an ion beam, gas cluster beam (GCB), or other etch process that can be limited in its location and directed in a specific non-orthogonal direction. The etch parameters are carefully controlled to correct the non-orthogonal alignment of the first layer, with the etch angle ranging from 30 degrees to 85 degrees relative to the substrate surface. The directional etch is performed at a power of 50W to 500W, a pressure of 1 mTorr to 100 mTorr, and for a duration of 30 seconds to 5 minutes. The non-orthogonal alignment of the second opening creates a pathway that connects the first opening to the first feature despite their initial misalignment.

[0047] S6: Forming a second feature in the second opening, the second feature in contact with the first feature. The second feature is formed by depositing a conductive material into the second opening. The deposition process may include physical vapor deposition, chemical vapor deposition, electroplating, or a combination thereof. The conductive material may be the same as or different from the material of the first feature, and may include metals such as copper, aluminum, tungsten, ruthenium, or conductive compounds. After deposition, a planarization process such as chemical mechanical polishing (CMP) may be performed to remove excess material and provide a flat surface for subsequent processing steps. In an embodiment, the directional etch used to form the second opening is performed using a multi-step etching process. The first step uses a higher power setting of 400W to 500W to initiate the opening, followed by a second step at a lower power setting of 100W to 200W to carefully control the angle and trajectory of the etch path toward the first feature.In another embodiment, the second feature is formed using a selective deposition process that deposits material in the second opening without requiring a subsequent planarization step. This selective deposition process involves a nucleation layer followed by a bottom-up fill process that minimizes void formation in the conductive path.

[0048] The resulting structure provides a reliable electrical connection between the first and second features despite their initial misalignment, which increases manufacturing yield and allows for greater flexibility in circuit design. The non-orthogonal connection path also enables more compact device layouts by accommodating misalignments that would otherwise require larger design rules or spacing between features.

[0049] In an embodiment, a method for forming interconnections with non-orthogonal alignment is provided. The method includes forming a first feature and second feature on or in a substrate. The first and second features are conductive lines, metal traces, or active regions formed through deposition, etching, or implantation processes on a semiconductor substrate. The first and second features are formed using conventional photolithography techniques, where a photoresist layer is deposited, exposed through a mask, developed, and then the underlying material is etched to form the desired features.

[0050] After forming the first and second features, a first layer is formed over the first and second features. The first layer is an interlayer dielectric (I LD) material such as silicon dioxide, silicon nitride, or a low-k dielectric material. The first layer is formed using chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or spin-on techniques. The thickness of the first layer ranges from about 100 nm to about 1000 nm, providing sufficient electrical isolation between the underlying features and subsequent conductive structures.

[0051] Next, a second layer is formed over the first layer. The second layer is a could be a mask material such as silicon nitride, silicon carbide, silicon oxynitride, or photoresist. The second layer is deposited using CVD, PECVD, or atomic layer deposition ( ALD) techniques. The thickness of the second layer ranges from about 50 nm to about 300 nm, providing sufficient etch resistance during subsequent processing.

[0052] The method continues by patterning the second layer to form a first and second opening in the second layer. The patterning may also be performed using photolithography, where a photoresist layer is exposed using a desired pattern, and developed. The exposed portions of the second layer are then removed to form the first and second openings. The openings in the second layer define the locations where via openings will be formed in the underlying first layer.After forming the openings in the second layer, a directional etch process is used to form a first via opening in the first layer and a second via opening in the first layer. The directional etch process is an anisotropic etch process such as a VCB or ion beam with specific gas chemistry tailored to the composition of the first layer. The directionality of the etch process is controlled by adjusting the bias power, pressure, and gas flow rates in the etch chamber.

[0053] Importantly, the first via opening has a non-orthogonal alignment to the first feature, and the second via opening has a non-orthogonal alignment to the second feature. The non-orthogonal alignment means that the via openings are not perpendicular to the plane of the underlying features but instead are formed at an angle. This angled approach allows for improved electrical performance by reducing the resistance and capacitance of the resulting interconnection structure. The angle of the via openings relative to the underlying features may be between about 30 degrees and about 85 degrees. The direction of misalignment may be different for different features across the wafer.

[0054] The non-orthogonal alignment is achieved by tilting the substrate or the beam during the directional etch process. The angle of the via openings is controlled by adjusting the process parameters of the directional etch, such as gas composition, chamber pressure, and bias power along with the tilt. The non-orthogonal alignment enables more efficient routing of interconnections in complex integrated circuit designs, particularly in areas where space constraints limit conventional orthogonal via placement.

[0055] After forming the via openings, a third feature is formed in the first via opening and in contact with the first feature. Similarly, a fourth feature is formed in the second via opening and in contact with the second feature. The third and fourth features are conductive materials such as copper, aluminum, tungsten, ruthenium or other suitable metals or metal alloys.

[0056] The formation of the third and fourth features may involve depositing a barrier layer, such as titanium nitride or tantalum nitride, along the sidewalls and bottom of the via openings to prevent diffusion of the conductive material into the surrounding dielectric. A seed layer may then be deposited, followed by filling the via openings with the conductive material using techniques such as electroplating, physical vapor deposition, or chemical vapor deposition. After filling the via openings, excess material may be removed using chemical mechanical polishing (CMP) to planarize the surface.

[0057] The resulting structure provides electrical connections between the first and third features and between the second and fourth features, with the non-orthogonal alignment of the connections offeringadvantages in terms of reduced resistance, improved signal integrity, and more efficient use of chip area. The non-orthogonal vias can be particularly beneficial in high-frequency applications where signal integrity is critical, as they can reduce parasitic capacitance and inductance compared to conventional orthogonal vias.

[0058] The directional etch process may include a two-step etch, where an initial isotropic etch creates a slight undercut in the first layer beneath the openings in the second layer, followed by an anisotropic etch that forms the angled via openings. This two-step approach provides better control over the final angle and profile of the via openings.

[0059] In an embodiment of the present method, a semiconductor device is fabricated through a process that creates non-orthogonal via connections between different layers. The method includes multiple steps for forming interconnect structures with specific alignment characteristics.

[0060] The method begins with forming a first feature and a second feature on or in a substrate. The substrate is a semiconductor substrate such as silicon, silicon-on-insulator, or other suitable semiconductor material. The first and second features are conductive structures such as metal lines, contact pads, or active regions formed through deposition, etching, or implantation techniques. These features serve as connection points for subsequent layers and provide electrical pathways within the semiconductor device.

[0061] After forming the first and second features, a first layer is formed over both the first and second features. The first layer is a dielectric material such as silicon dioxide, silicon nitride, or a low-k dielectric material. This first layer provides electrical isolation between the underlying features and subsequent conductive structures. The first layer is deposited using techniques such as chemical vapor deposition (CVD), physical vapor deposition ( PVD), or atomic layer deposition (ALD) to achieve a uniform coverage over the topography created by the first and second features.

[0062] Following the formation of the first layer, a second layer is formed over the first layer. The second layer is another dielectric material, potentially with different etch characteristics than the first layer to enable selective etching processes. This second layer serves as a mask layer for subsequent via formation and helps define the locations where vias will be created to connect to the underlying features.

[0063] The method continues with patterning the second layer to form a first opening and a second opening in the second layer.Next, a directional etch process is used to form a first via opening in the first layer and a second via opening in the first layer. The directional etch process is an anisotropic plasma etch that preferentially etches in the vertical direction. Importantly, the first via opening is formed with a non-orthogonal alignment to the first feature in a first direction. Similarly, the second via opening is formed with a non- orthogonal alignment to the second feature in a second direction. The non-orthogonal alignment means that the via openings are not perfectly perpendicular to the surface plane of the respective features, but rather are formed at an angle.

[0064] The non-orthogonal alignment of the via openings may be achieved through various techniques, such as using specialized etch chemistries, adjusting etch parameters like pressure and power, or employing specialized masks with offset patterns. This non-orthogonal alignment provides advantages in terms of device density, reduced parasitic capacitance, or improved electrical performance by optimizing the connection path between different layers.

[0065] After forming the via openings, the method proceeds with forming a third feature in the first via opening. The third feature is in contact with the first feature, creating an electrical connection between them. The third feature is formed by depositing a conductive material such as copper, aluminum, tungsten, or a combination thereof, followed by a planarization process such as chemical mechanical polishing (CMP) to remove excess material outside the via opening.

[0066] Similarly, a fourth feature is formed in the second via opening and is in contact with the second feature. This fourth feature is formed using the same or similar processes as the third feature and establishes an electrical connection to the second feature. The third and fourth features may be formed simultaneously or in separate processing steps depending on the specific requirements of the device being fabricated.

[0067] The directional etch process comprises parameters specifically tuned to achieve the non-orthogonal alignment of the via openings. The etch chemistry may include fluorocarbon gases for etching dielectric materials, with the addition of other gases to control the etch profile and selectivity.

[0068] In another embodiment, the first direction and the second direction are different from each other, resulting in via openings which may also have different angles relative to the substrate surface. This configuration allows for optimized routing of connections in different regions of the device.

[0069] In yet another embodiment, the method further includes forming additional layers and interconnections above the third and fourth features to create a multi-level interconnect structure. This multi-levelstructure enables complex routing of electrical signals throughout the semiconductor device while maintaining the benefits of the non-orthogonal via connections.

[0070] The resulting semiconductor device with non-orthogonal via connections provides improved electrical performance due to shorter connection paths between features in different layers. Additionally, the non-orthogonal alignment allows for greater design flexibility in routing connections and can enable higher integration density of components within the semiconductor device.

[0071] In embodiments, unless otherwise stated or there is a logic conflict, terms and / or descriptions in different implementations are consistent and may be mutually referenced, and technical features in different embodiments may be combined based on an internal logical relationship thereof, to form a new embodiment.

Claims

Claims1. A method comprising:forming a first feature on or in a substrate;forming a first layer over the first feature;forming a second layer over the first layer;Patterning the second layer to form an opening in the second layer;using a directional etch to form a via opening in the first layer, the via opening having a non orthogonal alignment to the first feature; andForming a second feature in contact with the first feature.

2. The method of claim 1 further comprising:determining that the opening in the second layer has an overlay error and misalignment with the first feature in the z-direction; andconfiguring the directional etch to improve alignment of the opening with the first feature.

3. A method comprising:forming a first feature on or in a substrate;forming a first layer over the first feature;forming a second layer over the first layer;Patterning the second layer to form a first opening in the second layer, the opening misaligned from the first feature;using a directional etch to form a second opening in the first layer, the second opening having a non orthogonal alignment extending from the first opening to the first feature; andforming a second feature in the second opening, the second feature in contact with the first feature.

4. A method comprising:forming a first feature and second feature on or in a substrate;forming a first layer over the first and second feature;forming a second layer over the first layer;patterning the second layer to form a first and second opening in the second layer;using a directional etch process to forma first via opening in the first layer, the first via opening having a non orthogonal alignment to the first feature, anda second via opening in the first layer, the second via opening having a non orthogonal alignment to the second feature;forming a third feature in the first via opening and in contact with the first feature; and forming a fourth feature in the second via opening and in contact with the second feature.

5. A method comprising:forming a first feature and second feature on or in a substrate;forming a first layer over the first and second feature;forming a second layer over the first layer;patterning the second layer to form a first and second opening in the second layer;using a directional etch process to forma first via opening in the first layer, the first via opening having a non orthogonal alignment to the first feature in a first direction, anda second via opening in the first layer, the second via opening having a non orthogonal alignment to the second feature in a second direction;forming a third feature in the first via opening and in contact with the first feature; and forming a fourth feature in the second via opening and in contact with the second feature.

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