Wrap around contact epi process sequence

Abstract

The present disclosure generally relates to methods for forming a semiconductor device, a semiconductor device, and a processing system. The method includes forming a first epitaxial semiconductor layer on a cavity within the source / drain region of a semiconductor device structure formed on a substrate, forming a second highly doped recessed semiconductor layer that wraps around the first epitaxial semiconductor layer, and forming a metal contact plug. The first epitaxial semiconductor layer and the second epitaxial semiconductor layer are formed without breaking vacuum in the processing system. Embodiments of the present disclosure enable the formation of the semiconductor device that includes one or more layers with reduced contact resistance by using integrated processes that allows various operations of epitaxial semiconductor layer formation be performed within the same processing system.

Description

PATENTAttorney Docket No.: 44025279WO01WRAP AROUND CONTACT EPI PROCESS SEQUENCE BACKGROUNDField

[0001] Embodiments of the present invention generally relate to an apparatus, a method, and more specifically to a semiconductor device fabrication, and methods of forming electrical contacts within a semiconductor device structure.

[0002] Transistors are fundamental device elements of modern digital processors and memory devices, and have found applications in high-power electronics. Currently, there are a variety of transistor designs or types that may be used for different applications. Various transistor types include, for example, bipolar junction transistors (BJT), junction field-effect transistors (JFET), metal-oxide-sem iconductor field-effect transistors (MOS FET), vertical channel or trench field-effect transistors, and superjunction or multi-drain transistors. One or more of these types of transistors can be useful in both logic and memory applications.

[0003] A key challenge in semiconductor design, manufacture, and operation is contact resistance. Contact resistance is becoming a significant proportion of the overall device resistance due to scaling trends in 3D semiconductor devices. Multigate metal-oxide-sem iconductor field-effect transistors (MOS FETs) pose challenges in manufacturability due to their three-dimensional (3D) designs and small sizes. For example, during design and manufacture, or forming of metal oxide semiconductor (MOS) transistor semiconductor devices, such as those used in a complementary metal oxide semiconductor (CMOS), it is often desired to minimize contact resistance. Contacts that include a high contact resistance will have a decreased device performance. Increasing device performance of circuit containing devices including transistors, diodes, resistors, capacitors, and other passive and active electronic devices formed on a semiconductor substrate is typically a major factor considered during design, manufacture, and operation of those devices.

[0004] Therefore, there is a need for devices that include contacts with a decreased contact resistance and methods of forming the same.PATENTAttorney Docket No.: 44025279WO01SUMMARY

[0005] Embodiments of the present disclosure provide a semiconductor device comprising a semiconductor structure having a p-type metal oxide semiconductor (pMOS) region, the semiconductor device further comprising: a source / drain region comprising a first doping concentration of boron doped silicon germanium (SixGei-x):B, a first epitaxial semiconductor layer disposed within a cavity formed in the source / drain region, wherein the first epitaxial semiconductor layer comprises a second doping concentration of boron doped silicon germanium (SixGei-x):B, and the second doping concentration of boron doped silicon germanium is greater than the first doping concentration of boron doped silicon germanium; a second epitaxial semiconductor layer disposed within a first cavity, wherein the first cavity is formed within the first epitaxial semiconductor layer, and the second epitaxial semiconductor layer further comprises a third doping concentration of boron doped silicon germanium (SixGei-x):B, wherein the third concentration of (SixGei-x):B is greater than each of the first doping concentration and the second doping concentration of (SixGei-x):B; a metal silicide layer disposed on a second cavity, wherein the second cavity is formed within the second epitaxial semiconductor layer; and a metal contact plug, wherein the metal contact plug further comprises a conductor filled in a trench, wherein the trench is formed in a dielectric material to expose at least a portion of the second epitaxial semiconductor layer.

[0006] Embodiments of the present disclosure may further provide a semiconductor device comprising a semiconductor structure having a p-type metal oxide semiconductor (pMOS) region, the semiconductor device further comprising: a source / drain region comprising a first doping concentration of boron doped silicon germanium (SixGei-x):B, a first epitaxial semiconductor layer disposed within a first cavity within the source / drain region, wherein the first epitaxial semiconductor layer comprises a second doping concentration of boron doped silicon germanium (SixGei-X):B, and the second doping concentration of boron doped silicon germanium is greater than the first doping concentration of boron doped silicon germanium; one or more second epitaxial semiconductor layers disposed within one or more second cavities, wherein the one or more second cavities are formed within the first epitaxial semiconductor layer, and the second epitaxial semiconductor layer further comprisesPATENTAttorney Docket No.: 44025279WO01a third doping concentration of boron doped silicon germanium (SixGei-x):B, wherein the third concentration of (SixGei-x):B is greater than each of the first doping concentration and the second doping concentration of (SixGei-x):B; a metal silicide layer disposed within at least one of the one or more second cavities, wherein the one or more second cavities are formed within at least one of the one or more second epitaxial semiconductor layers; and a metal contact plug, wherein the metal contact plug further comprises a conductor filled in a trench, wherein the trench is formed in a dielectric material to expose at least a portion of one of the one or more second epitaxial semiconductor layers.

[0007] Embodiments of the present disclosure provide a method of forming an electrical contact within a p-type metal oxide semiconductor (pMOS) region of a semiconductor device, comprising: forming a metal contact plug within a semiconductor material region of a semiconductor device structure formed on a substrate, and wherein the forming of the metal contact plug comprises: forming a first epitaxial semiconductor layer within a first cavity within a source / drain region of a semiconductor structure device formed on a substrate by an epitaxial process, wherein the source / drain region comprises a first doping concentration of epitaxially grown boron doped silicon germanium (SixGei-x):B, and the first epitaxial semiconductor layer comprises a second doping concentration of (SixGei-x):B; forming a second cavity within the first epitaxial semiconductor layer by an anisotropic cavity etch process, wherein the anisotropic cavity etch process comprises delivering a process gas comprising hydrogen (H2), chlorine (CI2) and one or more inert gases and biasing the substrate; forming a second epitaxial semiconductor layer within the second cavity by epitaxial process, the second epitaxial semiconductor layer further comprising a third doping concentration of boron doped silicon germanium (SixGei-x):B, wherein the third concentration of (SixGei-x):B is greater than each of the first doping concentration and the second doping concentration of (SixGei-x):B; and forming a third cavity within the second epitaxial semiconductor layer to form a metal contact plug, the metal contact plug further comprising a conductor filled in a trench, wherein the trench is formed in a dielectric material to expose at least a portion of the second epitaxial semiconductor layer.PATENTAttorney Docket No.: 44025279WO01

[0008] Embodiments of the present disclosure may further provide a method of forming an electrical contact within a p-type metal oxide semiconductor (pMOS) region of a semiconductor device, comprising: forming a metal contact plug within a semiconductor material region of a semiconductor device structure formed on a substrate, and wherein the forming of the metal contact plug comprises: forming a first epitaxial semiconductor layer within a first cavity within a source / drain region of a semiconductor structure device formed on a substrate by an epitaxial process, wherein the source / drain region comprises a first doping concentration of epitaxially grown boron doped silicon germanium (SixGei-x):B, and the first epitaxial semiconductor layer comprises a second doping concentration of (SixGei-x):B; forming a second cavity within the first epitaxial semiconductor layer by an isotropic cavity etch process, wherein the isotropic cavity edge process comprises partial removal of the first epitaxial semiconductor layer selective to the epitaxially grown boron doped silicon germanium (SixGei-x):B layer comprising the source / drain region; forming a second epitaxial semiconductor layer within the second cavity by epitaxial process, the second epitaxial semiconductor layer further comprising a third concentration of boron doped silicon germanium (SixGei-x):B, wherein the third concentration of (SixGei-x):B is greater than each of the first doping concentration and the second doping concentration of (SixGei-x):B; and forming a third cavity within the second epitaxial semiconductor layer to form a metal contact plug, the metal contact plug further comprising a conductor filled in a trench, wherein the trench is formed in a dielectric material to expose at least a portion of the second epitaxial semiconductor layer.

[0009] Embodiments of the present disclosure may further provide a method of forming an electrical contact within a p-type metal oxide semiconductor (pMOS) region of a semiconductor device, comprising: forming a source / drain region on the exposed surfaces of the semiconductor structure by epitaxial process, the source / drain region comprising a first concentration of boron doped silicon germanium (SixGei-x):B; removing a portion of the source / drain region to expose a surface of the semiconductor structure formed on a substrate by an anisotropic cavity etch process, wherein the anisotropic cavity etch process comprises delivering a process gas comprising hydrogen (H2), chlorine (CI2) and one or more inert gases and biasing the substrate; forming a first epitaxial semiconductor layer on the exposed surfaces of thePATENTAttorney Docket No.: 44025279WO01semiconductor structure within the source / drain region, wherein the first epitaxial semiconductor layer comprises a second doping concentration of boron doped silicon germanium (SixGei-x):B, and the second concentration of (SixGei-x):B is greater than the first doping concentration of (SixGei-x):B; forming one or more first cavities within the first epitaxial semiconductor layer by an isotropic cavity etch process, wherein the isotropic cavity edge process comprises partial removal of the first epitaxial semiconductor layer selective to the epitaxially grown boron doped silicon germanium (SixGei-x):B layer comprising the source / drain region; forming one or more second epitaxial semiconductor layers within at least one of the one or more first cavities by epitaxial process, wherein the one or more second epitaxial semiconductor layers comprises a third concentration of boron doped silicon germanium (SixGei-x):B, the third concentration of (SixGei-x):B is greater than each of the first doping concentration and the second doping concentration of (SixGei-x):B; and forming one or more second cavities within at least one of the one or more second epitaxial semiconductor layers to form a metal contact plug; the metal contact plug further comprising a conductor filled in a trench, wherein the trench is formed in a dielectric material to expose at least a portion of the one or more second epitaxial semiconductor layers.

[0010] Embodiments of the present disclosure further provide a processing system. The processing system includes a transfer chamber, one or more process chambers coupled to the transfer chamber, and a system controller configured to cause a processing system to perform operations including: forming a first epitaxial semiconductor layer in a cavity within the source / drain region of a semiconductor device formed on a substrate; forming a second epitaxial semiconductor layer on one or more first cavities, wherein the one or more first cavities are formed within the first epitaxial semiconductor layer; forming a metal silicide layer on one or more second cavities, where in the one or more second cavities are formed within the second epitaxial semiconductor layer, and the first epitaxial semiconductor layer, the one or more first cavities, the second epitaxial semiconductor layer, the one or more second cavities, and the metal silicide layer are formed without exposing the substrate to the atmosphere. The processing system further comprising: forming a dielectric material over the metal silicide layer; forming a trench in the dielectric material to expose atPATENTAttorney Docket No.: 44025279WO01least a portion of the one or more second epitaxial semiconductor layers; and filing the trench with a conductor.

[0011] Embodiments provided herein further include a method to optimize electrical contact formation within the second epitaxial semiconductor layer by reducing lateral growth by a cavity etch process, thus resulting in improved growth loading of the second epitaxial semiconductor layer comprising the highest doping concentration of (SixGei-x):B, the method comprising: directionally and non-conformably depositing a film layer over the material layers laterally adjacent to the first epitaxial semiconductor layer disposed within a first cavity within the source / drain region prior to the formation of the second cavity within the first epitaxial semiconductor layer; and forming a second cavity within the first epitaxial semiconductor layer by an anisotropic cavity etch process, wherein the anisotropic cavity etch process further comprises delivering a process gas comprising hydrogen (H2), chlorine (CI2) and one or more inert gases and biasing the substrate.

[0012] Embodiments provided herein further include an alternative method to optimize electrical contact formation within the second epitaxial semiconductor layer by reducing lateral growth by a cavity etch process, thus resulting in improved growth loading of the second epitaxial semiconductor layer comprising the highest doping concentration of (SixGei-x):B, the method comprising: forming a spacer protect liner (SPL) blanket (i.e., conformally) on the exposed surfaces of the first epitaxial semiconductor layer disposed within a first cavity within the source / drain region, and on the exposed surfaces of the material layers laterally adjacent to the first epitaxial semiconductor layer disposed within a first cavity within the source / drain region; etching the SPL blanket; and forming a second cavity within the first epitaxial semiconductor layer by an anisotropic cavity etch process, wherein the anisotropic cavity etch process further comprises delivering a process gas comprising hydrogen (H2), chlorine (CI2) and one or more inert gases and biasing the substrate.BRIEF DESCRIPTION OF THE DRAWINGS

[0013] So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of whichPATENTAttorney Docket No.: 44025279WO01are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of its scope, and may admit to other equally effective embodiments.

[0014] Figure 1 is a schematic top view of a multi-chamber processing system according to one or more embodiments of the present disclosure.

[0015] Figure 2A is a cross sectional view of a processing chamber, according to one or more embodiments of the present disclosure.

[0016] Figure 2B is an enlarged view of a portion of the processing chamber of Figure 2A, according to one or more embodiments of the present disclosure.

[0017] Figure 3 is a cross sectional view of a processing chamber, according to one or more embodiments of the present disclosure.

[0018] Figures 4A and 4B depict a cross-sectional view of a gate-all-around (GAA) device with a nanosheet structure according to one or more embodiments of the present disclosure.

[0019] Figure 5 is a flow diagram of the method 500 of forming an electrical contact in a semiconductor structure, according to one or more embodiments of the present disclosure.

[0020] Figure 6 is a flow diagram of the method 600 of forming an electrical contact in a semiconductor structure, according to one or more embodiments of the present disclosure.

[0021] Figures 7A-7B, 8A-8B, 9A - 9D, 10A-10B, and 11A-11B depict cross-sectional views of the gate-all-around (GAA) device illustrated in Figure 4B at different stages corresponding to the performance of one or more operations of the method 500 illustrated in Figure 5, according to one or more embodiments of the present disclosure.

[0022] Figures 12A-12B, 13A-13C, and 14A - 14D depict cross-sectional views of the gate-all-around (GAA) device illustrated in Figure 4B at different stagesPATENTAttorney Docket No.: 44025279WO01corresponding to the performance of one or more operations of the method 600 illustrated in Figure 6, according to one or more embodiments of the present disclosure.

[0023] Figure 15 is a flow diagram of the method 1500 for optimizing electrical contact formation on the semiconductor device illustrated in Figure 4B during the performance of one or more operations of method 500 depicted in Figure 5, according to one or more embodiments of the present disclosure.

[0024] Figure 16 is a flow diagram of the method 1600 for optimizing electrical contact formation on the semiconductor device illustrated in Figure 4B during the performance of one or more operations of method 600 depicted in Figure 6, according to one or more embodiments of the present disclosure.

[0025] Figures 17A - 17C, depict cross sectional views of a portion of the gate-all-around (GAA) device illustrated in Figure 4B at different stages of methods 1500 and 1600 depicted in Figures 15 and 16, respectively, according to one or more embodiments of the present disclosure.

[0026] Figures 18A - 18C, depict cross sectional views of a portion of the gate-all-around (GAA) device illustrated in Figure 4B at different stages of methods 1500 and 1600 depicted in Figures 15 and 16, respectively, according to one or more embodiments of the present disclosure.

[0027] Figure 19 is a side view of a directional deposition assembly according to one or more embodiments of the present disclosure.

[0028] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.DETAILED DESCRIPTION

[0029] Embodiments of the present disclosure generally relate to methods and systems for forming devices that include electrical contacts that have an improvedPATENTAttorney Docket No.: 44025279WO01contact resistance over conventional contact structure designs. More specifically, embodiments described herein provide methods for forming a semiconductor device, a semiconductor device, and a processing system. Embodiments of the disclosure include the formation of a source / drain region that includes a silicon containing epitaxially grown first material layer having a first doping concentration disposed on a silicon containing epitaxially grown second material layer having a second doping concentration, and a silicon containing epitaxially grown third material layer having a third doping concentration disposed within a cavity formed within the first material layer, wherein the third material layer is formed on the surface(s) of the first material layer. The first material layer has a lower electrical resistance than the second material layer, and the third material layer has a lower electrical resistance than the first material layer. As a result, the electrical contact resistance of the source / drain region is reduced. A processing system is configured to perform a method of forming the semiconductor device where at least the first material layer, the first cavity, the second material layer, and the third material layer are all formed without breaking vacuum in a processing system. Embodiments provided herein further include a method to optimize electrical contact formation within the first material layer by reducing lateral growth created during a cavity etch process, thus resulting in improved growth loading of the third material layer with the highest dopant concentration, that serves as an interface between the first material layer and the metal contact plug.

[0030] The foregoing broadly outlines the techniques described in this disclosure. It is contemplated that the concepts of the present disclosure can be implemented for a planar transistor device or for a three-dimensional transistor device, such as fin field effect transistors (FinFETs), horizontal gate all around (HGAA) FETs, vertical gate all around (VGAA) FETs, nanowire channel FETs, strained semiconductor devices, or other useful semiconductor device.

[0031] Figure 1 is a schematic top view of a multi-chamber processing system 100, according to one or more embodiments of the present disclosure. The processing system 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chambers 108, 110 with respective transfer robots 112, 114, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, and 130. AsPATENTAttorney Docket No.: 44025279WO01detailed herein, in some embodiments, substrates in the processing system 100 are processed in and transferred between the various chambers without exposing the substrates to an ambient environment exterior to the processing system 100 (e.g., an atmospheric ambient environment such as may be present in a fab). For example, the substrates can be processed in and transferred between the various chambers maintained at a low pressure (e.g., less than or equal to about 300 Torr) or vacuum environment without breaking the low pressure or vacuum environment among various processes performed on the substrates in the processing system 100. Accordingly, in some embodiments, the processing system 100 may provide for an integrated solution for some processing of substrates. However, in some embodiments, an ex-situ processing method may be used. The ex-situ processing method will include the performance of a plurality of process steps within a first multi-chamber processing system and a different plurality of process steps being performed within a second multi-chamber processing system. The ex-situ processing method will include a vacuum break step that is needed to transfer the substrates between the first and the second processing systems.

[0032] Examples of a processing system that may be suitably modified in accordance with the teachings provided herein include the Endura®, Producer® or Centura® integrated processing systems or other suitable processing systems commercially available from Applied Materials, Inc., located in Santa Clara, California. It is contemplated that other processing systems (including those from other manufacturers) may be adapted to benefit from aspects described herein.

[0033] In the illustrated example of Figure 1, the factory interface 102 includes a docking station 132 and factory interface robots 134 to facilitate transfer of substrates. The docking station 132 is adapted to accept one or more front opening unified pods (FOUPs) 136. In some examples, each factory interface robot 134 generally includes a blade 138 disposed on one end of the respective factory interface robot 134 adapted to transfer the substrates from the factory interface 102 to the load lock chambers 104, 106.

[0034] The load lock chambers 104, 106 have respective ports 140, and 142 coupled to the factory interface 102 and respective ports 144, and 146 coupled to thePATENTAttorney Docket No.: 44025279WO01transfer chamber 108. The transfer chamber 108 further has respective ports 148, and 150 coupled to the holding chambers 116, and 118 and respective ports 152, 154 coupled to processing chambers 120, and 122. Similarly, the transfer chamber 110 has respective ports 156, and 158 coupled to the holding chambers 116, 118 and respective ports 160, 162, and 164, and 166 coupled to processing chambers 124, 126, 128, and 130. The ports 144, 146, 148, 150, 152, 154, 156, 158, 160, 162, 164, and 166 can be, for example, slit valve openings with slit valves for passing substrates therethrough by the transfer robots 112, 114 and for providing a seal between respective chambers to prevent a gas from passing between the respective chambers. Generally, any port is open for transferring a substrate therethrough. Otherwise, the port is closed.

[0035] The load lock chambers 104, 106, transfer chambers 108, 110, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, and 130 may be fluidly coupled to a gas and pressure control system (not specifically illustrated). The gas and pressure control system can include one or more gas pumps (e.g., turbo pumps, cryo-pumps, roughing pumps), gas sources, various valves, and conduits fluidly coupled to the various chambers. In operation, a factory interface robot 134 transfers a substrate from a FOUR 136 through a port 140 or 142 to a load lock chamber 104 or 106. The gas and pressure control system then pumps down the load lock chamber 104 or 106. The gas and pressure control system further maintains the transfer chambers 108, 110 and holding chambers 116, 118 with an interior low pressure or vacuum environment (which may include an inert gas). Hence, the pumping down of the load lock chamber 104 or 106 facilitates passing the substrate between, for example, the atmospheric environment of the factory interface 102 and the low pressure or vacuum environment of the transfer chamber 108.

[0036] With the substrate in the load lock chamber 104 or 106 that has been pumped down, the transfer robot 112 transfers the substrate from the load lock chamber 104 or 106 into the transfer chamber 108 through the port 144 or 146. The transfer robot 112 is then capable of transferring the substrate to and / or between any of the processing chambers 120, 122 through the respective ports 152, 154 for processing and the holding chambers 116, 118 through the respective ports 148, 150PATENTAttorney Docket No.: 44025279WO01for holding to await further transfer. Similarly, the transfer robot 114 is capable of accessing the substrate in the holding chamber 116 or 118 through the port 156 or 158 and is capable of transferring the substrate to and / or between any of the processing chambers 124, 126, 128, 130 through the respective ports 160, 162, 164, 166 for processing and the holding chambers 116, 118 through the respective ports 156, 158 for holding to await further transfer. The transfer and holding of the substrate within and among the various chambers can be in the low pressure or vacuum environment provided by the gas and pressure control system.

[0037] The processing chambers 120, 122, 124, 126, 128, and 130 can be any appropriate chamber for processing a substrate. In some examples, the processing chamber 120 can be capable of performing an etch process, the processing chamber 122 can be capable of performing a cleaning process, the processing chamber 124 can be capable of performing a selective removal process, and the processing chambers 126, 128, 130 can be capable of performing respective epitaxial growth processes. The processing chamber 120 may be a Sym3® or Selectra™ Etch chamber available from Applied Materials of Santa Clara, California. The processing chamber 122 may be a ClarionTM or SiCoNi™ Pre-clean chamber available from Applied Materials of Santa Clara, Calif. The processing chamber 126, 128, or 130 may be a Centura™ Epi chamber available from Applied Materials of Santa Clara, California.

[0038] A system controller 168 is coupled to the processing system 100 for controlling the processing system 100 or components thereof. For example, the system controller 168 may control the operation of the processing system 100 using a direct control of the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, and 130 of the processing system 100 or by controlling controllers associated with the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, and 130. In operation, the system controller 168 enables data collection and feedback from the respective chambers to coordinate performance of the processing system 100.

[0039] The system controller 168 generally includes a central processing unit (CPU) 170, memory 172, and support circuits 174. The CPU 170 may be one of any form of a general purpose processor that can be used in an industrial setting. ThePATENTAttorney Docket No.: 44025279WO01memory 172, or non-transitory computer-readable medium, is accessible by the CPU 170 and may be one or more of memory such as random access memory (RAM), read only memory (ROM), floppy disk, hard disk, or any other form of digital storage, local or remote. The support circuits 174 are coupled to the CPU 170 and may comprise cache, clock circuits, input / output subsystems, power supplies, and the like. The various methods disclosed herein may generally be implemented under the control of the CPU 170 by the CPU 170 executing computer instruction code stored in the memory 172 (or in memory of a particular processing chamber) as, for example, a software routine. When the computer instruction code is executed by the CPU 170, the CPU 170 controls the chambers to perform processes in accordance with the various methods disclosed herein.

[0040] Other processing systems can be in other configurations. For example, more or fewer processing chambers may be coupled to a transfer apparatus. In the illustrated example, the transfer apparatus includes the transfer chambers 108, 110 and the holding chambers 116, 118. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as a transfer apparatus in a processing system.

[0041] Figure 2A is a cross sectional view of a processing chamber 200, according to one or more embodiments, that is adapted to perform a pre-clean process and / or a plasma enhanced etching or deposition process as detailed below. The processing chamber 200 may be the processing chamber 122 shown in Figure 1. Figure 2B is an enlarged view of a portion of the processing chamber 200 of Figure 2A.

[0042] The processing chamber 200 may be particularly useful for performing a thermal or plasma-based cleaning process and / or a plasma assisted dry etch process. The processing chamber 200 includes a chamber body 202, a lid assembly 204, and a support assembly 206. The lid assembly 204 is disposed at an upper end of the chamber body 202, and the support assembly 206 is at least partially disposed within the chamber body 202. A vacuum system can be used to remove gases from processing chamber 200. The vacuum system includes a vacuum pump 208 coupled to a vacuum port 210 disposed in the chamber body 202. The processing chamberPATENTAttorney Docket No.: 44025279WO01200 also includes a controller 212 for controlling processes within the processing chamber 200.

[0043] The lid assembly 204 includes stacked components adapted to provide precursor gases and / or a plasma to a processing region 214 within the processing chamber 200. A first plate 216 is coupled to a second plate 218. A third plate 220 is coupled to the second plate 218. The lid assembly 204 may be connected to a power source (not shown) for supplying a plasma to a cone-shaped chamber 222 formed in the lid assembly 204. The lid assembly 204 can also be connected to a remote plasma source 224 that creates the plasma upstream of the lid stack. The remote plasma cavity (e.g., the processing region 214, the first plate 216, and the second plate 218 in Figures 2A-2B) is coupled to a gas source 226 via the remote plasma source 224 (or the gas source 226 is coupled directly to the lid assembly 204 in the absence of the remote plasma source 224). The gas source 226 may include a gas source that is adapted to provide helium (He), argon (Ar), or other inert gas. In some configurations, the gas provided by the gas source 226 can be energized into a plasma that is provided to the lid assembly 204 by use of the remote plasma source 224. In alternate embodiments, the gas source 226 may provide process gases that can be activated by the remote plasma source 224 prior to being introduced to a surface of the substrate that is disposed within the processing chamber 200. Referring to Figure 2B, the cone-shaped chamber 222 has an opening 228 that allows a formed plasma to flow from the remote plasma source 224 to a volume 230 formed in a fourth plate 232 of the lid assembly 204.

[0044] In some configurations of the lid assembly 204, a plasma is generated within the cone-shaped chamber 222 by the application of energy delivered from a plasma source. In one example, the energy can be provided by biasing the lid assembly 204 to capacitively couple RF, VHF and / or UHF energy to the gases positioned in the cone-shaped chamber 222. In this configuration of the lid assembly 204, the remote plasma source 224 may not be used, or not be installed within the lid assembly 204.

[0045] A central conduit 234, which is formed in the fourth plate 232, is adapted to provide the plasma generated species provided from the volume 230 through a fifth plate 236 to a mixing chamber 238 formed in a sixth plate 240 of the lid assembly 204.PATENTAttorney Docket No.: 44025279WO01The central conduit 234 communicates with the mixing chamber 238 through an opening 242 in the fifth plate 236. The opening 242 may have a diameter less than, greater than or the same as a diameter of the central conduit 234. In the embodiment of Figure 2B, the opening 242 has diameter the same as the central conduit 234.

[0046] The fourth plate 232 also includes inlets 244 and 246 that are adapted to provide gases to the mixing chamber 238. The inlet 244 is coupled to a first gas source 248 and the inlet 246 is coupled to a second gas source 250. The first gas source 248 and the second gas source 250 may include processing gases as well as inert gases, for example inert gases such as argon and / or helium, utilized as a carrier gas. The first gas source 248 may include ammonia (NH3) as well as argon (Ar). The second gas source 250 may contain fluorine containing gases, hydrogen containing gases, or a combination thereof. In one example, the second gas source 250 may contain hydrogen fluoride (HF) as well as argon (Ar).

[0047] As illustrated in Figure 2B, in some configurations, the inlet 244 is coupled to the mixing chamber 238 through a cylindrical channel 252 (shown in phantom) and holes 254 formed in the fifth plate 236. The inlet 246 is coupled to the mixing chamber 238 through a cylindrical channel 256 (shown in phantom) and holes 258 formed in the fifth plate 236. The holes 254, 258 formed in the fifth plate 236 are generally sized so that they enable a uniform flow of gases, which are provided from their respective gas source 248, 250, into the mixing chamber 238. In one configuration, the holes 258 have a diameter that is less than a width of the opening defined by the opposing sidewalls of the cylindrical channel 256 formed in the fourth plate 232. The holes 258 are typically distributed around the circumference of the center-line of the cylindrical channel 256 to provide uniform fluid flow into the mixing chamber 238. In one configuration, the holes 254 have a diameter that is less than a width of the opening defined by the opposing sidewalls of the cylindrical channel 252 formed the fourth plate 232. The holes 254 are typically distributed around the circumference of the center-line of the cylindrical channel 252 to provide uniform fluid flow into the mixing chamber 238.

[0048] The inlets 244 and 246 provide respective fluid flow paths laterally through the fourth plate 232, turning toward and penetrating through the fifth plate 236 to thePATENTAttorney Docket No.: 44025279WO01mixing chamber 238. The lid assembly 204 also includes a seventh plate or first gas distributor 260, which may be a gas distribution plate, such as a showerhead, where the various gases mixed in the lid assembly 204 are flowed through perforations 262 formed therein. The perforations 262 are in fluid communication with the mixing chamber 238 to provide flow pathways from the mixing chamber 238 through the first gas distributor 260. Referring back to Figure 2A, a blocker plate 264 and a gas distribution plate, such as a second gas distribution plate 266, which may be a gas distribution plate, such as a showerhead, is disposed below the lid assembly 204.

[0049] Alternatively, a different cleaning process may be utilized to clean the substrate surface. For example, a remote plasma containing helium (He) and ammonia (NH3) may be introduced into the processing chamber 200 through the lid assembly 204, while ammonia (NH3) may be directly injected into the processing chamber 200 via a separate gas inlet 268 that is disposed at a side of the chamber body 202 and coupled to a gas source (not shown).

[0050] The support assembly 206 may include a substrate support 270 to support a substrate 272 thereon during processing. The substrate support 270 may be coupled to an actuator 274 by a shaft 276 which extends through a centrally-located opening formed in a bottom of the chamber body 202. The actuator 274 may be flexibly sealed to the chamber body 202 by bellows (not shown) that prevent vacuum leakage around the shaft 276. The actuator 274 allows the substrate support 270 to be moved vertically within the chamber body 202 between a processing position and a loading position. The loading position is slightly below the opening of a tunnel (not shown) formed in a sidewall of the chamber body 202.

[0051] The substrate support 270 has a flat, or a substantially flat, substrate supporting surface for supporting a substrate 272 to be processed thereon. The substrate support 270 may be moved vertically within the chamber body 202 by the actuator 274, which is coupled to the substrate support 270 by the shaft 276. For some process operations, the substrate support 270 may be elevated to a position in close proximity to the lid assembly 204 to control the temperature of the substrate 272 being processed. As such, the substrate 272 may be heated via radiation emitted from the second gas distribution plate 266, or another radiant source, or by convectionPATENTAttorney Docket No.: 44025279WO01or conduction from the second gas distribution plate 266 through an intervening gas. In some process steps, the substrate may be disposed on lift pins 278 to perform additional thermal processing operations, such as performing an annealing step.

[0052] Figure 3 is a schematic cross-sectional view of a processing system 30 that is configured to perform one or more of the plasma processing methods set forth herein. In some embodiments, the processing system 30 is configured for plasma-assisted etching processes, such as a reactive ion etch (RIE) plasma processing. However, it should be noted that the embodiments described herein may also be used with processing systems configured for use in other plasma-assisted processes, such as plasma-enhanced deposition processes, for example, plasma-enhanced chemical vapor deposition (PECVD) processes, plasma-enhanced atomic layer deposition (PEALD) processes, plasma treatment processing or plasma-based ion implant processing, for example, plasma doping (PLAD) processing.

[0053] The processing system 30 generally includes a processing chamber 300, a lid assembly 376, a support assembly 336, and a system controller 326. As shown, the processing system 30 includes a plurality of plasma source assemblies that are each adapted to deliver a radio frequency (RF), direct current (DC) or pulsed voltage waveforms to one or more electrodes and / or one or more coils disposed within the processing chamber 300. In one configuration example, as shown in Figure 3, the processing chamber 300 includes four plasma source assemblies, such as a first capacitively coupled plasma (CCP) assembly 394, a second capacitively coupled plasma (CCP) assembly 395, a first inductively coupled plasma (ICP) assembly 396, and a second inductively coupled plasma (ICP) assembly 397. In some embodiments, the processing chamber 300 includes an additional optional source assembly 391 that is configured to deliver an RF signal to an electrode within the processing chamber 300 to generate and / or sustain a plasma 301 within a processing volume 329 of the processing chamber 300.

[0054] The processing chamber 300 typically includes a chamber body 313 that includes one or more sidewalls 322 and a chamber base 324, which collectively, with a chamber lid 323 of the lid assembly 376, define the processing volume 329. The one or more sidewalls 322 and chamber base 324 generally include materials that arePATENTAttorney Docket No.: 44025279WO01sized and shaped to form the structural support for the elements of the processing chamber 300 and are configured to withstand the pressures and added energy applied to them while the plasma 301 is generated within a vacuum environment maintained in the processing volume 329 of the processing chamber 300 during processing. In one example, the one or more sidewalls 322 and chamber base 324 are formed from a metal, such as aluminum, an aluminum alloy, or a stainless steel alloy. A gas inlet 328 disposed through the chamber lid 323 is used to deliver one or more processing gases to the processing volume 329 from a processing gas source 319 that is in fluid communication therewith. The processing chamber 300 includes a vacuum pump 320. A substrate 303 is loaded into, and removed from, the processing volume 329 through an opening (not shown) in one of the one or more sidewalls 322, which is sealed with a slit valve (not shown) during plasma processing of the substrate 303. The gas source 319 is configured to provide one or more of the processing gases to the processing volume 329 of the processing chamber 300. The gas source 319 is configured to provide one or more gases utilized in the methods described herein, such as a halogen containing gas (e.g., CI2, Br2, F2, I2, HBr, HCI, CH3F, C4F8, CHF3, etc.), a hydrogen containing gas (e.g., H2), an oxygen containing gas (e.g., O2), and one or more inert gases (e.g., He, Ar, Ne, Kr, etc.).

[0055] The system controller 326, also referred to herein as a processing chamber controller, includes a central processing unit (CPU) 333, a memory 334, and support circuits 335. The system controller 326 can also form part of the system controller 168 described above. The system controller 326 is used to control the process sequence used to process the substrate 303. The CPU 333 is a general-purpose computer processor configured for use in an industrial setting for controlling the processing chamber and sub-processors related thereto. The memory 334 described herein, which is generally non-volatile memory, may include random access memory, readonly memory, floppy or hard disk drive, or other suitable forms of digital storage, local or remote. The support circuits 335 are conventionally coupled to the CPU 333 and comprise cache, clock circuits, input / output subsystems, power supplies, and the like, and combinations thereof. Software instructions (program) and data can be coded and stored within the memory 334 for instructing a processor within the CPU 333. A software program (or computer instructions) readable by CPU 333 in the systemPATENTAttorney Docket No.: 44025279WO01controller 326 determines which tasks are performable by the components in the processing system 30. Typically, the software program, which is readable by CPU 333 in the system controller 326, includes code, which, when executed by the processor (CPU 333), performs tasks relating to the plasma processing methods described herein. The program may include instructions that are used to control the various hardware and electrical components within the processing system 30 to perform the various process tasks and various process sequences used to implement the methods described herein.

[0056] In some embodiments, the lid assembly 376 includes the chamber lid 323 and the one or more plasma source assemblies, such as two inductively coupled plasma (ICP) assemblies 396, 397 illustrated in Figure 3. As shown in Figure 3, each ICP assembly 396, 397 includes a coil 381, 382, respectively, that is configured to inductively couple a biasing signal generated by a generator 350 to a plasma 301 formed in the processing volume 329 of the processing chamber 300 during plasma processing. In this configuration, the chamber lid 323 includes a dielectric material that is configured to allow the fields generated by the coils 381 , 382 during the delivery of the biasing signal, such as an RF signal provided by the generator 350 and through an RF match 351 to help generate and sustain the plasma 301 in the processing volume 329. The provided RF signal can include the delivery of an RF waveform at a frequency between 100 kHz and 120 MHz, such as frequency between 2 MHz and 60 MHz, at a RF power level between 100 Watts and about 1000 Watts.

[0057] However, in some alternate embodiments of the chamber 300, the lid assembly 376 includes the chamber lid 323 that includes one or more of the capacitively coupled plasma (CCP) assemblies, such as an RF driven showerhead assembly that is disposed over a surface of a substrate during plasma processing.

[0058] The substrate support assembly 336, as shown in Figure 3, includes a substrate support 305 (e.g., ESC substrate support) and one or more lower electrodes, which are coupled to a biasing source assembly, such as the source assemblies 394, 395. In some embodiments, the substrate support assembly 336 can additionally include a support base 307, an insulator plate 311, a ground plate 312 and substrate lift assembly 332. The support base 307 is electrically isolated from the chamber basePATENTAttorney Docket No.: 44025279WO01324 by the insulator plate 311, and the ground plate 312 is interposed between the insulator plate 311 and the chamber base 324. The substrate support 305 is thermally coupled to and disposed on the support base 307. In some embodiments, the support base 307 is configured to regulate the temperature of the substrate support 305, and the substrate 303 disposed on the substrate support 305, during substrate processing. Typically, the substrate support 305 is formed of a dielectric material, such as a bulk sintered ceramic material, such as a corrosion-resistant metal oxide or metal nitride material, for example, aluminum oxide (AI2O3), aluminum nitride (AIN), titanium oxide (TiO), titanium nitride (TiN), yttrium oxide (Y2O3), mixtures thereof, or combinations thereof. In embodiments herein, the substrate support 305 further includes the bias electrode 304 embedded in the dielectric material thereof.

[0059] The one or more lower electrodes can include a bias electrode 304 and / or an edge electrode 315 that are formed within the substrate support 305, and are coupled to one or more source assemblies, such as the two source assemblies 394, 395. The source assembly 394 is coupled to the bias electrode 304 and the source assembly 395 is coupled to the edge electrode 315, and are each configured to deliver a waveform generated by a source generator 350 to a plasma 301 formed in the processing volume 329 of the processing chamber 300 during plasma processing. In some embodiments, the source assemblies 394, 395 include an RF power source, a DC power source, or a pulsed DC power source that are configured to deliver a biasing signal, such as an RF signal, constant DC signal, or asymmetric pulsed voltage waveform provided by the generator 350 to help bias the substrate and / or generate and sustain the plasma 301 in the processing volume 329. In some embodiments, the biasing signal comprises an RF signal that is provided at a frequency between 100 kHz and 120 MHz, such as frequency between 2 MHz and 60 MHz, at an RF power level between zero and about 1000 Watts, such as between about 5 Watts and 500 Watts. In some other embodiments, the biasing signal comprises an asymmetric pulsed DC signal that is provided at a frequency between 100 kHz and 500 kHz, an on-time duty cycle of between 10% and 95%, at an applied voltage level between about +100 Volts and -8000 volts, such as between about +10 Volts and -5000 volts. In some other embodiments, the biasing signal comprises a constant DC signal that is provided at an applied voltage level between about +5000 Volts and -8000 volts.PATENTAttorney Docket No.: 44025279WO01

[0060] In one configuration, the bias electrode 304 is a chucking pole used to secure (i.e. , chuck) the substrate 303 to the substrate supporting surface 305A of the substrate support 305 and to bias the substrate 303 with respect to the processing plasma 301 using one or more of the biasing schemes described herein. Typically, the bias electrode 304 is formed of one or more electrically conductive parts, such as one or more metal meshes, foils, plates, or combinations thereof.

[0061] The source assemblies 394, 395 may also each include a clamping network 316 so that a high voltage bias applied to the bias electrode 304 and / or edge control electrode 315. In some embodiments, the bias electrode 304 is electrically coupled to a clamping network 316 and the edge electrode 315 is electrically coupled to a clamping network 316. The clamping networks provide a chucking voltage thereto, such as static DC voltage between about -5000 V and about +5000 V, using an electrical conductor, such as the coaxial power delivery line 306 (e.g., a coaxial cable). The clamping network 316 includes bias compensation circuit elements 316A, a DC power supply 355, and a bias compensation module blocking capacitor, which is also referred to herein as the blocking capacitor C5. The blocking capacitor C5 is disposed between the output of a generator 350 and the bias electrode 304. Applying similarly configured bias waveforms and clamping voltages to the bias electrode 304 and edge control electrode 315 can help improve the plasma uniformity across the surface of the substrate during processing and thus improve the plasma processing process results.

[0062] As discussed above, in some embodiments, the substrate support assembly 336 includes the edge control electrode 315 that is positioned below the edge ring 314 and surrounds the bias electrode 304 and / or is disposed a distance from a center of the bias electrode 304. In general, for a processing chamber 300 that is configured to process circular substrates, the edge control electrode 315 is annular in shape, is made from a conductive material, and is configured to surround at least a portion of the bias electrode 304. In some embodiments, such as shown in Figure 3, the edge control electrode 315 is positioned within a region of the substrate support 305. In some embodiments, as illustrated in Figure 3, the edge control electrode 315 includes a conductive mesh, foil, and / or plate that is disposed a similar distance (i.e., Z-PATENTAttorney Docket No.: 44025279WO01direction) from the substrate supporting surface 305A of the substrate support 305 as the bias electrode 304. In some other embodiments, the edge control electrode 315 includes a conductive mesh, foil, and / or plate that is positioned on or within a region of a quartz pipe 310, which surrounds at least a portion of the bias electrode 304 and / or the substrate support 305. Alternately, in some other embodiments (not shown), the edge control electrode 315 is positioned within or is coupled to the edge ring 314, which is disposed on and adjacent to the substrate support 305. In this configuration, the edge ring 314 is formed from a semiconductor or dielectric material (e.g., AIN, etc.).

[0063] In some embodiments, the processing chamber 300 includes a source assembly 391 that is configured to deliver an RF signal to an electrode, such as the support base 307, within the processing chamber 300 via a conductive line 367 to generate and / or sustain, such as the support base 307 the plasma 301 in the processing volume 329. In some embodiments, the source assembly 391 includes an RF generator 318 that is configured to deliver an RF waveform signal having a frequency that is greater than 1 MHz or more, or about 2 MHz or more, such as about 13.56 MHz or more through an RF match 360 that is connected to the electrode, which is used to RF bias a substrate during processing.First Contact Structure Formation Process Example

[0064] Figure 5 provides a method 500 of forming an electrical contact within a semiconductor device, such as a nanosheet stack type of device (e.g., horizontal gate-all-around (hGAA) transistor device, a backside power delivery network (BSPDN) device and / or a backside power rail (BPR) device). An example of nanosheet structures 420A in Figure 4A and 420B in Figure 4B include the GAA devices 422A and 422B, respectively, depicted in view 400 of Figure 4. The GAA devices 422A and 422B of Figures 4A and 4B are provided herein as examples for use in the processing sequence scenarios described herein. As illustrated in Figures 4A and 4B, the nanosheet structures 420A and 420B include an n-type metal-oxide-sem iconductor field-effect-transistor (nMOS FET) that includes an nMOS GAA device 422A and a p-type MOST FET (pMOS FET) that includes a pMOS GAA device 422B. In this example, if the MOS FET is an nMOS FET, then the source and drain include n+PATENTAttorney Docket No.: 44025279WO01doped regions and the body includes a p-doped region. If the MOS FET is a pMOS FET, then the source and drain are p+ doped regions and the body is an n-doped region.

[0065] The nanosheet structures 420A, 420B are formed on substrate 402. The term “substrate” as used herein refers to a layer of material that serves as a basis for subsequent processing operations and includes a surface to be cleaned. The substrate may be a silicon based material, or any suitable insulating materials or conductive materials as needed. The substrate may include a material such as crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or non-patterned wafers, silicon on insulator (SOI), carbon doped silicon oxides, silicon nitride, doped silicon germanium, gallium arsenide, glass, or sapphire.

[0066] The nMOS GAA devices 422A and pMOS GAA devices 422B each have a gate 404A, 404B surrounding the nanosheet structure 420A, 420B with a gate cap 406A, 406B and source / drain regions 408A, 408B on each side of the nanosheet structure 420, all of which are formed within source / drain contact trenches 434 formed on the substrate 402. For simplicity of discussion purposes, the phrase “source / drain” or “source / drain region” are used herein to describe a region of a semiconductor device formed on a substrate that includes a source region or a drain region, or both a source region and a drain region. The pMOS FET of the nanosheet structure 420B, in the example described herein, has a first nanosheet 410B, a second nanosheet 412B, and a third nanosheet 414B which may be formed, in some embodiments, of a silicon (Si) material, which in some cases can be doped with an element such as Boron (B) or germanium (Ge). The nMOS FET of the nanosheet structure 420A, has a first nanosheet 410A, a second nanosheet 412A, and a third nanosheet 414A which may be formed, in some embodiments, of a silicon (Si) material, which in some cases can be doped with an element such as phosphorous (P). The number of nanosheets in a stack can be more or less than the examples shown in Figures 4A and 4B. In some embodiments, the nanosheets may have a thickness 430 of approximately 5 nm to approximately 10 nm, such as from about 6 nm to 9 nm. The nanosheets, in thisPATENTAttorney Docket No.: 44025279WO01example, may be further separated by inner spacers 405 composed of a dielectric material, such as silicon dioxide (SiC ) or other useful material.

[0067] The source / drain regions 408A of the nMOS FET, in this example, are formed of epitaxially grown silicon (Si) material, which in some cases can be doped with an element such as phosphorus (P). The source / drain regions 408B of the pMOS FET, in this example, are formed of an epitaxially grown silicon germanium (SixGei-x) material, where X may be from approximately 0.5 to approximately 0.95, such as between 0.5 and 0.9. In addition, in this example, as will be discussed in detail below, the source / drain region of the pMOS FET may be further doped with p-type dopants such as boron (B), with the concentration of between about 1O20cm-3and about 5 x 1021cm-3.

[0068] During block 502 of method 500 the partially formed GAA device 422B as depicted in view 400 of Figure 4B is placed in a process chamber for the beginning of the formation of the metal contact plug process sequence. During block 502 and / or 504, in some examples, a pre-clean process can be performed in a processing chamber 122 shown in Figure 1, or the processing chambers 200 or 300 shown in Figures 2A-2B and 3. The pre-clean process during blocks 502 and 504 may be performed without breaking vacuum in a multi-chamber processing system, such as the multi-chamber processing system 100 shown in Figure 1.

[0069] The pre-clean process is configured to remove contaminants, such as carbon-containing contaminants (e.g., patterning residues), or oxide-containing contaminants (e.g., native oxide layers) formed on the exposed surface of the nanosheet structure 420B, which includes the exposed surfaces of the source / drain regions 408B of the pMOS FET regions. The pre-clean process may include an anisotropic remote plasma assisted dry etch process, such as a reactive ion etching (RIE) process, using a plasma formed from a gas including hydrogen (H), argon (Ar), helium (He), or a combination thereof. The pre-clean process may alternately or additionally include an isotropic plasma etch process, such as a dry chemical etch process, using anhydrous hydrofluoric acid (HF) and ammonia (NH3), or a SiCoNi™ dry etch process, using a plasma formed from a gas including ammonia (NH3), or nitrogen trifluoride (NF3). The dry etch process is selective for oxide layers, and thusPATENTAttorney Docket No.: 44025279WO01does not readily etch silicon, germanium, or nitride layers regardless of whether the layers are amorphous, crystalline or polycrystalline. Selectivity of the dry etch process for oxide versus silicon or germanium is at least about 3:1, and usually 5:1 or better, sometimes 10:1.

[0070] During block 506 a first epitaxial semiconductor layer L1 (hereafter L1 layer) is formed in the source / drain contact trenches 434 by an epitaxial deposition process on the exposed surfaces of the source / drain contact trenches 434 formed on the substrate 402. In one or more embodiments, the L1 layer is also referred to herein as an epitaxial base layer and comprises a first doping concentration of boron doped silicon germanium (SixGei-x):B with a Ge concentration from approximately 5% to approximately 15%, such as about 10% and a B doping concentration from approximately 5 x 1019cm-3to approximately 1 x 102° cm-3. The selective epitaxial growth process may be performed at a temperature of between about 600°C and about 750°C.

[0071] During block 508, a first cavity within the formed L1 layer is filled, as shown in Figure 7A, with a second epitaxial semiconductor layer L2 (or hereafter L2 layer) formed by a selective epitaxial growth process. The L2 layer is deposited on the formed L1 layer and is fabricated from the same material as the L1 layer, with the exception that the dopant concentration within the L2 layer is substantially higher than that of the material in the L1 layer. In one or more embodiments, the L2 layer comprises a second doping concentration of boron doped silicon germanium (SixGei-x):B with a Ge concentration from approximately 45% to approximately 55%, such as about 50% and a B doping concentration from approximately 1 x 102° cm-3to approximately 5 x 102° cm-3, such as 3 x 102° cm-3. The selective epitaxial growth process may be performed at a temperature of between about 600°C and about 750°C. The L2 layer is configured to fill the trench 434 without forming a void therein, and is used to generate strain within the L1 layer and cover the exposed surfaces of the L1 layer without defects. The L2 layer in this example, may have a thickness between about 20 nm and about 40 nm, such as between about 25 nm and about 35 nm.PATENTAttorney Docket No.: 44025279WO01

[0072] A cross-sectional view created by the sectioning line 415 of the pMOS GAA device 422B, which is shown in 7A, is depicted in Figure 7B showing the L1 layer and the L2 layer that are characterized by a diamond shape structure. In this example, at block 508, the diamond shape L2 layer blocks the view of the ends of the nanosheets 41 OB, 412B, and 414B that have regions separated by inner spacers 405, which are composed of a dielectric material. As shown in Figure 7B, the source / drain region L1 has been selectively grown on the exposed regions of the substrate 402, which are separated by the inner spacer 405 material, and the L2 layer is selectively grown on the L1 layer material to form the epitaxially grown diamond shaped regions of the L2 layer.

[0073] During block 555, a cavity shaping process is performed on the exposed portion of the L2 layer to form a first cavity 831 shown in Figures 8A and 10A within the contact trenches 434. The cavity shaping process may be performed in an etch chamber, such as the processing chamber 120 shown in Figure 1, or a processing chamber 200, 300 illustrated in Figures 2A and 3. The cavity shaping process in method 500 may be performed without breaking vacuum in a multi-chamber processing system, such as the multi-chamber processing system 100 shown in Figure 1. It is further contemplated in this disclosure, that in some embodiments, it may be desirable to perform an ex-situ processing method in which the cavity shaping process of block 555 is performed in a first processing system and the processes that follow are performed in a second processing system. In this case, after performing the cavity shaping process 555 in the first processing system, the substrate is transferred to a second processing system for the post processing of the substrate culminating with block 520.

[0074] The cavity shaping process 555 is used to refresh and prepare pure contamination free exposed surfaces of the MOS FET cavities on which a contact (e.g., metal silicide) can be formed within the desired MOS FET region in subsequent deposition processes. The cavity shaping process 555 is also used to optimize a device stress and increase contact area to reduce contact resistance of the electrical contact, thus leading to improved device performance.PATENTAttorney Docket No.: 44025279WO01

[0075] In one or more embodiments, operations in block 510 within the cavity shaping process 555 may be performed subsequently to those operations of block 508. Alternatively, operations in block 512 may be performed after performing block 508 (i.e. only block 510 is performed during block 555) while in one or more embodiments, operations in block 512 may be performed after performing block 508 (i.e., only block 512 is performed during block 555), or in some other embodiments both blocks 510 and 512 are performed within the cavity shaping process 555 leading to block 514 of the method 500.

[0076] As shown in Figures 8A and 10A, the cavity shaping process may remove at least a portion of the formed L2 layer to form a second cavity 831 within the contact trench 434. The cavity shaping process at block 510 includes an anisotropic cavity etch process to form a second cavity 831 within the L2 layer. The anisotropic cavity etch process will include a plasma etching process that can be performed in one of the processing chambers 200 or 300 illustrated in Figures 2A and 3, respectively. During the plasma etching process, an etching process gas is introduced into the chamber . The etching process gas may comprise one or more etchants. The etchants may be excited by a radio frequency (RF) signal. The etchant includes a halogencontaining gas, optionally a hydrogen-containing (H2) gas, and optionally an inert gas. In one or more embodiments, the halogen-containing gas is chlorine gas, and the hydrogen containing gas is a hydrogen (H2) containing gas, and the optional inert gas is argon, helium, or both. Exemplary chlorine-containing gases include diatomic chlorine (CI2) gas. The inert gas may include at least one of argon, helium, neon, xenon, and the like. The anisotropic cavity etch process will further include the application of a bias to a substrate support to promote bombardment of the surface of the substrate by ions formed in the generated plasma.

[0077] After the completion of block 510, as shown in Figure 8A, the second cavity 831 formed within the L2 layer will include a generally U-shaped or V-shaped angled sidewall. Due to the anisotropic nature of the process, the portion of the second contact cavity 831 in block 510 is predominantly formed in a vertical direction to a desired depth within the directly exposed upper surface of the L2 layer, and in some processes not exposing the laterally adjacent surfaces of the adjacent material regions (e.g.,PATENTAttorney Docket No.: 44025279WO01nanosheets 410B, 412B, and 414B). In configurations similar to the example shown in Figure 8A, the second cavity 831 can have a depth of between about 2 nm and about 30 nm, such as 5 nm and about 15 nm with a maximum width of the U-shaped or V-shaped cavity of between about 5 nm and about 30 nm, such as about 10 nm and about 15 nm. In this example, a gap 812 formed between the phantom diamond shape border 810 and the surface of L2 layer depicts an amount of material that is etched from the L2 layer during block 510. That is, the gap 812 shown in the cross-sectional view 415 (Figure 8B) schematically illustrates the anisotropic removal of material from the upper surfaces of the L2 layer.

[0078] A cross-sectional view 415 of the pMOS GAA device shown in 8A after the completion of block 510 is depicted in Figure 8B showing the L1 layer, and the diamond shape L2 layer disposed on the L1 layer. In this example, the cross-sectional view of the diamond shape L2 layer fully blocks the cross-sectional view of nanosheets 412B, and 414B and may have regions separated by inner spacers 405 composed of a dielectric material.

[0079] In one or more embodiments, block 512 within the cavity shaping process 555, can be directly performed after the completion of block 508 in order to form a second cavity within the L2 layer by an isotropic cavity etch process. In one or more embodiments, the isotropic etching process includes a plasma etching process that can be performed in the processing chamber 200 or 300 illustrated in Figures 2A and 3, respectively.

[0080] The plasma etching process can be a dry chemical etching process that can be performed in the same chamber as block 510. The plasma etching process can be a dry chemical etching process that includes the use of a capacitively-coupled-plasma (CCP) or an inductively-coupled-plasma (ICP) source assembly that is configured to provide a radio frequency (RF) signal to a source electrode within the processing chamber to generate or sustain the plasma within the processing volume of the processing chamber. In one or more embodiments, the etching process gas includes the use of a gas mixture that includes a chlorine containing gas, such as diatomic chlorine (CI2) gas, and a hydrogen (H2) gas mixture. However, in other embodiments, an alternate second process gas mixture is provided during block 512 and can includePATENTAttorney Docket No.: 44025279WO01a mixture of gases such as HBr / H2, HCI, or HCI / H2 and can further include one or more inert gases, such as Ar and / or (He) at desired flow rates.

[0081] In one or more embodiments, the magnitude of the RF signal applied to the source electrode during block 512 is greater than the magnitude of the RF signal applied to the source electrode during block 510. In some embodiments, the magnitude of the substrate bias applied to the substrate biasing electrode (e.g., items 271, 304 or 307) during block 512 is less than the magnitude of the substrate bias applied to the substrate biasing electrode during block 510. In some embodiments, a pulsed source power supplied to the source electrode and a pulsed substrate bias supplied to the substrate biasing electrode during block 512 are synchronized to improve the plasma properties during processing.

[0082] At block 512 the isotropic etching process is performed to form a second cavity within the L2 layer. An example of the second cavity 831 formed in this block is shown in Figure 10A, where the exposed surfaces of the L2 layer after the formation of the second cavity 831 formed within the L2 layer disposed within the contact trench 434 are shown to be characterized by a planar or flat surface (Figure 10A) with vertical sidewalls in contrast to the U-shaped and V-shaped second cavities with angled side walls depicted in Figure 8A formed during the anisotropic cavity etch process in block 510.

[0083] A cross-sectional view 415 of the pMOS GAA device shown in Figure 10A after the completion of block 512 is depicted in Figure 10B showing the L1 layer, the L2 layer of a second doping concentration, and the diamond shape L2 layer only partially blocking nanosheet 410B due to the formation of the second cavity within the L2 layer. In this example, the cross-sectional view created by the sectioning line 415 shows the diamond shape L2 layer fully blocking the view of nanosheets 412B, and 414B while partially blocking the view of nanosheet 410B with regions separated by inner spacers 405 composed of a dielectric material. In this example, the gap 1012 between the phantom diamond shape border 1010 and the L2 layer schematically depicts an amount of material that is removed from the L2 layer during the isotropic cavity etch process. That is, the gap 1012 illustrates the selective removal of the L2 layer, which is more uniform across all of the exposed surfaces of the L2 layer versusPATENTAttorney Docket No.: 44025279WO01the anisotropic removal performed during block 510, as shown by comparing Figures 8B and 10B.

[0084] After the completion of one or more of the blocks within the cavity shaping process 555 of method 500, the formation of a third epitaxial semiconductor layer L3 (hereafter L3 layer) shown in Figures 9A and 11A, is achieved by an epitaxial deposition process during block 514. The L3 layer is selectively formed within the second cavity formed by the performance of the cavity shaping process 555 and at least partially fills the second cavity formed within the L2 layer. In one or more embodiments, L3 layer completely fills without void the first cavity within L2 layer as shown in Figures 9A and 11 A. The L3 layer is recessed within the first cavity, as shown in Figures 9A and 11 A, and is positioned on the exposed surfaces of (i.e., “wraps around”) the L2 layer. The cross-sectional view created by sectioning line 415 of the source / drain region shown in Figures 9B and 11 B show a recessed L3 layer that wraps around the diamond shaped L2 layer, and as a result covers the nanosheets 410B, 412B, and 414B.

[0085] The L3 layer is fabricated from the same material as the L1 layer and the L2 layer, with the exception that the dopant concentration of the L3 layer is higher than each of the doping concentrations of the L1 layer and L2 layer. In the methods described herein, for example, the L3 layer comprises a third doping concentration of boron doped silicon germanium (SixGei-x):B that is highly active and typically shows activations in the range from approximately between 5 x 1O20cm-3to approximately 1 x 1021cm’3. The selective epitaxial process for the formation of L3 layer during block 514 is characterized by a slower growth rate than the L2 layer, with a thickness from about approximately 5 nm to 10 nm, such as about 8 nm and in a range of temperatures between about 300°C and about 450°C. In one or more embodiments, the L3 layer may have a thickness comparable to the thickness 430 of nanosheets 410B, 412B, and 414B of approximately 5 nm to approximately 10 nm, such as about 6 nm. In this example, according to the configurations shown in Figures 9A and 11 A, the highly doped L3 layer epitaxially regrown at a lower temperature, increases the active doping of the epitaxial film leading to a decrease in the source / drain region resistance and a decrease in the contact resistance.PATENTAttorney Docket No.: 44025279WO01

[0086] During block 516, a third cavity is formed within the L3 layer. The third cavity may be performed by use of the processes and chemistries described above with respect to the cavity shaping process 555 described above of method 500. Figures 9C and 9D show an example of a third cavity 916 within L3 layer that is filled with a metal silicide layer during block 518. In one or more embodiments, the silicide formation process of block 518 may include the formation of a metal silicide, such as a titanium silicide (TiSix), a cobalt silicide (CoSix), a zirconium silicide (ZrSix), a hafnium silicide (HfSix), a nickel platinum silicide (NiPtSix), or other useful silicide layer that can be formed on the surface of the second cavity 916 (e.g., boron doped silicon germanium (SiGe):B surface). The silicide formation process of block 518 may be performed without breaking vacuum environment in a multi-chamber processing system, such as the multi-chamber processing system 100 shown in Figure 1. However, as noted above, in some configurations where the cavity shaping process 555 of method 500 is performed in another tool (e.g., ex-situ processing), the subsequent processing operations of method 500 can be performed in a multi-chamber processing system, where block 518 is performed prior to continuing on with the subsequent operations.

[0087] In one or more embodiments, the silicide formation process performed in block 518 includes a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like that non-selectively forms on the second cavity 916 within L3. In some embodiments, the deposition process is a thermal-CVD or PECVD deposition process that is performed at a temperature of between about 300°C and about 800°C and at a pressure of between 1 °Torr and 50°Torr and by use of a precursor containing titanium (Ti), cobalt (Co), nickel (Ni), tantalum (Ta), lanthanum (La), yttrium (Y), hafnium (Hf), and / or zirconium (Zr). The silicide formation process 518 may include the formation of a metal silicide, such as a titanium silicide (TiSix), a cobalt silicide (CoSix), a zirconium silicide (ZrSix), a hafnium silicide (HfSix), a nickel platinum silicide (NiPtSix). The silicide formation process of block 518 may be performed without breaking vacuum environment in a multi-chamber processing system, such as the multi-chamber processing system 100 shown in Figure 1. However, as noted above, in some configurations where the cavity shaping process 555 is performed in another tool (e.g., ex-situ processing), the subsequent processingPATENTAttorney Docket No.: 44025279WO01operations of method 500 can be performed in a multi-chamber processing system, where block 518 is performed prior to continuing on with the subsequent operations.

[0088] Within block 520, after the formation of the metal silicide layer, a metal contact plug 924 is formed within the second cavity 916 and on the formed silicide layer that is disposed on the L3 layer as shown in Figures 9C and 9D. In one or more embodiments, the L3 layer, characterized by the highest doping concentration of boron doped silicon germanium (SixGei-x), serves as an interface between the first epitaxial semiconductor layer and the metal contact plug and has an effect of reducing the contact resistance due to its high doping concentration and activation level.

[0089] The formation of the metal contact plug 924 shown in Figures 9C and 9D include the formation of a dielectric layer (not shown) having a trench 434 formed over the pMOS semiconductor device. In one example, the dielectric material can be an interlayer dielectric, and can be fabricated from a dielectric material, such as, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or a combination thereof. Block 520 further includes a metal fill process to form the metal contact plug 924. The metal contact plug 924 may be formed of contact plug metal material, such as tungsten (W), cobalt (Co), ruthenium (Ru), or molybdenum (Mo) and may include a metal that has a desirable work function. The metal fill process in block 520 may include a chemical vapor deposition (CVD) process using a tungsten-containing precursor, such as WFe, or a cobalt-containing precursor, in a processing chamber, such as the processing chamber 126, 128, or 130 shown in Figure 1.

[0090] While Figures 9C and 9D illustrate a metal contact plug structure based on the cavity 931 shown in Figure 9A formed within the second cavity 831 depicted in Figure 8A this configuration merely serves for exemplary purposes, and it is not intended to limit the scope of the disclosure provided herein since one skilled in the art would appreciate that the formation of one or more metal contact plugs can also be completed within the second cavity 831 shown in Figure 10A by following the process sequence of method 500 shown in Figure 5 and described herein.PATENTAttorney Docket No.: 44025279WO01

[0091] After the metal fill process, the semiconductor structure shown in Figures 9C and 9D may be planarized, by use of a chemical mechanical planarization (CMP) process.Second Contact Structure Formation Process Example

[0092] Figure 6 depicts a process flow diagram of an alternative method 600 of forming a metal contact plug in the pMOS GAA device 422B shown in Figure 4B according to an embodiment of the present disclosure. In this contact plug process sequence, the cavity shaping process 555 of method 500 is performed in an alternative sequence from the sequence presented in method 500 depicted in Figure 5. The same reference numerals are used for components that are substantially the same as those of the prior discussed embodiment, and the description of repeated component and processes may be omitted.

[0093] Blocks 602, 604, and 606 are similar to or the same as blocks 502, 504, and 506 explained above and use the pMOS GAA semiconductor device structure 422B, shown in Figure 4B as the starting point, and thus will not be re-recited again here.

[0094] During block 608, a portion of the L1 layer is removed to form an interface 1299 between the L1 layer and the substrate 402 of the semiconductor device shown in Figure 12A. The partial removal of a portion of the L1 layer disposed within the contact trench 434 is accomplished by an anisotropic cavity etch process similar to the process described during block 510, which is performed after the L1 layer was formed to from the cavity 1231. Figure 12B depicts the cross-sectional view 415 of the source / drain region of the semiconductor device shown in Figure 12A where the view of the nanosheets structures 410B, 412B, and 414B is unobstructed in sharp contrast to, for example, the cross-sectional view of Figure 8A depicted in Figure 8B after the completion of block 510.

[0095] Figures 13A and 13B illustrate the L2 layer formed during block 610. The L2 layer formed during block 610 of method 600 is similar to the L2 layer formed in block 508 of method 500 shown in Figure 5. The L2 layer formed during block 610 grows from the exposed regions of the substrate 402 and fills at least portion of the cavity region 1231 that includes portions of the L1 layer. As discussed previously, the L2PATENTAttorney Docket No.: 44025279WO01layer comprises a second doping concentration of boron doped silicon germanium (SixGei-x):B with a Ge concentration from approximately 45% to approximately 55%, such as about 50% and a B doping concentration from approximately 1 x 1O20cm-3to approximately 5 x 102° cm-3, such as 3 x 102° cm-3. The selective epitaxial growth process may be performed at a temperature of between about 600°C and about 750°C. The role of the L2 layer is to fill portions of the trench 434 without void, generate strain within the L1 layer and fill the contact trench 434 and contact the exposed surfaces of the remaining portions of the L1 layer without defects. The L2 layer in this example may have a thickness between about 20 nm and about 40 nm, such as between about 25 nm and about 35 nm. A cross-sectional view 415 of Figure 13A is shown in Figure 13B. In this example, at block 610, the diamond shape L2 layer blocks the view of nanosheets 41 OB, 412B, and 414B and may have regions separated by inner spacers 405 composed of a dielectric material.

[0096] Figure 13C illustrates the one or more first cavities 1231 formed within the L2 layer during block 612 by an isotropic cavity shaping process similar to the one performed in block 512 of method 500 described above. Due to the isotropic etching process performed in block 612, the one or more first cavities 1231 are aligned with and at least one is in contact with the interface 1299 of the substrate 402. In this configuration, one or more first cavities 1231 are formed on the top of the source / drain region, shown as section 1333. Alternatively or additionally, as shown in section 1344, this configuration also allows for the formation of a cavity 1231 on the bottom of the source / drain region that is in contact with interface 1299 of the substrate 402.

[0097] Block 614 of method 600 includes the formation of one or more L3 layers within at least one of the one or more first cavities 1231 formed during block 612 depicted in Figures 14A and 14B. The formation of the L3 layers is achieved by an epitaxial process similar to that of block 514 of method 500. The L3 layers are formed within the one or more first cavities 1231. The one or more first cavities 1231 are aligned with, and at least one is in contact with, the interface 1299 of the formed device structure formed on the front side of the substrate 402. In one or more embodiments, the L3 layers at least partially fill the one or more first cavities 1231. In one or more embodiments, the one or more L3 layers are recessed within the one or more firstPATENTAttorney Docket No.: 44025279WO01cavities, as shown in the cross-sectional view created by the sectioning line 415 of the source / drain region in Figure 14B fully blocking the view of the nanosheets 41 OB, 412B, and 414B.

[0098] The one or more L3 layers are fabricated from the same material as the L1 layer and the L2 layer, with the exception that the dopant concentration of L3 is higher than each of the doping concentrations of the L1 layer and L2 layer. In the methods described herein, the one or more L3 layers comprise a third doping concentration of boron doped silicon germanium (SixGei-x):B that is highly active and typically shows activations in the range from approximately between 5 x 1020cm’3to approximately 1 x 1021cm’3. The selective epitaxial process for the formation of L3 layer during block 614 is similar to the one described in block 514 and is characterized by a slower growth rate than the L2 layer, with a thickness from about approximately 5 nm to 10 nm, such as about 8 nm and in a range of temperatures between about 300°C and about 450°C. In one or more embodiments, the one or more L3 layers may have a thickness comparable to the thickness 430 of nanosheets 41 OB, 412B, and 414B of approximately 5 nm to approximately 10 nm, such as about 6 nm. This configuration provides a highly active L3 layer on the top of the source / drain region and on the bottom 1344 of the source / drain region that is in contact with the substrate 402 at the interface 1299. This configuration not only leads to a decreased frontside contact resistance as previously discussed in Figures 9C and 9D during block 520 of method 500 but also to a decreased contact resistance for backside contact formation, which will be discussed in detail in the forthcoming description of Figures 14C and 14D.

[0099] In one or more embodiments, blocks 616, 618, and 620 of method 600 shown in Figure 6 are similar to the processes and chemistries described above with respect to blocks 516, 518, and 520 of method 500 shown in Figure 5. The aforementioned blocks of method 600 include: forming one or more second cavities within at least one of the L3 layers; forming a metal silicide layer within at least one of the one or more formed second cavities; and forming a metal contact plug within at least one of the one or more formed second cavities. As shown in Figures 14C and 14D and as described above during method 500, a metal contact plug 924 is formed within the second cavity 916 and is filled with a silicide layer and disposed within thePATENTAttorney Docket No.: 44025279WO01L3 layer. The metal contact plug further includes the formation of a dielectric layer (not shown) having a trench 434 formed over the pMOS GAA semiconductor device shown in Figure 14A.

[0100] Additionally or alternatively, in one or more embodiments, method 600, as seen in Figures 14C and 14D, can be used to form a contact within a backside 1455 power delivery network (BPDN) or backside 1455 power rail (BPR) device structure. While not discussed in detail, the present disclosure contemplates that during block 616 of method 600 a feature opening through interface 1299 and a subsequent preclean process can be performed on a partially formed nanosheet stack-based device such as that one shown in Figure 14A. The feature opening and pre-clean process can be performed in a processing chamber, such as the processing chamber 122 shown in Figure 1, or one of the processing chambers 200 or 300 shown in Figures 2A-2B and 3. The feature opening and pre-clean process 616 may be performed without breaking vacuum environment in a multi-chamber processing system, such as the multi-chamber processing system 100 shown in Figure 1.

[0101] During a BPDN or BPR device contact formation process sequence, block 616 will include the formation of a plurality of openings (not shown) aligned with and in contact with interface 1299 of the formed source / drain regions of the semiconductor structure device shown in Figure 14C formed on the front side of the substrate 402. After the formation of the plurality of openings, a cavity shaping process, such as that of method 555, is performed during block 616 to form the contact cavity 916 within the L3 layer leading to the formation of the contact plug 924 in block 620. The formation of a metal contact plug 924 within a backside power delivery network (BPDN) 1455 or backside power rail (BPR) 1455 device structure shown in Figure 14C allows for the cavity 916 to be within the highly doped and active L3 layer resulting in a lower contact resistance for backside contact formation since the highly doped L3 layer will facilitate the delivery of a high current density into the bottom nanosheet (e.g., 412B), which is a critical challenge in the industry due to the high resistance of the L1 layer.Contact Cavity Formation Process ExamplesPATENTAttorney Docket No.: 44025279WO01

[0102] Embodiments provided herein further include an integrated cavity etch process sequence as methods 1500 and 1600 depicted in Figures 15 and 16, respectively, to optimize electrical contact formation within the L3 layer by reducing lateral growth of openings formed during a cavity etch process sequence. Methods 1500 and 1600 can be integrated within method 500 (shown in Figure 5) after step 508 and within method 600 (shown in Figure 6) after step 606 aimed at improving the growth loading of the L3 layer comprising the highest doping concentration of (SixGei-x):B. Thus resulting in an improved performance of the semiconductor device due to the reduction of contact resistance achieved.

[0103] The cavity etch process sequence illustrated in method 1500 of Figure 15 starts with the semiconductor device shown in Figure 7A formed during block 508. As previously described, during block 508, a first cavity within the L1 layer is formed on the exposed portions of the L1 layer and the cavity is conformally filled, as shown in Figure 7A, with an L2 layer formed by a selective epitaxial growth process. The L2 layer fills the first cavity formed within the L1 layer and is fabricated from the same material as the L1 layer, with the exception that the boron doped silicon germanium (SixGei-x):B doping concentration of the L2 layer is substantially higher than that of the L1 layer.

[0104] At block 509A of method 1500, a non-conformal deposition layer (also referred to as a directional deposition of a film layer) 1702 is formed over the surfaces laterally adjacent to the L1 layer and L2 layer, which includes the sidewalls 1706, 1708, and 1710 of the gate cap 406B. In some cases, the non-conformal deposition layer is also disposed over at least a portion of the exposed L1 layer immediately adjacent to nanosheets 410B, 412B, and 414B as shown in Figures 17A and 17B and 17C.

[0105] As shown in Figures 17B and 17C, the non-conformal deposition layer 1702 can include an asymmetric lateral deposition, that is, the thickness of the layer 1702 can be adjusted, as will be briefly discussed below, resulting in different thicknesses of the layer 1702 deposited over sidewalls 1706, 1708, and 1710 along the Z and X directions. In one example, the non-conformal deposition layer 1702 formed on the sidewalls of the gate cap 406B is of greater thickness 1799 along the X direction than the thickness 1755 along the Z direction. This configuration merely serves forPATENTAttorney Docket No.: 44025279WO01exemplary purposes, and it is not intended to limit the scope of the disclosure provided herein since one skilled in the art would appreciate that the formation of the non-conformal deposition layer 1702 could also be formed over the surfaces laterally adjacent to the L1 layer shown in the configuration of Figure 12A, that is after the completion of block 606 of method 600 depicted in Figure 6.

[0106] Figure 19 illustrates a side view of an apparatus for forming the non-conformal deposition layer 1702 according to embodiments of the disclosure. As shown, an extraction assembly 1980 may be coupled to a plasma chamber, such as chamber 122 shown in Figure 1, and include an extraction plate 1984 and a beam blocker 1982. The extraction assembly 1980 may further include a collimation plate 1986, disposed between the extraction plate 1984 and the non-conformal deposition layer 1702 formed over sidewalls 1706, 1708, and 1710 surrounding the gate cap 406B as shown in Figures 17A and 17B. The extraction of an ion beam may be achieved by a bias voltage applied between the plasma chamber 122 and the non-conformal deposition layer 1702, dependent upon the targeted ion energy. To generate an angled ion beam, the beam blocker 1982 may be arranged to block a portion of the aperture 1990, formed with the extraction plate 1984, so that the ion beam 1988 is extracted from the plasma chamber 122 along the edge of the aperture as shown.

[0107] In the example shown in Figures 17A and 19, the angled ion beam 1700 is generated by using a beam blocker 1982 within the extraction assembly 1980. The ion beam 1700 may exit the plasma chamber and form the non-conformal layer 1702 partially around the gate cap regions 406B (e.g., 1706, 1708, and 1710) over a range of incident angles (9), measured with respect to the Z-direction in a direction normal to the gate cap 406B. The incident angle (6) can be adjusted and changed by manipulating components within the extraction assembly 1980 changing in this way the coverage of the non-conformal deposition layer 1702 on the regions adjacent to the L1 layer and the L2 layer.

[0108] To select for a given angle of incidence (or narrow range angle of incidence) (K), the collimation plate 1986 may be provided with a collimation aperture 1990. Figure 19 illustrates four possible placements for the collimation aperture 1992.PATENTAttorney Docket No.: 44025279WO01Increasing the value of 0 will lead to a higher value of K. For example, in Figure 19 for an offset Oi , the corresponding 01 is 12 - 21 degrees. Larger offsets will produce larger angles of incidence. Thus for a given placements of the collimation aperture 1992, ions exiting the plasma chamber 122 will be blocked from traversing to the non-conformal deposition layer 1702, except those ions having the suitable angle of incidence to pass through the collimation aperture 1992 and strike the portions of the forming non-conformal deposition layer 1702. Thus, by switching between different collimation plates having different values of 0, the apparatus in Figure 19 presents a convenient means to vary the angle of incidence of ions of a reactive beam to be applied to a substrate to change the coverage of the non-conformal deposition layer 1702 disposed over the gate cap 406B and regions immediately adjacent to the gate cap 406B (e.g., a portion of the exposed L1 layer).

[0109] In the example presented here, the directional deposition process is used to deliver a masking material (e.g., oxide carbon, nitride, silicon, metal, etc.) at a nonzero angle of inclination (0) relative to a perpendicular direction (e.g., Z-direction) to the top surface 1710 of the gate cap 406B. In one or more embodiments, the non-zero angle of inclination may be chosen so that the masking material impacts just the sidewall 1706, the upper surface 1710 of the gate cap 406B, and the sidewall 1708 as shown in 17B. It will be appreciated that coverage by the masking material is dependent on the non-zero angle (0) of inclination.

[0110] In an alternate embodiment to block 509A, as illustrated in Figures 18A, 18B, and 18C, a conformal deposition layer 1802 (also referred to as a “spacer protect liner 1802”) is alternatively formed over the surface of the L1 layer, the L2 layer, and over the surfaces laterally adjacent to both L1 layer and L2 layer, which includes the sidewalls 1806, 1808, and 1810 of the gate cap 406B during blocks 509B and 606B of methods 1500 and 1600, respectively. The conformal deposition layer 1802 formed over the exposed surfaces of the L1 layer, L2 layer, and around the gate cap 406B (e.g., sidewalls 1806, 1806, and 1810), can be formed by use of a conformal deposition process, such as chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a plasma enhanced atomic layer deposition (PEALD), a plasma enhanced chemical vapor deposition (PECVD) process, or any useful technique.PATENTAttorney Docket No.: 44025279WO01Typically, the conformal deposition layer is formed of materials such as aluminum oxide (AI2O3), silicon dioxide (SiO2), and Silicon oxycarbonnitride (SiOCN).

[0111] As illustrated in Figures 18A, 18B, and 18C, the conformal deposition layer has a symmetric lateral deposition thickness due to the use of a conformal deposition process. In one example, due to the non-directional nature of the deposition process, the thickness 1899 and 1855 along spacer protect liner 1802 formed on the sidewalls 1806, 1808, and 1810 of the gate cap 406B along the X and Z directions is the same as the thickness 1866 formed along the L1 layer and the L2 layer along the Z direction.

[0112] During blocks 509C and 606C of method 1500 and 1600 (Figures 15 and 16), an etching of the spacer protect liner (also referred to as a layer trimming process) is performed to remove one or more portions of the deposited conformal deposition layer 1802. In one or more embodiments, as shown in Figure 18B, a portion of the spacer protect liner is removed leaving exposed the sidewall 1810 of the gate cap 406B. Similarly, the layer trimming process may, in addition, expose at least a portion of the top surface 833 of the L1 layer and L2 layer within the source / drain region.

[0113] In some embodiments, the etching of the spacer protect liner can be performed in an extraction assembly (not shown) or in a separate plasma processing chamber such as processing chamber 122 shown in Figure 1, by use of plasma dry etching process that is configured to remove the portions of the conformal deposition layer 1802 by use of an anisotropic etching process. In some embodiments, the trimming process can include a reactive ion etching process that is configured to selectively etch the material (e.g., carbon) used to form the conformal deposition layer 1802 relative to the materials forming the L1 and L2 layers (e.g., Ge, Si) within the source / drain region.

[0114] The purpose of the integrated cavity etch process sequence of methods 1500 and 1600 is to physically isolate and avoid the subsequent etching of portions of the semiconductor device laterally adjacent to the L1 and L2 epitaxial semiconductor layers (e.g., nanosheets 410B, 412B, 414B and gate cap 406B) during the formation of the metal contact plug within the highly doped L3 layer during methods 500 and 600 described above.PATENTAttorney Docket No.: 44025279WO01

[0115] After the completion of either blocks 509A or 606A or alternatively, the completion of blocks 509B followed by 509C or 606B followed by 606C of the integrated cavity etch process shown in Figures 15 and 16, an anisotropic cavity etch (described in blocks 510 and 608 above ) is performed to form a second cavity 831, shown in Figures 17C and 18C (also shown in Figure 8A). The second cavity 831 within the first epitaxial semiconductor layer, as described above, may have a 11-shaped or V-shaped angled sidewalls.

[0116] After the completion of the anisotropic cavity etch during blocks 510 and 608 of method 500 and 600 (i.e., after the completion of blocks 1502 or 1602), the post processing of the semiconductor device continues with blocks 1504 or 1604 until the formation of the metal contact plug described above during blocks 520 and 620 is achieved.

[0117] While the foregoing is directed to embodiment of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

PATENTAttorney Docket No.: 44025279WO01What is claimed is:

1. A semiconductor device comprising:a first epitaxial semiconductor layer disposed within a cavity formed in a source / drain region of a semiconductor device structure formed on a substrate; a second epitaxial semiconductor layer disposed within a first cavity, wherein the first cavity is formed within the first epitaxial semiconductor layer;a metal silicide layer disposed on a second cavity, wherein the second cavity is formed within the second epitaxial semiconductor layer; anda metal contact plug formed on the metal silicide layer.

2. The semiconductor device of claim 1 , wherein a surface of the cavity formed in the source / drain region further comprises an epitaxial base layer on which the first epitaxial semiconductor layer is disposed on.

3. The semiconductor device of claim 1 , wherein the semiconductor device structure comprises a first layer of silicon, a second layer of silicon germanium, and subsequent alternating layers thereof stacked vertically on the substrate.

4. The semiconductor device of claim 1 , wherein the source / drain region comprises a first doping concentration of boron doped silicon germanium and the first epitaxial semiconductor layer comprises a second doping concentration of boron doped silicon germanium, and the second doping concentration of boron doped silicon germanium is greater than the first doping concentration of boron doped silicon germanium.

5. The semiconductor device of claim 4, wherein the second epitaxial semiconductor layer comprises a third doping concentration of boron doped silicon germanium, the third doping concentration of boron doped silicon germanium is greater than the second doping concentration of boron doped silicon germanium, and the third doping concentration of boron doped silicon germanium is greater than the first doping concentration of boron doped silicon germanium.PATENTAttorney Docket No.: 44025279WO016. The semiconductor device of claim 1 , wherein the second epitaxial semiconductor layer is recessed within the first cavity and wraps around the first epitaxial semiconductor layer.

7. The semiconductor device of claim 1 , wherein the second epitaxial semiconductor layer is formed as an interface between the first epitaxial semiconductor layer and the metal contact plug.

8. The semiconductor device of claim 1 , wherein the substrate comprises a first side and a second side, the semiconductor device structure is formed on the first side of the substrate, and the metal contact plug is formed on the second cavity on the second side of the substrate.

9. The semiconductor device of claim 1 , wherein the metal silicide layer comprises titanium silicide, cobalt silicide, zirconium silicide, hafnium silicide, or nickel platinum silicide.

10. A semiconductor device comprising:a first epitaxial semiconductor layer disposed within a first cavity within a source / drain region of a semiconductor device structure formed on a substrate; one or more second epitaxial semiconductor layers disposed within one or more second cavities, wherein the one or more second cavities are formed within the first epitaxial semiconductor layer;a metal silicide layer disposed within at least one of the one or more second cavities, wherein the one or more second cavities are formed within at least one of the one or more second epitaxial semiconductor layers; anda metal contact plug formed on the metal silicide layer.PATENTAttorney Docket No.: 44025279WO0111. The semiconductor device of claim 10, wherein a surface of the first cavity formed within the source / drain region further comprises an epitaxial base layer on which the first epitaxial semiconductor layer is disposed on.

12. The semiconductor device of claim 10, wherein the semiconductor device structure comprises a first layer of silicon, a second layer of silicon germanium, and subsequent alternating layers thereof stacked vertically on the substrate.

13. The semiconductor device of claim 10, wherein the source / drain region comprises a first doping concentration of boron doped silicon germanium and the first epitaxial semiconductor layer comprises a second doping concentration of boron doped silicon germanium, and the second doping concentration of boron doped silicon germanium is greater than the first doping concentration of boron doped silicon germanium.

14. The semiconductor device of claim 13, wherein the one or more second epitaxial semiconductor layers comprise a third doping concentration of boron doped silicon germanium, the third doping concentration of boron doped silicon germanium is greater than the second doping concentration of boron doped silicon germanium, and the third doping concentration of boron doped silicon germanium is greater than the first doping concentration of boron doped silicon germanium.

15. The semiconductor device of claim 10, wherein the one or more second epitaxial semiconductor layers are recessed within the one or more first cavities, the one or more second epitaxial semiconductor layers wrap around the first epitaxial semiconductor layer, and at least one of the one or more second epitaxial semiconductor layers is formed as an interface between the first epitaxial semiconductor layer and the substrate.

16. The semiconductor device of claim 10, wherein at least one of the one or more second epitaxial semiconductor layers is formed as an interface between the first epitaxial semiconductor layer and the metal contact plug.PATENTAttorney Docket No.: 44025279WO0117. A method of forming a semiconductor device, the method comprising:forming a first epitaxial semiconductor layer within a first cavity within a source / drain region of a semiconductor device structure formed on a substrate, wherein the first epitaxial semiconductor layer fills at least a portion of the first cavity;forming a second cavity within the first epitaxial semiconductor layer; forming a second epitaxial semiconductor layer within the second cavity; forming a third cavity within the second epitaxial semiconductor layer; forming a metal silicide layer within the third cavity; andforming a metal contact plug within the third cavity.

18. The method of claim 17, wherein the first epitaxial semiconductor layer, the second cavity, the second epitaxial semiconductor layer, the third cavity, and the metal silicide layer are formed without exposing the substrate to the atmosphere.

19. The method of claim 17, wherein a surface of the first cavity within the source / drain region further comprises an epitaxial base layer on which the first epitaxial semiconductor layer is disposed on.

20. The method of claim 17, wherein the semiconductor device structure comprises a first layer of silicon, a second layer of silicon germanium, and subsequent alternating layers thereof stacked vertically on the substrate.

21. The method of claim 17, wherein the source / drain region comprises a first doping concentration of boron doped silicon germanium and the first epitaxial semiconductor layer comprises a second doping concentration of boron doped silicon germanium, and the second doping concentration of boron doped silicon germanium is greater than the first doping concentration of boron doped silicon germanium.

22. The method of claim 21 , wherein the second epitaxial semiconductor layer comprises a third doping concentration of boron doped silicon germanium, the third doping concentration of boron doped silicon germanium is greater than the secondPATENTAttorney Docket No.: 44025279WO01doping concentration of boron doped silicon germanium, and the third doping concentration of boron doped silicon germanium is greater than the first doping concentration of boron doped silicon germanium.

23. The method of claim 17, wherein the second epitaxial semiconductor layer is recessed within the first cavity and wraps around the first epitaxial semiconductor layer.

24. The method of claim 17, wherein the second epitaxial semiconductor layer is formed as an interface between the first epitaxial semiconductor layer and the metal contact plug.

25. The method of claim 17, wherein the second cavity comprises a V-shape with angles sidewalls or U-shape with angled sidewalls, and the second cavity is formed by an anisotropic cavity etch.

26. The method of claim 25, wherein an integrated cavity etch process sequence is performed prior to the anisotropic cavity etch and the integrated cavity etch process sequence comprises:depositing a non-conformal deposition layer over a portion of the semiconductor device structure, wherein the portion of the semiconductor device structure comprises a gate cap.

27. The method of claim 26, wherein the non-conformal deposition layer comprises carbon, silicon oxide, silicon nitride, silicon, ora self-assembled monolayer (SAM).

28. The method of claim 17, wherein the second cavity comprises a planar or flat surface with vertical sidewalls, and the second cavity is formed by an isotropic cavity etch.PATENTAttorney Docket No.: 44025279WO0129. The method of claim 28, wherein an integrated cavity etch process sequence is performed prior to the isotropic cavity etch and the integrated cavity etch process sequence comprises:depositing a conformal deposition layer over a portion of the semiconductor device structure, wherein the portion of the semiconductor device structure comprises a gate cap, the first epitaxial semiconductor layer, and the source / drain region.

30. The method of claim 29, wherein the conformal deposition layer comprises silicon dioxide, aluminum oxide, and Silicon oxycarbonnitride.

31. A method of forming a semiconductor device, the method comprising:removing a portion of a source / drain region of a semiconductor device structure formed on a substrate to expose a surface of the semiconductor device structure;forming a first epitaxial semiconductor layer on the exposed surface of the semiconductor device structure within the source / drain region;forming one or more first cavities within the first epitaxial semiconductor layer; forming one or more second epitaxial semiconductor layers within at least one of the one or more first cavities;forming one or more second cavities within at least one of the one or more second epitaxial semiconductor layers;forming a metal silicide layer within at least one of the one or more second cavities in a processing system, wherein the first epitaxial semiconductor layer, the one or more first cavities, the one or more second epitaxial semiconductor layers, the one or more second cavities, and the metal silicide layer are formed without exposing the substrate to the atmosphere; andforming a metal contact plug within at least one of the one or more second cavities.PATENTAttorney Docket No.: 44025279WO0132. The method of claim 31 , wherein the semiconductor device structure comprises a first layer of silicon, a second layer of silicon germanium, and subsequent alternating layers thereof stacked vertically on the substrate.

33. The method of claim 31 , wherein the source / drain region comprises a first doping concentration of boron doped silicon germanium and the first epitaxial semiconductor layer comprises a second doping concentration of boron doped silicon germanium, and the second doping concentration of boron doped silicon germanium is greater than the first doping concentration of boron doped silicon germanium.

34. The method of claim 33, wherein the one or more second epitaxial semiconductor layers comprises a third doping concentration of boron doped silicon germanium, the third doping concentration of boron doped silicon germanium is greater than the second doping concentration of boron doped silicon germanium, and the third doping concentration of boron doped silicon germanium is greater than the first doping concentration of boron doped silicon germanium.

35. The method of claim 31 , wherein the one or more second epitaxial semiconductor layers are recessed within the one or more first cavities, the one or more second epitaxial semiconductor layers wrap around the first epitaxial semiconductor layer, and at least one of the one or more second epitaxial semiconductor layers is formed as an interface between the first epitaxial semiconductor layer and the substrate.

36. The method of claim 31 , wherein at least one of the one or more second epitaxial semiconductor layers is formed as an interface between the first epitaxial semiconductor layer and the metal contact plug.

37. The method of claim 31 , wherein the source / drain region further comprises an epitaxial base layer on which the first epitaxial semiconductor layer is disposed on.PATENTAttorney Docket No.: 44025279WO0138. A processing system comprising:a transfer chamber;a plurality of process chambers coupled to the transfer chamber; and a controller configured to cause a process to be performed in the processing system that includes:forming a first epitaxial semiconductor layer on a source / drain region of a semiconductor device structure formed on a substrate;forming a second epitaxial semiconductor layer on a first cavity, wherein the first cavity is formed within the first epitaxial semiconductor layer;forming a metal silicide layer on a second cavity, wherein the second cavity is formed within the second epitaxial semiconductor layer; and the source / drain region, the first epitaxial semiconductor layer, the first cavity, the second epitaxial semiconductor layer, the second cavity, and the metal silicide layer are formed without exposing the substrate to the atmosphere.

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