Etching method to recess SIGE and sigec in epi stack with selectivity to silicon

Abstract

Embodiments of the present disclosure generally relate to 3D semiconductor device fabrication techniques. More specifically, embodiments, described herein provide processes by which to selectively etch layers of SiGe and / or SiGeC from Si layers. In some embodiments, a method for processing a semiconductor device includes positioning a semiconductor device in a processing volume of a processing chamber. The semiconductor device includes alternating silicon (Si) layers and silicon germanium (SiGe) layers. The method further includes introducing a process gas to the processing chamber. The process gas includes an etchant gas and a passivation gas. The method further includes performing a selective etch operation using the process gas to remove the SiGe layers from the semiconductor device.

Description

PATENTAttorney Docket No.: 44025773WO01ETCHING METHOD TO RECESS SIGE AND SIGEC IN EPI STACK WITH SELECTIVITY TO SILICON BACKGROUNDField

[0001] Embodiments of the present disclosure generally relate to 3D semiconductor device fabrication techniques. More specifically, embodiments, described herein provide processes by which to selectively etch layers of silicon germanium (SiGe) and / or silicon germanium carbon (SiGeC) from Si layers.Description of the Related Art

[0002] Epitaxial superlattice heterostructures can be used to form three dimensional semiconductor devices (e.g., dynamic random access memory (DRAM)) and components for rapid storage of information provided by a processor component of a computer. More specifically, 3D DRAM refers to the architectural storing of bits in the vertical direction, similar to 3D NAND. However, DRAM is almost 1000x faster than NAND and achieves this speed by using a high mobility silicon substrate as the starting material to form the channel. The high speed of DRAM also comes from a charge that can be moved quickly in and out of the capacitor. As semiconductor devices scale in the vertical direction (e.g., 3D DRAM), new material innovations are required to enable high mobility and ultra-low defect channels.

[0003] Some epitaxial superlattice heterostructures having SiGe sacrificial layers can be used for semiconductor device and / or component processing, due to the faster etch rate of SiGe layers when using conventional etchant gases (e.g., NF3 and / or F2 based etchants). However, the etch rate and / or etch selectivity of the SiGe layer during conventional etchant gas processing will decrease if Ge% is reduced, SiGe layer thickness is reduced, and / or the SiGe layer is doped with carbon. Such reductions in etch rate and / or etch selectivity can lead to inadequate removal of the SiGe sacrificial layer, and ultimately reduced performance of the semiconductor device and / or component.PATENTAttorney Docket No.: 44025773WO01

[0004] Thus, there is a need to develop new semiconductor devices, materials, and / or manufacturing processes.SUMMARY

[0005] Embodiments of the present disclosure generally relate to 3D semiconductor device fabrication techniques. More specifically, embodiments, described herein provide processes by which to selectively etch layers of SiGe and / or SiGeC from Si layers.

[0006] In some embodiments, a method for processing a semiconductor device includes positioning a semiconductor device in a processing volume of a processing chamber. The semiconductor device includes alternating silicon (Si) layers and silicon germanium (SiGe) layers. The method further includes introducing a process gas to the processing chamber. The process gas includes an etchant gas and a passivation gas. The method further includes performing a selective etch operation using the process gas to remove the SiGe layers from the semiconductor device.

[0007] In some embodiments, a method for processing a semiconductor device includes positioning a semiconductor device in a processing volume of a processing chamber. The semiconductor device includes alternating silicon (Si) layers and silicon germanium (SiGe) layers. The method further includes introducing a process gas to the processing chamber. The process gas includes a first gas component and a second gas component. The method further includes performing a selective etch operation using the process gas to remove the SiGe layers from the semiconductor device. The first gas component exhibits a higher etch rate than the second gas component.

[0008] In some embodiments, a method for processing a semiconductor device includes positioning a semiconductor device in a processing volume of a processing chamber. The semiconductor device includes alternating silicon (Si) layers and silicon germanium (SiGe) layers. The method further includes introducing a process gas to the processing chamber. The process gas includes an etchant gas and a passivation gas. The etchant gas and the passivation gas are sequentially introduced to the processing chamber via a pulsing operation. The pulsing operation includesPATENTAttorney Docket No.: 44025773WO01introducing the etchant gas to the processing chamber for a first time in a range of about 0.25 sec to about 10 sec and stopping flow of the etchant gas to the processing chamber for a second time in a range of about 0.25 sec to about 10 sec. The pulsing operation further includes introducing the passivation gas to the processing chamber during the second time and stopping flow of the passivation gas to the processing chamber during the first time. The method further includes performing a selective etch operation using the process gas to remove the SiGe layers from the semiconductor device.BRIEF DESCRIPTION OF THE DRAWINGS

[0009] So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of its scope, and may admit to other equally effective embodiments.

[0010] FIG. 1 is a schematic representation of a processing system, according to an embodiment described herein.

[0011] FIG. 2 is a process flow diagram of a method, according to an embodiment described herein.

[0012] FIG. 3A is a partial schematic cross-sectional views of a semiconductor device, according to an embodiment described herein.

[0013] FIG. 3B is a partial schematic cross-sectional views of a semiconductor device, according to an embodiment described herein.

[0014] FIG. 3C is a partial schematic cross-sectional views of a semiconductor device, according to an embodiment described herein.

[0015] FIG. 4A is a graphical representation of a gas flow profile of the process gas components being introduced to a processing chamber during a processing method, according to an embodiment described herein.PATENTAttorney Docket No.: 44025773WO01

[0016] FIG. 4B is a graphical representation of a gas flow profile of the process gas components being introduced to a processing chamber during a processing method, according to an embodiment described herein.

[0017] FIG. 4C is a graphical representation of a gas flow profile of the process gas components being introduced to a processing chamber during a processing method, according to an embodiment described herein.

[0018] FIG. 4D is a graphical representation of a gas flow profile of the process gas components being introduced to a processing chamber during a processing method, according to an embodiment described herein.

[0019] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.DETAILED DESCRIPTION

[0020] Embodiments of the present disclosure generally relate to methods for processing epitaxial superlattice heterostructures, such as 3D semiconductor fabrication techniques. Generally, the method and structures provided herein enable production of 3D semiconductor devices. More specifically, embodiments, described herein provide processes by which to selectively etch layers of silicon germanium (SiGe) and / or silicon germanium carbon (SiGeC) from silicon (Si) layers. Embodiments described herein include selective etch processes using process gas compositions to increase etch rate and etch selectivity towards SiGe layers and / or SiGeC layers without causing material surface or bulk damage to the underlying Si layers.

[0021] FIG. 1 illustrates a schematic representation of a processing system 100 for use with one or more embodiments of the present disclosure. The processing system 100 can include suitable process chambers configured for one or more of chemical vapor deposition (CVD) and etching. Exemplary processing systems that may be used to perform the inventive methods disclosed herein may include, but are not limited to,PATENTAttorney Docket No.: 44025773WO01a physical vapor deposition chamber, a CVD chamber, an etching chamber, or any other suitable chamber known to one of ordinary skill in the art. Other process chambers, including those from other manufacturers, may also be suitably used in connection with the teachings provided herein.

[0022] For example, a processing system 100 described below facilitates operation of the methods described herein such that there are limited or no vacuum breaks between processes. Reduced vacuum breaks may limit or prevent contamination (e.g., oxidation) of the substrate and may further enhance throughput by reducing the amount of time between processes and reducing or eliminating certain processes such as native oxide removal operations or other operations that would otherwise be required where the process to be performed sequentially in standalone process chambers.

[0023] The processing system 100 includes a vacuum-tight processing platform (processing platform 101), a factory interface 104, and a system controller 102. The processing platform 101 comprises multiple process chambers, such as for example 114A, 114B, 114C, and 114D operatively coupled to a vacuum substrate transfer chamber (transfer chamber 103). The factory interface 104 is operatively coupled to the transfer chamber 103 by one or more load lock chambers (two load lock chambers, such as 106A and 106B shown in FIG. 1).

[0024] In some embodiments, the factory interface 104 comprises at least one docking station 107, at least one factory interface robot 138 to facilitate the transfer of one or more semiconductor substrates (e.g., wafers). The docking station 107 is configured to accept one or more front opening unified pod (FOUR). Four FOURS, such as 105A, 105B, 105C, and 105D are shown in the embodiment of FIG. 1. The factory interface robot 138 is configured to transfer the substrates from the factory interface 104 to the processing platform 101 through the load lock chambers, such as 106A and 106B. Each of the load lock chambers 106A and 106B have a first port coupled to the factory interface 104 and a second port coupled to the transfer chamber 103. The load lock chamber 106A and 106B are coupled to a pressure control system (not shown) which pumps down and vents the load lock chambers 106A and 106B to facilitate passing the substrates between the vacuum environment of the transferPATENTAttorney Docket No.: 44025773WO01chamber 103 and the substantially ambient (e.g., atmospheric) environment of the factory interface 104. The transfer chamber 103 has a vacuum robot 142 disposed within the transfer chamber 103. The vacuum robot 142 is capable of transferring substrates 121 between the load lock chamber 106A and 106B and the process chambers 114A, 114B, 114C, and 114D.

[0025] In some embodiments, the process chambers 114A, 114B, 114C, and 114D, are coupled to the transfer chamber 103. The process chambers 114A, 114B, 114C, and 114D comprise at least a CVD chamber and an etch chamber. Additional CVD chambers and / or etch chambers may also be provided.

[0026] In some embodiments, a deposition chamber is provided that is configured to deposit a stack of alternating Si layers and SiGe layers or SiGeC layers onto a substrate surface. The deposition chamber may be configured to provide one or more dopants in one or more of the Si layers and SiGe or SiGeC layers.

[0027] In some embodiments, an etch chamber is provided that is configured to anisotropically etch a vertical trench or feature through the stack of alternating Si layers and SiGe layers or SiGeC layers. In some embodiments, the etch chamber may be configured to isotropically etch a recess in the stack of alternating Si layers and SiGe layers or SiGeC layers. In some embodiments, the etch chamber is provided that is configured to isotropically etch an opening in the stack of alternating Si layers and SiGe layers or SiGeC layers.

[0028] In some embodiments, one or more optional service chambers (shown as 116A and 116B) may be coupled to the transfer chamber 103. The service chambers 116A and 116B may be configured to perform other substrate processes, such as degassing, oxide removal, orientation, substrate metrology, cool down and the like.

[0029] The system controller 102 controls the operation of the processing system 100 using a direct control of the process chambers 114A, 114B, 114C, and 114D or alternatively, by controlling the computers (or controllers) associated with the process chambers 114A, 114B, 114C, and 114D and the processing system 100. In operation, the system controller 102 enables data collection and feedback from the respective chambers and systems to optimize performance of the processing system 100. ThePATENTAttorney Docket No.: 44025773WO01system controller 102 generally includes a central processing unit (CPU) 130, a memory 134, and a support circuit 132. The CPU 130 may be any form of a general-purpose computer processor that can be used in an industrial setting. The support circuit 132 is conventionally coupled to the CPU 130 and may comprise a cache, clock circuits, input / output subsystems, power supplies, and the like. Software routines, such as processing methods as described above may be stored in the memory 134 (e.g., non-transitory computer readable storage medium) and, when executed by the CPU 130, transform the CPU 130 into a specific purpose computer (system controller 102). The software routines may also be stored and / or executed by a second controller (not shown) that is located remotely from the processing system 100.

[0030] FIG. 2 is a process flow diagram of a method 200 for processing an epitaxial superlattice heterostructure (hereinafter referred to as a “semiconductor device”), such as a dynamic random access memory (DRAM) device. FIG. 3A-3C are partial schematic cross-sectional views of a semiconductor device 300 during one or more operations of the method 200. The method 200 can include providing a semiconductor device 300 to a processing chamber (e.g., a processing chamber within the processing system 100) and etching a portion of the semiconductor device 300 to form a feature 310 therein. A process gas may then be introduced to the processing chamber to perform a selective etch operation on the semiconductor device 300.

[0031] In operation 210 of the method 200, a substrate upon which a semiconductor device 300 is formed is introduced to a processing chamber (e.g., a processing chamber within the processing system 100). The semiconductor device 300 can include a memory stack 304 disposed on a surface of a substrate 302, as shown in FIG. 3A. The memory stack 304 can include alternating layers, such as alternating Si layers 306 and SiGe layers 308 (e.g., SiGe layers and / or SiGeC layers). The SiGe layers 308 can include a germanium (Ge) content of about 2 mol% to about 40 mol%, such as about 10 mol% to about 30 mol%, such as about 15 mol% to about 20 mol%, alternatively about 3 mol% to about 10 mol%, alternatively about 10 mol% to about 15 mol%, alternatively about 20 mol% to about 30 mol%, alternatively about 30 mol% to about 40 mol%. In one or more embodiments, the SiGe layers have a Ge content of about 25 mol% or less, such as 15 mol% or less, such as about 12 mol%PATENTAttorney Docket No.: 44025773WO01or less, such as about 10 mol% or less, such as about 8 mol% or less, such as about 5 mol% or less. In some embodiments, the SiGe layers include a dopant disposed therein. The dopant within the SiGe layers may include a carbon dopant (C), a boron dopant (B), a phosphorus dopant (P), or a combination thereof. In one or more embodiments, the dopant is present within the SiGe layer at a concentration of about 0.1 atomic% to about 2 atomic%, such as about 0.5 atomic% to about 1.5 atomic%, such as about 0.75 atomic% to about 1.25 atomic%, alternatively about 0.1 atomic% to about 0.5 atomic%, alternatively about 0.5 atomic% to about 0.75 atomic%, alternatively about 0.75 atomic% to about 1 atomic%, alternatively about 1 atomic% to about 1.25 atomic%, alternatively about 1.25 atomic% to about 1.5 atomic%, alternatively about 1.5 atomic% to about 2 atomic%.

[0032] It should be noted that, when used herein, a substrate 302 may refer to any substrate and / or material surface formed on a substrate upon which film processing may be performed during a fabrication process. A substrate material may, for example, include, but is not limited to, silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon doped silicon oxides, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and / or any other materials, such as, for instance, metals, metal nitrides, metal alloys, and / or any other conductive materials (which may be specific to a particular implementation, application, use, etc.). Substrates may also include semiconductor wafers. Substrates may be exposed to one or more pretreatment processes, such as, for example, to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, e-beam cure and / or bake the substrate surface. The substrate surface and / or substrate may include an underlayer, such as, for instance, upon depositing a film / layer and / or partial film / layer onto a substrate surface, an exposed surface of the deposited film / layer becomes the substrate surface.

[0033] For ease of illustration, FIG. 3A-3C show only a limited number of such layers. As can be understood, any number of layers may be stacked directly on top of one another. As used herein, the term "on", as used with respect to a film and / or a layer of a film, may include the film and / or layer being directly disposed on a surface, and / or on one or more underlayers between the film and / or layer and the surface.PATENTAttorney Docket No.: 44025773WO01

[0034] A layer may refer to a single crystalline layer of material and / or multiple crystalline layers of the same material, which, may, upon being combined, form a single crystalline layer. The semiconductor device 300 may, for example, include a plurality of alternating Si layers 306 and SiGe layers 308, where thicknesses and / or heights of each Si layer 306 and SiGe layer 308 may vary.

[0035] In some embodiments, each of the Si layers 306 may have a height (e.g., thickness) greater than a height (e.g., thickness) of each of the SiGe layers 308. In some embodiments, one or more of the Si layers 306 have a height of about 5 nm to about 100 nm, such as about 20 nm to about 80 nm, such as about 40 nm to about 60 nm, alternatively about 5 nm to about 20 nm, alternatively about 20 nm to about 40 nm, alternatively about 40 nm to about 50 nm, alternatively about 50 nm to about 60 nm, alternatively about 60 nm to about 80 nm, alternatively about 80 nm to about 100 nm. In some embodiments, one or more of the SiGe layers 308 have a height about 5 nm to about 50 nm, such as about 10 nm to about 40 nm, such as about 20 nm to about 30 nm, alternatively about 5 nm to about 10 nm, alternatively about 10 nm to about 20 nm, alternatively about 20 nm to about 25 nm, alternatively about 25 nm to about 30 nm, alternatively about 30 nm to about 40 nm, alternatively about 40 nm to about 50 nm.

[0036] In operation 220 of the method 200, the semiconductor device 300 may undergo an anisotropic etching process to create a feature 310 through the alternating Si layers 306 and SiGe layers 308, as shown in FIG 3B. The anisotropic etching can be done in any suitable manner to form the feature 310 through each of the alternating Si layers 306 and SiGe layers 308.

[0037] In operation 230 of the method 200, a process gas is introduced to the processing chamber (e.g., a processing chamber within the processing system 100). The process gas may include an etchant gas and / or a passivation gas. The etchant gas may include any suitable etchant gas, such as a chlorine (Cl) based etchant gas and / or a fluorine (F) based etchant gas. In one or more embodiments, the etchant gas includes at least one of chlorine trifluoride (CIF3), iodine heptaflouride (IF7), fluorine gas (F2), chlorine gas (CI2), iodine pentafluoride (IFs), hydrochloric acid (HCI), and combinations thereof. In at least one embodiment, the etchant gas includes CIF3. ThePATENTAttorney Docket No.: 44025773WO01passivation gas may be selected from a group of gases having a slower etch rate and / or higher sticking probability than the etchant gas. In one or more embodiments, the passivation gas includes at least one of iodine heptaflouride (IF7), perfluoropentane (C5F12), boron trichloride (BCI3), iodine pentafluoride (IFs), ethanol,, hydrogen gas (H2), hydrochloric acid (HCI), and combinations thereof. In at least one embodiment, the passivation gas includes IF7. In some embodiments, the process gas further includes a carrier gas, such as argon (Ar), nitrogen (N2), hydrogen (H2), neon (Ne), krypton (Kr), and combinations thereof. Each of the components of the process gas may be introduced to the processing chamber either simultaneously and / or independently.

[0038] In some embodiments, the process gas is introduced to the processing chamber at a gas flow rate of about 0.1 seem to about 100 seem, such as about 1 seem to about 90 seem, such as about 20 seem to about 80 seem, such as about 40 seem to about 60 seem, alternatively about 0.1 seem to about 1 seem, alternatively about 1 seem to about 200 seem, alternatively about 20 seem to about 40 seem, alternatively about 40 seem to about 50 seem, alternatively about 50 seem to about 60 seem, alternatively about 60 seem to about 80 seem, alternatively about 80 seem to about 90 seem, alternatively about 90 seem to about 100 seem. In one or more embodiments, the etchant gas is introduced to the processing chamber at a gas flow rate of about 0.5 seem to about 5 seem, such as about 1 seem to about 4 seem, such as about 2 seem to about 3 seem, alternatively about 0.5 seem to about 1 seem, alternatively about 1 seem to about 2 seem, alternatively about 3 seem to about 4 seem, alternatively about 4 seem to about 5 seem. In one or more embodiments, the passivation gas is introduced to the processing chamber at a gas flow rate of about 0.1 seem to about 10 seem, such as about 1 seem to about 9 seem, such as about 2 seem to about 8 seem, such as about 4 seem to about 6 seem, alternatively about 0.1 seem to about 1 seem, alternatively about 1 seem to about 2 seem, alternatively about 2 seem to about 4 seem, alternatively about 4 seem to about 5 seem, alternatively about 5 seem to about 6 seem, alternatively about 6 seem to about 8 seem, alternatively about 8 seem to about 9 seem, alternatively about 9 seem to about 10 seem. The process gas may include both the etchant gas and the passivation gas in a molar ratio of about 10:1 to about 1:1000 (etchant gas: passivation gas), such as about 5:1 toPATENTAttorney Docket No.: 44025773WO01about 1:500, such as about 2:1 to about 1:100, alternatively about 10:1 to about 5:1, alternatively about 5:1 to about 2:1, alternatively about 2:1 to about 1:1, alternatively about 1:1 to about 1:100, alternatively about 1:100 to about 1:500, alternatively about 1:500 to about 1:1000. In at least one embodiment, the carrier gas is introduced to the processing chamber at a gas flow rate of about 10 seem to about 2000 seem, such as about 100 seem to about 1500 seem, such as about 500 seem to about 1250 seem, alternatively about 10 seem to about 100 seem, alternatively about 100 seem to about 500 seem, alternatively about 500 seem to about 1000 seem, alternatively about 1000 seem to about 1250 seem, alternatively about 1250 seem to about 1500 seem, alternatively about 1500 seem to about 2000 seem.

[0039] In operation 240 of the method 200, a selective etch operation is performed on the semiconductor device 300 to remove at least one of the layers therefrom, as shown in FIG. 30. The selective etch operation can be thermal etch operation that may optionally include forming a plasma within the processing volume from the process gas. The composition of the process gas may be selected so as to preferentially remove layers composed of one composition from the semiconductor device 300 without affecting and / or damaging layers composed of a different composition. In at least one embodiment, the selective etch operation substantially removes the SiGe layers 308 from the semiconductor device 300 without damaging the bulk of the Si layers 306, as shown in FIG. 3C. Without being bound by theory, the inclusion of the passivation gas in the process gas composition limits and / or eliminates potential damage (e.g., pitting) that might be incurred by the Si layers during the selective etch operation.

[0040] The temperature within the processing chamber may be maintained at a temperature of about -80 °C to about 200 °C during the selective etch operation, such as about -20 °C to about 140 °C, such as about 40 °C to about 80 °C, alternatively about -80 °C to about -20 °C, alternatively about -20 °C to about 40 °C, alternatively about 80 °C to about 140 °C, alternatively about 140 °C to about 200 °C. The selective etch operation may be conducted at a pressure of about 0.1 Pa to about 100 Pa, such as about 1 Pa to about 90 Pa, such as about 20 Pa to about 80 Pa, such as bout 40 Pa to about 60 Pa, alternatively about 0.1 Pa to about 1 Pa, alternatively about 1 PaPATENTAttorney Docket No.: 44025773WO01to about 20 Pa, alternatively about 20 Pa to about 40 Pa, alternatively about 40 Pa to about 50 Pa, alternatively about 50 Pa to about 60 Pa, alternatively about 60 Pa to about 80 Pa, alternatively about 80 Pa to about 90 Pa, alternatively about 90 Pa to about 100 Pa.

[0041] In some embodiments, the selective etch operation includes the formation of plasma. The plasma may be formed by applying a radio frequency (RF) power to the process gas. In one or more embodiments, the plasma is formed from a remote plasma source to generate the radical species. The RF power may be applied capacitively or inductively. The RF power applied to the process gas may be in the range of about 5 W to about 300 W, such as about 50 W to about 250 W, such as about 100 W to about 200 W, alternatively about 5 W to about 50 W, alternatively about 50 W to about 100 W, alternatively about 100 W to about 150 W, alternatively about 150 W to about 200 W, alternatively about 200 W to about 250 W, alternatively about 250 W to about 300 W. The RF power may be applied to the process gas at a frequency of about 2 MHz to about 100 MHz, such as about 20 MHz to about 80 MHz, such as about 40 MHz to about 60 MHz, alternatively about 2 MHz to about 20 MHz, alternatively about 20 MHz to about 40 MHz, alternatively about 40 MHz to about 50 MHz, alternatively about 50 MHz to about 60 MHz, alternatively about 60 MHz to about 80 MHz, alternatively about 80 MHz to about 100 MHz.

[0042] The selective etch operation may be applied to the semiconductor device 300 for a process time of about 1 min to about 20 min, such as about 5 min to about 15 min, alternatively about 1 min to about 5 min, alternatively about 5 min to about 10 min, alternatively about 10 min to about 15 min, alternatively about 15 min to about 20 min. In some embodiments, the selective etch operation exhibits an etch rate of the target layer composition (e.g., the SiGe layer 308) of about 0.1 nm / min to about 20 nm / min, such as about 1 nm / min to about 15 nm / min, such as about 5 nm / min to about 10 nm / min, alternatively about 0.1 nm / min to about 1 nm / min, alternatively about 1 nm / min to about 5 nm / min, alternatively about 10 nm / min to about 15 nm / min, alternatively about 15 nm / min to about 20 nm / min.

[0043] As previously discussed, the components of the process gas may be introduced to the processing chamber either simultaneously and / or independently.PATENTAttorney Docket No.: 44025773WO01Furthermore, the composition of the process gas may be selected so as to preferentially remove layers composed of one composition from the semiconductor device 300 without affecting and / or damaging layers composed of a different composition. In some embodiments, the composition of the process gas may be tuned by changing the gas flow profiles of the process gas components (e.g., the etchant gas, the passivation gas, and / or the carrier gas) being introduced to the processing chamber, so as to increase the etch selectivity of the selective etch operation.

[0044] FIG. 4A-4D illustrate various exemplary gas flow profiles of the process gas components being introduced to the processing chamber during operation 230. FIG.4A shows an exemplary gas flow profile that includes each of the process gas components being simultaneously and continuously introduced to the processing chamber. In such an example, the flow rate of a process gas component being introduced to the processing chamber is independent of the other process gas components being introduced thereto. As illustrated in FIG. 4A, the flow rate of gas 1 is greater than the flow rate of both gas 2 and gas 3, and the flow rate of gas 2 is greater than the flow rate of gas 3. In some embodiments, gas 1 is composed of the etchant gas, the passivation gas, the carrier gas, or a combination thereof. In some embodiments, gas 2 is composed of the etchant gas, the passivation gas, the carrier gas, or a combination thereof. In some embodiments, gas 3 is composed of the etchant gas, the passivation gas, the carrier gas, or a combination thereof.

[0045] FIG. 4B shows an exemplary gas flow profile that includes each of the process gas components being simultaneously introduced to the processing chamber via a pulsing operation. In such an example, the components of the process gas are introduced to the processing chamber for a time (denoted as “x” in FIG. 4B) ranging from about 0.1 seem to about 20 seem, such as about 1 seem to about 15 seem, such as about 5 seem to about 10 seem, alternatively about 0.1 seem to about 1 seem, alternatively about 1 seem to about 5 seem, alternatively about 10 seem to about 15 seem, alternatively about 15 seem to about 20 seem. The process gas flow to the processing chamber is subsequently ceased for a time (denoted as “y” in FIG. 4B) ranging from about 1 s to about 20 mins, such as about 1 min to about 15 min, such as about 5 min to about 10 min, alternatively about 1 s to about 1 min, alternativelyPATENTAttorney Docket No.: 44025773WO01about 1 min to about 5 min, alternatively about 10 min to about 15 min, alternatively about 15 min to about 20 min. The gas flow profile of the process gas to the processing chamber may be cyclically repeated throughout operation 230, wherein the components of the process gas are introduced to the processing chamber for a time (x) and ceased for a time (y). As illustrated in FIG. 4B, the flow rate of gas 1 is greater than the flow rate of both gas 2 and gas 3, and the flow rate of gas 2 is greater than the flow rate of gas 3. In some embodiments, gas 1 is composed of the etchant gas, the passivation gas, the carrier gas, or a combination thereof. In some embodiments, gas 2 is composed of the etchant gas, the passivation gas, the carrier gas, or a combination thereof. In some embodiments, gas 3 is composed of the etchant gas, the passivation gas, the carrier gas, or a combination thereof.

[0046] FIG. 4C shows an exemplary gas flow profile that includes the process gas components being simultaneously and independently introduced to the processing chamber. In such an example, gas 1 is continuously introduced to the processing chamber at a constant flow rate, while gas 2 is introduced to the processing chamber for a time (denoted as “x” in FIG. 4C) ranging from about 1 s to about 20 mins, such as about 1 min to about 15 min, such as about 5 min to about 10 min, alternatively about 1 s to about 1 min, alternatively about 1 min to about 5 min, alternatively about 10 min to about 15 min, alternatively about 15 min to about 20 min. The gas flow of gas 2 to the processing chamber is subsequently ceased for a time (denoted as “y” in FIG. 40) ranging from about 1 s to about 20 mins, such as about 1 min to about 15 min, such as about 5 min to about 10 min, alternatively about 1 s to about 1 min, alternatively about 1 min to about 5 min, alternatively about 10 min to about 15 min, alternatively about 15 min to about 20 min. The gas flow profile of gas 2 to the processing chamber may be cyclically repeated throughout operation 230, wherein gas 2 introduced to the processing chamber for a time (x) and ceased for a time (y), while also simultaneously and / or continuously flowing gas 1 to the processing chamber. As illustrated in FIG. 40, the flow rate of gas 1 is greater than the flow rate of gas 2. In some embodiments, gas 1 is composed of the etchant gas, the passivation gas, the carrier gas, or a combination thereof. In some embodiments, gas 2 is composed of the etchant gas, the passivation gas, the carrier gas, or a combination thereof.PATENTAttorney Docket No.: 44025773WO01

[0047] FIG. 4D shows an exemplary gas flow profile that includes the process gas components being independently introduced to the processing chamber. In such an example, both gas 1 and gas 2 are introduced to the processing chamber at different times via a pulsing operation. For instance, gas 2 is introduced to the processing chamber for a time (denoted as “x” in FIG. 4D) ranging from about 1 s to about 200 s, such as about 50 s to about 150 s, such as about 75 s to about 125 s, alternatively about 1 s to about 50 s, alternatively about 50 s to about 75 s, alternatively about 75 s to about 100 s, alternatively about 100 s to about 125 s, alternatively about 125 s to about 150 s, alternatively about 150 s to about 200 s. The gas flow of gas 2 to the processing chamber is subsequently ceased for a time (denoted as “y” in FIG. 4D) ranging from about 1 s to about 200 s, such as about 50 s to about 150 s, such as about 75 s to about 125 s, alternatively about 1 s to about 50 s, alternatively about 50 s to about 75 s, alternatively about 75 s to about 100 s, alternatively about 100 s to about 125 s, alternatively about 125 s to about 150 s, alternatively about 150 s to about 200 s. During the time (y) in which gas 2 is ceased from being introduced to the processing chamber, gas 1 is introduced to the processing chamber. The gas flow profile of gas 2 and gas 1 to the processing chamber may be cyclically repeated throughout operation 230, wherein gas 2 introduced to the processing chamber for a time (x) and ceased for a time (y), while gas 1 is introduced to the processing chamber for a time (y) and ceased for a time (x). As illustrated in FIG. 4D, the flow rate of gas 1 is greater than the flow rate of gas 2. In some embodiments, gas 1 is composed of the etchant gas, the passivation gas, the carrier gas, or a combination thereof. In some embodiments, gas 2 is composed of the etchant gas, the passivation gas, the carrier gas, or a combination thereof.

[0048] Overall, the process disclosed herein enables selective etching of SiGe layers from Si layers of an epitaxial superlattice heterostructure. More specifically, the process disclosed herein is capable of rapidly etching SiGe layers composed of a low Ge content (e.g., SiGe layers composed of less than 10% Ge), without causing material surface or bulk damage to the alternating Si layers. Additionally and / or alternatively, the process disclosed herein may be used to etch blanket films or structured samples with different patterns and aspect ratios. The process disclosedPATENTAttorney Docket No.: 44025773WO01herein may be used in the fabrication of 3D semiconductor devices and / or structures, and / or any other structures necessitating SiGe and / or SiGeC etch selective to Si.

[0049] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

PATENTAttorney Docket No.: 44025773WO01What is claimed is:

1. A method for processing a semiconductor device, the method comprising: positioning a semiconductor device in a processing volume of a processing chamber, wherein the semiconductor device comprises alternating silicon (Si) layers and silicon germanium (SiGe) layers;introducing a process gas to the processing chamber, the process gas comprising an etchant gas and a passivation gas; andperforming a selective etch operation using the process gas to remove the SiGe layers from the semiconductor device.

2. The method of claim 1 , wherein the SiGe layers comprise a germanium content of about 25 mol% or less.

3. The method of claim 1 , wherein the SiGe layers include a dopant disposed therein, wherein:the dopant is selected from carbon (C), boron (B), phosphorus (P), or a combination thereof, andthe dopant is present in the SiGe layers at a concentration of about 0.1 atomic% to about 2 atomic%.

4. The method of claim 1, wherein the etchant gas comprises chlorine trifluoride (CIF3).

5. The method of claim 4, wherein the passivation gas comprises iodine heptaflouride (IF7).

6. The method of claim 5, wherein the process gas further comprises a carrier gas, wherein:the carrier gas comprises argon (Ar), nitrogen (N2), hydrogen (H2), neon (Ne), krypton (Kr), or a combination thereof, andPATENTAttorney Docket No.: 44025773WO01the carrier gas is introduced to the processing chamber at a gas flow rate of about 10 seem to about 2000 seem.

7. The method of claim 4, wherein the etchant gas is introduced to the processing chamber at a gas flow rate of about 0.1 seem to about 100 seem.

8. The method of claim 1, wherein the passivation gas comprises iodine heptaflouride (IF?).

9. The method of claim 8, wherein the passivation gas is introduced to the processing chamber at a gas flow rate of about 0.5 seem to about 10 seem.

10. The method of claim 1, wherein the selective etch operation comprises introducing a plasma to the processing volume of the processing chamber.

11. The method of claim 10, wherein the selective etch operation comprises removing the SiGe layers from the semiconductor device at an etch rate of about 0.05 nm / s to about 5 nm / s.

12. A method for processing a semiconductor device, the method comprising: positioning a semiconductor device in a processing volume of a processing chamber, wherein the semiconductor device comprises alternating silicon (Si) layers and silicon germanium (SiGe) layers;introducing a process gas to the processing chamber, the process gas comprises a first gas component and a second gas component; andperforming a selective etch operation using the process gas to remove the SiGe layers from the semiconductor device, wherein the first gas component exhibits a higher etch rate than the second gas component.

13. The method of claim 12, wherein:the first gas component is continuously introduced to the processing chamber at a gas flow rate of about 0.5 seem to about 10 seem; andPATENTAttorney Docket No.: 44025773WO01the second gas component is continuously introduced to the processing chamber at a gas flow rate of about 0.1 seem to about 10 seem.

14. The method of claim 12, wherein:the first gas component is continuously introduced to the processing chamber at a gas flow rate of about 0.1 seem to about 100 seem; andthe second gas component is introduced to the processing chamber via a pulsing operation at a gas flow rate of about 0.1 seem to about 10 seem, wherein the pulsing operation comprises flowing the second gas component, which comprises a passivation gas, to the processing chamber for a first period of time and stopping the flow of the passivation gas to the processing chamber for a second period of time, the pulsing operation being repeated for one or more cycles.

15. The method of claim 14, wherein the first period of time is in a range of about 1 s to about 20 min.

16. The method of claim 14, wherein the second period of time is in a range of about 1 min to about 10 min.

17. The method of claim 12, wherein:the first gas component is introduced to the processing chamber via a pulsing operation at a gas flow rate of about 0.5 s to about 10 s, wherein the pulsing operation comprises flowing the first gas component, which comprises an etchant gas, to the processing chamber for a first period of time and stopping the flow of the etchant gas to the processing chamber for a second period of time, the pulsing operation being repeated for one or more cycles; andthe second gas component is continuously introduced to the processing chamber at a gas flow rate of about 0.2 s to about 10 s.

18. The method of claim 17, wherein the first period of time is in a range of about 0.25 s to about 10 s, and the second period of time is in a range of about 0.25 s to about 10 s.PATENTAttorney Docket No.: 44025773WO0119. The method of claim 12, wherein:the first gas component and the second gas component are introduced to the processing chamber via a pulsing operation, the pulsing operation comprising flowing the first gas component and the second gas component to the processing chamber for a first period of time in a range of about 0.25 s to about 10 s and stopping the flow of the first gas component to the processing chamber for a second period of time in a range of about 0.25 s to about 10 s, the pulsing operation being repeated for one or more cycles;the first gas component is introduced to the processing chamber at a gas flow rate of about 0.1 seem to about 100 seem; andthe second gas component is introduced to the processing chamber at a gas flow rate of about 0.1 seem to about 10 seem.

20. A method for processing a semiconductor device, the method comprising: positioning a semiconductor device in a processing volume of a processing chamber, wherein the semiconductor device comprises alternating silicon (Si) layers and silicon germanium (SiGe) layers;introducing a process gas to the processing chamber, the process gas comprising an etchant gas and a passivation gas, wherein:the etchant gas and the passivation gas are sequentially flown into the processing chamber via a pulsing operation,the pulsing operation comprising introducing the etchant gas to the processing chamber for a first time in a range of about 0.25 s to about 10 s and stopping the flow of the etchant gas to the processing chamber for a second time in a range of about 0.25 s to about 10 s, andthe pulsing operation further comprising introducing the passivation gas to the processing chamber during the second time and stopping the flow of the passivation gas to the processing chamber during the first time; and performing a selective etch operation using the process gas to remove the SiGe layers from the semiconductor device.

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