Silicon-organic hybrid modulator including insulating layer

Abstract

A modulator includes a waveguide covered with an organic electro-optic (OEO) material, transmission lines coupled between the slot waveguide and drive electrodes, and an insulating layer disposed between the transmission lines and the OEO material. A method of manufacturing a silicon-organic hybrid modulator includes forming an initial insulating layer over the transmission lines and the slot waveguide of the modulator, etching the initial insulating layer to form an insulating layer that covers the transmission lines, and forming the OEO material over the insulating layer.

Description

PATENT Attorney Docket No.: 797AA0005PCSILICON-ORGANIC HYBRID MODULATOR INCLUDING INSULATING LAYERCROSS REFERENCE TO RELATED APPLICATION

[0001] This application claims priority to U.S. Provisional Patent Application No.63 / 748,343 filed on January, 22, 2025, entitled SILICON-ORGANIC HYBRID MODULATOR INCLUDING DIELECTRIC LAYER, which is hereby incorporated by reference in its entirety.TECHNICAL FIELD

[0002] The present disclosure relates to photonic components with improved power efficiency in the fields of data communications, telecommunications, and the like. In particular, the present disclosure relates to a silicon-organic hybrid (SOH) electro-optic modulator with superior optical mode confinement and lower drive voltage, incorporation of such modulators on photonic integrated circuits (PICs), and methods of manufacture of such modulators.BACKGROUND

[0003] Electro-optic modulators convert time-varying electrical signals into time-varying optical signals, encoding parameters such as intensity, phase, and / or polarization. Modulation can be accomplished by a variety of mechanisms, including nonlinear optical effects such as the Pockels or Kerr effects, free carrier dispersion at semiconductor junctions, electroabsorption, quantum wells, etc.

[0004] In a silicon-organic hybrid (SOH) modulator, an organic electro-optic (OEO) material may be used to form a waveguide in which at least a portion of the OEO material is covered on one or both sides by silicon, and the optical-mode confinement is provided by the refractive-index contrast between the OEO material and silicon. Conventional architectures typically place doped silicon in direct contact with the OEO material. This configuration may allow for increased parasitic current during poling, potentially reducing poling efficiency, and also may result in a significant portion of the optical mode being confined in non-poled regions of the OEO material. Since the OEO material is lossier than silicon orPATENT Attorney Docket No.: 797AA0005PCsilicon dioxide at telecom wavelengths and substantially more conductive than silicon dioxide, these effects may limit modulator performance.SUMMARY

[0005] In an embodiment, a modulator includes a waveguide covered with an organic electro-optic (OEO) material, transmission lines coupled between the slot waveguide and drive electrodes, and an insulating layer disposed between the transmission lines and the OEO material.

[0006] In an embodiment, a method of manufacturing a silicon-organic hybrid modulator includes forming an initial insulating layer over the transmission lines and the slot waveguide of the modulator, etching the initial insulating layer to form an insulating layer that covers the transmission lines, and forming the OEO material over the insulating layer.

[0007] In an embodiment, a method of manufacturing a silicon-organic hybrid modulator includes forming an initial insulating layer over the transmission lines and the slot waveguide, etching the initial insulating layer until the slot waveguide and the transmission lines are exposed to form a first insulating layer, forming a second insulating layer over the transmission lines, and forming the OEO material over the second insulating layer.BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG. 1 illustrates a modulator according to an embodiment of the present disclosure.

[0009] FIG. 2 illustrates a modulator according to an embodiment of the present disclosure.

[0010] FIG. 3 illustrates a modulator according to an embodiment of the present disclosure.

[0011] FIGS. 4A and 4B illustrate modulators according to embodiments of the present disclosure.

[0012] FIG. 5 illustrates a modulator according to an embodiment of the present disclosure.

[0013] FIGS. 6A-6F illustrate a method of fabricating a modulator according to an embodiment.

[0014] FIGS. 7 A, 7B, and 7C illustrate processes of etching using an etch stop layer to form openings according to embodiments.PATENT Attorney Docket No.: 797AA0005PC

[0015] FIGS. 8A and 8B illustrate a method of fabricating a modulator according to an embodiment.

[0016] FIGS. 9A-9C illustrate a method of fabricating a modulator according to an embodiment.

[0017] FIGS. 10A and 10B illustrate a method of fabricating a modulator according to an embodiment.

[0018] FIGS. 11 A and 1 IB illustrate a conventional SOH modulator and an SOH modulator according to an embodiment of the present disclosure, respectively.

[0019] FIGS. 12A and 12B illustrate a conventional SOH modulator and an SOH modulator according to an embodiment of the present disclosure, respectively.

[0020] FIG. 13 illustrates doping profiles in the modulator of FIGS. 12A and 12B.

[0021] FIGS. 14A-14C illustrate a process of etching an initial insulating layer using multiple photolithography processes according to an embodiment of the present disclosure.DETAILED DESCRIPTION

[0022] In the following description, certain illustrative embodiments have been illustrated and described. As those skilled in the art would realize, these embodiments may be modified in various different ways without departing from the scope of the present disclosure.Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals may designate like elements in the specification.

[0023] As used herein, including in the claims, “or” as used in a list of items (e.g., a list of items prefaced by a phrase such as “at least one of’ or “one or more of’ or “one or both of’) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C).

[0024] FIG. 1 illustrates a modulator (e.g., an SOH modulator) 104 according to an embodiment of the present disclosure. The SOH modulator 104 in FIG. 1 includes a substrate 121, a slot waveguide 120, first and second transmission lines 126A and 126B, first and second electrodes 128A and 128B, an OEO material 130. and an insulating layer 112. For example, the slot waveguide 120 includes first and second waveguide rails 124 A andPATENT Attorney Docket No.: 797AA0005PC124B and a slot 122, and the insulating layer 112 includes first and second portions 112A and 112B.

[0025] The substrate 121 in FIG. 1 may include an oxide material (e.g., silicon dioxide). The first and second waveguide rails (e.g., silicon rails) 124A and 124B in FIG. 1 define the slot 122 therebetween. The transmission line 126A in FIG. 1 couples the first electrode (e.g., first driving electrode) 128A and the first waveguide rail 124 A, and the second transmission line 126B in FIG. 1 couples the second electrode (e.g., second driving electrode) 128B and the second rail 124B.

[0026] The SOH modulator 104 in FIG. 1 may function as a Pockels effect modulator, which is fabricated using conventional silicon photonics techniques and includes the OEO material 130. In the embodiment of FIG. 1, the OEO material 130 fills the slot 122. In such an embodiment, the optical mode is substantially confined in a low-index region between the first and second silicon rails 124A and 124B.

[0027] An insulating layer (e.g., a dielectric layer) may be formed between the first and second transmission lines 126 A and 126B and the OEO material 130 to cover at least the first and second transmission lines 126A and 126B. Since such an insulating layer separates the transmission lines 126A and 126B from the OEO material 130, the insulating layer may significantly reduce parasitic conductance during poling and other operations and effectively confine the optical mode inside the slot waveguide 120, thereby improving modulator performance. Throughout the specification and claims, such an insulating layer (e.g., a dielectric layer) is intentionally formed and excludes any naturally formed oxide (e.g., a native oxide) that is not intentionally fabricated and is instead formed incidentally and / or under ambient conditions upon exposure of an underlying material (e.g., silicon) to oxygen; for example, this exclusion does not apply to an oxide intentionally formed by oxidizing the underlying material (e.g., by athermal oxidation process).

[0028] In some embodiments, such an insulating layer may be disposed conformally to the transmission lines 126A and 126B and the slot waveguide 120. In some embodiments, the insulating layer may have an upper surface substantially coplanar with an upper surface of each of the rails 124A and 124B. In some embodiments, the insulating layer may have a tapered opening and covers outer sidewalls of the rails 124A and 124B. In some embodiments, the insulating layer may have a tapered opening and covers outer sidewalls andPATENT Attorney Docket No.: 797AA0005PCupper surfaces of the rails 124A and 124B. In some embodiments, the insulating layer may have a stepped opening and covers outer sidewalls of the rails 124A and 124B.

[0029] In some embodiments, the insulating layer includes at least one of SiCh, ZrCh. HfCh, AI2O3. or T1O2. In some embodiments, the insulating layer includes at least one of SisN4, silicon or nitrogen-rich silicon nitride, or silicon oxynitride.

[0030] FIG. 2 illustrates a modulator according to an embodiment of the present disclosure. For example, the modulator may be suitable for use as the modulator 104 in FIG. 1.

[0031] An insulating layer (e.g., a dielectric layer) 212 in FIG. 2 is deposited conformally to transmission lines (e.g., silicon transmission lines) 226A and 226B and waveguide rails 224 A and 224B.

[0032] Although the insulating layer 213 in the embodiment of FIG. 2 is show n as a distinct element from another insulating layer 212 including first and second portions 212A and 212B, embodiments of the present disclosure are not limited thereto. For example, the insulating layer 213 may be a third portion of the insulating layer 212 to integrally form the insulating layer 212 with the first and second portions 212A and 212B.

[0033] FIG. 3 illustrates a modulator according to an embodiment of the present disclosure. For example, the modulator may be suitable for use as the modulator 104 in FIG. 1.

[0034] An insulating layer (e.g., a dielectric layer) 312 in FIG. 3 may cover transmission lines 326A and 326B and outer sidewalls of w aveguide rails 324A and 324B, such that an upper surface of the dielectric layer 312 is substantially coplanar with an upper surface of the waveguide rails 324A and 324B. For example, a first portion 312A has a protruding portion from a first inner sidewall of the dielectric layer 312 with an upper surface (e.g., a top surface) that is substantially coplanar with the upper surface of the waveguide rail 324A, and a second portion 312B has a protruding portion from a second inner sidewall of the dielectric layer 312 with an upper surface (e.g., a top surface) that is substantially coplanar with the upper surface of the second waveguide rail 324B.

[0035] FIGS. 4A and 4B illustrate modulators according to embodiments of the present disclosure. For example, these modulators may be suitable for use as the modulator 104 in FIG. 1.PATENT Attorney Docket No.: 797AA0005PC

[0036] The modulator includes an insulating layer (e.g., a dielectric layer) between first and second transmission lines 426A and 426B and an OEO material 430. Such a dielectric layer may be formed to cover transmission lines 426A and 426B of the modulator and at least outer sidewalls of waveguide rails 424A and 424B of the modulator.

[0037] In some embodiments, the dielectric layer 412 disposed over the transmission lines 426A and 426B is tapered towards a slot waveguide including the rails 424A and 424B, with a range of geometries possible depending on particular combinations of etching and deposition processes. Specifically, the dielectric layer (e.g., SiCh layer) 412 in FIGS. 4A and 4B includes a tapered opening. For example, the dielectric layer 412 including first and second portions 412A1 and 412B1 in the embodiment of FIG. 4A covers the transmission lines 426A and 426B, the outer sidewalls of the rails 424A and 424B, and top surfaces of the rails 424A and 424B. The dielectric layer 412 including first and second portions 412A2 and 412B2 in the embodiment of FIG. 4B covers the transmission lines 426A and 426B and the outer sidewalls of the rails 424A and 424B. In some embodiments, the dielectric layer 412 may cover the transmission lines 426A and 426B, the outer sidewalls of the rails 424A and 424B, and portions of top surfaces of the rails 424A and 424B. Although the embodiments shown in FIGS. 4A and 4B each include the tapered opening with a substantially straight profile, embodiments of the present disclosure are not limited thereto. For example, the tapered opening may have a curved profile (e.g., a concave profile).

[0038] FIG. 5 illustrates a modulator according to an embodiment of the present disclosure. For example, the modulator may be suitable for use as the modulator 104 in FIG. 1.

[0039] In some embodiments, an insulating layer (e.g., a dielectric layer) disposed over transmission lines 526A and 526B is stepped towards a slot waveguide including waveguide rails 524A and 524B. For example, a dielectric layer (e.g., SiCh layer) 512 in FIG. 5 includes a stepped opening and the dielectric layer 512 covers the transmission lines 526A and 526B and outer sidewalls of the rails 524A and 524B. Although the embodiment in FIG. 5 shows the opening with two steps, embodiments of the present disclosure are not limited thereto. In other embodiments, the number of steps in the stepped opening may vary according to embodiments.

[0040] FIGS. 6A-6F illustrate a method of fabricating a modulator according to an embodiment. Such a method may be suitable for making the modulator shown in FIG. 3.PATENT Attorney Docket No.: 797AA0005PC

[0041] Referring to FIG. 6A, the method includes forming (e.g., depositing) an initial insulating layer (e.g., initial dielectric layer) 6121 over transmission lines 626A and 626B and waveguide rails 624A and 624B. Referring to FIGS. 6B and 6C, the method further includes forming a photoresist (PR) layer 607 and patterning the PR layer 607 to form a PR pattern that exposes a top surface of the initial dielectric layer 6121 using photolithography. In other embodiments, such a PR pattern may be formed using imprint lithography, direct-write lithography, or other suitable patterning techniques. In some embodiments, a hard mask (not shown) may be disposed between the PR layer 607 and the initial insulating layer 6121 to tolerate a relatively long etch process for the initial dielectric layer 6121.

[0042] The method further includes etching the initial dielectric layer 6121 to form a dielectric layer 612 covering the transmission lines 626A and 626B. For example, referring to FIGS. 6D and 6E, the etching is performed to form an opening OP to leave portions of the initial dielectric layer 6121 covering the transmission lines 626A and 626B and expose upper surfaces (e.g., top surfaces) and inner sidewalls of the rails 624A and 624B. As a result, a dielectric layer 612 including first and second portions 612A and 612B is formed, and then the PR pattern is removed.

[0043] Although the method according to the embodiment shown in FIGS. 6A-6F includes a single photolithography process, embodiments of the present disclosure are not limited thereto. In some embodiments, one or more additional photolithography processes may be performed to form the structure shown in FIG. 6E. For example, FIGS. 14A-14C illustrate a process of etching an initial insulating layer (e g., an initial dielectric layer) 14121 using multiple photolithography processes. Referring to FIG. 14A. an initial opening OP’ may be formed by removing a portion of the initial dielectric layer 14121 using a first PR pattern PR1, and then a second PR pattern PR2 may be formed in the opening OP’. Referring to FIG. 14B, the initial dielectric layer 14121 may be etched using the second PR pattern PR2, the second PR pattern PR2 may be removed, and then the initial dielectric layer 14121 may be further etched to form an intermediate opening OP”. Referring to FIG. 14C, the initial dielectric layer 14121 may be further etched to form an opening OP and an insulating layer (e.g., a dielectric layer) 1412 including first and second portions 1412A and 1412B.PATENT Attorney Docket No.: 797AA0005PC

[0044] In some embodiments, the etch profile is controlled by varying the anisotropy of the etch, including ratio of physical and chemical contributions to the etch. In some embodiments, an etch process using fluorine-containing species is used.

[0045] In some embodiments, one or more etch stop layers are used to control the etch rate and profile, as will be described below. For example, FIGS. 7A and 7B illustrate a process of etching using an etch stop layer 731 to form an opening OP1 (e.g., the opening OP in FIG. 6E) according to an embodiment, and FIGS. 7 A and 7C illustrate a process of etching using an etch stop layer 731 to form an opening OP2 according to an embodiment.

[0046] Referring to FIG. 7A, the etch stop layer 731 is provided over the first and second transmission lines 726A and 726B. In some embodiments, the etch stop layer 731 may be provided over the first and second transmission lines 726A and 726B and the waveguide rails 724A and 724B to further extend over the rails 724A and 724B. A first etch process may be performed to remove a portion of an initial insulating layer 7121 and expose the etch stop layer 731. Subsequently, a second etch process may be formed to leave portions of the initial dielectric layer 7121 covering the transmission lines 726A and 726B and expose the rails (e.g., upper surfaces and inner sidewalls of the rails) 724A and 724B, thereby forming an opening OP1 in FIG. 7B. The first etch process may be faster, more anisotropic, and less selective (e.g., Si: SiCh selectivity) than the second etch process. For example, the first etch process may be a fluorocarbon-based plasma etch process, and the second etch process may be a wet etch process.

[0047] The etch stop layer 731 in FIG. 7A includes a first portion 731 A and a second portion 73 IB that overlap first transmission line 726A and second transmission line 726B, respectively, in a plan view. For example, an inner edge of the first portion 731 A of the etch stop layer 731 may be substantially aligned with an outer sidewall of a first waveguide rail 724A, and an inner edge of the second portion 73 IB of the etch stop layer 731 may be substantially aligned with an outer sidewall of a second waveguide rail 724B. In some embodiments, a width (e.g., a length in the horizontal direction of FIG. 7 A) of each of the first and second portions 731 A and 73 IB is sufficient to substantially prevent the transmission line 726A or 726B from being etched in the etch processes. Since the transmission lines 726A and 726B are not exposed to the etch processes, more precise control of conductance of the transmission lines 726A and 726B may be possible, and the requiredPATENT Attorney Docket No.: 797AA0005PCetch selectivity may be reduced. For example, the etch stop layer 732 may include SiN, TiN, or Al.

[0048] Although the upper surface of the first portion 712A and the upper surface of the second portion 712B of the dielectric layer 712 are substantially coplanar with the upper surface of the waveguide rails 724A and 724B in the embodiment of FIG. 7B, respectively, embodiments of the present disclosure are not limited thereto. For example, referring to FIG.7C, the upper surface of the first portion 712A and the upper surface of the second portion 712B of the dielectric layer 712 may be inclined with respect to the upper surface of the first waveguide rail 724 A and the upper surface of the second waveguide rail 724B, respectively, thereby forming an opening OP2. Although though the embodiment shown in FIGS. 7A-7C a process of etching using the etch stop layer 731, embodiments of the present disclosure are not limited thereto. For example, the initial dielectric layer 731 may be etched without using the etch stop layer 731 until the rails 724A and 724B and the transmission lines 726A and 726B are exposed.

[0049] Referring back to FIG. 6F, the method further includes forming an OEO material 630 over the dielectric layer 612. For example, referring to FIG. 6F, the OEO material 630 is formed to fill a slot between the inner sidewalls of the rails 624A and 624B and the opening OP of the dielectnc layer 612.

[0050] FIGS. 8A and 8B illustrate a method of fabricating a modulator according to an embodiment. Such a method may be suitable for making the modulator shown in FIG. 2, which includes a dielectric layer deposited conformally to transmission lines and waveguide rails.

[0051] The method according to the embodiment in FIGS. 8A and 8B includes some of the above-described processes shown in FIGS. 6A-6F, which may be omitted in the interest of brevity. The method further includes etching an initial dielectric layer until a slot waveguide including waveguide rails 824A and 824B and transmission lines 826A and 826B are exposed to form first and second portions 812A and 812B of an insulating layer (e.g., a dielectric layer) 812. For example, referring to FIG. 8 A, the etching is performed to expose outer sidewalls, upper surfaces, and inner sidewalls of the rails 824A and 824B in the slot waveguide and upper surfaces of the transmission lines 826A and 826B. In an embodiment, the etching process uses a material of the transmission lines 826A and 826B as an etch stop.PATENT Attorney Docket No.: 797AA0005PC

[0052] The method further includes forming an insulating layer (e.g., a dielectric layer) 813 over the transmission lines 826A and 826B. For example, referring to FIG. 8A, the dielectric layer 813 is deposited conformally to the rails 824A and 824B, a slot 822 between the rails 824A and 824B, and the transmission lines 826A and 826B. The method further includes forming an OEO material 830 over the dielectric layer 813. For example, referring to FIG.8B, the OEO material 830 is formed to fill the remaining space in the slot 822 between the inner sidewalls of the rails 824A and 824B and in an opening OP’ of the dielectric layer 812.

[0052] In some embodiments, the above-described etching process includes at least one of plasma etching, wet etching, or vapor etching. In some embodiments, the above-described deposition process includes atomic layer deposition (ALD).

[0053] FIGS. 9A-9C illustrate a method of fabricating a modulator according to an embodiment. Such a method may be suitable for making the modulator shown in FIG. 4A, which includes a dielectric layer with a tapered opening.

[0054] The method includes some of the above-described processes shown in FIGS. 6A-6F, which may be omitted in the interest of brevity. The method further includes etching an initial dielectric layer to form an insulating layer (e.g., a dielectric layer) covering transmission lines and rails. For example, referring to FIGS. 9A and 9B, the etching is performed using the PR pattern to form a dielectric layer 912 having a tapered opening TO and expose inner sidewalls of rails 924A and 924B, and then the PR pattern is removed.

[0055] The method further includes forming an OEO material 930 over the dielectric layer 912. For example, referring to FIGS. 9B and 9C, an OEO material 930 is deposited to fill a slot 922 between the inner sidewalls of the rails 924A and 924B and the tapered opening TO of the dielectric layer 912.

[0056] FIGS. 10A and 10B illustrate a method of fabricating a modulator according to an embodiment. Such a method may be suitable for making the modulator shown in FIG. 5, which includes a dielectric layer including a stepped opening.

[0057] The method includes an etch process using a plurality of etch stop layers. For example, FIGS. 10A and 10B illustrate an etch process using first and second etch stop layers 1033 and 1035 to form a stepped opening SO according to an embodiment.PATENT Attorney Docket No.: 797AA0005PC

[0058] Referring to FIG. 10A, the first etch stop layer 1033 including first and second portions 1033A and 1033B is provided over first and second transmission lines 1026A and 1026B. and the second etch stop layer 1035 including the first and second portion 1035 A and 1035B is provided between the first etch stop layer 1033 and the transmission lines 1026A and 1026B. A first etch process may be formed to remove a portion of an initial insulating layer 10121 and expose the first and second etch stop layer 1033 and 1035. Subsequently, a second etch process may be formed to form a stepped opening SO to leave portions of the initial dielectric layer 10121 covering the transmission lines 1026A and 1026B and expose the rails (e.g., upper surfaces and inner sidewalls of the rails) 1024A and 1024B. The first etch process may be faster, more anisotropic, and less selective (e.g., Si:SiCh selectivity) than the second etch process. For example, the first etch process may be a fluorocarbon-based plasma etch process, and the second etch process may be a wet etch process.

[0059] The first etch stop layer 1033 in FIG. 10A includes the first portion 1033 A and the second portion 1033B that overlap the first transmission line 1026A and the second transmission line 1026B, respectively, in a plan view. The second etch stop layer 1035 in FIG. 10A includes the first portion 1035A that overlaps the first waveguide rail 1024A and the first transmission line 1026 A, and the second portion 1035B that overlaps the second waveguide rail 1024B and the second transmission line 1026B, in a plan view. The first and second etch stop layers 1033 and 1035 may substantially prevent the transmission lines 1026A and 1026B from being exposed to the etch processes. As a result, more precise control of conductance of the transmission lines 1026A and 1026B may be possible, and the required etch selectivity may be reduced. For example, each of the first and second etch stop layers 1033 and 1035 may include SiN, TiN, or Al. In some embodiments, the first etch stop layer 1033, the second etch stop layer 1035, or both may be at least partially removed in the first etch process. For example, when each of the first etch stop layer 1033 and the second etch stop layer 1035 includes SiN or TiN, the first and second etch stop layers 1033 and 1035 may be at least partially removed using a fluorocarbon-based plasma etch process. When each of the first etch stop layer 1033 and the second etch stop layer 1035 includes Al (e.g., AI2O3), the first and second etch stop layers 1033 and 1035 may be at least partially removed using a chlorine-based plasma etch process. In some embodiments, the first etch stop layer 1033, the second etch stop layer 1035, or both may be at least partially removed in an additional etch process.PATENT Attorney Docket No.: 797AA0005PC

[0060] FIGS. 11 A and 1 IB illustrate a conventional SOH modulator and an SOH modulator according to an embodiment of the present disclosure, respectively. These modulators each include the JRD1 OEO material, a 150 nm wide slot waveguide with 220 nm wide silicon rails, a 220 nm device layer thickness, and a 70 nm transmission line height, and operate at 1550 nm.

[0061] Table 1 (below) includes finite difference eigenmode (FDE) calculations obtained for the conventional SOH modulator shown in FIG. 11 A and the modulator according to the embodiment shown in FIG. 1 IB. Compared to the conventional SOH modulator, the FDE calculations predict a 20% improvement to VnL, a 15% increase in optical loss (a), and a net 7% improvement in loss-efficiency product (aV.-L) in the embodiment of FIG. 11 B including a silicon dioxide layer over the transmission lines and the rails. Without wishing to be bound by theory, the improvement in performance may be primarily due to improvements in the optical mode confinement parameter E.

[0062] Table 1. FDE simulation results

[0063] FIGS. 12A and 12B illustrate a conventional SOH modulator and an SOH modulator according to an embodiment of the present disclosure, respectively. FIG. 13 illustrates doping profiles in the modulator of FIGS. 12A and 12B.

[0064] Table 2 (below) includes finite element (FEM) thermal and electrical conductivity¬ calculations obtained for the conventional SOH modulator shown in FIG. 12A and the embodiment shown in FIG. 12B. Compared to the conventional SOH modulator, FEM thermal and electrical conductivity calculations for the embodiment in FIG. 12B predict a significant reduction in parasitic current at 150°C. where 150°C is the maximum expected poling temperature for crosslinkable materials such as HLD.PATENT Attorney Docket No.: 797AA0005PC

[0065] Table 2. FEM simulation results

[0066] As shown in Table 2, treating the OEO material as a lossy dielectric with a conductivity of 4E-6 S / m at 150°C and using doping levels of 1E18 cm'3(n), 1E19 cm'3(n+), and 1E20 cm'3(n++), with standoff distances from the slot edge of 0.5 m (n+) and 1 pm (n++), as shown in FIG. 13, resistance in the absence of any OEO material or oxide was predicted to be 3.79 GO. When sufficient OEO material to overcoat the device layer by 1 pm of OEO is added, resistance is predicted to decrease to 1.85 GQ. However, a 150 nm thick silicon dioxide layer over the doped transmission lines is predicted to increase resistance to 5.85 GQ in the presence of the same 1 um of OEO material. This represents a ~3x reduction in leakthrough current, increasing the poling field that can be realized during processing and reducing probability of shorting. Similar or greater current reduction could also be achieved with a relatively thin (e.g., 5 nm) conformal layer of ZrO2. Slot waveguide geometries, doping levels, different oxides, etch or deposition profiles, or combinations thereof, may vary according to embodiments.

[0067] Al. An embodiment of the present disclosure includes a silicon-organic hybrid modulator, comprising:a slot waveguide filled with an organic electro-optic (OEO) material; transmission lines coupled between the slot waveguide and drive electrodes; and a dielectric material covering the transmission lines.

[0068] A2. The modulator of Al, wherein the dielectric material is disposed conformally to the transmission lines and the slot waveguide.PATENT Attorney Docket No.: 797AA0005PC

[0069] A3. The modulator of Al, wherein the slot waveguide includes a pair of rails and a slot formed between the rails, and the dielectric material has an upper surface substantially coplanar with an upper surface of each of the rails.

[0070] A4. The modulator of Al, wherein the slot waveguide includes a pair of rails and a slot formed between the rails, and the dielectric material has an opening filled with the OEO material .

[0071] A5. The modulator of A4, wherein the opening of the dielectric material is a tapered opening, and the dielectric material further covers outer sidewalls of the rails.

[0072] A6. The modulator of A5, wherein the dielectric material further covers upper surfaces of the rails.

[0073] A7. The modulator of A7, wherein the opening of the dielectric material is a stepped opening, and the dielectric material further covers outer sidewalls of the rails.

[0074] A8. The modulator of Al, wherein modulation efficiency (VuL) of the modulator is less than about 1 V-mm (e.g., 0.95 to 1.04 V-mm).

[0075] A9. The modulator of Al, wherein a 3 dB bandwidth of the modulator is greater than about 40 GHz (e.g., 39.5 to 40.5 GHz).

[0076] A10. The modulator of Al, wherein the dielectric material is silicon dioxide (SiCh).

[0077] Al 1. The modulator of Al, wherein the dielectric material is at least one of SiCh, ZrCh, HfCh, AI2O3, TiCh, or a combination thereof.

[0078] Al 2. The modulator of Al, wherein the dielectric material is at least one of SisN-i. silicon or nitrogen-rich silicon nitride, silicon oxynitride, or a combination thereof.

[0079] A13. The modulator of Al, wherein the dielectric material includes ZrCh, HfCh, AI2O3, TiCh, or a combination thereof

[0080] A14. The modulator of Al, wherein the dielectric material includes nitride.PATENT Attorney Docket No.: 797AA0005PC

[0081] Al 5. The modulator of A5, wherein the dielectric material is tapered between an outer edge of each of the rails and an edge of an upper surface (e.g., a top surface) of the dielectric material.

[0082] Al 6. The modulator of A6, wherein the dielectric material is tapered between an inner edge of each of the rails and an edge of an upper surface (e.g., a top surface) of the dielectric material.

[0083] A17. The modulator of Al, wherein the OEO material is thermally crosslinkable.

[0084] Al 8. The modulator of Al, wherein the OEO material is HLD.

[0085] Al 9. A photonic integrated circuit comprising one or more modulators that include the modulator of Al.

[0086] A20. An embodiment of the present disclosure includes a method of manufacturing a silicon-organic hybrid modulator, wherein the modulator includes a slot waveguide filled with an organic electro-optic (OEO) material and transmission lines couped to the slot waveguide, the method comprising:forming an initial dielectric layer over the transmission lines and the slot waveguide of the modulator;etching the initial dielectric layer to form a dielectric layer covering the transmission lines; andforming the OEO material over the dielectnc layer.

[0087] A21. The method of A20, wherein etching the initial dielectric layer includes one or more plasma etch processes.

[0088] A22. An embodiment of the present disclosure includes a method of manufacturing a silicon-organic hybrid modulator, wherein the modulator includes a slot waveguide filled with an organic electro-optic (OEO) material and transmission lines couped to the slot waveguide, the method comprising:forming an initial dielectric layer over the transmission lines and the slot waveguide of the modulator;etching the initial dielectric layer until the slot waveguide and the transmission lines are exposed;PATENT Attorney Docket No.: 797AA0005PCforming a dielectric layer over the transmission lines; andforming the OEO material over the dielectric layer.

[0089] A23. The method of A22, wherein the dielectric layer is conformally deposited to the exposed transmission lines and the slot waveguide using one or more atomic layer deposition processes.

[0090] The description herein is provided to enable a person having or inary skill in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to a person having ordinary' skill in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not limited to the embodiments and designs described herein but is to be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

PATENT Attorney Docket No.: 797AA0005PCWHAT IS CLAIMED IS:

1. A modulator, comprising:a waveguide covered with an organic electro-optic (OEO) material; transmission lines coupled between the waveguide and drive electrodes; and an insulating layer disposed between the transmission lines and the OEO material.

2. The modulator of claim 1, wherein the insulating layer is disposed conformally to the transmission lines and the waveguide.

3. The modulator of claim 1, wherein the waveguide is a slot waveguide including a pair of rails and a slot formed between the rails, and the insulating layer has an opening filled with the OEO material.

4. The modulator of claim 3, wherein the insulating layer has an upper surface substantially coplanar with an upper surface of each of the rails.

5. The modulator of claim 3, wherein the opening of the insulating layer is a tapered opening, and the insulating layer covers outer sidewalls of the rails.

6. The modulator of claim 5, wherein the insulating layer further covers upper surfaces of the rails.

7. The modulator of claim 3, wherein the opening of the dielectric material is a stepped opening, and the insulating layer covers outer sidewalls of the rails.

8. The modulator of claim 1, wherein modulation efficiency (VnL) of the modulator is less than about 1 V-mm.9 The modulator of claim 1, wherein a 3 dB bandwidth of the modulator is greater than about 40 GHz.

10. The modulator of claim 1, wherein the insulating layer includes at least one of SiO2, ZrO2, HfO2, A12O3, or TIO2.PATENT Attorney Docket No.: 797AA0005PC11. The modulator of claim 1, wherein the insulating layer includes at least one of SisN4, silicon or nitrogen-rich silicon nitride, or silicon oxynitride.

12. A photonic integrated circuit comprising one or more modulators that include the modulator of claim 1.

13. A method of manufacturing a silicon-organic hybrid modulator, wherein the modulator includes first and second transmission lines and a slot waveguide covered with an organic electro-optic (OEO) material, the first and second transmission lines coupling first and second electrodes to the slot waveguide, the slot waveguide including a pair of rails and a slot formed between the rails, the method comprising:forming an initial insulating layer over the transmission lines and the slot waveguide of the modulator;etching the initial insulating layer to form an insulating layer that covers the transmission lines; andforming the OEO material over the insulating layer.

14. The method of claim 13, further comprising:providing an etch stop layer over the first and second transmission lines; wherein etching the initial insulating layer comprises:performing a first etch process to remove a portion of the initial insulating layer and expose the etch stop layer; andperforming a second etch process to leave portions of the initial insulating layer covering the first and second transmission lines and expose the rails.

15. The method of claim 14, wherein the etch stop layer includes at least one of SiN, TiN, or Al.

16. The method of claim 14, wherein the etch stop layer is further provided to extend over the rails.

17. The method of claim 13, further comprising:providing a first etch stop layer over the first and second transmission lines; andPATENT Attorney Docket No.: 797AA0005PCproviding a second etch stop layer between the first etch stop layer and the transmission lines;wherein etching the initial insulating layer comprises:performing a first etch process to remove a portion of the initial insulating layer and expose the first and second etch stop layers; andperforming a second etch process to leave portions of the initial insulating layer covering the first and second transmission lines and expose the rails.

18. The method of claim 13, wherein etching the initial insulating layer is performed to form the insulating layer having a tapered opening and expose inner sidewalls of the rails.

19. A method of manufacturing a silicon-organic hybrid modulator, wherein the modulator includes a slot waveguide covered with an organic electro-optic (OEO) material and transmission lines couped to the slot waveguide, the method comprising:forming an initial insulating layer over the transmission lines and the slot waveguide: etching the initial insulating layer until the slot waveguide and the transmission lines are exposed to form a first insulating layer;forming a second insulating layer over the transmission lines; andforming the OEO material over the second insulating layer.

20. The method of claim 19, wherein the second insulating layer is conformally deposited to the transmission lines and the slot waveguide using one or more atomic layer deposition processes.

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