Pulsed voltage source with multiple stages for plasma processing applications

Abstract

Embodiments of the disclosure include an apparatus and method of generating a voltage waveform by generating an output voltage at a common node. The method generally includes (i) generating a first pulse at a first voltage at the common node at a first time based on a first transformer ratio of a first transformer included in a first voltage stage, (ii) generating a second pulse at a second voltage at the common node at the first time based on a second transformer ratio of a second transformer included in a second voltage stage, and (iii) generating a third pulse at a third voltage at the common node at the first time based on a third transformer ratio of a third transformer included in a third voltage stage.

Description

PATENTAttorney Docket No.: 44024475WO01PULSED VOLTAGE SOURCE WITH MULTIPLE STAGES FOR PLASMA PROCESSING APPLICATIONS BACKGROUNDField

[0001] Embodiments of the present disclosure generally relate to a system used in semiconductor device manufacturing. More specifically, embodiments of the present disclosure relate to a plasma processing system used to process a substrate.Description of the Related Art

[0002] Reliably producing high aspect ratio features is one of the key technology challenges for the next generation of semiconductor devices. One method of forming high aspect ratio features uses a plasma-assisted etching process to bombard a material formed on a surface of a substrate through openings formed in a patterned mask layer formed on the substrate surface.

[0003] With technology node advancing towards 2nm, the fabrication of smaller features with larger aspect ratios requires atomic precision for plasma processing. For etching processes where the plasma ions play a major role, ion energy control is always challenging the semiconductor equipment industry. In a typical plasma-assisted etching process, the substrate is positioned on an electrostatic chuck (ESC) disposed in a processing chamber, a plasma is formed over the substrate, and ions are accelerated from the plasma towards the substrate across a plasma sheath, i.e. , region depleted of electrons, formed between the plasma and the surface of the substrate. Traditionally radio frequency (RF) substrate biasing methods, which use sinusoidal RF waveforms to excite the plasma and form the plasma sheath, have been unable to desirably form these smaller device feature sizes. Recently, it has been found that utilizing pulsed plasma sources to deliver high voltage direct current (DC) pulses to one or more electrodes within a processing chamber can be useful in desirably controlling the plasma sheath formed over the surface of the substrate.

[0004] Traditionally, pulsed power sources provide pulsed DC bias to a cathode, a metal plate known that can be coupled to the plasma using capacitive coupling through a dielectric layer. Switching frequency, and power dissipation capability are some of the major design considerations while designing such pulsed power sources. ToPATENTAttorney Docket No.: 44024475WO01facilitate high switching speed, metal-oxide-sem iconductor field-effect transistors (MOSFETs) are predominantly used in the pulsed power sources. However, the significant progress in the field of SiC and GaN MOSFETs notwithstanding, the maximum operating switching frequency of these MOSFETs is limited to tens of kHz to a few hundred kHz. As the device dimensions shrink under 10nm in the semiconductor industry, pulsed DC bias sources with a switching frequency in the upper half of the hundreds of kHz range could be a tremendous tool to further control critical high aspect ratio features like etch selectivity and uniformity.

[0005] Accordingly, there is a need in the art for pulsed voltage source and biasing methods that are able to enable the completion of a desirable plasma-assisted process on a substrate.SUMMARY

[0006] To the accomplishment of the foregoing and related ends, the one or more aspects comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the appended drawings set forth in detail certain illustrative features of the one or more aspects. These features are indicative, however, of but a few of the various ways in which the principles of various aspects may be employed.

[0007] Embodiments provided herein generally include apparatus, e.g., plasma processing systems, and methods for the plasma processing of a substrate in a processing chamber.

[0008] Embodiments of the present disclosure are directed to a method of generating a voltage waveform. The method generally includes generating an output voltage at a common node, which includes ( / ') generating a first pulse at a first voltage at the common node at a first time based on a first transformer ratio of a first transformer included in a first voltage stage, ( / ' / ) generating a second pulse at a second voltage at the common node at the first time based on a second transformer ratio of a second transformer included in a second voltage stage, and (7 / 7) generating a third pulse at a third voltage at the common node at the first time based on a third transformer ratio of a third transformer included in a third voltage stage, where a secondary winding of the first transformer, a secondary winding of the secondPATENTAttorney Docket No.: 44024475WO01transformer, and a secondary winding of the third transformer are coupled in series between a reference potential node and the common node, and where the output voltage includes the first voltage, the second voltage, and the third voltage.

[0009] Embodiments of the present disclosure provide a power supply circuit. The power supply circuit generally includes a first group of voltage stages configured to generate a first pulse at a first voltage at a common node during a first time period, a second group of voltage stages configured to generate a second pulse at a second voltage at the common node during a second time period, where the second voltage is a fraction of the first voltage, a third group of voltage stages configured to generate a third pulse at a third voltage at the common node during a third time period, and a fourth group of voltage stages configured to generate a fourth pulse at a fourth voltage at the common node during a fourth time period.

[0010] Embodiments of the present disclosure provide a power supply circuit. The power supply circuit generally includes a first voltage stage, a second voltage stage, a third voltage stage, memory, and a processor coupled to the memory. The processor may generally be configured to perform a method for generating a waveform. The method generally includes generating a output voltage at a common node coupled to the first voltage stage, the second voltage stage, and the third voltage stage, including: ( / ) generating a first pulse at a first voltage at the common node during a first time period based on a first transformer ratio of a first transformer included in the first voltage stage, ( / / ') generating a second pulse at a second voltage at the common node during the first time period based on a second transformer ratio of a second transformer included in the second voltage stage, and (7 / 7) generating a third pulse at a third voltage at the common node during the first time period based on a third transformer ratio of a third transformer included in the third voltage stage, where a secondary winding of the first transformer, a secondary winding of the second transformer, and a secondary winding of the third transformer are coupled in series between a reference potential node and the common node, and where the output voltage includes the first voltage, the second voltage, and the third voltage.PATENTAttorney Docket No.: 44024475WO01BRIEF DESCRIPTION OF THE DRAWINGS

[0011] So that the manner in which the above -recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of its scope and may admit to other equally effective embodiments.

[0012] Figure 1 is a schematic cross-sectional view of a processing system, in which embodiments of the present disclosure may be implemented.

[0013] Figure 2 illustrates stray capacitance and substrate support capacitance associated with a processing chamber, in accordance with certain embodiments of the present disclosure.

[0014] Figure 3 illustrates an example voltage waveform that can be provided during plasma processing, in accordance with certain embodiments of the present disclosure.

[0015] Figure 4 illustrates a schematic view of a pulser, in accordance with certain embodiments of the present disclosure.

[0016] Figure 5 illustrates a charging circuit used to charge a capacitive element, in accordance with certain aspects of the present disclosure.

[0017] Figure 6 illustrates a schematic view of a voltage stage of a pulser that includes multiple voltage sources, in accordance with certain embodiments of the present disclosure.

[0018] Figure 7 is a process flow diagram illustrating a method of waveform generation, in accordance with certain embodiments of the present disclosure.

[0019] Figures 8A-8E illustrate example output voltages over time that can be provided during plasma processing, in accordance with certain embodiments of the present disclosure.PATENTAttorney Docket No.: 44024475WO01

[0020] Figure 9 illustrates a schematic view of a 16 stage pulser, in accordance with certain embodiments of the present disclosure.

[0021] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.DETAILED DESCRIPTION

[0022] Certain embodiments of the present disclosure are generally directed to techniques and apparatus for generating a voltage waveform for a plasma processing system. Generating the voltage waveform may involve using a pulsed power source (e.g., a waveform generator or pulser) that includes a plurality of stacked voltage stages (e.g., modules) to generate an output voltage at a common node of the pulsed power source. The use of multiple stacked voltage stages enables greater flexibility for producing voltage waveforms with desired characteristics and allows for the production of voltage waveforms with a desired energy distribution function (IEDF) at the surface of a substrate included in the plasma processing system.

[0023] In some embodiments, each of the voltage stages in a pulsed power source may be configured to generate pulses at the same voltage level. However, in these embodiments, the pulsed power source may be capable of using a limited number of combinations of voltage stages included in the pulsed power source to generate a narrow number of voltage set points. In addition, the pulsed power source may be unable to achieve a high resolution when generating the voltage set points.

[0024] Embodiments described herein are directed to a pulsed power source where each individual voltage stage included in the pulsed power source, or in some embodiments, various groups of voltage stages included in the pulsed power source, are configured to generate pulses at different voltage levels, based on the voltage source and the transformer ratio of each voltage stage. In this manner, a greater number of combinations of the voltage stages included in the pulsed power source may be used to reliably generate the output voltage at a wider range of voltage set points. Furthermore, the pulsed power source may be capable of achieving higherPATENTAttorney Docket No.: 44024475WO01resolution (e.g., more accurately generate the voltage set points), especially when generating low output voltages.Plasma Processing System Examples

[0025] Figure 1 is a schematic cross-sectional view of a processing system 10, in which embodiments of the present disclosure may be implemented. In some embodiments, the processing system 10 may be configured for plasma-assisted etching processes, such as a reactive ion etch (RIE) plasma processing. However, it should be noted that the embodiments described herein may be also be used with processing systems configured for use in other plasma-assisted processes, such as plasma-enhanced deposition processes such as, for example, plasma-enhanced chemical vapor deposition (PECVD) processes, plasma-enhanced physical vapor deposition (PEPVD) processes, plasma-enhanced atomic layer deposition (PEALD) processes, plasma treatment processing or plasma-based ion implant processing (e.g., plasma doping (PLAD) processing).

[0026] As shown, the processing system 10 is configured to form a capacitively coupled plasma (CCP) and includes a processing chamber 100. The processing chamber 100 includes an upper electrode (e.g., chamber lid 123) disposed in a processing volume 129 facing a lower electrode (e.g., the substrate support assembly 136) also disposed in the processing volume 129. In a typical CCP processing system, a radio frequency (RF) source (e.g., RF generator 118) is electrically coupled to one of the upper or lower electrode, and delivers an RF signal configured to ignite and maintain a plasma (e.g., the plasma 101). In this configuration, the plasma is capacitively coupled to each of the upper and lower electrodes and is disposed in a processing region therebetween. Typically, the opposing one of the upper or lower electrodes is coupled to ground or to a second RF power source. One or more components of a substrate support assembly 136, such as the support base 107, may be electrically coupled to a plasma generator assembly 163, which includes the RF generator 118. The chamber lid 123 may be electrically coupled to ground. As shown, the processing system 10 includes the processing chamber 100, the substrate support assembly 136, and a system controller 126.PATENTAttorney Docket No.: 44024475WO01

[0027] The processing chamber 100 typically includes a chamber body 113 that includes the chamber lid 123, one or more sidewalls 122, and a chamber base 124, which collectively define the processing volume 129. In some cases, the processing chamber 100 may include opposing walls 132, as illustrated. The one or more sidewalls 122 and chamber base 124 generally include materials that are sized and shaped to form the structural support for the elements of the processing chamber 100 and are configured to withstand the pressures and added energy applied to them while a plasma 101 is generated within a vacuum environment maintained in the processing volume 129 of the processing chamber 100 during processing. In one example, the one or more sidewalls 122 and chamber base 124 are formed from a metal, such as aluminum, an aluminum alloy, or a stainless steel alloy.

[0028] A gas inlet 128 disposed through the chamber lid 123 is used to deliver one or more processing gases to the processing volume 129 from a processing gas source 119 that is in fluid communication therewith. A substrate 103 is loaded into, and removed from, the processing volume 129 through an opening (not shown) in one of the one or more sidewalls 122, which is sealed with a slit valve (not shown) during plasma processing of the substrate 103.

[0029] The system controller 126, also referred to herein as a processing chamber controller, includes a central processing unit (CPU) 133, a memory 134, and support circuits 135. The system controller 126 is used to control the process sequence used to process the substrate 103, including the substrate biasing methods described herein. The CPU 133 is a general-purpose computer processor configured for use in an industrial setting for controlling the processing chamber and sub-processors related thereto. The memory 134 described herein, which is generally non-volatile memory, may include random access memory, read-only memory, floppy or hard disk drive, or other suitable forms of digital storage, local or remote. The support circuits 135 are conventionally coupled to the CPU 133 and comprise cache, clock circuits, input / output subsystems, power supplies, and the like, and combinations thereof. Software instructions (program) and data can be coded and stored within the memory 134 for instructing one or more processors within the CPU 133. A software program (or computer instructions) readable by CPU 133 in the system controller 126PATENTAttorney Docket No.: 44024475WO01determines which tasks are performable by the components in the processing system 10.

[0030] Typically, the program, which is readable by CPU 133 in the system controller 126, includes code, which, when executed by one or more processors (e.g., included in the CPU 133) individually or collectively, performs tasks relating to the plasma processing schemes described herein. The program may include instructions that are used to control the various hardware and electrical components within the processing system 10 to perform the various process tasks and various process sequences used to implement the methods described herein. In one embodiment, the program includes instructions that are used to perform one or more of the operations described below in relation to Figure 7.

[0031] The processing system may include a plasma generator assembly 163, a first pulsed voltage (PV) source assembly 196 for establishing a first PV waveform at a bias electrode 104, and a second PV source assembly 197 for establishing a second PV waveform at an edge control electrode 115. The first PV waveform or the second PV waveform may be generated using a waveform generator as described in more detail herein with respect to Figures 4 and 6. In some embodiments, the plasma generator assembly 163 delivers an RF signal to the support base 107 (e.g., power electrode or cathode) which may be used to generate (maintain and / or ignite) a plasma 101 in a processing region disposed between the substrate support assembly 136 and the chamber lid 123. In some embodiments, the RF generator 118 is configured to deliver an RF signal having a frequency that is greater than about 1 MHz or more, or about 2 MHz or more, such as about 13.56 MHz or more.

[0032] As discussed above, in some embodiments, the plasma generator assembly 163, which includes an RF generator 118 and an RF generator assembly (which includes an RF matching circuit 162 and a first filter assembly 161 ), is generally configured to deliver a desired amount of a continuous wave (CW) or pulsed RF power at a desired substantially fixed sinusoidal waveform frequency to a support base 107 of the substrate support assembly 136 based on control signals provided from the system controller 126. During processing, the plasma generator assembly 163 is configured to deliver RF power (e.g., an RF signal) to the support base 107 disposed proximate to the substrate support 105, and within the substrate support assemblyPATENTAttorney Docket No.: 44024475WO01136. The RF power delivered to the support base 107 is configured to ignite and maintain a processing plasma 101 of processing gases disposed within the processing volume 129.

[0033] In some embodiments, the support base 107 is an RF electrode that is electrically coupled to the RF generator 118 via the RF matching circuit 162 and the first filter assembly 161, which are both disposed within the RF generator assembly. The first filter assembly 161 includes one or more electrical elements that are configured to substantially prevent a current generated by the output of a PV waveform generator 150 from flowing through an RF power delivery line 167 and damaging the RF generator 118. The first filter assembly 161 acts as a high impedance (e.g., high Z) to the PV signal generated from a PV pulse generator P1 within the PV waveform generator 150, and thus inhibits the flow of current to the RF matching circuit 162 and RF generator 118.

[0034] In some embodiments, the RF generator assembly and the RF generator 118 are used to ignite and maintain a processing plasma 101 using the processing gases disposed in the processing volume 129 and fields generated by the RF power (RF signal) delivered to the support base 107 by the RF generator 118. The processing volume 129 is fluidly coupled to one or more dedicated vacuum pumps through a vacuum outlet 120, which maintain the processing volume 129 at sub-atmospheric pressure conditions and evacuate processing and / or other gases, therefrom. In some embodiments, the substrate support assembly 136, disposed in the processing volume 129, is disposed on a support shaft 138 that is grounded and extends through the chamber base 124. However, in some embodiments, the RF generator assembly is configured to deliver an RF power to the bias electrode 104 disposed in the substrate support 105 versus the support base 107.

[0035] The substrate support assembly 136, as briefly discussed above, generally includes the substrate support 105 (e.g., ESC substrate support) and support base 107. In some embodiments, the substrate support assembly 136 can additionally include an insulator plate 111 and a ground plate 112, as is discussed further below. The support base 107 is electrically isolated from the chamber base 124 by the insulator plate 111, and the ground plate 112 is interposed between the insulator plate 111 and the chamber base 124. The substrate support 105 is thermally coupled toPATENTAttorney Docket No.: 44024475WO01and disposed on the support base 107. In some embodiments, the support base 107 is configured to regulate the temperature of the substrate support 105, and the substrate 103 disposed on the substrate support 105, during substrate processing.

[0036] Typically, the substrate support 105 is formed of a dielectric material, such as a bulk sintered ceramic material, such as a corrosion-resistant metal oxide or metal nitride material, for example, aluminum oxide (AI2O3), aluminum nitride (AIN), titanium oxide (TiO), titanium nitride (TiN), yttrium oxide (Y2O3), mixtures thereof, or combinations thereof. In embodiments herein, the substrate support 105 further includes the bias electrode 104 embedded in the dielectric material thereof. In some embodiments, one or more characteristics of the RF power used to maintain the plasma 101 in the processing region over the bias electrode 104 are determined and / or monitored by measuring an RF waveform established at the bias electrode 104.

[0037] In one configuration, the bias electrode 104 is a chucking pole used to secure (i.e. , chuck) the substrate 103 to the substrate supporting surface 105A of the substrate support 105 and to bias the substrate 103 with respect to the processing plasma 101 using one or more of the pulsed-voltage biasing schemes described herein. Typically, the bias electrode 104 is formed of one or more electrically conductive parts, such as one or more metal meshes, foils, plates, or combinations thereof.

[0038] In some embodiments, the bias electrode 104 is electrically coupled to a clamping network 116, which provides a chucking voltage thereto, such as static DC voltage between about -5000 V and about 5000 V, using an electrical conductor, such as the coaxial power delivery line 106 (e.g., a coaxial cable). As will be discussed further below, the clamping network 116 includes bias compensation circuit elements 116A, a DC power supply 155, and a bias compensation module blocking capacitor, which is also referred to herein as the blocking capacitor Cs. The blocking capacitor Cs is disposed between the output of a PV waveform generator 150 and the bias electrode 104.

[0039] The substrate support assembly 136 may further include the edge control electrode 115 that is positioned below the edge ring 114 and surrounds the bias electrode 104 and / or is disposed a distance from a center of the bias electrode 104.PATENTAttorney Docket No.: 44024475WO01In general, for a processing chamber 100 that is configured to process circular substrates, the edge control electrode 115 is annular in shape, is made from a conductive material, and is configured to surround at least a portion of the bias electrode 104. In some embodiments, such as shown in Figure 1, the edge control electrode 115 is positioned within a region of the substrate support 105. In some embodiments, as illustrated in Figure 1, the edge control electrode 115 includes a conductive mesh, foil, and / or plate that is disposed a similar distance (i.e. , Z-direction) from the substrate supporting surface 105A of the substrate support 105 as the bias electrode 104. In some other embodiments, the edge control electrode 115 includes a conductive mesh, foil, and / or plate that is positioned on or within a region of a quartz pipe 110, which surrounds at least a portion of the bias electrode 104 and / or the substrate support 105. Alternately, in some other embodiments (not shown), the edge control electrode 115 is positioned within or is coupled to the edge ring 114, which is disposed on and adjacent to the substrate support 105. In this configuration, the edge ring 114 is formed from a semiconductor or dielectric material (e.g., AIN, etc.).

[0040] The edge control electrode 115 can be biased by use of a PV waveform generator that is different from the PV waveform generator 150 that is used to bias the bias electrode 104. In some embodiments, the edge control electrode 115 can be biased by use of a PV waveform generator 150 that is also used to bias the bias electrode 104 by splitting part of the power to the edge control electrode 115. In one configuration, a first PV waveform generator 150 of the first PV source assembly 196 is configured to bias the bias electrode 104, and a second PV waveform generator 150 of a second PV source assembly 197 is configured to bias the edge control electrode 115.

[0041] A power delivery line 157 electrically connects the output of the PV waveform generator 150 of the first PV source assembly 196 to an optional filter assembly 151 and the bias electrode 104. While the discussion below primarily discusses the power delivery line 157 of the first PV source assembly 196, which is used to couple a PV waveform generator 150 to the bias electrode 104, the power delivery line 158 of the second PV source assembly 197, which couples a PV waveform generator 150 to the edge control electrode 115, will include the same or similar components. The electrical conductor(s) within the various parts of the powerPATENTAttorney Docket No.: 44024475WO01delivery line 157 may include: (a) one or a combination of coaxial cables, such as a flexible coaxial cable that is connected in series with a rigid coaxial cable, (b) an insulated high-voltage corona-resistant hookup wire, (c) a bare wire, (d) a metal rod, (e) an electrical connector, or (f) any combination of electrical elements in (a) - (e). The optional filter assembly 151 includes one or more electrical elements that are configured to substantially prevent a current generated by the output of the RF generator 118 from flowing through the power delivery line 157 and damaging the PV waveform generator 150. The optional filter assembly 151 acts as a high impedance (e.g., high Z) to RF signal generated by the RF generator 118, and thus inhibits the flow of current to the PV waveform generator 150.

[0042] The second PV source assembly 197 includes a clamping network 116 so that a bias applied to the edge control electrode 115 can be similarly configured to the bias applied to the bias electrode 104 by the clamping network 116 coupled within the first PV source assembly 196. Applying similarly configured PV waveforms and clamping voltages to the bias electrode 104 and edge control electrode 115 can help improve the plasma uniformity across the surface of the substrate during processing and thus improve the plasma processing process results.

[0043] In some embodiments, the processing chamber 100 further includes the quartz pipe 110, or collar, that at least partially circumscribes portions of the substrate support assembly 136 to prevent the substrate support 105 and / or the support base 107 from contact with corrosive processing gases or plasma, cleaning gases or plasma, or byproducts thereof. Typically, the quartz pipe 110, the insulator plate 111, and the ground plate 112 are circumscribed by a cathode liner 108. In some embodiments, a plasma screen 109 is positioned between the cathode liner 108 and the sidewalls 122 to prevent plasma from forming in a volume underneath the plasma screen 109 between the cathode liner 108 and the one or more sidewalls 122.Example Representative Circuit of a Processing Chamber

[0044] Figure 2 illustrates stray capacitance and substrate support capacitance 200 associated with a processing chamber, in accordance with certain embodiments of the present disclosure. The stray capacitance 204 (Cstray) represents the capacitance between an electrode of the processing chamber 100 (e.g., chamber lidPATENTAttorney Docket No.: 44024475WO01123, substrate support assembly 136) and ground (e.g., ground plate 112), and a substrate support capacitance 202, also referred to herein as an electrostatic chuck capacitance (Cesc), which represents the capacitance between a bias electrode (e.g., bias electrode 104) and the substrate supporting surface (e.g., substrate supporting surface 105A). As shown, Cesc is created between an output node (labeled llout) and a complex load (e.g., plasma load) which is simply represented by resistive element 206. To have a square shape for a voltage pulse on the load, a slope is implemented for the voltage across Cesc and the voltage across Cstray (e.g., voltage at llout), as described in more detail herein. The current across Cstray (e.g., compensation current (Icomp)) may be equal to the load current (lioad) across Cesc multiplied by the ratio of the capacitance of Cstray and the capacitance of Cesc. The output current (lout) may be equal to the sum of lioad and Icomp, which may be represented by the equation:Example Voltage Waveform for Processing Chamber

[0045] Figure 3 illustrates an example voltage waveform 300 that can be provided during plasma processing, in accordance with certain embodiments of the present disclosure. The voltage waveform 300 may include a series of pulses 310 that may be delivered to an electrode disposed within a processing chamber, such as the bias electrode 104 shown in Figure 1. The pulses 310 may each include a first portion 312 and a second portion 314, as illustrated. Each of the series of pulses 310 of the voltage waveform 300 generally includes two main stages: a sheath collapse stage and an ion current stage. At the beginning of the ion current stage, a drop of wafer voltage creates a high voltage sheath above the substrate, accelerating positive ions to the substrate 103. The positive ions deposit a positive charge on the substrate surface and tend to gradually increase the substrate voltage positively. If a square wave is supplied, the ion current towards the substrate creates a positive slope of the substrate voltage during the ion current stage. To have a square shape for the voltage pulse on the load, a negative slope is implemented for the voltage at llout during the ion current stage, as shown in Figure 3, which is used to form the voltage across the electrostatic chuck capacitive element.PATENTAttorney Docket No.: 44024475WO01

[0046] Implementing the slope at the bias electrode 104 and electrostatic chuck capacitor during the ion current stage is generally referred to as current compensation, which is used to form the constant voltage seen at the load during this stage. The voltage difference between the beginning and end of the ion current phase determines the IEDF width. The larger the voltage difference, the wider the distribution of ion energies, and thus a wider IEDF width. To achieve monoenergetic ions and a narrower IEDF width, current compensation operations are performed to flatten the substrate voltage waveform in the ion current phase. In some embodiments, the voltage waveform can be delivered at a frequency (1 / TP) between about 50 kHz and 1000 kHz. In some embodiments, the voltage waveform established at the electrode has an on-time, which is defined as the ratio of the ion current time period (e.g., length of ion current stage) and the waveform period Tp (e.g., length of sheath collapse stage + length of ion current stage), is greater than 50%, or greater than 70%, such as between 80% and 95%. In some embodiments, a voltage waveform, which has a waveform cycle has a period Tp (e.g., about 2.5 ps), is serially repeated within a burst that has a burst period that is between about 100 microseconds (ps) and about 10 milliseconds (ms). The burst of pulses 310, or series of pulses 310 over a period of time, can have a burst duty cycle that is between about 5% - 100%, such as between about 50% and about 95%, wherein the duty cycle is the ratio of the burst period divided by the burst period plus a non-burst period (i.e., no PV waveforms are generated) that separates the burst periods. As shown, the sheath collapse stage may have a duration of TSH, which may be about 200ns.Waveform Generator Examples

[0047] Figure 4 illustrates a pulser 400 (also referred to herein as a waveform generator), in accordance with certain embodiments of the present disclosure. In some embodiments, the pulser 400 may be included in a power supply circuit (e.g., PV waveform generator 150) of a processing chamber (e.g., processing chamber 100). As shown, the pulser 400 includes a number of stacked inductive adder modules, hereinafter referred to as voltage stages or modules (e.g., 440, 442, 444). Although three serially connected voltage stages are shown in Figure 4, any number of voltage stages may be included in the pulser 400. For example, the pulser 400 may include 16 serially connected voltage stages.PATENTAttorney Docket No.: 44024475WO01

[0048] The pulser 400 may include pulse capacitive elements 402, 404, and 406 (labeled C1, C2, and C3, respectively), as well as transistors 410, 412, and 414 (labeled as Q1, Q2, and Q3, respectively). The capacitive elements 402, 404, and 406 may be referred to herein as voltage sources 402, 404, 406, respectively. Transistors 410, 412, and 414 may be power transistors (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) with a parallel diode (e.g., a body diode D1, D2, and D3, respectively). Each transistor 410, 412, 414 may act as a switch, and may be referred to as a switches 410, 412, 414, respectively, herein. In some embodiments, transistor 410, 412, 414 may be implemented on a printed circuit board. Capacitive elements 402, 404, and 406 may serve as voltage storage elements that may be charged using a charging circuit, such as the circuit illustrated in Figure 5. In some embodiments, the transistors 410, 412, and 414 may each be coupled to a gate drive circuit 418, 420, 422, as illustrated. Each gate drive circuit 418, 420, 422 may have a trigger, which may receive a signal from the system controller 126 in order to be enabled or disabled to set the state of the gate within the respective transistor 410, 412, 414. The capacitive elements illustrated in Figures 4 and 6 are effectively acting as voltage sources. While the example pulser 400 illustrates capacitive elements to facilitate understanding, any suitable voltage source may be used.

[0049] The resistive element 424 (labeled R1 ) represents an internal serial resistive element of the pulser coupled to the load 426. The complex load 426, which may be formed by a plasma formed in plasma processing chamber, may be represented by capacitive element 428 (labeled C4) and resistive element 430 (labeled R2). As shown, the capacitive element 406 and transistor 414 form a first voltage stage 444 (e.g., module), and the capacitive element 404 and transistor 412 form a second voltage stage 442 (e.g., module). The pulser 400 also includes a third voltage stage 440 (e.g., module) having the capacitive element 402 and transistor 410. The output of the pulser 400 is coupled to a common node 480 that is coupled (e.g., capacitively coupled) to the complex load 426. While the pulser 400 is implemented with three voltage stages, the aspects of the present disclosure may be implemented with one, two, or more than three voltage stages. In some embodiments of a pulser 400, one or more of the voltage stages may be duplicated one or more times, such as a configuration that includes a first voltage stage 444, two or more second voltage stages 442, and a third voltage stage 440.PATENTAttorney Docket No.: 44024475WO01

[0050] In some embodiments, the common node 480 and the load 426 are configured to be capacitively coupled to the support base 107, due to the delivery of RF power, provided to the support base 107, by the RF generator 118. In some embodiments, the common node 480 may be configured to be capacitively coupled to a cathode RF feed provided through node 190 (Figure 1). During plasma processing, the plasma 101 will act as the complex load 426.

[0051] In some embodiments, and as shown in Figure 4, the pulser 400 may include a first voltage stage 444. The first voltage stage 444 has a first switch (e.g., combination of transistor 414, gate drive circuit 422, and trigger) with a first terminal coupled to a first terminal of a first voltage source (e.g., capacitive element 406) at node N9. A second terminal of the first switch is coupled to a ground reference (labeled “GND”) at node N11. The first voltage stage 444 may further include a first transformer 470 with a core 476, a primary winding 472 coupled to a second terminal of the first voltage source 406 at node N10, and a secondary winding 474 with a first end coupled to the first ground reference via node N12. The primary winding of the first transformer is also coupled to the ground reference at node N11. The first voltage stage 444 may further include a first diode D3 in parallel with the primary winding 472 of the first transformer 470. A first end of the diode D3 may be coupled to the second terminal of the first voltage source 406 and the primary winding at node N10, and a second end of the diode D3 may be coupled to first terminal of the first switch 414 and the primary winding via node N12. The first transformer may have a first transformer ratio. The ratio of the transformer is the ratio between the number of primary turns (WP) in the primary winding 472 to the number of secondary turns (Ws) in the secondary windings 474 with respect to each other. The transformer ratio (i.e., WP:WS) produces either a step-up voltage transformer (i.e., Ws > WP) or a step-down voltage transformer (i.e., Ws < WP).

[0052] In some embodiments, and as shown in Figure 4, the pulser 400 may include a second voltage stage 442. The second voltage stage 442 has a second switch (e.g., combination of transistor 412, gate drive circuit 420, and trigger) with a first terminal coupled to a first terminal of a second voltage source (e.g., capacitive element 404) at node N5. A second terminal of the second switch is coupled to a second ground reference (labeled “GND”) at node N7. The second voltage stage 442PATENTAttorney Docket No.: 44024475WO01may further include a second transformer 460 with a core 466, a primary winding 462 coupled to a second terminal of the second voltage source 404 at node N6, and a first end of a secondary winding 464 that is coupled to a second end of the secondary winding 474 of the first transformer 470. The primary winding of the second transformer 460 is also coupled to the ground reference at node N7. The second voltage stage 442 may further include a second diode D2 in parallel with the primary winding 462 of the second transformer 460. A first end of the diode D2 may be coupled to the second terminal of the second voltage source 404 and the primary winding at node N6, and a second end of the diode D2 may be coupled to first terminal of the second switch 412 and the primary winding via node N8. The second transformer 460 may have a second transformer ratio, as described above. In some embodiments of the pulser 400, such as a configuration where there are only two voltage stages (i.e. , voltage stages 442 and 444), a second end of the secondary winding 464 of the second transformer 460 may be configured to be coupled to an electrode disposed within the processing chamber 100, such as the bias electrode 104 through the common node 480.

[0053] In some embodiments, and as shown in Figure 4, the pulser 400 may include a third voltage stage 440. The third voltage stage 440 has a third switch (e.g., combination of transistor 410, gate drive circuit 418, and trigger) with a first terminal coupled to a first terminal of a third voltage source (e.g., capacitive element 402) at node N1. A second terminal of the third switch is coupled to a third ground reference (labeled “GND”) at node N3. The third voltage stage 440 may further include a third transformer 450 with a core 456, a primary winding 452 coupled to a second terminal of the third voltage source 402 at node N2, and a secondary winding 454 that has a first end coupled to the second end of the secondary winding 464 of the second transformer 460. The primary winding of the third transformer is also coupled to the ground reference at node N3. The third voltage stage 440 may further include a third diode D1 in parallel with the primary winding 452 of the third transformer 450. A first end of the diode D1 may be coupled to the second terminal of the third voltage source 402 and the primary winding at node N2, and a second end of the diode D1 may be coupled to first terminal of the third switch 410 and the primary winding via node N4. The third transformer may have a third transformer ratio, as is described above. In some embodiments of the pulser 400, as shown in Figure 4, a second end of thePATENTAttorney Docket No.: 44024475WO01secondary winding 454 of the third transformer 450 may be configured to be coupled to an electrode disposed within the processing chamber 100, such as the bias electrode 104 through the common node 480. In some cases, and as illustrated, the primary winding 472 of the first voltage stage 444, the primary winding 462 of the second voltage stage 442, and the primary winding 452 of the third voltage stage 440 are not coupled together.

[0054] In some embodiments, the core (e.g., 456, 466, 476) utilized in the transformers 450, 460, 470 of the modules 440, 442, 444 of the pulser 400 are used to adjust the output waveform that is possible for the pulser 400. The characteristics of the core (e.g., 456, 466, 476) dictate the maximum allowable switching frequency and pulse width of the output waveform that can be created by the pulser 400. Some of the characteristics of a core (e.g., 456, 466, 476) that can have an impact on the output waveform that is created by the pulser 400 include magnetic saturation flux density, magnetic flux swing, remnant flux density, cross sectional area, volume, and weight. In some embodiments, each of the cores (e.g., 456, 466, 476) has at least one of a magnetic saturation flux density of between 1.4 tesla (T) and 1.8 T, a magnetic flux swing of between 2.4 T and 3.6 T, a remnant flux density of between 0.2 T and 0.8 T, a cross sectional area of between 6 square centimeters (cm2) and 9 cm2, a weight of between 2 kilograms (kg) and 4 kg, and a volume of between 700 cubic centimeters (cm3) and 1500 cm3.

[0055] In some embodiments, different cores (e.g., 456, 466, 476) may be used in different modules 440, 442, 444 of the pulser 400 in order to customize the characteristics of the output waveform. In some embodiments, each module 440, 442, 444 has its own ground reference. In some embodiments, the first, second and third transformer ratios in each the transformers 450, 460, 470 are the same. In other embodiments, one or more of the transformers in a pulser 400 has a different transformer ratio from the other transformers in the other stages within the pulser 400. In addition, each module being ground referenced also may reduce isolation breakdown (e.g., arcing) between the gate drive circuits at higher voltages, which can prove problematic in certain conventional pulser designs. In some embodiments, the output of each module 440, 442, 444 is tied to the same ground reference as the gatePATENTAttorney Docket No.: 44024475WO01drive circuit input, so the pulser 400 may suffer less from electromagnetic interference during operation.

[0056] In some embodiments, the transformer ratio (i.e., first transformer ratio) of the first transformer may be the same as the transformer ratio (i.e., second transformer ratio) of the second transformer. In other embodiments, the transformer ratio of the first transformer may be different than the transformer ratio of the second transformer. For example, the first transformer ratio may be smaller than the second transformer ratio, or larger than the second transformer ratio. In some embodiments, the transformer ratio (i.e., third transformer ratio) of the third transformer may be the same as the transformer ratio of the first transformer and the second transformer. In other embodiments, the transformer ratio of the third transformer may be different than the transformer ratio of the first transformer and the second transformer. There may be any combination of transformer ratios among the transformers for each voltage stage 440, 442, 444 (e.g., module). The transformer ratio of the transforms may be modified to customize the output voltage waveform of the pulser 400 with different voltages and different pulse widths. Each module 440, 442, 444 can deliver a pulse, and each pulse seen at the common node 480 is dependent on the voltage stored in the capacitive elements 402, 404, 406 of the respective modules and the transformer ratio. Triggering multiple modules of a pulser 400 with varying transformer ratios may allow for the output signal shape and pulse width generated in the secondary windings of the modules to be modified to suit a desired IEDF. In some embodiments, the transformers (e.g., 450, 460, 470) of each of the voltage stages 440, 442, 444 (e.g., module) are connected in series.

[0057] As shown, each of the capacitive elements 402, 404, and 406 may be charged to a specific voltage, depending on the characteristics of the waveform being implemented. The transistor, gate drive circuit, and trigger in each module 440, 442, 444 may operate as a switch, controlled by the system controller 126. For example, each of the capacitive elements 402, 404, and 406 are charged to 800 volts (V) when the gate drive circuit, and the trigger (e.g., transistor 410, 412, 414) in each module 440, 442, 444 operates as a closed switch. In some implementations, the capacitive elements 402, 404, and 406 may be charged to greater or lower voltages to implement different voltage levels for a waveform suitable for different implementations. In somePATENTAttorney Docket No.: 44024475WO01embodiments, each of the voltage stages 440, 442, and 444 may have a modular design that facilitates easy replacement in case of malfunction. The operation of the pulser 400 for generating the waveform shown in Figure 3 is described in more detail with respect to Figures 7-8E.

[0058] Figure 5 illustrates a charging circuit 500 used to charge a capacitive element 512, in accordance with certain aspects of the present disclosure. The capacitive element 512 may correspond to any one of the capacitive elements (e.g., 402, 404, 406, 602, 604, and 606) of the modules (e.g., 440, 442, 444, and 640) of the pulser 400. In other words, a charging circuit (e.g., similar to charging circuit 500) may be implemented for each of modules 440, 442, 444, and 640 to charge the capacitive elements to their respective voltages, as described herein. The charging circuit 500 may include an inverter 502 for converting a DC voltage to an alternating current (AC) voltage. The AC voltage may be provided to a primary winding 506 of a transformer 504. The transformer 504 may generate an AC voltage at the secondary winding 508 having a higher voltage than the AC voltage at the primary winding 506. For example, to charge capacitive element 512, the AC voltage at the secondary winding 508 may have a peak voltage of 1200 V. The AC voltage at the secondary winding 508 may be provided to a rectifier 510 to generate a DC signal used to charge the capacitive element 512.

[0059] Figure 6 illustrates a schematic view of a voltage stage 640 of a pulser (e.g., similar to pulser 400) that includes multiple voltage sources (e.g., voltage sources 602, 604, 606), in accordance with certain embodiments of the present disclosure. The voltage stage 640 may be similar to any or all of the voltage stages shown in Figure 4 (e.g., voltage stages 440, 442, 444, etc.), but instead of including a single voltage source (e.g. voltage source 402, 404, 406, etc.), the voltage stage 640 may include a plurality of voltage sources (e.g., voltage sources 602, 604, 606, each with a pulse capacitive element C6, C7, C8, respectively) that can each provide voltages at different voltage levels. Each of the pulse capacitive element C6, C7, C8 may enable the voltage stage 640 to generate a pulse at a different voltage level by selecting a desired pulse capacitive element C6, C7, C8 at the desired time. In one example, a pulser (e.g., similar to pulser 400) may include any number of voltage stages 640,PATENTAttorney Docket No.: 44024475WO01either in combination with voltage stages 440, 442, 444, or instead of voltage stages 440, 442, 444.

[0060] The voltage stage 640 may include a switching circuit that includes a first switch SW1 and a second switch SW2 configured to enable the selection of any of the plurality of voltage sources 602, 604, 606, depending on the desired voltage of the pulse to be generated by the voltage stage 640. For example, when the voltage stage 640 will provide a pulse at a voltage level corresponding to the voltage source 602, the first switch SW1 may couple the node N1 to a first end of capacitive element C6 (e.g., included in voltage source 602) and the second switch SW2 may couple the node N2 to a second end of capacitive element C6 to enable the voltage source to supply the transformer 450 and generate a pulse of a voltage corresponding to capacitive element C4 at the common node 480. Although three voltage sources are illustrated in the voltage stage 640, any number of voltage sources may be used. In this manner, using a voltage stage like voltage stage 640 may enable a pulser to easily and quickly switch between multiple voltage sources in a voltage stage during voltage waveform generation, depending on the desired output voltage. In addition, a single voltage stage may be able to generate potentially any number of different output voltages at the common node 480, depending on how many voltage sources are included in the pulser and which voltage source is selected.Voltage Waveform Generation Examples

[0061] Embodiments described herein may allow for various combinations of the voltage stages included in a pulser to be used to generate the output voltage at the common node at for a wide range of voltage set points, and may enable the pulser to achieve high resolution (e.g., more accurately generate the voltage set points), especially when generating low output voltages.

[0062] Figure 7 is a process flow diagram illustrating a method 700 of waveform generation, in accordance with certain embodiments of the present disclosure. The method 700 may be performed by a waveform generation system, including a waveform generator such as the pulser 400 and / or control circuitry such as the system controller 126. The pulser 400 may include one or more of the voltage stages 440, 442, 444, and 640 described herein. The method 700 discussion below is describedPATENTAttorney Docket No.: 44024475WO01in conjunction with the schematic of the pulser 400 that is illustrated in Figure 4. As discussed above, in some embodiments, the common node 480 illustrated in Figure 4 is configured to be coupled to an electrode within the plasma processing system 100.

[0063] The method 700 may include, at operation 710, generating an output voltage (e.g., a voltage set point) at a common node (e.g., common node 480).

[0064] The operation 710 may include, at operation 712, generating a first pulse at a first voltage at the common node during a first time period based on a first transformer ratio of a first transformer (e.g., transformer 470) included in a first voltage stage (e.g., voltage stage 444).

[0065] The operation 710 may include, at operation 714, generating a second pulse at a second voltage at the common node during a second time period based on a second transformer ratio of a second transformer (e.g., transformer 460) included in a second voltage stage (e.g., voltage stage 442).

[0066] The operation 710 may include, at operation 716, generating a third pulse at a third voltage at the common node during a third time period based on a third transformer ratio of a third transformer (e.g., transformer 450) included in a third voltage stage (e.g., voltage stage 440). A secondary winding of the first transformer (e.g., secondary winding 474), a secondary winding of the second transformer (e.g., secondary winding 464), and a secondary winding of the third transformer (e.g., secondary winding 454) are coupled in series (e.g., as illustrated in Figure 4). The output voltage at the common node may include the first voltage (e.g., from the first voltage stage), the second voltage (e.g., from the second voltage stage), and the third voltage (e.g., from the third voltage stage).

[0067] According to certain embodiments, the operation 710 may include, at operation 718, generating a fourth pulse at a fourth voltage at the common node during a fourth time period based on a fourth transformer ratio of a fourth transformer included in a fourth voltage stage, wherein the output voltage may further include the fourth voltage. The fourth voltage stage may be implemented, as, for example, the voltage stage 440, 442, 444, or 640. A secondary winding of the fourth transformer is coupled in series with the secondary winding of the first transformer, the secondary winding of the second transformer, and the secondary winding of the third transformer. ThePATENTAttorney Docket No.: 44024475WO01output voltage at the common node may further include the fourth voltage (e.g., from the fourth voltage stage). In some embodiments, the first time period, the second time period, the third time period, and / or the fourth time period may at least partially overlap. That is, the pulses from various voltage stages of the pulser may be overlapped to generate a greater voltage at the output voltage, as desired.

[0068] In some embodiments, the second voltage may be a first fraction of the first voltage, the third voltage may be a second fraction of the second voltage, and / or the fourth voltage may be a third fraction of the third voltage. For example, first fraction may be (e.g., the second voltage may be of the first voltage), the second fraction may be 14 (e.g., the third voltage may be 1 / 4 of the first voltage), and the third fraction may be 1 / 8 (e.g., the fourth voltage may be 1 / 8 of the first voltage). In some embodiments, a magnitude of the first voltage may be the same as a magnitude of the second voltage, and a magnitude of the third voltage may be different from the magnitude of the first voltage and the second voltage.

[0069] In some embodiments, each voltage stage may include a voltage source (e.g., voltage sources 402, 404, 406), a switch (e.g., transistors 410, 412, 414) coupled to the voltage source, and a primary winding (e.g., primary windings 452, 462, 472) coupled to the voltage source. The secondary winding of the first transformer, the secondary winding of the second transformer, the secondary winding of the third transformer, and / or the secondary winding of the fourth transformer is coupled between the common node and a reference potential node (e.g., electrical ground labeled “GND” at node N11, also referred to herein as “ground” and / or “ground reference”), as illustrated in Figure 4.

[0070] According to certain embodiments, generating the output voltage at the common node at operation 710 may include generating a fourth pulse at a fourth voltage at the common node during a fourth time period based on a fourth transformer ratio of a fourth transformer included in a fourth voltage stage, generating a fifth pulse at a fifth voltage at the common node during a fifth time period based on a fifth transformer ratio of a fifth transformer included in a fifth voltage stage, and generating a sixth pulse at a sixth voltage at the common node during a sixth time period based on a sixth transformer ratio of a sixth transformer included in a sixth voltage stage. In some embodiments, a first cycle may include the first time period, the second timePATENTAttorney Docket No.: 44024475WO01period, and the third time period, and a second cycle occurring after the first cycle may include the fourth time period, the fifth time period, and the sixth time period. The output voltage at operation 710 may be generated at the common node during the first cycle and the second cycle. In this manner, the plurality of voltage stages of the pulser enable the pulser to have redundant voltage stages, such that different voltage stages of the pulser may be used in to generate the same voltage waveform using pulses from the voltage stages. That is, different combinations of the voltage stages of the pulser may be utilized to generate a desired voltage at the common node, allowing the pulser to manage and balance usage of the various voltage stages (e.g., to ensure that certain voltage stages are not overused or underused compared to other voltage stages and ensure substantially equal workloads across voltage stages). As a result, the lifetime of the pulser may be extended (e.g., by delaying maintenance and / or replacement of individual voltage stages of the pulser and the associated pulser downtime during maintenance and / or replacement when the pulser is unable to be used).

[0071] In addition, due to the redundancy of the voltage stages of the pulser, the pulser may be capable of operation even when one or more voltage stages are nonfunctional (e.g., a pulser may use equivalent functioning voltage stages in place of non-functional voltage stages, or even different combinations of functioning voltage stages configured to supply different voltage levels to compensate for any nonfunctional voltage stages).

[0072] In some embodiments, the second time period begins after the first time period begins and before the first time period ends, and the third time period begins after the second time period begins and before the second time period ends. In this manner, the first pulse (e.g., during the first time period), the second pulse (e.g., during the second time period), and the third pulse (e.g., during the third time period) may be consecutive pulses, and the first time period may partially overlap with the second time period, and the second time period may partially overlap with the third time period. In some cases, the first time period and the second time period may be cyclically performed two or more times. In some cases, the first time period and the second time period may be sequentially performed.PATENTAttorney Docket No.: 44024475WO01

[0073] Embodiments of the present disclosure may enable a pulser to generate a more sensitive output voltage that can be configured to more accurately mimic the charging of the substrate (e.g., substrate 103) during voltage waveform generation, as a result voltage stages included in the pulsed power source being configured to generate pulses at different voltage levels. Figures 8A-8E illustrate example output voltages over time that can be provided during plasma processing, in accordance with certain embodiments of the present disclosure. The output voltages in Figures 8A-8E each include the pulse 310 that may be delivered to an electrode disposed within a processing chamber, such as the bias electrode 104 shown in Figure 1. The pulse 310 (which may represent a single pulse of a series of pulses 310) may include the first portion 312 and the second portion 314, as illustrated.

[0074] In Figure 8A, the pulse 310 may include four consecutive voltage steps S1 , which form a linear voltage ramp for the pulse 310, as illustrated. For example, the voltage step S1 may be 100 V. That is, the pulser may use four different voltage stages each configured to generate a voltage of 100 V at the output voltage to generate the four consecutive voltage steps S1 of 100 V for the pulse 310, resulting in a voltage of 400 V at the output voltage. Figure 8B may be similar to Figure 8A, except that the voltage steps S2 may be smaller. For example, the voltage step S2 may be 50 V, and the pulser may generate four consecutive voltage steps S2 of 50 V for the pulse 310, resulting in a voltage of 200 V at the output voltage. Figure 8C may be similar to Figure 8B, except that the voltage steps S3 may be smaller. For example, the voltage step S3 may be 25 V, and the pulser may generate four consecutive voltage steps S3 of 25 V for the pulse 310, resulting in a voltage of 100 V at the output voltage. Figure 8D may be similar to Figure 8C, except that the voltage steps S4 may be smaller. For example, the voltage step S4 may be 12.5 V, and the pulser may generate four consecutive voltage steps S4 of 12.5 V of the pulse 310, resulting in a voltage of 50 V at the output voltage. As a result of the different voltage stages, the pulser may be capable of generating the pulses 310 illustrated in Figures 8A-8D, each pulse 310 having a different step size. As a result, the pulser may be capable of using larger or smaller voltage steps when generating the output voltage, depending on the desired functionality.PATENTAttorney Docket No.: 44024475WO01

[0075] In Figure 8E, the pulse 310 may include four consecutive voltage steps S1 , S2, S3, and S4, which form a non-linear voltage ramp for the pulse 310. That is, each of the four voltage steps S1, S2, S3, and S4 shown in Figure 8E may gradually decrease from a 100 volt voltage step S1 down to a 12.5 volt voltage step S4. In this manner, the pulse 310 may result in a curved voltage ramp (as opposed to the linear voltage ramp of Figures 8A-8D). In some embodiments, generating the pulse 310 of Figure 8E (with the curved and more gradual voltage ramp) with the pulser may enable increased customization of the voltage decay compensation of a plasma processing system, and may enable the pulser to more accurately mimic rate of the charging of the substrate (e.g., substrate 103) during voltage waveform generation.

[0076] In some embodiments, the common node is coupled to a bias electrode (e.g., bias electrode 104) disposed within a substrate support (e.g., substrate support 105) disposed within a plasma processing system (e.g., processing system 10).

[0077] In some embodiments, a pulser (e.g., pulser 400) may include four groups of voltage stages, each group of voltage stages configured to generate a pulse at a different voltage. Each of the voltage stages of the four groups may be implemented as one of the voltage stage 440, 442, 444, 640, which are described above. In some embodiments, each group of voltage stages may include four voltage stages, for a total of 16 voltage stages in the pulser.

[0078] The first group of voltage stages may be configured to generate a first pulse at a first voltage at a common node during a first time period, and the second group of voltage stages may be configured to generate a second pulse at a second voltage at the common node during a second time period. The third group of voltage stages may be configured to generate a third pulse at a third voltage at the common node during a third time period, and a fourth group of voltage stages may be configured to generate a fourth pulse at a fourth voltage at the common node during a fourth time period. The second voltage (e.g., from the second group of voltage stages) may be a first fraction (e.g., 14) of the first voltage (e.g., from the first group of voltage stages), the third voltage (e.g., from the third group of voltage stages) may be a second fraction (e.g., 14) of the second voltage, and / or the fourth voltage (e.g., from the fourth group of voltage stages) may be a third fraction (e.g., 1 / 8) of the third voltage. For example, the voltage stages of the first group may each be configured to generate 100 V at thePATENTAttorney Docket No.: 44024475WO01common node, the voltage stages of the second group may each be configured to generate 50 V at the common node, the voltage stages of the third group may each be configured to generate 25 V at the common node, and the voltage stages of the fourth group may each be configured to generate 12.5 V at the common node. In this manner, a pulser that includes different groups of voltage stages may enable the pulser to generate a wide range of voltage set points at the output voltage with high resolution.

[0079] In some embodiments, a pulser (e.g., pulser 400) may include three groups of voltage stages, each group of voltage stages configured to generate a pulse at a different voltage. Each of the voltage stages of the three groups may be implemented as one of the voltage stages 440, 442, 444, which are described above. In some embodiments, each group of voltage stages may include five voltage stages, for a total of 15 voltage stages in the pulser. The first group of voltage stages may be configured to generate a first pulse at a first voltage at a common node during a first time period, the second group of voltage stages may be configured to generate a second pulse at a second voltage (e.g., a voltage that is of the first voltage) at the common node during a second time period, and the third group of voltage stages may be configured to generate a third pulse at a third voltage (e.g., a voltage that is 1 / 8 of the first voltage) at the common node during a third time period.

[0080] In some embodiments, a pulser (e.g., pulser 400) may include 16 different voltage stages, each of the voltage stages configured to generate a pulse at a different voltage. Each of the voltage stages may be implemented as one of the voltage stages 440, 442, 444, which are described above. The first voltage stage may be configured to generate a first pulse at a first voltage at a common node during a first time period, the second voltage stage may be configured to generate a second pulse at a second voltage (e.g., a voltage of the first voltage) at the common node during a second time period, and the third voltage stage may be configured to generate a third pulse at a third voltage (e.g., a voltage 1 / 4 of the first voltage) at the common node during a third time period. The fourth voltage stage may be configured to generate a fourth pulse at a fourth voltage (e.g., a voltage 1 / 8 of the first voltage) at the common node during a fourth time period, the fifth voltage stage may be configured to generate a fifth pulse at a fifth voltage (e.g., a voltage 1 / 16 of the first voltage) at the commonPATENTAttorney Docket No.: 44024475WO01node during a fifth time period, and so on, with each additional voltage stage being configured to generate a pulse at the voltage of the previous stage (e.g., 1 / 32, 1 / 64, 1 / 128, etc.).

[0081] Figure 9 illustrates a schematic view of a multi-stage pulser, in accordance with certain embodiments of the present disclosure. The multi-stage pulser schematically illustrated in Figure 9 includes 16 voltage stages, such as voltage stages 940-955. Each voltage stage 940-955 may be implemented as any of, for example, voltage stages 440, 442, 444, and 640 described herein. Each voltage stage 940-955 is serially connected between a ground reference (labeled “GND”) and the common node 480 and the load 426, as illustrated. The voltage stages 940-955 may be grouped in fractional groups. For example, voltage stages 940-943 may each be configured to generate a pulse at a voltage of 100 V, voltage stages 944-947 may each be configured to generate a pulse at a voltage of 50 V (e.g., of the voltage of voltage stages 940-943), voltage stages 948-951 may each be configured to generate a pulse at a voltage of 25 V (e.g., 1 / 4 of the voltage of voltage stages 944-947), and voltage stages 952-955 may each be configured to generate a pulse at a voltage of 12.5 V (e.g., 1 / 8 of the voltage of voltage stages 940-943).

[0082] For example, during a first time period, the 16 stage pulser illustrated in Figure 9 may generate an output voltage of 187.5 V at the common node 480 by simultaneously ( / ') generating a first pulse at 100 V at the common node 480 during a first time period using voltage stage 940, ( / ' / ) generating a second pulse at 50 V at the common node 480 during the first time period using voltage stage 944, ( / / / ) generating a third pulse at 25 V at the common node 480 during the first time period using voltage stage 948, and ( / v) generating a fourth pulse at 12.5 V at the common node 480 during the first time period using voltage stage 952. In this example, during a second period of time, the 16 stage pulser illustrated in Figure 9 may generate an output voltage of 500 V at the common node 480 by simultaneously ( / ') generating a first pulse at 100 V at the common node 480 during a first time period using voltage stage 941, ( / / ') generating a second pulse at 100 V at the common node 480 during the first time period using voltage stage 942, ( / / / ) generating a third pulse at 100 V at the common node 480 during the first time period using voltage stage 943, ( / ) generating a fourth pulse at 50 V at the common node 480 during the first time period using voltage stagePATENTAttorney Docket No.: 44024475WO01945, (v) generating a fifth pulse at 25 V at the common node 480 during the first time period using voltage stage 949, and (w) generating a sixth pulse at 25 V at the common node 480 during the first time period using voltage stage 950. This example is merely illustrative, as each of the voltage stages 940-955 may each be configured to generate a pulse at any voltage level, and any combination of the voltage stages 940-955 may be used to generate any output voltage at the common node 480.

[0083] The processing chamber 100 includes the system controller 126, the central processing unit (CPU) 133, the memory 134, and support circuits 135, as described above. In some embodiments, the memory 134 may be implemented as a computer readable medium memory configured to store instructions (e.g., computer-executable code) that when executed by the CPU 133, cause the processing chamber 100 to perform the operations illustrated in Figure 7 and described above, or other operations for performing the various techniques discussed herein for providing a voltage waveform.

[0084] In some embodiments, the CPU 133 has one or more processors configured to, individually or collectively, implement the code stored in the memory 134. For example, the one or more processors include circuitry for generating a first pulse at a first voltage at a common node (e.g., common node 480) of a pulser (e.g., pulser 400) during a first time period based on a first transformer ratio of a first transformer (e.g., transformer 470) included in a first voltage stage (e.g., voltage stage 444), generating a second pulse at a second voltage at the common node of the pulser during a second time period based on a first transformer ratio of a second transformer (e.g., transformer 460) included in a second voltage stage (e.g., voltage stage 442), and generating a third pulse at a third voltage at the common node of the pulser during a third time period based on a first transformer ratio of a third transformer (e.g., transformer 450) included in a third voltage stage (e.g., voltage stage 440). In some embodiments, the one or more processors include circuitry for generating a fourth pulse at a fourth voltage at the common node of the pulser during a fourth time period based on a first transformer ratio of a fourth transformer included in a fourth voltage stage.PATENTAttorney Docket No.: 44024475WO01Additional Considerations

[0085] In the above description, details are set forth by way of example to facilitate an understanding of the disclosed subject matter. It should be apparent to a person of ordinary skill in the field, however, that the disclosed implementations are exemplary and not exhaustive of all possible implementations. Thus, it should be understood that reference to the described examples is not intended to limit the scope of the disclosure. Any alterations and further modifications to the described devices, instruments, methods, and any further application of the principles of the present disclosure are fully contemplated as would normally occur to one skilled in the art to which the disclosure relates. In particular, it is fully contemplated that the features, components, and / or steps described with respect to one implementation may be combined with the features, components, and / or steps described with respect to other implementations of the present disclosure. As used herein, the term “about” may refer to a + / -10% variation from the nominal value. It is to be understood that such a variation can be included in any value provided herein.

[0086] As used herein, “a processor,” “at least one processor” or “one or more processors” generally refers to a single processor configured to perform one or multiple operations or multiple processors configured to collectively perform one or more operations. In the case of multiple processors, performance of the one or more operations could be divided amongst different processors, though one processor may perform multiple operations, and multiple processors could collectively perform a single operation. Similarly, “a memory,” “at least one memory” or “one or more memories” generally refers to a single memory configured to store data and / or instructions, multiple memories configured to collectively store data and / or instructions.

[0087] As used herein, a phrase referring to “at least one of” or “one or more of’ a list of items refers to any combination of those items, including single members. As an example, “at least one of: a, b, or c” is intended to cover: a, b, c, a-b, a-c, b-c, and a-b-c, as well as any combination with multiples of the same element (e.g., a-a, a-a-a, a-a-b, a-a-c, a-b-b, a-c-c, b-b, b-b-b, b-b-c, c-c, and c-c-c or any other ordering of a, b, and c).PATENTAttorney Docket No.: 44024475WO01

[0088] The methods disclosed herein comprise one or more steps or actions for achieving the described method. The method steps and / or actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of specific steps and / or actions may be modified without departing from the scope of the claims.

[0089] The term “coupled” is used herein to refer to the direct or indirect coupling between two objects. For example, if object A physically touches object B and object B touches object C, then objects A and C may still be considered coupled to one another — even if objects A and C do not directly physically touch each other. For instance, a first object may be coupled to a second object even though the first object is never directly physically in contact with the second object.

[0090] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

PATENTAttorney Docket No.: 44024475WO01What is claimed is:

1. A method of generating a voltage waveform, the method comprising:generating an output voltage at a common node, comprising:generating a first pulse at a first voltage at the common node at a first time based on a first transformer ratio of a first transformer included in a first voltage stage;generating a second pulse at a second voltage at the common node at the first time based on a second transformer ratio of a second transformer included in a second voltage stage; andgenerating a third pulse at a third voltage at the common node at the first time based on a third transformer ratio of a third transformer included in a third voltage stage, wherein a secondary winding of the first transformer, a secondary winding of the second transformer, and a secondary winding of the third transformer are coupled in series between a reference potential node and the common node, and wherein the output voltage comprises the first voltage, the second voltage, and the third voltage.

2. The method of claim 1 , wherein the second voltage is a first fraction of the first voltage and wherein the third voltage is a second fraction of the first voltage.

3. The method of claim 2, wherein the first fraction is 1 / 2 and wherein the second fraction is 1 / 4.

4. The method of claim 1 , wherein a magnitude of the first voltage is the same as a magnitude of the second voltage, and wherein a magnitude of the third voltage is different from the magnitude of the first voltage and the second voltage.

5. The method of claim 1 , wherein each voltage stage comprises:a voltage source;a switch coupled to the voltage source; anda primary winding coupled to the voltage source, and wherein the primary winding of the first voltage stage, the primary winding of the second voltage stage, and the primary winding of the third voltage stage are not coupled together.PATENTAttorney Docket No.: 44024475WO016. The method of claim 1, wherein generating the output voltage at the common node further comprises:generating a fourth pulse at a fourth voltage at the common node at a second time based on a fourth transformer ratio of a fourth transformer included in a fourth voltage stage;generating a fifth pulse at a fifth voltage at the common node at the second time based on a fifth transformer ratio of a fifth transformer included in a fifth voltage stage; andgenerating a sixth pulse at a sixth voltage at the common node at the second time based on a sixth transformer ratio of a sixth transformer included in a sixth voltage stage,wherein the output voltage formed at the first time is maintained for a first time period, the output voltage formed at the second time is maintained for a second time period, and the first time period and the second time period are cyclically performed two or more times.

7. The method of claim 6, whereina magnitude of the first voltage is the same as a magnitude of the fourth voltage; a magnitude of the second voltage is the same as a magnitude of the fifth voltage; anda magnitude of the third voltage is the same as a magnitude of the sixth voltage.

8. The method of claim 1, wherein generating the output voltage at the common node further comprises:generating the first pulse at the first voltage at the common node during a second time period based on the first transformer ratio of the first transformer included in the first voltage stage; andgenerating the second pulse at the second voltage at the common node during the second time period based on the second transformer ratio of the second transformer included in the second voltage stage, wherein the output voltage comprises the first voltage and the second voltage during the second time period and wherein the first and second times are sequentially performed.PATENTAttorney Docket No.: 44024475WO019. The method of claim 1 , wherein the common node is coupled to a bias electrode disposed within a substrate support disposed within a plasma processing system.

10. A power supply circuit comprising:a first group of voltage stages configured to generate a first pulse at a first voltage at a common node during a first time period;a second group of voltage stages configured to generate a second pulse at a second voltage at the common node during a second time period, wherein the second voltage is a fraction of the first voltage;a third group of voltage stages configured to generate a third pulse at a third voltage at the common node during a third time period; anda fourth group of voltage stages configured to generate a fourth pulse at a fourth voltage at the common node during a fourth time period.

11. The power supply circuit of claim 10, wherein:the second voltage is a first fraction of the first voltage;the third voltage is a second fraction of the first voltage; andthe fourth voltage is a third fraction of the first voltage.

12. The power supply circuit of claim 11 , wherein:the first fraction is 1 / 2;the second fraction is 1 / 4; andthe third fraction is 1 / 8.

13. The power supply circuit of claim 10, wherein each voltage stage comprises:a voltage source;a switch coupled to the voltage source; anda primary winding of a transformer coupled to the voltage source, and wherein a secondary winding of the transformer of each voltage stage are coupled in series between the common node and a reference potential node.

14. The power supply circuit of claim 11 , wherein the first time period, the second time period, the third time period, and the fourth time period at least partially overlap.PATENTAttorney Docket No.: 44024475WO0115. A power supply circuit comprising:a first voltage stage;a second voltage stage;a third voltage stage;memory; anda processor coupled to the memory, the processor being configured to perform a method for generating a waveform, comprising:generating a output voltage at a common node coupled to the first voltage stage, the second voltage stage, and the third voltage stage, comprising:generating a first pulse at a first voltage at the common node during a first time period based on a first transformer ratio of a first transformer included in the first voltage stage;generating a second pulse at a second voltage at the common node during the first time period based on a second transformer ratio of a second transformer included in the second voltage stage; and generating a third pulse at a third voltage at the common node during the first time period based on a third transformer ratio of a third transformer included in the third voltage stage, wherein a secondary winding of the first transformer, a secondary winding of the second transformer, and a secondary winding of the third transformer are coupled in series between a reference potential node and the common node, and wherein the output voltage comprises the first voltage, the second voltage, and the third voltage.

16. The power supply circuit of claim 15, wherein the second voltage is a first fraction of the first voltage and wherein the third voltage is a second fraction of the second voltage.

17. The power supply circuit of claim 15, wherein a magnitude of the first voltage is the same as a magnitude of the second voltage and wherein a magnitude of the third voltage is different from the magnitude of the first voltage and the second voltage.

18. The power supply circuit of claim 15, wherein each voltage stage comprises:PATENTAttorney Docket No.: 44024475WO01a voltage source;a switch coupled to the voltage source; anda primary winding coupled to the voltage source, wherein the secondary winding of the first transformer, the secondary winding of the second transformer, and the secondary winding of the third transformer are coupled between the common node and the reference potential node.

19. The power supply circuit of claim 15, wherein generating the output voltage at the common node further comprises:generating a fourth pulse at a fourth voltage at the common node at a second time based on a fourth transformer ratio of a fourth transformer included in a fourth voltage stage;generating a fifth pulse at a fifth voltage at the common node at the second time based on a fifth transformer ratio of a fifth transformer included in a fifth voltage stage; andgenerating a sixth pulse at a sixth voltage at the common node at the second time based on a sixth transformer ratio of a sixth transformer included in a sixth voltage stage,wherein the output voltage formed during the first time period is maintained for the first time period, the output voltage formed at the second time is maintained for a second time period, and the first time period and the second time period are cyclically performed two or more times.

20. The power supply circuit of claim 19, whereina magnitude of the first voltage is the same as a magnitude of the fourth voltage; a magnitude of the second voltage is the same as a magnitude of the fifth voltage; anda magnitude of the third voltage is the same as a magnitude of the sixth voltage.

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