Compression compensation for power amplifer

Abstract

Compression compensation for power amplifiers is disclosed. In one aspect, a power amplifier may have a saturation detector associated with an output of an amplifier stage. The output of the saturation detector is provided to a plurality of comparators, which generate kick signals based on the output of the saturation detector exceeding respective predefined thresholds. The kick signals are then used by bias circuits or the like to boost input signals to compensate for compression and keep the outputs of the power amplifier stages more linear. Linear operation of the power amplifier stages allows for better compliance with the relevant wireless standards and improves the user experience, thereby.

Description

Ref. No. P241630-WO-UTL 1COMPRESSION COMPENSATION FOR POWER AMPLIFERPRIORITY APPLICATION

[0001] The present application is related to U.S. Provisional Patent Application Serial No. 63 / 748,483, filed on January 23, 2025, and entitled “COMPRESSION COMPENSATION FOR POWER AMPLIFIER,” the contents of which are incorporated herein by reference in their entirety.BACKGROUNDI. Field of the Disclosure

[0002] fhe technology of the disclosure relates generally to power amplifiers and techniques to provide compensation for compression caused by saturation of transistors in the power amplifier.II. Background

[0003] Computing devices abound in modem society, and more particularly, mobile communication devices have become increasingly common. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from pure communication tools into sophisticated mobile entertainment centers, thus enabling enhanced user experiences. With the advent of the myriad functions available to such devices, there has been increased pressure to find more bandwidth to convey data used by these functions. This demand for bandwidth has resulted in the continued evolution of wireless standards through the various generations (2G, 3G, 4G, 5G). With each generation, power amplifiers that boost signals for transmission are tasked with providing linear amplification across higher and wider frequency bands. Meeting the linearity requirements for the evolving wireless standards provides room for innovation.SUMMARY

[0004] Aspects disclosed in the detailed description include systems and methods for compression compensation for power amplifiers. In particular, a power amplifier mayWT Ref. No. 2867-3526-WORef. No. P241630-WO-UTL 2have a saturation detector associated with an output of an amplifier stage. The output of the saturation detector is provided to a plurality of comparators which generate kick signals based on the output of the saturation detector exceeding respective predefined thresholds. The kick signals are then used by bias circuits or the like to boost input signals to compensate for compression and keep the outputs of the power amplifier stages more linear. Linear operation of the power amplifier stages allows for better compliance with the relevant wireless standards and improves the user experience thereby.

[0005] While there are ample opportunities to use the saturation detectors of the present disclosure in front-end modules to assist in linear operation of the power amplifier stages, the present disclosure is not so limited. Information from the saturation detector may be provided to other elements in the transceiver such as a baseband processor and / or a power management circuit so that adjustments may be made to operation of such elements responsive to the conditions detected by the saturation detector so as to improve linear operation.

[0006] In this regard, in one aspect, a power amplifier is disclosed. The power amplifier includes an amplifier stage comprising an input and an output, a bias circuit coupled to the input, a saturation detection circuit coupled to the output and configured to provide a sensed power level signal, and a plurality of comparators coupled to the saturation detection circuit, each comparator configured to compare the sensed power level signal from the saturation detection circuit to a respective unique threshold, and at least one comparator responsive to the sensed power level signal exceeding the respective unique threshold providing a kick signal to the bias circuit to compensate for compression at the output.

[0007] In another aspect, a mobile communication device is disclosed. The mobile communication device includes a transceiver comprising a power amplifier. The power amplifier includes an amplifier stage comprising an input and an output, a bias circuit coupled to the input, a saturation detection circuit coupled to the output and configured to provide a sensed power level signal, and a plurality of comparators coupled to the saturation detection circuit, each comparator configured to compare the sensed power level signal from the saturation detection circuit to a respective unique threshold, and at least one comparator responsive to the sensed power level signal exceeding the respectiveWT Ref. No. 2867-3526-WORef. No. P241630-WO-UTL 3unique threshold providing a kick signal to the bias circuit to compensate for compression at the output.

[0008] In another aspect, a method of compensating for compression of a power amplifier is disclosed. The method includes sensing a saturation level with a saturation detector at an output of an amplifier stage, providing a sensed power level from the saturation detector to a plurality of comparators, each comparator having a respective unique threshold, responsive to the sensed power level exceeding a first unique threshold providing a first kick signal to a bias circuit associated with the amplifier stage and responsive to the sensed power level exceeding a second unique threshold providing a second kick signal to the bias circuit.

[0009] In another aspect, a communication system is disclosed. The communication system includes a baseband processor, BBP, comprising: a control circuit and a front-end module, FEM, coupled to the BBP comprising an amplifier chain, and a saturation detector associated with the amplifier chain and configured to detect compression by one or more amplifiers in the amplifier chain, wherein the saturation detector is configured to provide information relating to the compression to the BBP.BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a graph of output voltage levels versus time for a conventional power amplifier, where part of the waveform suffers from compression;

[0011] Figure 2 is a block diagram of a power amplifier with a compression compensation circuit according to aspects of the present disclosure;

[0012] Figure 3A is a block diagram of a multi-stage power amplifier with a compression compensation circuit according to aspects of the present disclosure;

[0013] Figure 3B is a graph showing how different thresholds for kick signals are generated responsive to changes in compression for the circuit of Figure 3A;

[0014] Figure 4 is a block diagram of a multipath, multi-stage power amplifier with a compression compensation circuit according to aspects of the present disclosure;

[0015] Figure 5 is a graph showing how different thresholds for kick signals are generated responsive to changes in compression for the circuit of Figure 4;WT Ref. No. 2867-3526-WORef. No. P241630-WO-UTL 4

[0016] Figure 6 is a block diagram of a multi-stage power amplifier with multiple saturation detectors working with the compression compensation according to aspects of the present disclosure;

[0017] Figure 7 is a block diagram of a differential multi-stage power amplifier with a compression compensation circuit according to aspects of the present disclosure;

[0018] Figure 8 is a block diagram of an adaptive bias circuit responsive to provide a threshold value for the comparators of the compression compensation circuits;

[0019] Figure 9 is a circuit diagram of the adaptive bias circuit of Figure 8;

[0020] Figure 10 is a circuit diagram of a bias circuit and comparator that provides the kick signal thereto responsive to saturation sensing;

[0021] Figure 11 A is a block diagram of saturation sensing circuitry with parasitic capacitance compensation;

[0022] Figure 11B is a block diagram of a differential amplifier saturation sensing circuitry that otherwise may be used in the circuit of Figure 11 A;

[0023] Figure 12 is a block diagram of saturation sensing circuitry with alternate parasitic capacitance compensation;

[0024] Figure 13A is a block diagram of a compression compensation circuit according to aspects of the present disclosure used with a Doherty amplifier;

[0025] Figure 13B is a block diagram of a true differential sensing approach for a differential power amplifier;

[0026] Figure 13C is a block diagram of a pseudo-differential sending approach for a differential power amplifier;

[0027] Figure 14 is a flowchart illustrating an exemplary process for compensating for compression according to aspects of the present disclosure;

[0028] Figure 15 is a block diagram of a mobile communication device, which may include the compression compensation circuit according to the present disclosure;

[0029] Figure 16 is a block diagram of a part of a communication system that highlights the interoperation of various elements and contextualizes use of the saturation detectors of the present disclosure;

[0030] Figure 17 is a block diagram of the communication system of Figure 16 with an added saturation detector configured to communicate with other elements to assist in operation of the communication device;WT Ref. No. 2867-3526-WORef. No. P241630-WO-UTL 5

[0031] Figure 18 is a block diagram of the communication system of Figure 17 with a cascaded communication link to a power management circuit through a baseband circuit;

[0032] Figures 19A & 19B illustrate an explicit envelope tracking (ET) power management circuit and an explicit average power tracking (APT) power management circuit, respectively used with saturation detection circuits of the present disclosure;

[0033] Figure 20 is a block diagram of the communication system of Figure 17 with an added temperature sensor to assist in control of various elements in the communication system;

[0034] Figure 21 A is a block diagram of the communication system of Figure 20 with the explicit API' power management circuit adjusting thresholds with the Vcc signal; and

[0035] Figure 21 B is a block diagram of the communication system of Figure 20 with the explicit ET power management circuit adjusting thresholds with an envelope voltage signal.DETAILED DESCRIPTION

[0036] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0037] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and similarly, a second element could be termed a first element without departing from the scope of the present disclosure. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0038] It will be understood that when an element, such as a layer, region, or substrate, is referred to as being “on” or extending “onto” another element, it can beWT Ref. No. 2867-3526-WORef. No. P241630-WO-UTL 6directly on or extend directly onto the other element, or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, no intervening elements are present. Likewise, it will be understood that when an element, such as a layer, region, or substrate, is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element, or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, no intervening elements are present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, no intervening elements are present.

[0039] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0040] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a," “an,” and “the” are intended to include the plural forms as well unless the context clearly indicates otherwise. It will be further understood that the terms “comprises," “comprising," “includes,” and / or “including,” when used herein, specify the presence of staled features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0041] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.WT Ref. No. 2867-3526-WORef. No. P241630-WO-UTL 7

[0042] In keeping with the above admonition about definitions, the present disclosure uses transceiver in a broad manner. Current industry literature uses “transceiver” in two ways. The first way uses transceiver broadly to refer to a plurality of circuits that send and receive signals. Exemplary circuits may include a baseband processor, an up / down conversion circuit, filters, amplifiers, couplers, and the like coupled to one or more antennas. A second way, used by some authors in the industry literature, refers to a circuit positioned between a baseband processor and a power amplifier circuit as a transceiver. This intermediate circuit may include the up / down conversion circuits, mixers, oscillators, filters, and the like, but generally does not include the power amplifiers. As used herein, the term transceiver is used in the first sense. Where relevant to distinguish between the two definitions, the terms “transceiver chain” and “transceiver circuit” are used, respectively.

[0043] Additionally, to the extent that the term “approximately” is used in the claims, it is herein defined to be within five percent (5%).

[0044] Aspects disclosed in the detailed description include systems and methods for compression compensation for power amplifiers. In particular, a power amplifier may have a saturation detector associated with an output of an amplifier stage. The output of the saturation detector is provided to a plurality of comparators, which generate kick signals based on the output of the saturation detector exceeding respective predefined thresholds. The kick signals are then used by bias circuits or the like to boost input signals to compensate for compression and keep the outputs of the power amplifier stages more linear. Linear operation of the power amplifier stages allows for better compliance with the relevant wireless standards and improves the user experience, thereby.

[0045] While there are ample opportunities to use the saturation detectors of the present disclosure in front-end modules to assist in linear operation of the power amplifier stages, the present disclosure is not so limited. Information from the saturation detector may be provided to other elements in the transceiver such as a baseband processor and / or a power management circuit so that adjustments may be made to operation of such elements responsive to the conditions detected by the saturation detector so as to improve linear operation.

[0046] Before addressing aspects of the present disclosure, a brief overview of the operation and compression of a power amplifier is provided with reference to Figure 1.WT Ref. No. 2867-3526-WORef. No. P241630-WO-UTL 8A discussion of aspects of the present disclosure begins below with reference to Figure 2. A discussion of aspects of the present disclosure in the broader context of the system of the communication device begins below with reference to Figure 16.

[0047] In this regard, Figure 1 illustrates a graph 100 showing output voltage for a power amplifier as a function of time and various radio frequency (RF) signals. The RF signals form a generally sinusoidal waveform around a supply voltage Vcc. As the signal strength increases, the portion 102 above Vcc grows, but the portion 104 below Vcc may be considered as two parts or regions. When the signal magnitude is generally less than Vcc, the waveform is generally undistorted in the first region 106. However, as the signal magnitude approaches or exceeds Vcc, the second region 108 experiences compression as the transistors in the power amplifier saturate. Further, the greater the signal magnitude, the longer the compression occurs (i.e., more of the waveform is flattened out, and the longer the transistor is saturated). Such compression results in non-linear operation of the power amplifier that may result in non-compliance with relevant wireless standards.

[0048] Aspects of the present disclosure contemplate adding a saturation sensor at an output of the power amplifier and using the sensed voltage in a plurality of comparators. Each of the comparators has a different threshold to which the sensed voltage is compared. When a threshold of a comparator is exceeded, indicative of a different level of compression at the output, a kick signal is provided from the respective comparator to a compensation circuit, such as a bias circuit, to boost an input and offset the compression. The different thresholds allow for different levels of compensation to be provided based on how much compression is occurring. Further, a time under compression may be evaluated to assist in determining how severe the compression is.

[0049] In this regard, Figure 2 illustrates a block diagram of a power amplifier 200 with compression compensation circuitry 202 associated therewith to compensate for different levels of compression at the output of the power amplifier 200. Specifically, the power amplifier 200 may have an input 204 and an output 206. In an exemplary aspect, the power amplifier 200 may include a transistor 208, which may be a bipolar junction transistor (B.TT) or the like. While only one transistor 208 is shown, it should be appreciated that multiple transistors may be present (e.g., cascoded). The input 204 may be coupled to a base of the BJT, and the output 206 may be coupled to a collector of theWT Ref. No. 2867-3526-WORef. No. P241630-WO-UTL 9BJT. In many cases, the power amplifier 200 and associated circuitry may be co-located in a package of one or more integrated circuits and / or external elements (e.g., an inductor may be a surface-mounted device in the package). Such a package may sometimes be referred to as a front-end module or FEM.

[0050] The output 206 may also be coupled to a power management integrated circuit (PMIC) 210, which may be an envelope tracker or average power tracker as needed or desired. The PMIC 210 may adjust a supply voltage provided for the output 206.

[0051] The output 206 is also coupled to the compression compensation circuitry 202. More particularly, the output 206 is coupled to a negative waveform selector and level shifter circuit 212. Additional details of this circuit 212 are provided below with reference to Figures 11 A- 12, but for this part of the discussion, the circuit 212 provides a sensed voltage signal (Vsense) boosted by a static bias circuit 214 to comparators 216( 1 )-216(N) where, as illustrated, N = 3. The comparators 216(1)-216(N) also receive comparison threshold signals from a multi -threshold generator circuit 218. As Vcc may change at high signal levels, the reference voltages used by the multi -threshold generator circuit 218 may need adjustment. That is, threshold signals are adjusted by a transistor 220 that maintains a saturated state regardless of Vcc through the use of a circuit 222. The transistor 220 matches and tracks the transistor 208 across process, temperature, and voltage variations, and may be further modified by a dynamic threshold adjustment circuit 224. The comparators 216(1)-216(N) output kick signals (Ip, In) that are used to change the signals for the power amplifier 200. The use of multiple comparators 216(1 )-216(N) allows for different thresholds to generate different kick signals, which may, in turn, change a magnitude or slope of compression compensation provided.

[0052] Note that the power amplifier 200 is not limited to a single stage, as illustrated in Figure 2, but rather, as illustrated in Figure 3A, the power amplifier 200 may be multiple amplifier stages 300(l)-300(M), where, as illustrated, M=3. The compensation circuitry 202 of Figure 2 is generalized into a saturation detection circuit 302 that provides kick signals to bias circuits 304(1 )-304(M). Thus, the saturation detection circuit 302 includes the level shifter circuit 212, the comparators 216(1)-216(N), and the multithreshold generator circuit 218.

[0053] The sensed voltage at the output 206 may exhibit different levels of compression depending on the input power, as illustrated in Figure 3B, where graph 340WT Ref. No. 2867-3526-WORef. No. P241630-WO-UTL 10shows the output power as a function of input power. Right before the transistors (e.g., transistor 208) begin to saturate at point 342, compression starts with a first slope. At a second point 344, the slope changes to a much steeper slope. Accordingly, a first kick signal (Pthl) may be generated for one of the bias circuits 304(l)-304(M) at a first input power 346 (even though the sensed voltage is the output power). It may be easier to offset early compression at a driver stage amplifier (e.g., power amplifier stage 300(2)) or even a predriver stage amplifier (e.g., power amplifier stage 300(M)). At a later compression or at input power 348, the second kick signal (e.g., Pth2) is generated and sent to another one of the bias circuits 304(l)-304(M).

[0054] It should be appreciated that not every bias circuit 304(1 )-304(M) needs to receive a kick signal, and kick signals for different bias circuits 304(1 )-304(M) may be triggered at different thresholds. Further, the amount of compression compensation a given one of the bias circuits 304(l)-304(M) provides may be varied as needed or desired. Further, the compression curves may be more than just two slopes, and thus, there may be thresholds that effectively indicate how deeply into compression the saturation detection circuit 302 senses. In essence, more stages and more thresholds provide more granularity in compression compensation.

[0055] While the above discussion has focused on single-ended power amplifiers, the present disclosure is not so limited. Thus, as illustrated in Figure 4, the power amplifier 200 of Figure 2 may be a multi-path power amplifier 400 that has a combiner 402 before the output 206. The power amplifier 400 has a first path 404(1) and a second path 404(2), each with respective optional predriver amplifiers 406(1), 406(2), driver amplifiers 408(1), 408(2), and output amplifiers 410(1), 410(2). The first path 404(1) may differ from the second path 404(2) by a 90-degree phase shift induced by a shift circuit 412. The saturation detection circuit 302 may provide kick signals to different ones of the bias circuits 414(1)-414(R) in the different paths 404(1), 404(2) based on different thresholds. In an exemplary aspect, where the power amplifier 400 is a Doherty amplifier, the initial thresholds affect the primary path (e.g., the first path 404(1)) before affecting the peaking path (e.g., the second path 404(2)).

[0056] Figure 5 illustrates graph 500, showing the compression of Figure 3B, as well as thresholds 502, 504, 506, where kick signals are generated for different bias circuits 414(1)-414(R).WT Ref. No. 2867-3526-WORef. No. P241630-WO-UTL 11

[0057] Note further that there may be multiple saturation detection circuits, as better illustrated in Figure 6. The saturation detection circuits may be associated with outputs of different ones of the amplifiers stages 3OO(1)-3OO(M). To prevent conflict, a first saturation detection circuit 600 may provide kick signals to all bias circuits 602(1)-602(M), while other saturation detection circuits 604 may provide kick signals only to their respective bias circuit 602(2). Still other permutations of this concept are also within the present disclosure.

[0058] Further, there may be multiple saturation detection circuits for multi-path amplifiers, as better illustrated in Figure 7. Unlike Figure 4, the first path 404(1) and the second path 404(2) both have saturation detector circuits 700(1), 700(2), which operate with different ones (or multiple ones) of the bias circuits 414(1)-414(R). Note that each path may have multiple saturation detector circuits (not shown, but similar to Figure 6), although at some point, the increased granularity provided reaches the point of diminishing returns.

[0059] As alluded to above, it may be appropriate to adjust the reference voltage used by the comparators when Vcc changes as a function of large signal levels. This change may be made by keeping the reference transistor 220 in saturation by an adaptive bias circuit 800, which, in Figure 8, is two current sources 802, 804. The current sources 802, 804 keep the collector of the transistor 220 at a constant ratio relative to the base of the transistor 220 and thus keep the transistor 220 saturated to provide a constant reference. The transistor 220 may be co-located with the transistors of the power amplifier so that PVT variations are kept to a minimum.

[0060] One way to implement the current sources 802, 804 is illustrated in Figure 9. Specifically, Vcc may be coupled to the base of the transistor 220 through a unidirectional diode 900 (e.g., a Schottky diode) and a resistor 902. The diode 900 prevents negative current flow when Vcc drops below Vce of the transistor 220. Vcc is also coupled to the collector of the transistor 220 through a resistor 904. Note that there may be situations where Vcc gets below Vbe plus the drop of the diode 900 and is unable to turn on the transistor 220. Thus, an additional voltage is provided to lift the base to a level where it can turn on. This additional voltage may be Vreg or Vbatt (battery) as needed or desired and may go through a resistor 906. This additional voltage makes sure that the transistor 220 remains in saturation even at low Vcc.WT Ref. No. 2867-3526-WORef. No. P241630-WO-UTL 12

[0061] Figure 10 provides additional details about exemplary comparators that may be used in the present disclosure. The output of the negative waveform selector and level shifter circuit 212 is provided at a base of a first transistor 1000. A second transistor 1002 provides a mirror, and a third transistor 1004 provides a tail current to the first and second transistors 1000, 1002. The first transistor 1000 provides the signal Ip, and the second transistor 1002 provides the signal In (see Figure 2). The second transistor 1002 gets a signal from the transistor 220 (also referred to as the saturation reference threshold generator in Figure 10). A bias current generator 1006 (which may be provided either by a current source 1008 or a voltage source 1010 with a bias resistor 1012) provides a bias current to two diode-connected transistors 1014, 1016. A resistor 1018 in the diode connection of the transistor 1014 makes it an amplifier. A capacitor 1020 acts as a filter. A resistor 1022 provides a voltage drop to an emitter- follower transistor 1024 such that when Ip is positive, the power amplifier 200 is debiased. However, above the threshold, Ip goes to zero, and In increases. As In increases, the debias of the power amplifier 200 goes away, leaving the voltage drop across the diode-connected transistors 1014, 1016, and the resistors to provide a positive bias on the power amplifier 200.

[0062] Figure 11A illustrates additional detail about the negative waveform selector and level shifter circuit 212. Specifically, diodes 1100, 1102 sense the negative side of the waveform. Specifically, when the voltage (sometimes called VCE) at the output 206 is positive, the diodes 1100, 1102 are off. When VCE goes down to saturation levels, the diodes 1100, 1102 turn on and pull the comparators 216(1)-216(N). The static bias circuit 214 (which may be a weak pull-up bias) lifts the waveform at the output 206 to provide Vsense. However, these diodes 1100, 1102 have a parasitic capacitance (shown as 1104 and sometimes referred to as Cpar) that may introduce some part of the RF signal and perturb Vsense. To balance things, an equivalent RF signal is added to the input on the other input of the comparators 216(1)-216(N). As such, the different threshold levels may not be constant voltages, but they include the same amount of RF signal from the output 206 that balances the RF signal through the parasitic capacitance 1104. However, to avoid the sensed signal from damaging the multi -threshold generator circuit 218, back-to-back diodes 1106, 1108 are provided in each signal line for each comparator 216(1)-216(N). The back-to-back diodes 1106, 1108 provide parasitic capacitances 1110, 1112. The back-to-back diodes 1106, 1108 are connected such that one (e.g., diode 1106) is inWT Ref. No. 2867-3526-WORef. No. P241630-WO-UTL 13the ON state and thus has a much larger capacitance when compared to the capacitance 1104, while the other diode (e.g., diode 1108) is in the OFF state that has a capacitance that balances Cpar. Thus, the diode 1108, which is OFF, balances and the diode 1106, which is ON, provides DC blocking.

[0063] The basic concept of the circuit 212 can be extended to a differential power amplifier as seen in Figure 1 IB. Specifically, differential amplifier 1150 is formed from a first amplifier 1152, and a second amplifier 1154. A first sensor 1156 for the first amplifier 1152, is formed from two diodes having an effective capacitance. A second sensor 1158 for the second amplifier 1154 is formed from two additional diodes also having an effective capacitance. In the case of a differential output, the differential amplifier has two outputs that are usually operating in opposition of the phase. As such, there are two waveforms that can be sensed and thus two measurements per signal cycle. This will reduce delay in the saturation detector, leading to higher detector bandwidth and allowing the sensor to operate with signals that have larger modulation bandwidth.

[0064] Figure 12 provides an alternate implementation that reduces the need for imbalanced diodes 1106, 1108 to provide better matching. Specifically, back-to-back diodes 1200, 1202 have a center node 1204 that is biased from ground through large resistors 1206 that minimize leakage current in the diodes 1200, 1202. In some cases, the lines from the multi-threshold generator circuit 218 may include bypass filtering capacitors 1208. It is also possible that the sense node 1210 has a holding capacitance to ground Chold. When present, the ratios of Cpar-to-Chold and Cpar-to-Ccomp are matched to ensure the common-mode rejection of the feedthrough RF signal from the output 206.

[0065] The above discussion mostly contemplates addressing compression at the output device (e.g., output amplifier stage 300(1)). However, at high power levels, the compression may occur not only in the output device but also in driver stages or even predriver stages. As such, an additional gain boost may be applied to compensate. Furthermore, at sufficiently high power levels, the sensitivity of the detectors may be reduced because the voltage has reached the VCEsat level, and as the power amplifier goes further into compression, only a small increase in the signal duty cycle happens. This situation also reduces the gain of any amplitude pre-distortion loop. Accordingly, an extra kick may be used. Such additional kick can be created by increasing VCEsatWT Ref. No. 2867-3526-WORef. No. P241630-WO-UTL 14reference voltage at high levels. This change in VCEsat may be done by providing a signal that activates only at high power levels. If the power amplifier 200 is a Doherty amplifier, such a signal can be provided by the peaking path (which already only activates at high power levels). The boost of VCEsat can be generated either by using a DC signal 1302 from a bias circuit 1300 of the peaking path 1304 illustrated in Figure 13A. Alternatively, the signal may come from the RF signal from the peaking path 1304 (see generally signal 1308). This RF signal may be converted to a baseband signal that is only active at high power levels. The boost signal (Iboost) may be provided through a boost resistor 1310 to the reference transistor 220.

[0066] There are two main ways to build a saturation detector for a power amplifier with a differential output. Figure 13B shows a true differential saturation detector, and Figure 13C shows a pseudo-differential saturation detector. The saturation detector has two sections: the RF section, with the two sensing branches 1330, 1332 connected to the differential output of the power amplifier 1334, and the baseband section, which is passed to the Chold capacitor 1336. An advantage of the true-differential saturation detector is that the RF signal is largely canceled at the Chold capacitor 136, and essentially, only baseband signals are present in the back-end of the saturation detector. From this perspective, it can be said that the true differential saturation detector has a first-order RF feedthrough cancellation, and there is no need for special techniques to neutralize or reduce the RF feedthrough. Again, output from this detector may be compared to multiple thresholds and multiple kick signals supplied to various bias circuits or the like.

[0067] Offsetting advantages of the true differential saturation detector of Figure 13B is that the slew-rate at the sensing node is not that large, and therefore the detector may not be able to follow fast-changing envelope signals, reducing the maximum modulation bandwidth the detector can follow. An alternate way to implement the detector is shown as a pseudo-differential scheme in Figure 13C. Each output node 1340, 1342 is coupled to a respective sensor 1344, 1346, which has its own holding nodes 1348, 1350. In this manner, the RF signal is not canceled at the sensing nodes, and the slew rate is relatively large. Two comparators 1352, 1354 may be used to sense when each side of the amplifier goes below the threshold voltage. The outputs of the comparators 1352, 1354 may be summed, and only at this node 1356 will the RF signal have its first order reduction.WT Ref. No. 2867-3526-WORef. No. P241630-WO-UTL 15

[0068] Figure 14 provides a flowchart of a process 1400 for using the compression compensation circuits of the present disclosure. In particular, the process 1400 begins by receiving a signal at the input 204 of a power amplifier 200 (block 1402). A circuit senses voltage at the output 206 (block 1404). The sensed voltage is compared to a first threshold (block 1406). If Vout > T1 (block 1408), a kick signal is sent to a first compensation circuit (e.g., a bias circuit) (block 1410). If Vout > T2 (block 1412), a kick signal is sent to a second compensation circuit (block 1414), and so on through the thresholds until compression reverses (block 1416) (i.e., on the upswing of the RF signal).

[0069] It should be noted that having acquired data about the conditions in the frontend module (e.g., through saturation detection at an output of the power amplifier), this data may have use outside the front-end module. For example, a baseband processor may set parameters based on information available to the BBP, but the BBP lacks ready access to information about the conditions inside the FEM. Similarly, a power management circuit (sometimes referred to as a power management integrated circuit or PMIC) may set parameters based on information from the BBP, but also lacks ready access to information about the conditions inside the FEM. Accordingly, aspects of the present disclosure contemplate providing information from the saturation detector and / or the temperature sensor to elements outside the FEM.

[0070] While specifically contemplated for cellular systems, it should be noted that aspects of the present disclosure are not so limited and may be applicable to other protocols such as WiFi, BLUETOOTH, ultrawideband (UWB), and the like.

[0071] In this regard, Figure 16 illustrates a modem 1600 with a FEM 1602 coupled to a BBP 1604 and a PMIC 1606. Note that the BBP 1604 may be a multi-chip set. The BBP 1604 may have a control circuit 1608 and a baseband modulator 1610. The control circuit 1608 may calculate a desired modulation scheme with a variety of parameters (or receive instructions from a remote source, such as a remote base station) with these parameters. These parameters may include frequency band, frequency channel, modulation type, bandwidth, and the like. These parameters may dictate changes in the operation of the FEM 1602, the PMIC 1606, and / or a transceiver circuit 1612.

[0072] Accordingly, based on the knowledge of the parameters, the control circuit 1608 may send information relating to settings to be used for transmission to the FEM 1602, the PMIC 1606, and the transceiver circuit 1612 through a bus 1614, which may,WT Ref. No. 2867-3526-WORef. No. P241630-WO-UTL 16for example, be a radio frequency front end (RFFE) bus compliant with the RFFE standard published by MIPI.

[0073] However, the BBP 1604 has little or no native awareness of what is happening at the FEM 1602 or at the load 1616 (e.g., an antenna). Thus, for example, environmental conditions 1618, such as temperature, VSWR, or the like that change the operation of an amplifier chain 1620 in the FEM 1602, are not considered when sending the settings from the BBP 1604.

[0074] The information from the saturation detector described above may act as a proxy for some of the environmental conditions 1618, and, if there were a mechanism to send such information to the BBP 1604, the settings could be controlled to offset the environmental conditions. Thus, while specific or precise environmental conditions (e.g., load impedance) may be obfuscated, knowing that the power amplifiers in the amplifier chain 1620 have started to compress can be used to take action to improve linearity, such as by changing the pre-distortion linearization coefficients, modifying settings within the transceiver circuit 1612, or the like. Aspects of the present disclosure contemplate sending information from the saturation detector and / or a temperature sensor to the BBP 1604 for this purpose.

[0075] In this regard, Figure 17 illustrates a modem 1700 that includes a saturation detector 1702 in the FEM 1602’. The saturation detector 1702 may directly communicate with APD circuitry 1704 in the FEM 1602’. Further, the saturation detector 1702 may communicate with the BBP 1604’ and the PMIC 1606’. The BBP 1604’ may send out modified setting information through the bus 1614’ while the PMIC 1606’ independently calculates any setting modifications needed responsive to the information from the FEM 1602’.

[0076] Alternatively, the information from the saturation detector 1702 can be provided initially to the BBP 1604’ and from there to the PMIC 1606’ as shown in modem 1700’ illustrated in Figure 18. While not shown, there may also be a direct connection between the saturation detector and the transceiver circuit, or there may be indirect communication through the BBP 1604’. as shown in Figure 17. It should be noted that any of the buses contemplated may be analog or digital, and the signals may be analog or digital signals. Still further, it is possible that an existing analog line may be shared. For example, the PMIC may provide the analog Vbias supply signal to the FEM. UnderWT Ref. No. 2867-3526-WORef. No. P241630-WO-UTL 17certain circumstances, a low swing digital signal can be transmitted through the existing analog line. Note further that the raw data from the saturation detector may be processed, and post-processed data sent to the other elements (e.g., the BBP, the PMIC, etc.).

[0077] Note that in any of these implementations, the saturation detector 1702 may have a relatively high sample rate, resulting in information that is changing at a relatively high frequency. The bus 1614’ may be used to convey this information, but in instances where the bus 1614’ is an RFFE-compliant bus, the frequency of information changes may exceed the bandwidth or clock speed of the RFFE-compliant bus. Thus, it is possible that a dedicated auxiliary bus may be provided. This auxiliary bus may be USB-compliant, PCIe-compliant, or the like to accommodate the high data rate. Likewise, there may be multiple buses between the different elements.

[0078] While the previous Figures have provided a generic PMIC 1606’, it should be appreciated that the PMIC 1606’ may be an envelope tracking (ET) PMIC 1902, as shown in modem 1900 A in Figure 19 A, or an average power tracking (APT) PMIC 1904, as shown in modem 1900B in Figure 19B.

[0079] Note that different elements may want to receive different types of information from the saturation detector. To this end, there may be different comparators associated with the saturation detector that trigger different signals to be conveyed, as better shown in Figure 20. In this regard, a modem 2000 includes a FEM 2002, a BBP 2004, and a PMIC 2006. The FEM 2002 includes a temperature sensor 2008 and a saturation detector 2010. The saturation detector 2010 may provide a signal to a plurality of comparators 2012(l)-2012(N) keyed to different thresholds. When a first threshold is surpassed (e.g., as indicated by the comparator 2012(1)), a first signal is provided to the various elements (e.g., the BBP 2004, the PMIC 2006, an APD circuit 2014, etc.). When a second threshold is surpassed (e.g., as indicated by the comparator 2012(2)), a second signal is provided to the various elements, and so on through the different comparators 2012(l)-2012(N). Still further, the thresholds may be a function of temperature, where the temperature sensor 2008 reports to a temperature threshold control circuit 2016 that sets thresholds for the comparators 2012(l)-2012(N). Note also that one or more filters 2018(1 )-2018(N) may be provided for the signal from the saturation detector 2010.

[0080] Note that different elements may react to different thresholds being exceeded. For example, only the APD circuit 2014 may make adjustments when the first thresholdWT Ref. No. 2867-3526-WORef. No. P241630-WO-UTL 18is exceeded, while both the PMIC 2006 and the BBP 2004 respond to the second threshold being exceeded (with no further adjustments from the APD circuit 2014), and all elements respond to the Nth threshold being exceeded. Those skilled in the art can envision mixing and matching thresholds and responses as needed or desired.

[0081] Figures 21A & 21B are similar to Figures 19A & 19B but highlight how the different PMICs can also provide signals to assist in controlling dynamic thresholds. More specifically, as illustrated in Figure 21 A, a modem 2100A may use an APT PMIC 2106, which provides a dynamic Vcc supply voltage signal to the amplifier chain 2108 and to the dynamic threshold control circuit 2116. The dynamic threshold control circuit 2116 may then set the threshold for the comparators 2012(l)-2012(N) as a function of the supply voltage and the temperature.

[0082] Similarly, in Figure 21B, a modem 2100B may use an ET PMIC 2126. The BBP 2004 may provide a dynamic envelope signal Ven-et to both the ET PMIC 2126 and to the dynamic threshold control circuit 2136. The dynamic threshold control circuit 2136 may then set the threshold for the comparators 2012(l)-2012(N) as a function of the envelope voltage and the temperature.

[0083] Note also that this expansion of the use of the saturation detectors works both in single-path amplifier chains and multi-path amplifier chains and may also work with multiple saturation detectors positioned at various points along the amplifier chain (i.e., not just at the output as illustrated). Examples include, but are not limited to, Doherty amplifiers, quadrature amplifiers, load modulated balanced amplifiers (LMBA), and the like.

[0084] Note also that aspects of the present disclosure also work with more complex communication devices that have multiple baseband processors, multiple transceivers, multiple FEM, and / or multiple PMICs. Different saturation detectors and different thresholds may trigger different responses from such multi-element communication devices.

[0085] The power amplifiers with compression compensation according to aspects disclosed herein may be provided in or integrated into any processor-based device. Examples, without limitation, include a set-top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smartphone,WT Ref. No. 2867-3526-WORef. No. P241630-WO-UTL 19a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smartwatch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter. Additionally, while the above discussion contemplates mobile computing devices, as evidenced by this list, the present disclosure is not so limited and any power amplifiers may benefit from the present disclosure. Further, infrastructure supporting mobile computing devices that include transmitters with power amplifiers may also benefit from the present disclosure.

[0086] Figure 15 is a schematic diagram of an exemplary communication device 1500 wherein the power amplifiers with compression compensation can be provided, for example, in transmission chains. Herein, the communication device 1500 can be any type of communication device, such as those listed above as well as access points, base stations (e.g., eNB or gNB), and any other type of wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, Ultra- wideband (UWB), and near field communications.

[0087] More particularly, the communication device 1500 will generally include a control system 1502, a baseband processor 1504, transmit circuitry 1506, receive circuitry 1508, antenna switching circuitry 1510, multiple antennas 1512, and user interface circuitry 1514. In a non- limiting example, the control system 1502 can be a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), as an example. In this regard, the control system 1502 can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receive circuitry 1508 receives radio frequency signals via the antennas 1512 and through the antenna switching circuitry 1510 from one or more base stations. A low noise amplifier and a filter of the receive circuitry 1508 cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signalWT Ref. No. 2867-3526-WORef. No. P241630-WO-UTL 20to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter(s) (ADC).

[0088] The baseband processor 1504 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations. The baseband processor 1504 is generally implemented in one or more digital signal processors (DSPs) and ASICs.

[0089] For transmission, the baseband processor 1504 receives digitized data, which may represent voice, data, or control information, from the control system 1502, which it encodes for transmission. The encoded data is output to the transmit circuitry 1506, where a digital-to- analog converter) s) (DAC) converts the digitally encoded data into an analog signal, and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier, such as the power amplifiers with compression compensation circuitry described above will amplify the modulated carrier signal to a level appropriate for transmission and deliver the modulated carrier signal to the antennas 1512 through the antenna switching circuitry 1510 to the antennas 1512. The multiple antennas 1512 and the replicated transmit and receive circuitries 1506, 1508 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0090] It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications, as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents,WT Ref. No. 2867-3526-WORef. No. P241630-WO-UTL 21electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0091] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.WT Ref. No. 2867-3526-WO

Claims

Ref. No. P241630-WO-UTL 22What is claimed is:

1. A power amplifier comprising:an amplifier stage comprising an input and an output;a bias circuit coupled to the input;a saturation detection circuit coupled to the output and configured to provide a sensed power level signal; anda plurality of comparators coupled to the saturation detection circuit, each comparator configured to compare the sensed power level signal from the saturation detection circuit to a respective unique threshold, and at least one comparator responsive to the sensed power level signal exceeding the respective unique threshold providing a kick signal to the bias circuit to compensate for compression at the output.

2. The power amplifier of claim 1, further comprising:a driver stage, the driver stage comprising a driver input and a driver output, the driver output coupled to the input; anda driver bias circuit coupled to the driver input.

3. The power amplifier of claim 2, further comprising a second saturation detection circuit coupled to the driver output.

4. The power amplifier of claim 2, wherein a second comparator, responsive to the sensed power level signal exceeding the respective unique threshold, provides a second kick signal to the driver bias circuit.

5. The power amplifier of claim 1, wherein the amplifier stage is single-ended.

6. The power amplifier of claim 1, wherein the amplifier stage is differential-ended.

7. The power amplifier of claim 1 , wherein the saturation detection circuit comprises a plurality of diodes.WT Ref. No. 2867-3526-WORef. No. P241630-WO-UTL 238. The power amplifier of claim 1, further comprising a plurality of bias circuits, wherein a second comparator is responsive to the sensed power level signal exceeding the respective unique threshold, provides a second kick signal to a second bias circuit in the plurality of bias circuits.

9. The power amplifier of claim 1, further comprising a multi -threshold generation circuit coupled to the plurality of comparators.

10. The power amplifier of claim 9, further comprising a saturated transistor coupled to the multi-threshold generation circuit.

11. The power amplifier of claim 1 integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smartphone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.

12. A mobile communication device comprising:a transceiver comprising a power amplifier, the power amplifier comprising: an amplifier stage comprising an input and an output;a bias circuit coupled to the input;a saturation detection circuit coupled to the output and configured to provide a sensed power level signal; anda plurality of comparators coupled to the saturation detection circuit, each comparator configured to compare the sensed power level signal from the saturation detection circuit to a respective unique threshold, and at least one comparator responsiveWT Ref. No. 2867-3526-WORef. No. P241630-WO-UTL 24to the sensed power level signal exceeding the respective unique threshold providing a kick signal to the bias circuit to compensate for compression at the output.

13. A method of compensating for compression of a power amplifier, comprising:sensing a saturation level with a saturation detector at an output of an amplifier stage;providing a sensed power level from the saturation detector to a plurality of comparators, each comparator having a respective unique threshold;responsive to the sensed power level exceeding a first unique threshold, providing a first kick signal to a bias circuit associated with the amplifier stage; and responsive to the sensed power level exceeding a second unique threshold, providing a second kick signal to the bias circuit.

14. The method of claim 13, further comprising sensing saturation levels at a second stage with a second saturation detector.

15. The method of claim 13, further comprising providing a third kick signal to a second bias circuit.

16. The method of claim 13, wherein the amplifier stage is single-ended.

17. The method of claim 13, wherein the amplifier stage is differential-ended.

18. A communication system comprising:a baseband processor, BBP, comprising:a control circuit;a front-end module, FEM, coupled to the BBP comprising:an amplifier chain; anda saturation detector associated with the amplifier chain and configured to detect compression by one or more amplifiers in the amplifier chain, wherein the saturation detector is configured to provide information relating to the compression to the BBP.WT Ref. No. 2867-3526-WORef. No. P241630-WO-UTL 2519. The communication system of claim 18, wherein the BBP comprises a chip set.

20. The communication system of claim 18, further comprising a power management circuit, wherein the saturation detector is configured to provide information relating to the compression to the power management circuit.

21. The communication system of claim 20, wherein the power management circuit comprises an average power tracking power management circuit.

22. The communication system of claim 20, wherein the power management circuit comprises an envelope tracking power management circuit.

23. The communication system of claim 18, further comprising a temperature sensor configured to detect a temperature within the amplifier chain, wherein the saturation detector detects compression based at least in part on a sensed temperature.

24. The communication system of claim 18, wherein the FEM further comprises an analog predistortion circuit, and the saturation detector is configured to provide information relating to the compression to the analog predistortion circuit.

25. The communication system of claim 20, wherein the saturation detector is configured to provide the information to the power management circuit through the BBP.

26. The communication system of claim 21 , wherein the saturation detector comprises a comparator and the comparator is configured to compare a sensed voltage from the amplifier chain to a threshold when detecting compression.

27. The communication system of claim 26, wherein the threshold is a function of a supply voltage from the average power tracking power management circuit.WT Ref. No. 2867-3526-WORef. No. P241630-WO-UTL 2628. The communication system of claim 22, wherein the saturation detector comprises a comparator and the comparator is configured to compare a sensed voltage from the amplifier chain to a threshold when detecting compression.

29. The communication system of claim 28, wherein the threshold is a function of an envelope tracking voltage signal from the BBP.

30. The communication system of claim 18, wherein the FEM further comprises a distortion detector.

31. The communication system of claim 30, wherein the distortion detector is selected from the group consisting of: a second saturation detector, a compression detector, an expansion detector, and a nonlinearity detector.

32. The communication system of claim 18, wherein the FEM further comprises a plurality of saturation detectors.

33. The communication system of claim 18, further comprising a plurality of BBP and a plurality of FEM.

34. The communication system of clam 18, wherein the information comprises a proxy for environmental conditions in the FEM.WT Ref. No. 2867-3526-WO

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