Dual-helix quantum architecture for accelerated quantum workload execution

Abstract

A method of operating a quantum computing system may include scheduling quantum gate operations across quantum nodes arranged along two intertwined helices based on angular adjacency and executing quantum gate operations concurrently on different subsets of the quantum nodes such that no quantum node participates in more than one quantum gate operation during a scheduling interval. The method may further include transferring quantum states between subsets of quantum nodes using inter-helix quantum couplers.

Description

Atorney Docket No. H7019.10012W001DUAL-HELIX QUANTUM ARCHITECTURE FOR ACCELERATED QUANTUM WORKLOAD EXECUTIONRELATED APPLICATIONS

[0001] This application claims the benefit of and priority to U.S. Non-Provisional Application No. 19 / 455,642 filed on January 21, 2026, U.S. Non-Provisional Application No. 19 / 455,631, filed on January 21, 2026, U.S. Non-Provisional Application No.19 / 455,637, filed on January 21, 2026, U.S. Non-Provisional Application No. 19 / 455,619, filed on January 21, 2026, all of which claim the benefit of and priority to U.S. Provisional Application No. 63 / 749,253 filed on January 24, 2025, U.S. Provisional Application No.63 / 753,176 filed on February 3, 2025, U.S. Provisional Application No. 63 / 753,181 filed on February 3, 2025, and U.S. Provisional Application No. 63 / 748,910 filed on January 23, 2025, the entire contents of which are hereby incorporated by reference in their entireties.TECHNICAL FIELD

[0002] The present disclosure relates to a dual-helix quantum architecture for accelerated quantum workload execution.BACKGROUND

[0003] Unless otherwise indicated herein, the materials described herein are not prior art to the claims in the present application and are not admitted to be prior art by inclusion in this section.

[0004] Quantum computing systems utilize quantum mechanical phenomena such as superposition and entanglement to perform computations that may be infeasible for classical computing systems. As quantum hardware scales, architectural organization, routing efficiency, and execution coordination become increasingly significant challenges.

[0005] Artificial intelligence workloads, including neural network training, optimization, and inference, impose additional demands on quantum computing systems. Such workloads often require repeated parameter updates, structured data flow, parallel execution, and coordination between quantum and classical processing components. Conventional planar quantum architectures may encounter limitations in scalability, routing complexity, and execution efficiency when applied to these workloads.

[0006] Accordingly, there is an ongoing need for quantum computing architectures and execution frameworks that improve spatial organization, support parallel execution, andAtorney Docket No. H7019.10012W001provide flexibility for a wide range of quantum algorithms and artificial intelligence workloads.

[0007] The subject matter claimed herein is not limited to embodiments that solve any disadvantages or that operate only in environments such as those described above. Rather, this background is only provided to illustrate one example technology area where some embodiments described herein may be practiced.SUMMARY

[0008] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential characteristics of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0009] A method of operating a quantum computing system may include scheduling quantum gate operations across quantum nodes arranged along two intertwined helices based on angular adjacency and executing quantum gate operations concurrently on different subsets of the quantum nodes such that no quantum node participates in more than one quantum gate operation during a scheduling interval. The method may further include transferring quantum information between subsets of quantum nodes using inter-helix quantum couplers.

[0010] Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The features and advantages of the invention may be realized and obtained by means of the instruments and combinations particularly pointed out in the appended claims. These and other features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.BRIEF DESCRIPTION

[0011] The present application can be best understood by reference to the embodiments described below taken in conjunction with the accompanying drawing figures, in which like parts may be referred to by like numerals.

[0012] FIG. 1A illustrates an example quantum computing system that includes a dualhelix quantum architecture.Atorney Docket No. H7019.10012W001

[0013] FIG. IB illustrates an example implementation of a quantum processing unit (QPU) included in the quantum computing system of FIG. 1 A.

[0014] FIG. 2 is a view of an example dual-helix quantum architecture showing interleaved A-helix chain and B- helix chain quantum nodes.

[0015] FIG. 3 is view illustrating an example spiral-unwrapped placement of quantum nodes on the A- helix chain and B- helix chain and quantum links between the quantum nodes.

[0016] FIG. 4 illustrates an example process flow for quantum computing using a dualhelix quantum architecture.

[0017] FIG. 5 depicts a flowchart of an example method of quantum computing.

[0018] FIG. 6 depicts a flowchart of another example method of quantum computing.

[0019] FIG. 7 depicts a flowchart of another example method of quantum computing.

[0020] FIG. 8 depicts a flowchart of another example method of quantum computing.

[0021] FIG. 9 depicts a flowchart of another example method of quantum computing.

[0022] FIG. 10 depicts a flowchart of another example method of quantum computing.DETAILED DESCRIPTION

[0023] To provide a more thorough understanding of various embodiments of the present invention, the following description sets forth numerous specific details, such as specific configurations, parameters, examples, and the like. It should be recognized, however, that such description is not intended as a limitation on the scope of the present invention but is intended to provide a beter description of the exemplary embodiments.

[0024] Quantum computing technologies have advanced significantly; however, scaling quantum systems introduces challenges related to execution coordination, routing overhead, and error accumulation. As the number of quantum nodes increases, the physical arrangement of those nodes and the manner in which quantum operations are scheduled become increasingly significant.

[0025] Conventional quantum architectures often rely on planar layouts or abstract connectivity graphs that may require frequent state-swapping or long-range routing operations. Such approaches can increase circuit depth and reduce execution fidelity. Accordingly, there is a need for quantum computing architectures that provide deterministic spatial organization and support efficient execution of quantum operations.

[0026] In some embodiments, these challenges are addressed by arranging quantum nodes along two intertwined helices. The dual-helix structure provides a three-dimensional spatialAtorney Docket No. H7019.10012W001organization in which adjacency relationships among quantum nodes are well-defined both along a helix and across the two helices. This geometry enables structured execution of quantum operations with reduced routing overhead.

[0027] Each quantum node may be assigned a spatial coordinate derived from its angular position along a helix. The spatial coordinate may be used by a control system to identify neighboring quantum nodes, determine permissible quantum gate connections, and schedule execution of quantum operations based on geometric proximity.

[0028] In some embodiments, quantum operations are scheduled such that gate connections are restricted to physically adjacent or geometrically proximate quantum nodes. Restricting gate connections in this manner may reduce the need for long-range quantum gates or state-swap operations, thereby reducing circuit depth and execution errors.

[0029] Quantum gate operations may be organized into execution layers and sublayers. Within a sublayer, no quantum node participates in more than one quantum gate operation, enabling conflict-free parallel execution of multiple quantum gates across different subsets of quantum nodes.

[0030] The dual-helix architecture further supports execution of quantum operations between quantum nodes positioned on different helices through inter-helix couplers. These couplers enable quantum-mechanical interaction, including state transfer or entangling operations between corresponding or nearby nodes on the two helices, without requiring multi -hop routing.OVERVIEW OF DUAL-HELIX QUANTUM ARCHITECTURE

[0031] In general, a quantum computing architecture as used in the embodiments described herein may include a plurality of quantum nodes arranged along two intertwined helices. The intertwined helices may extend along a longitudinal axis and may be offset angularly from one another. Each helix may include multiple quantum nodes positioned at different angular locations along the helix. An example dual-helix architecture is provided with respect to FIG. 2.

[0032] The dual-helix architecture provides a spatial organization in which quantum nodes have well-defined adjacency relationships along a helix and between helices. Quantum nodes on one helix may be coupled to corresponding or nearby nodes on the other helix using inter-helix connections, which may be referred to as rungs. These rungs may enable quantum communication, entanglement, or state transfer between the helices.Atorney Docket No. H7019.10012W001

[0033] The dual-helix architecture and associated system are described with respect to FIGS. 1 A, IB, 2, and 3. This dual-helix architecture is one example of a spatially organized quantum computing system. Other spatial arrangements may also be used, and the disclosed techniques are not limited to any particular physical geometry unless expressly stated in the claims.

[0034] FIG. 1A illustrates an example quantum computing system 100 (hereinafter “system 100”) that includes such a dual -helix quantum encoding architecture, arranged in accordance with at least one embodiment herein. In particular, the system 100 includes a dual-helix quantum encoding structure 102 (hereinafter “dual -helix structure 102”), a multidimensional modulation controller 104 (hereinafter “controller 104”), and an error correction module 106. The system 100 may further include a central control module 108, a task scheduler 110, a photon system 112, one or more sensors 114 (hereinafter generically “sensors 114” or “sensor 114”), one or more quantum processing units (QPUs) 116, one or more memory modules 118, one or more real-time feedback loops 120, a classical computing interface 122, one or more waveguides and / or dynamic couplers 124, and an entanglement and cross-talk management module 126 (hereinafter “entanglement module 126”).

[0035] In general, the dual-helix structure 102 may include a first helix chain 102 A and a second helix chain 102B. Each of the first helix chain 102 A and the second helix chain 102B may include at least one of high-transparency quartz, fused silica, silicon nitride (SiN), lithium niobate (LiNbCh), and / or other suitable material(s). The controller 104 may be configured to modulate quantum information in the first and second helix chains 102 A, 102B using one or more of frequency modulation, phase modulation, and amplitude modulation. The dual-helix structure 102 may be configured to perform parallel quantum operations within the first helix chain 102A and the second helix chain 102B, e.g., under the direction or control of one or more of the central control module 108 or the task scheduler 110. The error correction module 106 may be configured to implement error correction within the first and second helix chains 102A, 102B using frequency modulation, phase modulation, and amplitude modulation provided through the controller 104.

[0036] The helix chains 102 A, 102B may operate in parallel, each processing different quantum tasks simultaneously. The architecture of the system 100 may dynamically assign tasks to different helix chains 102A, 102B based on the complexity of the computations.

[0037] The system 100 may monitor, e.g., constantly or continuously, the modulated dimensions of frequency, phase, and amplitude of the helix chains 102 A, 102B. ForAtorney Docket No. H7019.10012W001example, the sensors 114 may monitor the modulated dimensions of each of the first and second helix chains 102A, 102B. If one modulated dimension experiences an error (e.g., a phase drift), the system 100 may detect the error through real-time monitoring, e.g., by the sensors 114, and correct the error using the unaffected dimensions, e.g., using the error correction module 106, to restore an intended quantum state and / or maintain quantum state coherence.

[0038] The controller 104 may modulate the frequency, phase, and / or amplitude of each helix chain 102A, 102B in real-time. The controller 104 may ensure that each helix chain 102 A, 102B operates at an optimal modulation level to prevent overlap or signal degradation. For example, the controller 104 may be configured to modulate, respectively, the phase, the frequency, and the amplitude of the dual -helix structure 102 of FIG. 1 A. The controller 104 modulating the phase, frequency, and / or amplitude of the dual -helix structure 102 may include the controller 104 modulating the properties of individual photons or other quantum carriers that are processed at the various nodes of the dual-helix structure 102, rather than modifying structural properties of the dual -helix structure 102 itself.

[0039] Alternatively or additionally, a phase coupling mechanism may be implemented using the controller 104, together with one or more sensors 114, and / or the error correction module 106. The phase coupling mechanism may ensure phase synchronization between the helix chains 102A, 102B to reduce computational errors caused by phase misalignment. The phase coupling mechanism may detect phase drifts (e.g., using a phase sensor of the sensors 114) and correct misalignment by adjusting the phase of the affected helix chain 102A, 102B via the error correction module 106 and / or the controller 104.

[0040] In an example implementation, the classical computing interface 122 of FIG. 1A may be configured to receive classical data input. The classical computing interface 122 may be configured to convert the classical data input into quantum information suitable for processing by the dual -helix structure 102 and / or any of the QPUs 116. The classical computing interface 122 may be configured to transmit the quantum information to the controller 104 for modulation and processing in the first and second helix chains 102 A, 102B.

[0041] The dual-helix quantum encoding architecture embodied in the system 100 of FIG.1 may serve as a foundation for transmitting, receiving, and decoding quantum -encoded photons. The system 100 may support encoding and transmission functionalities as well as quantum processing and memory / storage integration.Atorney Docket No. H7019.10012W001

[0042] The system 100 may include or support quantum gates and circuits for performing operations on qubits stored within the helix chains 102A, 102B, examples of which are described with respect to FIG. IB and which may be incorporated into the dual-helix structure 102. Processing may occur at designated quantum nodes along each helix chain 102A, 102B, where modulation of frequency, phase, and amplitude, e.g., using the controller 104, may enable operations such as quantum logic gates (e.g., CNOT, Hadamard).

[0043] The parallel nature of the helix chains 102 A, 102B may allow for concurrent quantum computations. The task scheduler 110 may dynamically assign tasks across the helix chains 102 A, 102B to optimize, or at least improve, overall computational throughput. Nodes within the dual -helix structure 102 may act as quantum memory units, storing quantum states encoded via frequency, phase, and amplitude modulation. Alternately or additionally, the nodes within the dual-helix structure 102 may act as quantum processing elements that store and manipulate quantum states for computational operations in quantum computing applications.

[0044] The dual-helix quantum encoding architecture depicted in FIG. 1A may be combined with conventional computing systems to create a hybrid quantum-classical system. For example, the classical computing interface 122 may receive classical data inputs and convert them into quantum -encoded information for processing and transmit quantum computation results back as classical data outputs.

[0045] FIG. IB illustrates an example implementation of the QPU 116 of FIG. 1A, arranged in accordance with at least one embodiment herein. As illustrated, the QPU 116 of FIG. IB may include one or more of a readout subsystem module 128 (hereinafter “readout module 128”), a spatial data decoder 130, one or more polarization analyzers 132, one or more mode sorters 134, one or more interferometers 136, one or more quantum error correction protocols 138, a subsequent processing module 140, one or more single-qubit operations 142, one or more multi-qubit operations 144, a parallel processing dual-helix 146, and a feedback and intermediate data storage 148. The single-qubit operations 142 may include, for example, a Hadamard gate or other suitable single-qubit operations. The multi-qubit operations 144 may include, for example, a controlled NOT gate (C-NOT), a Toffoli gate (or controlled-CNOT or CCNOT gate or SWAP gate), or other suitable multiqubit operations. The parallel processing dual-helix 146 may be a subset or functional implementation of the dual helix structure 102 in FIG. 1A. The parallel processing dual-helix 146 may be optimized for use within a single QPU 116 (whereas the dual helixAtorney Docket No. H7019.10012W001structure 102 may operate at the system level). The dual helix structure 102 may be a core component of the overall system 100 and may be integrated into one or more QPUs (116). However, the dual helix structure 102 may have broader functionality beyond a single QPU, supporting multiple QPUs and system wide parallel operations. Individual QPUs (116) may contain or include a localized implementation of a dual helix structure, referred to as the parallel processing dual-helix 146 herein. The feedback and intermediate data storage 148 may output data that may be, e.g., sent back to the dual-helix structure 102 of FIG. 1A at block 150 and / or transmited to one or more other QPUs at block 152.

[0046] The waveguides and dynamic couplers 124 are depicted in FIG. 1A as being external to the dual -helix structure 102. In other embodiments, one or more of the waveguides and / or dynamic couplers 124 may be integrated directly into and / or embedded within the dual-helix structure 102, facilitating internal routing of encoded photons between processing nodes.

[0047] Referring to FIGS. 1A-1B, each QPU 116 includes a subsystem, such as the readout subsystem module 128, to detect and decode photons. The readout subsystem module 128 may include the spatial data decoder 130, the polarization analyzer 132, the mode sorter 134, and / or the interferometer 136. The readout subsystem module 128 may detect the incoming photons (received from the dual helix structure 102 via the waveguides and dynamic couplers 124) and extract quantum states using, e.g., the polarization analyzer 132 to detect polarization of each photon, the mode sorter 134 to detect 0AM of each photon, and / or the interferometer 136 to detect the phase of each photon. The extracted quantum states may be mapped to qubits in the QPU 116 for subsequent processing.

[0048] The quantum error correction protocols 138 may be applied to ensure data integrity during transmission and decoding. The quantum error correction protocols 138 may include surface codes, Shor codes, or other suitable quantum error detection and / or correction protocols. The quantum error correction protocols 138 may be part of and / or implemented by the error correction module 106 of FIG. 1 A. The quantum error correction protocols 138 may be an internal component or implementation of the broader error correction module 106. The QPU 116 may execute the quantum error correction protocols 138 as part of its quantum processing.

[0049] The subsequent processing module 140 may include the single-qubit operations 142, the multi -qubit operations 144, and / or the parallel processing dual -helix 146. The QPU 116 may perform single-qubit operations 142 (e.g., X, Z, Hadamard gates) to manipulateAtorney Docket No. H7019.10012W001individual qubits based on a given computation task. The QPU 116 may also execute multiqubit operations 144.

[0050] Processed quantum states generated by the subsequent processing module via the single-qubit operations 142, the multi-qubit operations 144, and / or the parallel processing dual-helix 146 may be sent back to the dual-helix structure 102 of FIG. 1A for storage or further routing, as indicated at block 150, and / or transmited to other QPUs 116 for additional computation, as indicated at block 152. Quantum memory modules, such as the memory module 118 of FIG. 1 A, may store intermediate results or checkpointed states for multi-step computations.

[0051] Referring to FIG. 1A, the central control module 108 may coordinate data flow between the dual-helix structure 102 and the QPUs 116, and may ensure that operations are synchronized. The central control module 108 may dynamically allocate QPU resources based on task priority and node availability. The real-time feedback loops 120 may monitor state fidelity, gate execution, and / or routing efficiency. Adjustments may be made dynamically, e.g., as part of the real-time feedback loops 120, to reduce losses and optimize performance.

[0052] Further description of the system 100 is found in U.S. Patent Application No.19 / 083,366, filed on March 18, 2025, entitled Dual-Helix Quantum Encoding Architecture And Multidimensional Quantum Computing System and U.S. Patent Application No.19 / 208,461, filed on May 14, 2025, entitled Quantum Secure Communication Protocol And Device Based On Double-Helix Structure Composite Multi-Layer Encoding, the entire disclosure of which are incorporated herein by reference in their entireties.

[0053] FIG. 2 is a view of an example dual-helix quantum architecture showing interleaved A-helix chain and B-helix chain quantum nodes, arranged in accordance with at least one embodiment herein. The layout includes A-helix chain quantum nodes, labeled A0 through A31 and denoted by crosses (A0-A31), and B-helix chain quantum nodes, labeled B0 through B31 and denoted by open squares (B0-B31), each arranged along two interleaved helical paths. The A-helix chain and B-helix chain helices are offset by approximately 180 degrees at each Z level, resulting in paired A and B quantum nodes at the same vertical (Z) position in 3D space. This arrangement visually represents the logical adjacency and pairing of A and B quantum nodes at each height, as well as the nearest-neighbor connections along each helix.

[0054] The phrase "dual-helix logical node layout," as used in this disclosure, refers to an arrangement of quantum nodes in 3D space in which two interleaved chains of quantumAtorney Docket No. H7019.10012W001nodes follow helical paths, with each chain offset from the other by a fixed angular phase. The purpose of the dual-helix logical quantum node layout is to provide a logical framework for organizing quantum nodes such that both local and cross-chain adjacency are preserved, thereby supporting efficient routing and scalable quantum processor architectures. The term "logical" is used herein to clarify that the node organization defined in 3D space is distinct from the physical layout of node cores described in two-dimensional (2D) space for various embodiments described herein.

[0055] The mapping relationship between the dual-helix logical node layout 200 and the planar mapping coordinate frame 300 is established by projecting each node from its three-dimensional position onto the two-dimensional plane in a manner that preserves adjacency and logical pairing. In some embodiments, the dual-helix logical node layout 200 provides the starting three-dimensional coordinates for each A-helix chain and B-helix chain node, and the projection process defines the layout in X' and Y' such that, in many implementations, similarly-indexed nodes that are proximate to each other in the 3D layout retain relative spatial proximity in the 2D layout.

[0056] The parametric equations for the 3D helix may be represented, for example, as x(9) = r * cos(9), y(9) = r * sin(9), and z(9) = (p * 9) / (2 * 7t), where r is the helix radius, p is the z-direction pitch, and theta is the angular coordinate. The planar projection may use, for example, mapping equations such as X' = z and Y' = (r * 9) mod (2 * n * r), with the modulo function in the Y' mapping ensuring that nodes from different turns of the helix are distributed within a fixed vertical range in the planar layout. The preservation of logical connectivity and adjacency in the projected layout may be achieved by maintaining the adjacency of nearest-neighbor quantum nodes along each chain (A-helix chain and B-helix chain), as well as the vertical alignment of cross-chain node pairs (A_i and B i).

[0057] FIG. 3 is a view illustrating an example spiral-unwrapped placement of quantum nodes on the A-helix chain and B-helix chain and links 301 and 302 between the quantum nodes, arranged in accordance with at least one embodiment herein. In FIG. 3, the links 301 couple quantum nodes which are nearest neighbors within the same slanted column. The links 302 provide connections between nodes in adjacent slanted columns that are substantially aligned in the vertical (Y1) direction. For instance, the links 301 may be established between nearest-neighbor nodes such as B5 and B6 or between A19 and A20, while the links 302 may provide cross-chain connections between nodes such as Al and Bl or B20 and A20, where the nodes are located in adjacent slanted columns and have the same index number.Atorney Docket No. H7019.10012W001

[0058] In some embodiments, the links 301 and the links 302 may be configured to provide signal routing between quantum nodes. The links 301 and the links 302 may include in-plane waveguide paths and vertical interconnects for cross-layer communication. Examples of such photonic routing layers may include silicon nitride waveguide layers, silicon dioxide cladding layers, or other dielectric waveguide structures configured for low-loss optical transmission. Other links may be made between other of the quantum nodes than those illustrated. For example, links may be formed between the Al and A3. In these and other embodiments, links may be formed so that any two nodes may be reached in a reduced hop count by utilizing both intra-strand neighbor links and inter-strand links, thereby achieving logarithmic-diameter connectivity across the entire quantum processing architecture.QUANTUM NODE MODEL AND SPATIAL ORGANIZATION

[0059] In some embodiments, each quantum node may be associated with a spatial coordinate derived from its position along a helix in a dual-helix structure, such as illustrated in FIGS. 2 and 3. The spatial coordinate may include an angular position 9 and, optionally, corresponding Cartesian coordinates (x, y, z). In some embodiments, the angular position 9 may be determined according to 9i = i A9, where i represents a node index and A9 represents an angular increment between successive nodes. The Cartesian coordinates may be derived from the angular position according to xi = r cos(9i), yi = r sin(9i), and zi = (h / 27t) • 9i, where r represents a helix radius and h represents a helix pitch. The spatial coordinate may provide a correspondence between node index and physical position within a three-dimensional helical structure.

[0060] The spatial coordinate may be used for addressing, routing, scheduling, or organizing quantum operations. In one embodiment, the spatial coordinate may serve as an addressable quantum register that may be manipulated by quantum gates. The spatial coordinate may facilitate efficient routing by allowing quantum operations to be scheduled based on physical proximity of nodes, thereby reducing communication overhead and circuit depth. Alternately or additionally, such spatial relationships may be used to constrain or prioritize quantum operations, reduce routing overhead, or organize execution.

[0061] In some embodiments, a dual-helix structure and the associated quantum nodes on the helix structure may be divided into segments. Each segment may comprise a contiguous group of quantum nodes along a helix chain. The segment boundaries may be defined by angular positions along the helical structure.Atorney Docket No. H7019.10012W001

[0062] The selection of segments, e.g., the segment boundaries, may be based on the computational requirements of a quantum workload. The number of quantum nodes in each segment may be determined by the angular span of the segment. For example, a segment spanning an angular range of A9 may contain Nsegment quantum nodes, where Nsegment may be calculated as A9 divided by the angular step between adjacent nodes. The angular step between adjacent nodes may be denoted as 89. The relationship may be expressed, for example, as Nsegment = A9 / 69. The angular span A9 of each segment may be selected based on the coherence time of the quantum nodes, the complexity of the quantum operations to be performed within the segment, and the desired level of parallelism across segments.

[0063] The number of quantum nodes in each segment may range from a minimum of two nodes to a maximum up to the total number of nodes in a complete helical turn. A complete helical turn may correspond to an angular span of 2TI radians. The number of nodes per complete turn may be denoted as Nturn. The maximum number of nodes in a segment may therefore be up to Nturn. The minimum number of nodes in a segment may be two nodes, which may enable the simplest form of quantum entanglement operations between adjacent nodes within the segment.

[0064] The selection of segment boundaries may be performed algorithmically based on the structure of a quantum circuit to be executed. For example, a quantum circuit may comprise multiple layers of quantum gates. Each layer may correspond to a set of quantum operations that may be executed in parallel. The segment boundaries may be selected to align with natural boundaries in the quantum circuit structure. For example, segment boundaries may be placed between layers of quantum gates that require synchronization or aggregation of results. The segment boundaries may also be placed to reduce the number of quantum operations that span across segment boundaries, thereby reducing the communication overhead between segments.

[0065] The segments may be of equal size, with each segment containing the same number of quantum nodes. Alternatively, the segments may be of varying sizes, with different segments containing different numbers of quantum nodes. The size of each segment may be determined based on the computational load assigned to that segment. Segments assigned more computationally intensive tasks may contain more quantum nodes. Segments assigned less computationally intensive tasks may contain fewer quantum nodes. This variable segment sizing may enable load balancing across a dual-helix structure.Atorney Docket No. H7019.10012W001

[0066] The segments may be contiguous along the helix chain, with each segment immediately following the previous segment in the angular coordinate. Alternatively, the segments may be non-contiguous, with gaps between segments. The gaps between segments may contain quantum nodes that are not assigned to any segment during a particular computational phase. These unassigned nodes may be used for error correction operations, calibration operations, or future computational tasks.

[0067] The segments may be defined on a single helix chain, such as the first helix chain 102 A or the second helix chain 102B. Alternatively, the segments may span across both helix chains, with each segment containing quantum nodes from both the first helix chain 102 A and the second helix chain 102B. Segments that span across both helix chains may utilize the rung couplers to enable quantum operations between nodes on different helix chains within the same segment.

[0068] In some embodiments, the segment boundaries may enable parallel execution of quantum operations across multiple segments. In these and other embodiments, different segments may be prepared for different computational subtasks or execution roles.

[0069] Note that while the dual-helix structure may be divided into segments in some embodiments, other embodiments may not have the dual-helix structure divided into segments.QUANTUM STATE ENCODING AND POSITIONAL MODES

[0070] In some embodiments, quantum states processed by the architecture may include one or more encoding dimensions. These dimensions may include, by way of example and not limitation, amplitude, phase, polarization, frequency, orbital angular momentum, or other degrees of freedom. Each encoding dimension may provide an independent or partially independent channel for representing information within the quantum state. The combination of multiple encoding dimensions may enable high-dimensional quantum state representations that may support complex computational tasks.

[0071] In some embodiments, the spatial coordinate of a quantum node may serve as an additional encoding dimension. The spatial coordinate may be derived from the angular position 9 of the quantum node along the helix. The spatial coordinate may be represented as a positional mode within the quantum state. The positional mode may be expressed, for example, as |9), where 9 corresponds to the angular position of the quantum node. The positional mode may be treated as a quantum register or logical label that may be manipulated by quantum operations. The positional mode may enable position-dependentAtorney Docket No. H7019.10012W001quantum operations that may exploit the geometric structure of the double-helix architecture.

[0072] Note that the use of positional modes is optional and may vary depending on the quantum algorithm or workload being executed.

[0073] As an example of positional modes in the dual -helix structure 102, each quantum node may store a quantum state that may include orbital angular momentum (0AM) modes, polarization states, phase values, and / or spatial position information. The 0AM modes may be initialized to specific angular momentum values 1. The polarization states may be initialized to horizontal, vertical, left-circular, or right-circular polarization. The phase values may be initialized to specific phase angles cp. The spatial position information may be encoded in a positional mode corresponding to the node's angular coordinate 9. For example, each quantum node positioned along the two intertwined helices may be assigned a corresponding spatial coordinate (xi, yi, zi) derived from the angular position 9i according to one or more parametric relationships, for example, xi = r cos(9i), yi = r sin(9i), and zi = (h / 27t) 9i, where r denotes the helix radius, h denotes the pitch, and 0i = i • A0 represents the angular coordinate of node i. The spatial coordinate 9i may function as a logical register within a quantum state representation |1, p, cp; 9) and / or as a physical address identifying the geometric location of the node within the three-dimensional helical structure.

[0074] In some embodiments, the dual nature of the spatial coordinate may enable quantum circuits to perform position-dependent operations by applying phase gates based on 9i, selecting neighboring nodes based on angular proximity, or routing quantum information along paths determined by the helical geometry. The mapping between node index i and spatial position 9i may provide a consistent addressing scheme that may be exploited by compilation algorithms to minimize routing overhead and by runtime schedulers to distribute computational tasks across spatially localized segments of the helix.

[0075] In some embodiments, the spatial coordinate may be encoded into the quantum state through positional phase tagging, wherein a unitary operator, for example, Upos(k) = exp(ik9i) may be applied to each node to embed the angular position as a phase factor. The resulting state, for example, eA(ik9i)|l, p, cp; 9) may carry positional information that may be accessed through interference-based operations or Fourier transforms performed across the 9-register. The positional phase tagging may enable circuits to implement convolutionlike operations by coupling nodes at positions 9 and 9 ± kA9, where the phase relationship between coupled nodes may encode spatial frequency components analogous to classical convolutional kernels.Atorney Docket No. H7019.10012W001

[0076] In some embodiments, the positional mode may allow for restrictions on gate connections to physically adjacent or geometrically proximate nodes, thereby reducing the need for long-range SWAP operations that typically introduce errors and increase circuit depth in planar quantum architectures.

[0077] In some embodiments, the positional mode may allow for segment-scoped parameter tying mechanism that may apply shared trainable parameters across all nodes in a segment, such that gradient updates computed at individual nodes may be averaged to produce a single parameter update applied uniformly throughout the segment. The positional mode may thus serve as both a quantum degree of freedom that may be manipulated by gates and measurements, and as a classical index that may be used by compilers and schedulers to organize quantum operations according to the physical topology of the double-helix architecture.EXECUTION, SCHEDULING, AND PARALLELISM FRAMEWORK

[0078] In some embodiments, the quantum computing architecture as discussed in this disclosure may be organized into layers and / or sublayers such that no quantum node participates in more than one operation within a given layer. As a result, each layer may represent a set of quantum operations that may be executed in parallel without conflict, where conflict may be defined as two or more operations attempting to act on the same quantum node simultaneously. The organization into layers may enable efficient parallel execution of quantum operations while maintaining the integrity of quantum states at each node. The layer structure may be determined by analyzing the connectivity graph of the quantum computing architecture and identifying sets of operations that may be performed concurrently without violating the constraint that each node participates in at most one operation per layer.

[0079] The architecture may support multiple sublayers within a layer of quantum computation, referred to as sublayers, where each sublayer may correspond to a distinct set of non-conflicting operations. The number of sublayers required for a given layer of quantum computation may depend on the connectivity pattern of the operations and the physical topology of the quantum nodes along the intertwined helices. Operations within a sublayer may be executed simultaneously across different quantum nodes, thereby reducing the overall execution time for the layer.

[0080] In some embodiments, the layer organization may be particularly advantageous in architectures where quantum nodes are spatially distributed along helical structures, as theAtorney Docket No. H7019.10012W001geometric arrangement may naturally suggest groupings of operations that may be performed in parallel without interference. Note that the scheduling mechanisms described herein are provided as illustrative examples of how quantum operations may be coordinated on a spatially organized architecture. The architecture does not require any particular scheduling strategy, and different scheduling approaches may be used depending on the algorithm, workload, or hardware implementation.PARAMETER HANDLING AND OPTIMIZATION SUPPORT

[0081] Furthermore, the quantum computing architecture described herein may support various approaches to parameter management during quantum operations. Parameters in quantum circuits may include rotation angles, phase values, coupling strengths, and other adjustable quantities that influence the behavior of quantum gates and operations. The manner in which parameters are handled may affect the efficiency, accuracy, and scalability of quantum computations performed on the architecture.

[0082] In some embodiments, parameters may be managed at different levels of granularity within the quantum computing architecture. At a local level, individual quantum nodes may maintain parameter values that govern the behavior of quantum gates applied at those nodes. At a segment level, groups of quantum nodes organized into segments may share parameter values, thereby reducing the total number of independent parameters that must be managed and optimized. At a global level, parameter values may be coordinated across multiple segments or across the entire quantum computing architecture to maintain consistency and coherence in quantum operations. The hierarchical organization of parameter management may enable efficient scaling of quantum computations while maintaining control over the behavior of individual quantum operations. Different levels of parameter management may be employed depending on the specific requirements of the quantum algorithm being executed, the characteristics of the quantum hardware, and the desired trade-offs between computational efficiency and operational flexibility.

[0083] In some embodiments, parameter aggregation may be performed classically, quantum-mechanically, or using hybrid approaches. The dual-helix architecture is not limited to any particular optimization algorithm or parameter update rule. Gradient-based methods, reinforcement learning techniques, heuristic optimizers, or other optimization approaches may be used depending on the application.Atorney Docket No. H7019.10012W001

[0084] The parameter handling mechanisms described herein are intended to illustrate architectural support for parameterized quantum algorithms and do not define a specific optimization method unless expressly claimed.ILLUSTRATIVE Al WORKFLOWS SUPPORTED BY THE ARCHITECTURE

[0085] By way of example only, the disclosed architecture may support a variety of artificial intelligence workflows, including but not limited to:• Quantum neural network training and inference• Variational quantum optimization for machine learning or combinatorial problems • Similarity -based inference or data placement• Hybrid quantum-classical execution pipelines

[0086] These workflows are provided as non-limiting examples. The architecture may support other quantum algorithms and workloads beyond artificial intelligence applications.

[0087] FIG. 4 illustrates an example process flow 400 for quantum computing using a dual-helix quantum architecture, arranged in accordance with at least one embodiment herein. The process flow 400 may be executed by the system 100 of FIG. 1 A, utilizing the dual-helix structure 102 and associated components. The process flow 400 may support quantum neural network training, variational quantum optimization, or other quantum artificial intelligence tasks by leveraging the spatial topology and multi-dimensional encoding capabilities of a dual-helix architecture. The process flow 400 is illustrative and may be modified depending on workload requirements and hardware configuration.

[0088] The process flow 400 may include an initialization / design phase 402, an orchestration phase 406, an execution phase 408, a parameter adjustment phase 410, an error correction phase 412, a convergence / evaluation phase 414, and an inference and output phase 416. Each phase may be performed sequentially or with partial overlap depending on the specific quantum computing task and hardware configuration.

[0089] In some embodiments, the process flow 400 improves execution efficiency by utilizing geometry-aware scheduling, including layered and sublayered execution in which quantum gate operations are organized to avoid node conflicts and enable concurrent execution across different node subsets or segments. Such execution coordination may reduce routing overhead, reduce circuit depth, and improve overall fidelity for quantum workloads.Atorney Docket No. H7019.10012W001

[0090] In some embodiments, the process flow 400 supports concurrent execution of different classes of quantum workloads by coordinating time windows and execution resources across distributed node segments while preserving coherence. For example, the process flow 400 may distribute quantum gate operations across helical segments to increase parallelism and may coordinate execution using geometry-aware scheduling informed by node location, coupling availability, and measured hardware conditions. Any references to specific workloads are illustrative and are not required for operation or limitation of the disclosed execution architecture.

[0091] The initialization / design phase 402 may include preparing quantum nodes positioned along the two intertwined helices of the dual -helix structure 102 for execution of quantum circuits. Initialization may include configuring one or more initial quantum states, establishing one or more quantum connections between nodes (including inter-helix couplers), and optionally defining one or more execution segments for parallel operation.

[0092] In some embodiments, the initialization / design phase 402 prepares quantum nodes in one or more predetermined basis states depending on a circuit to be executed. For example, a set of quantum nodes may be prepared in a ground or reference state (e.g., such as a |O)0n state for n nodes) by applying reset operations to drive qubits to a defined initial condition. In photonic implementations, the reference state may correspond to absence of a photon in a particular mode, and in superconducting implementations, the reference state may correspond to a ground state of a qubit.

[0093] In some embodiments, the dual-helix topology may be utilized to generate distributed superposition and entanglement structures across multiple quantum nodes, including across nodes positioned along a helix and across nodes coupled by inter-helix couplers. Such entanglement structures may be generated using entangling operations between geometrically proximate nodes, including nearest-neighbor nodes along a helix and cross-helix node pairs.

[0094] Distributed superposition and entanglement may enable quantum interference effects during circuit execution. For example, a first quantum node may be entangled with a second quantum node using a two-qubit operation such as a controlled-NOT gate, a controlled-phase gate, or other entangling operation. The resulting correlation may facilitate propagation of quantum information across multiple pathways defined by the node topology.

[0095] In some embodiments, entangling operations may be selected and organized based on positional information associated with the quantum nodes. For example, node pairs mayAtorney Docket No. H7019.10012W001be selected based on angular proximity along a helix or based on corresponding positions across the two helices. Entangling operations may be organized into sublayers such that no quantum node participates in more than one entangling operation per sublayer, enabling parallel execution and reduced circuit depth.

[0096] Certain workloads may utilize alternative initial states (e.g., superposition-prepared states) in which one or more nodes are initialized using single-qubit gates such as Hadamard gates. Such alternative initialization schemes are optional and may be selected based on the circuit to be executed.

[0097] In some embodiments, inference or decision workloads may be executed by preparing one or more entangled states and executing gate operations that evaluate multiple candidate pathways in parallel. Such workloads are described as non-limiting examples of circuits that may be executed on the disclosed dual-helix execution architecture.

[0098] During execution of such workloads, quantum gate operations may be performed between nodes to propagate quantum information through the architecture. In some embodiments, gate execution creates entanglement between nodes and allows information to be distributed across multiple node groups concurrently, subject to scheduling constraints that avoid node contention.

[0099] In some embodiments, an initialization procedure may generate or reference an execution graph or dependency representation describing relationships among computational elements to be processed by the quantum circuit. The dependency representation may be used to determine which quantum nodes should be initialized and which couplings should be enabled to support efficient execution under the dual-helix topology.

[0100] For example, a dependency representation may include an adjacency matrix in which entries represent interaction strength or correlation between elements. The dependency representation may be used to inform selection of an initial configuration of quantum states and couplings based on available quantum resources and geometric connectivity.

[0101] In some embodiments, one or more initialization states may be generated based on dominant structural components of a dependency representation. Such states may be normalized and mapped to quantum superposition states using state preparation techniques that include sequences of rotation gates and controlled operations applied to quantum nodes positioned along the two intertwined helices.Atorney Docket No. H7019.10012W001

[0102] Prepared quantum states may be assigned to quantum nodes based on node coordinates and connectivity. Nodes assigned related states may be grouped into segments to facilitate parallel execution. Entangling operations may be applied between nodes within a helix and across helices via inter-helix couplers to support efficient execution paths while minimizing long-range routing.

[0103] The initialization / design phase 402 may involve specific hardware components of the system 100. For example, the controller 104 may generate control signals for state preparation operations, including voltage pulses, laser pulses, or radio-frequency pulses depending on qubit modality. The central control module 108 may coordinate timing of initialization operations across multiple nodes, and the sensors 114 may monitor initialization fidelity. The error correction module 106 may detect and correct initialization errors.

[0104] The initialization / design phase 402 may initialize quantum nodes on both helix chains 102 A and 102B. In some embodiments, corresponding nodes across helices are configured for inter-helix coupling after initialization, enabling cross-helix gate operations and state transfer using rung couplers.

[0105] The initialization / design phase 402 may configure segment boundaries within the dual-helix structure 102. Each segment may comprise a contiguous group of quantum nodes along a helix chain, and segment boundaries may be defined by angular positions along the helix. Segmentation enables parallel execution by allowing different segments to execute non-conflicting gate operations concurrently.

[0106] Selection of segments may be based on execution requirements of a quantum circuit, including coherence constraints, expected circuit depth, coupling availability, and desired level of parallelism. For example, a segment spanning an angular range A0 may contain Nsegment nodes, where Nsegment may be estimated based on the angular step between adjacent nodes. Segment definitions may be stored as configuration information used by the control system during scheduling.

[0107] In some embodiments, a segment may include at least a plurality of quantum nodes and may extend up to approximately a full helical turn (e.g., 2TI radians). Segment size may be selected to balance locality and parallelism, such that intra-segment gate operations are preferentially executed using local couplings while inter-segment interactions are scheduled to avoid contention.

[0108] Segment boundaries may be selected algorithmically based on a quantum circuit structure. For example, segments may be aligned with execution layers, with boundariesAtorney Docket No. H7019.10012W001chosen to minimize gate operations that span across segments. Reducing cross-segment interactions may reduce routing overhead and may simplify scheduling.

[0109] Segments may be of equal size or varying sizes. In some embodiments, segment size is selected based on a workload allocation or execution load, such that segments assigned higher execution demand include more nodes than segments assigned lower execution demand.

[0110] Segments may be contiguous or may include gaps. In some embodiments, unassigned nodes serve as reserved resources for calibration, error management, rerouting, or execution of auxiliary operations.

[0111] Segments may be defined on a single helix chain or may span both helix chains. For segments spanning both helix chains, inter-helix couplers may enable gate operations between nodes on different chains within the same segment, facilitating cross-helix operations with reduced routing.

[0112] In some embodiments, an aggregator node may optionally be assigned to a segment to collect measurement outcomes or intermediate results produced within the segment. The aggregator node may be coupled to other nodes in the segment via one or more communication channels to support reduction or consolidation of segment-level outputs.

[0113] In some embodiments, an aggregator node is positioned to reduce average communication distance within a segment, such as at or near a geometric center of the segment. Positioning the aggregator node may reduce latency for result collection and may improve synchronization when segment outputs are used for subsequent execution scheduling.

[0114] In some embodiments, segments operate independently during at least a portion of an execution phase 408. Segment independence may be maintained by scheduling constraints that avoid inter-segment gate operations during local execution windows. During local execution, nodes within a segment may perform single-qubit operations, two-qubit operations with neighboring nodes, and measurement operations according to a scheduled sublayer structure.

[0115] After completion of a local execution window, nodes in a segment may provide measurement results or intermediate outputs to an aggregator node. The aggregator node may perform a reduction operation that combines information from multiple nodes to generate a consolidated output for the segment.

[0116] In some embodiments, aggregated segment outputs may be combined across multiple segments using an inter-segment reduction scheme. Such reduction is illustrativeAtorney Docket No. H7019.10012W001and may be implemented using classical aggregation of measurement results or other suitable mechanisms, depending on the workload and hardware configuration.

[0117] An inter-segment reduction scheme may be implemented using a tree topology, such as a binary tree, in which aggregator nodes exchange results and compute combined outputs at successive levels. Tree-based reduction may reduce total aggregation depth relative to sequential collection.

[0118] Tree-based aggregation may proceed until a global or partially consolidated result is obtained. The number of aggregation levels may scale sublinearly with respect to the number of segments. The consolidated result may be stored, output, or used to inform subsequent scheduling decisions.

[0119] In some embodiments, segment boundaries and aggregator assignments may be dynamically reconfigured based on execution requirements, detected or anticipated hardware conditions, or resource utilization. Dynamic reconfiguration may include adjusting angular spans of segments, reassigning nodes to segments, or reassigning aggregator roles to maintain performance and reduce contention.

[0120] During dynamic reconfiguration, boundaries of segments may be adjusted by changing an angular span assigned to each segment. For example, a segment may be expanded or contracted by updating configuration information associated with quantum nodes and any segment management logic. Segment resizing may be used to adapt execution resources to a quantum circuit structure, to respond to measured hardware conditions, or to reduce contention during concurrent execution.

[0121] When segment boundaries are reconfigured, assignment of quantum nodes to segment management entities may change. For example, a quantum node previously associated with a first segment or first control domain may be reassigned to a second segment or second control domain. Reassignment may include updating connectivity information and enabling or disabling communication channels used for scheduling, state transfer, or measurement result collection.

[0122] Segment management entities, including nodes designated for coordination, may be dynamically reassigned, activated, or deactivated. Such reassignment may be performed to balance execution load, to isolate degraded regions of hardware, or to maintain target scheduling constraints as quantum workloads change over time.

[0123] In some embodiments, the initialization / design phase 402 prepares quantum states with one or more encoding dimensions. For example, a quantum state stored at a quantum node may include one or more of orbital angular momentum (0AM) mode information,Atorney Docket No. H7019.10012W001polarization state information, phase information, and positional information associated with a node’s angular coordinate. In some embodiments, each quantum node positioned along the intertwined helices is associated with a deterministic spatial coordinate (xi, yi, zi) derived from an angular position 9i according to parametric relationships such as xi = r cos(9i), yi = r sin(9i), and zi = (h / 27t)-0i, where r denotes a helix radius, h denotes a pitch, and 0i = i- A0 represents an angular coordinate of node i. The angular coordinate 9i may serve as a physical address identifying geometric location of the node within the helical structure.

[0124] The spatial coordinate may enable position-dependent execution control. For example, quantum circuits may apply phase gates based on 9i, select neighboring nodes based on angular proximity, or route quantum information along paths determined by helical geometry. The deterministic relationship between node index and angular position provides a consistent addressing scheme that may be used by compilation and scheduling logic to reduce routing overhead and to distribute execution across localized segments.

[0125] In some embodiments, the spatial coordinate is embedded into a quantum state through positional phase tagging. For example, a unitary operator such as Upos(k) = exp(ikOi) may be applied to embed angular position as a phase factor. The resulting state may carry positional information that can be leveraged during execution, for example via interference-based operations, basis transformations, or scheduling constraints that depend on angular position.

[0126] In some embodiments, positional information is used to restrict gate connections to physically adjacent or geometrically proximate nodes. Restricting connections in this manner may reduce the need for long-range SWAP operations, reduce circuit depth, and improve execution fidelity relative to some architectures that rely on frequent multi-hop routing.

[0127] In some embodiments, positional information and segmentation are used by the control system to facilitate application of common control settings across groups of nodes or to coordinate execution in localized regions. Such grouping may reduce control overhead and simplify scheduling by enabling repeated application of consistent gate parameter values within an execution segment. Any parameter-update mechanisms are optional and may be implemented using classical, quantum, or hybrid control processes depending on workload requirements.

[0128] Following state preparation, the initialization / design phase 402 may include assigning computational elements to quantum nodes using angular coordinate ordering. ForAtorney Docket No. H7019.10012W001example, elements may be assigned to node positions 9i to align logical adjacency of computational elements with geometric adjacency of nodes, thereby reducing state-transfer distance during subsequent execution.

[0129] Computational elements may include input data values, intermediate computation values, or model variables that participate in quantum gate operations. Such elements may be encoded into quantum states stored at quantum nodes using any suitable encoding scheme supported by the hardware.

[0130] In some embodiments, an assignment of computational elements to quantum nodes is stored in a mapping table associating element identifiers with node positions along the helices. The mapping table may be used by state preparation circuitry and by scheduling logic to select execution paths that reduce routing overhead. The assignment may remain fixed for a computation cycle or may be updated between cycles based on resource availability or execution constraints.

[0131] In some embodiments, an assignment procedure may account for relationships between computational elements, such as correlation, dependency, or interaction frequency, to reduce communication overhead during execution. Relationship metrics may include similarity functions, distance metrics, or connectivity scores or other relationship indicators. Such metrics are illustrative and may be used in combination with geometric constraints of the dual-helix topology.

[0132] In some embodiments, computational elements are ordered prior to assignment so that elements expected to interact frequently are placed at nearby angular positions along a helix. Ordering may be derived from graph-based or matrix-based representations of relationships among elements. The resulting ordering may be mapped to nodes in increasing 9 or other angular ordering to promote locality during gate execution.

[0133] In some embodiments, subsets of computational elements may be preferentially placed on a same helix chain to reduce cross-helix transfers, while other elements are placed on the opposing helix to balance execution load. Placement policies may be selected to minimize routing overhead and to respect available couplings and scheduling constraints without requiring a fixed placement rule.

[0134] As one non-limiting example, an input tensor may be partitioned into multiple elements for assignment to quantum nodes. Elements that are adjacent in an input ordering may be placed at nearby angular positions or otherwise geometrically proximate positions to reduce communication distance for operations involving neighboring elements.Atorney Docket No. H7019.10012W001

[0135] In some embodiments, assignments may alternate between the two helices to enable efficient cross-helix operations using inter-helix couplers. Such alternation is optional and may be selected based on one or more of circuit structure, coupling availability, or desired scheduling behavior.

[0136] As another non-limiting example, variables of an optimization model may be assigned to quantum nodes based on interaction structure among variables. Variables with stronger interactions may be assigned to nodes with smaller angular separation or nodes coupled via inter-helix couplers, reducing routing overhead during execution of two-qubit operations.

[0137] In some embodiments, assignment may evaluate candidate node locations for an element based on physical distance to already-assigned interacting elements. Distance may be measured as one or more of angular distance along the helix, a hop count along available links, or a Euclidean distance in three-dimensional space. A cost function may be used to select an assignment that reduces expected routing or state-transfer cost without requiring a specific cost formulation.

[0138] In some embodiments, assignments alternate between helix chains to balance utilization while maintaining locality. Strongly interacting elements may be placed at nodes that are directly coupled (for example, via rung couplers) to enable direct gate operations without multi-hop transfers.

[0139] The initialization / design phase 402 may include encoding computational information into composite quantum states using one or more degrees of freedom supported by the hardware. For example, 0AM, polarization, phase, and positional information or other state parameters may be used in photonic implementations to encode multiple channels of information per node.

[0140] In some embodiments, a composite quantum state may be expressed as a tensor product across multiple degrees of freedom. Positional information may be embedded via phase tagging or other position-dependent modulation proportional to the spatial coordinate to support geometry-aware execution and routing.

[0141] In some embodiments, classical data values are transformed into quantum state parameters using normalization and encoding operations prior to loading the states onto the quantum nodes. The specific encoding process may vary depending on qubit modality and application requirements.

[0142] In some embodiments, multiple data channels may be multiplexed across polarization states, mode indices, or other degrees of freedom. For example, polarizationAtorney Docket No. H7019.10012W001controllers may be used in photonic implementations to prepare designated polarization bases, while equivalent operations may be performed in other qubit modalities.

[0143] In some embodiments, a high-dimensional mode space (e.g., an 0AM mode space) enables compact encoding and supports basis-dependent operations. Mode selection and readout may be performed using mode sorters, interferometric elements, or other measurement apparatus as described herein.

[0144] In some embodiments, tokenized inputs or sequential elements may be mapped to angular coordinates 9t or associated angular positions with a predetermined step A0 or another spacing scheme. Positional phase tagging may be applied to embed angular position into the quantum state to support geometry-aware routing and execution coordination across the dual-helix topology.

[0145] In some embodiments, the initialization / design phase 402 includes calibration of quantum gates and measurement apparatus, preparation of error management infrastructure, and loading of pre-compiled circuit templates. Calibration may include characterizing gate fidelity, coherence times, and control parameter ranges, and storing calibration data in lookup tables for use during execution.

[0146] The initialization / design phase 402 may further include establishing communication channels between quantum nodes and classical control systems, allocating memory resources, and defining time windows for different operation types. In some embodiments, readiness verification is performed by executing test circuits to confirm proper operation and detect faults prior to executing a target workload.

[0147] The initialization / design phase 402 may involve specific hardware components of the dual-helix structure 102. The multidimensional modulation controller 104 may generate control signals for state preparation operations. The control signals may include voltage pulses for superconducting qubits, laser pulses for photonic qubits, or radio-frequency pulses for ion trap qubits. The central control module 108 may coordinate the timing of initialization operations across multiple quantum nodes. The task scheduler 110 may determine which quantum nodes may be initialized for particular computational tasks. The sensors 114 may monitor the fidelity of prepared quantum states. The error correction module 106 may detect and correct initialization errors that may occur during state preparation.

[0148] The initialization / design phase 402 may prepare quantum nodes on both the first helix chain 102 A and the second helix chain 102B. The quantum nodes on the first helix chain 102 A may be initialized to the same quantum state as quantum nodes on the secondAtorney Docket No. H7019.10012W001helix chain 102B. Alternatively, the quantum nodes on the first helix chain 102 A may be initialized to a different quantum state than quantum nodes on the second helix chain 102B. The initialization of quantum nodes on different helix chains may enable parallel processing of different computational tasks. The rung couplers may establish quantum connections between corresponding nodes on the first helix chain 102 A and the second helix chain 102B after initialization.

[0149] In some embodiments, the initialization / design phase 402 may include segmentation of the quantum nodes and / or segmentation of multi-dimensional encoding resources.

[0150] In some embodiments, the initialization / design phase 402 may include mapping input datasets to quantum nodes. The mapping process may utilize the deterministic spatial coordinates of quantum nodes along the helical structure to assign computational elements to specific quantum nodes in a manner that preserves locality. The assignment process may determine which computational element occupies which quantum node position.

[0151] In some embodiments, the initialization / design phase 402 may include other operations. For example, the initialization / design phase 402 may include calibration of quantum gates and measurement apparatus, preparation of error correction infrastructure, and loading of pre-compiled quantum circuits or circuit templates. Calibration may involve characterization of gate fidelities, measurement of coherence times, and determination of one or more suitable optimal control parameters, with calibration data stored in lookup tables for use during circuit execution. Error correction infrastructure may include stabilizer measurement circuits, syndrome extraction logic, and error decoding algorithms configured in a manner consistent with the helical structure geometry. Pre-compiled circuits representing standard operations such as quantum Fourier transforms or neural network layer implementations may be loaded from a circuit library to reduce compilation time.

[0152] The orchestration phase 406 may follow initialization and may include compilation and scheduling operations that transform a logical circuit into an executable configuration for the dual-helix architecture. Compilation may include mapping logical qubits to physical nodes based on spatial coordinates and connectivity, and scheduling gate operations into layers and sublayers to enable parallel execution while avoiding node contention.

[0153] In some embodiments, orchestration may include mapping computational stages or circuit layers to localized node groups to improve locality and throughput. Such mapping is workload-dependent and may be applied to various circuit structures, including but not limited to layered computational models or other staged execution structures.Atorney Docket No. H7019.10012W001

[0154] The orchestration logic may optimize assignments and schedules based on connectivity requirements and resource constraints, including coupling fidelity, segment availability, and expected gate concurrency. The optimization may balance objectives such as minimizing circuit depth, maximizing parallelism, and reducing routing overhead without requiring a specific optimization criterion.

[0155] In some embodiments, the orchestration phase 406 includes a method for mapping circuit stages or logical gate layers of a quantum circuit onto quantum nodes positioned along the two intertwined helices. The mapping method may assign each stage of a plurality of stages to a distinct set of quantum nodes such that stages that exchange quantum information frequently are assigned to sets of quantum nodes that are adjacent along a helix and / or connected across helices by rung couplers. In some embodiments, adjacent stages are stages that are consecutive in an ordered execution sequence of the circuit. Assigning consecutive stages to node sets located on different helices may enable efficient inter-stage communication through cross-strand rung connections while maintaining spatial locality within each stage during execution.

[0156] The mapping method may begin by determining a number of quantum nodes required for a first stage of the circuit. The determination may be based on a width parameter associated with the stage, such as a number of logical qubits, a number of concurrent operations, or a resource requirement for representing the stage’s state space. In some embodiments, the first stage is assigned to a contiguous set of quantum nodes positioned along a first helix chain, where contiguous nodes are positioned at consecutive angular positions along the helical structure or otherwise treated as adjacent for scheduling purposes.

[0157] For a second stage adjacent to the first stage, the method may determine a number of quantum nodes required for the second stage and select a second set of quantum nodes on a second helix chain, where the number of quantum nodes in the second set equals the determined number for the second stage. In some embodiments, successive stages are alternately assigned between the first helix chain and the second helix chain. For example, a first stage may be mapped to a contiguous segment of nodes on helix chain A, a second stage may be mapped to a corresponding segment on helix chain B, a third stage may return to helix chain A, and a fourth stage may return to helix chain B. This alternating assignment may enable spatial pipelining, in which execution of a first stage on helix A may overlap in time with execution of a second stage on helix B, subject to scheduling constraints that avoid node contention. Cross-strand rung couplers may facilitate inter-stage state transferAtorney Docket No. H7019.10012W001between stages residing on opposite helices. The alternating assignment may reduce the need for long-range routing along a single helix in some execution scenarios, because each stage may exchange quantum information with predecessor and successor stages via short rung connections rather than multi-hop transfers along extended helical paths.

[0158] In some embodiments, the mapping method forms quantum connections between different sets of quantum nodes on different helices using rung couplers that provide direct quantum communication channels between node pairs. Such connections may support direct state transfer and entangling operations between node sets. In some embodiments, coupling strength Kij of a rung interconnect may be adjusted to maintain target entanglement fidelity Ftarget or another performance metric, according to a feedback relationship that increases or decreases coupling strength in response to measured performance. The feedback relationship may be of the form Kij(t+l)=Kij (t)+l(F target- Fij (t)), where is a tuning coefficient and Fij(t) is a measured fidelity obtained through calibration. Automatic tuning may compensate for thermal drift, optical drift, or other variations during operation.

[0159] In some embodiments, the orchestration phase 406 includes organizing entangling operations between adjacent nodes along the helical strands. Organizing entangling operations between adjacent nodes may be referred to as Helical Neighbor Coupling (HNC). HNC may refer to a quantum gate execution strategy that exploits geometric adjacency of quantum nodes positioned along the dual-helix structure to minimize circuit depth and routing overhead. In some embodiments, HNC restricts two-qubit entangling operations to physically adjacent or geometrically proximate node pairs, thereby reducing the need for long-range SWAP operations that introduce errors and increase circuit depth in planar architectures relative to the dual-helix topology.

[0160] In some embodiments, an adjacency set for a node i is defined as N(i)={i±k | l<k<K}, where K represents a maximum neighbor span or other proximity criterion. The adjacency set identifies nodes within a specified angular distance of node i along the helical path. For example, when k=l, the adjacency set includes immediate neighbors at i-1 and i+1. When k=2, the adjacency set includes neighbors at i-2 and i+2. The parameter K may be selected based on desired coupling range and physical constraints of the quantum hardware and may vary during execution.

[0161] Helical Neighbor Coupling may organize quantum gate operations into pairs (i,j) where jGN(i). Each pair may represent a two-qubit entangling operation between nodes i and j. The set of available pairs forms a connectivity graph in which nodes are vertices andAtorney Docket No. H7019.10012W001available entangling connections are edges. Edges may be classified into (i) helical neighbor edges connecting adjacent angular coordinates on the same helix, (ii) cross-strand rung edges connecting nodes on different helices at corresponding or near-corresponding positions, and (iii) long-range edges implemented through one or more of multi-hop routing or teleportation.

[0162] In some embodiments, the connectivity graph is edge-colored so that no node participates in more than one gate operation within a single sublayer. Edge-coloring enables parallel execution of multiple gate operations without conflicts, thereby reducing total circuit depth. For example, for each stride level k from 1 to K, candidate pairs may be partitioned into color classes using an edge-coloring or conflict-avoidance technique such that no two pairs in a color class share a node, and each color class is executed as a sublayer.

[0163] In some embodiments, cross-strand rung connections are incorporated into HNC. A primary rung may connect node Ai to node Bi at a corresponding angular coordinate. Secondary rung connections may connect node Ai to node Bi+2Am for m=0, 1,2,..., [log2NJ or other offset relationships to provide reduced-diameter connectivity across the architecture. Such rung connectivity enables long-range interactions to be performed in fewer routing steps (e.g., reduced linearly or non-linearly) rather than liner-hop routing.

[0164] An example implementation may include N=64 nodes, Nturn=8 nodes per turn, and A9=27t / 8=7t / 4 by way of illustration only. The helix may be divided into S=8 segments of 8 nodes each, and neighbor span may be set to K=2. For stride k=l, one sublayer may include gates (0,1), (2, 3), (4, 5),... and a second sublayer may include gates (1,2), (3, 4), (5, 6), .... For stride k=2, one sublayer may include gates (0,2), (4, 6), (8, 10), ... and a second sublayer may include gates (2, 4), (6, 8), (10, 12),.... Cross-rung gates (Ai,Bi) may be executed in a separate layer. This organization may reduce circuit depth relative to planar routing schemes.

[0165] In some embodiments, after orchestration partitions gates using HNC, the orchestration phase 406 further organizes quantum gate operations into execution layers based on physical adjacency relationships. A scheduling method may group quantum gates into layers such that gates within a layer can be executed in parallel without conflicts, and further into sublayers where necessary. A conflict occurs when two gates share a common quantum node, requiring that node to participate in multiple operations during the same execution interval. The scheduling method prevents such contention by ensuring that no quantum node participates in more than one gate operation per layer or per sublayer, during a scheduling interval, as applicable.Atorney Docket No. H7019.10012W001

[0166] In some embodiments, a first layer includes single-qubit gate operations (e.g., Rx, Ry, Rz, Hadamard, phase gates), which may be executed in parallel because they do not require inter-node coordination. A second layer includes two-qubit gate operations between helical neighbors along the same helix. These may be organized into two or more sublayers via edge-coloring. A third layer includes cross-strand rung gates between nodes on different helices, which may be executed in parallel when each node participates in at most one rung operation. A fourth layer includes long-range operations between non-adjacent nodes, implemented using one or more of teleportation, multi-hop routing, or secondary rung paths.

[0167] For teleportation-based long-range operations, pre-shared entanglement may be generated between source and destination nodes or along intermediate paths, followed by Bell-state measurements and conditional corrections. For multi-hop routing, SWAP operations or equivalent state-transfer operations may move quantum state along an intermediate node path, and the scheduler may minimize such operations by preferentially mapping frequently interacting logical qubits to geometrically proximate nodes.

[0168] In some embodiments, scheduling incorporates positional mode information when assigning gates to layers. Gates connecting nodes with similar angular positions may be scheduled earlier or grouped to reduce average routing distance. Scheduling may also incorporate segment boundaries such that gates within a segment are scheduled earlier and gates that span segments are scheduled later, in some scheduling strategies enabling concurrent execution of segment-local operations and reducing inter-segment contention.

[0169] An example of the layered scheduling method may be illustrated using a quantum circuit having multiple execution stages mapped onto a dual-helix architecture with 32 quantum nodes, 16 nodes on each helical strand. A first stage may be assigned to nodes A0 through A7 on the first helix chain 102 A, a second stage may be assigned to nodes B0 through B7 on the second helix chain 102B, a third stage may be assigned to nodes A8 through Al 5 on the first helix chain 102A, and a fourth stage may be assigned to nodes B8 through B15 on the second helix chain 102B. This mapping is illustrative and demonstrates spatially distributed execution using alternating helix placement.

[0170] In the example, a first stage may include single-qubit rotation gates applied to each of nodes A0 through A7. These single-qubit gates may be assigned to a first scheduling layer and executed in parallel. The circuit may further include two-qubit entangling gates between adjacent nodes along the first helix chain 102A, such as gates between (A0, Al), (Al, A2), (A2, A3), (A3, A4), (A4, A5), (A5, A6), and (A6, A7). These helical neighborAtorney Docket No. H7019.10012W001gates may be assigned to a second scheduling layer and organized into two sublayers using edge-coloring. A first sublayer may include gates (AO, Al), (A2, A3), (A4, A5), and (A6, A7), and a second sublayer may include gates (Al, A2), (A3, A4), and (A5, A6).

[0171] The circuit may include cross-strand rung gates that connect nodes on the first helix chain 102 A to corresponding nodes on the second helix chain 102B. For example, rung gates may connect node AO to node BO, node Al to node Bl, and so forth through node A7 to node B7. Such cross-strand rung gates may be assigned to a third scheduling layer. Because each node participates in at most one rung operation, the rung gates may be executed in parallel within a single sublayer of the third scheduling layer.

[0172] The layered scheduling method may be adapted to accommodate different types of quantum gate operations beyond the single-qubit and two-qubit gates described above. Multi-qubit gates involving three or more quantum nodes may be decomposed into sequences of single-qubit and two-qubit gates and assigned to appropriate scheduling layers. Measurement operations may be assigned to dedicated measurement layers after completion of a set of gate layers. Conditional operations that depend on measurement outcomes may be assigned to layers that execute after measurement results are obtained and processed by control circuitry.

[0173] The scheduling method may incorporate dynamic adjustments based on real-time feedback from the quantum hardware. For example, sensors 114 may monitor gate fidelity, coherence times, coupling drift, and / or readout performance during circuit execution. If a quantum node or connection exhibits degraded performance, the scheduling method may reassign gates involving that node or connection to alternative nodes or connections, or may modify a schedule by re-running an edge-coloring procedure with updated constraints. Updated schedules may be communicated to controller 104 and QPUs 116 for subsequent executions.

[0174] The scheduling method may provide technical advantages over conventional quantum circuit scheduling approaches. For example, exploiting helical adjacency may reduce SWAP operations required to implement a circuit, thereby reducing circuit depth and improving fidelity. Organizing gates into layers based on physical proximity enables parallel execution, reducing total execution time. Incorporating positional mode information and segment boundaries into scheduling may further reduce routing overhead and contention during execution.

[0175] In some embodiments, the orchestration phase 406 includes a time-window scheduling algorithm configured to allocate temporal execution intervals to differentAtorney Docket No. H7019.10012W001operation classes across the quantum computing architecture. The algorithm may partition execution time into discrete time windows, and each window may be assigned to an operation class such as circuit execution, calibration, readout, or idle. The time-window scheduling algorithm may determine which segments of the dual -helix structure 102 execute which operation class during each time window based on priority, segment availability, and resource constraints.

[0176] During the orchestration phase 406, verification operations may confirm readiness of the quantum system before execution begins. Verification may include checking that quantum nodes are initialized to designated states, confirming that rung couplers between helix chains are operating within fidelity thresholds, and validating that segment boundaries are correctly established such that no quantum node is assigned to conflicting execution roles.

[0177] The orchestration phase 406 may further include resource allocation operations that distribute computational resources across the quantum computing architecture. Resource allocation may include assigning classical control resources to specific segments, reserving measurement apparatus for designated nodes or subsystems, and reserving memory resources for intermediate state storage required by multi-stage circuit execution.

[0178] The orchestration phase 406 may also include synchronization operations that coordinate timing across distributed components of the quantum computing architecture. Synchronization may include establishing clock references or other timing coordination mechanisms for concurrent segment execution, calibrating delay compensation for crossstrand rung communications to account for path length differences, and setting trigger signals for coordinated gate execution across multiple segments. The orchestration phase 406 may include pre-computation operations such as generating lookup tables for positional phase values corresponding to node angular coordinates and computing reference measurement outcomes for verification.

[0179] The orchestration phase 406 may further include error budget allocation operations that distribute allowable error rates across components and operations. Error budget allocation may include assigning fidelity targets to gate operations, determining syndrome measurement frequencies, and establishing thresholds for triggering error correction procedures, segment remapping, or schedule adjustments.

[0180] The orchestration phase 406 may further include communication channel establishment operations that configure data pathways between quantum and classical subsystems. Communication channels may include pathways for transmitting measurementAtorney Docket No. H7019.10012W001results from QPUs to classical post-processing systems and pathways for transmitting control instructions and scheduling updates from classical controllers to quantum hardware.

[0181] The execution phase 408 may follow orchestration and involve running quantum circuits on the quantum computing architecture. The execution phase 408 may include applying quantum gates to quantum nodes, performing measurements, and collecting results according to schedules and mappings established during orchestration. Execution may leverage the spatial topology of the dual-helix structure to enable parallel operation across segments while maintaining coherence and reducing contention.

[0182] During the execution phase 408, single-qubit gates may be applied first in parallel across all quantum nodes requiring such operations. Single-qubit gates may include rotation gates such as Rx(9), Ry(9), and Rz(9), Hadamard gates, phase gates, and other unitary operations that act on individual nodes without requiring inter-node coordination. Singlequbit gates within a layer may be executed simultaneously subject to control hardware addressing capacity.

[0183] Following execution of single-qubit gates, two-qubit gates between helical neighbor nodes may be executed according to an edge-coloring schedule. Helical neighbor nodes may be positioned at adjacent angular coordinates along a helical strand. Two-qubit gates may include CNOT gates, CZ gates, controlled-phase gates, and other entangling operations. These gates may be organized into sublayers such that each sublayer contains gates that do not share common nodes, enabling parallel execution without conflicts.

[0184] After helical neighbor gates, cross-strand rung gates may be applied between nodes on different helical strands. Rung gates may connect nodes on the first helix chain 102A to corresponding nodes on the second helix chain 102B, for example at substantially the same vertical position or with an angular offset of approximately TI or another offset determined by geometry or implementation. Because each node may participate in at most one rung operation, rung gates may be executed in parallel within a single sublayer.

[0185] For gates requiring long-range connections between nodes not directly connected by helical neighbor links or rung connections, the execution phase 408 may implement long-range operations using quantum teleportation, multi-hop routing through intermediate nodes, and / or secondary interconnect paths as described herein.

[0186] In some embodiments, execution control includes segment-scoped control parameter sharing. For example, one or more control parameter values associated with quantum gate operations may be shared across quantum nodes within a defined segment to simplify control and reduce configuration overhead. Such shared control parameters mayAtorney Docket No. H7019.10012W001include rotation angles, coupling strengths, or phase offsets applied within a segment during an execution window.

[0187] Quantum nodes positioned along the intertwined helices may be partitioned into segments, where each segment comprises a contiguous group of nodes along a helix strand or spanning both strands. Segment boundaries may be defined by angular positions along the helix. A segment may span an angular range from ©start to ©end, where ©end = ©start + A0segment or another segment-defining relationship, and the number of nodes within a segment may be determined by the angular step A9 between adjacent nodes.

[0188] Each quantum node within a segment may be associated with one or more control parameter values that configure quantum gate operations applied to the node. Control parameters may include rotation angles for single-qubit gates, coupling strengths for two-qubit gates, or phase offsets for positional phase tagging operations. During execution, gate operations may be applied using the current control parameter values associated with the segment.

[0189] In some embodiments, segment-scoped control parameter values are updated between execution windows based on hardware calibration results, measured drift, or scheduling constraints. Such updates may be performed by classical control circuitry and applied uniformly across nodes of a segment prior to executing a subsequent circuit layer.

[0190] In some embodiments, segment-scoped control parameter sharing enforces that all nodes within a segment use the same value for a given parameter type. For a segment containing nodes {il, i2, ..., in}, a shared parameter value may be broadcast to each node such that a consistent configuration is applied across the segment during execution.

[0191] In some embodiments, the shared parameter value is generated using an aggregation of local measurements or calibration values collected from nodes within the segment. For example, measurement outcomes, fidelity estimates, or drift indicators may be combined to determine a segment-level configuration value that is applied to all nodes in the segment.

[0192] The quantum computing architecture may support multiple control parameter types, where each parameter type configures a different aspect of quantum gate operations. Segment-scoped parameter sharing may be applied independently to each parameter type, such that each parameter type has a segment-level shared value.

[0193] Segment-scoped control parameter sharing may be applied to positional phase tagging operations. For example, a positional phase tagging operation may apply a phase factor exp(ikOi) to a node i, where k is a tunable parameter and 6i is the angular position.Atorney Docket No. H7019.10012W001In some embodiments, nodes within a segment share a common k value during an execution window to maintain consistent spatial encoding behavior.

[0194] Segment-scoped control parameter sharing may be applied to helical neighbor coupling operations. For example, entangling gates between nodes at positions 0i and 0i±k or other proximity-defined relationships may be parameterized by a coupling strength and / or a phase offset. In some embodiments, a segment-level shared coupling parameter is applied to all entangling gates of a given stride type within the segment during execution.

[0195] Segment-scoped control parameter sharing may provide technical advantages including reduced control complexity, reduced configuration bandwidth, and improved execution stability under drift and noise. Applying shared configuration values across multiple nodes may reduce variance in execution behavior across a segment and may simplify scheduling and calibration procedures.

[0196] Segment boundaries may be selected to align with natural divisions in a quantum circuit structure, such as boundaries between execution stages, repetition blocks, or locality regions identified by compilation. Aligning segments to circuit structure may reduce crosssegment interactions and may simplify schedule generation.

[0197] Segment granularity may be selected based on a trade-off between control simplification and flexibility. Coarse-grained segmentation reduces the number of distinct configurations but may reduce adaptability to spatially varying conditions. Fine-grained segmentation increases configurability but may increase configuration overhead.

[0198] In some embodiments, segment-scoped control parameter sharing is applied asymmetrically across the two helical strands. For example, segments on the first helix chain 102A may use different angular spans or parameter sets than segments on the second helix chain 102B. Asymmetric segmentation may be used to accommodate differing physical conditions or differing execution roles across the two strands.

[0199] In some embodiments, segment-level execution configuration is dynamically adjusted during operation of the quantum computing system. Initially, the architecture may employ fine-grained segmentation with many small segments to support localized execution control and calibration. Over time, segmentation may be coarsened by merging adjacent segments to reduce configuration overhead and to improve scheduling efficiency. Dynamic segmentation may be controlled by monitoring execution metrics across segments, including calibration drift, gate fidelity estimates, coherence-time estimates, routing contention, and / or measurement error rates. When adjacent segments exhibitAtorney Docket No. H7019.10012W001similar execution characteristics, the segments may be merged to reduce control complexity while maintaining execution performance.

[0200] In some embodiments, segment-level configuration is combined with cross-strand synchronization. When corresponding segments on the first helix chain 102 A and the second helix chain 102B perform related execution roles, one or more control parameter values for these segments may be synchronized to maintain consistent behavior across the strands. Synchronization may be implemented by applying the same segment-level configuration values to both strands during a scheduling interval, or by coordinating updates using inter-helix rung connections that provide communication channels between corresponding nodes on opposite strands.

[0201] In some embodiments, segment-level configuration values control settings of physical gate-implementation hardware. For photonic implementations, shared configuration values may set parameters of optical modulators, phase shifters, beam spliters, tunable couplers, or interferometric elements that implement quantum gate operations. In superconducting implementations, shared configuration values may configure amplitude, frequency, and phase characteristics of microwave pulses applied to qubits and couplers. In ion-trap implementations, shared configuration values may set intensity, frequency, or duration of laser pulses applied to trapped ions. Other physical implementations may use corresponding control mechanisms.

[0202] In some embodiments, segment-level configuration is monitored and validated to promote uniform application across nodes within a segment. The system may track variance of configuration values, calibration residuals, measurement outcomes, or fidelity indicators within each segment. If a segment exhibits divergence beyond a threshold, the system may trigger a resynchronization operation to restore segment consistency, may subdivide the segment to localize control, or may remap execution away from degraded nodes.

[0203] In some embodiments, segment-level configuration may interact with error management. When errors occur within a segment, the error correction module 106 may detect the errors and apply corrective actions. During such corrective actions, the system may temporarily adjust execution scheduling, segment boundaries, or segment configuration values to isolate affected resources and maintain overall execution stability.

[0204] In some embodiments, segment-level configuration supports adaptive execution management. For example, the system may coordinate updates at local and segment levels, and may optionally compute a system-level configuration update based on aggregated measurement results from multiple segments. Aggregation may be implemented usingAtorney Docket No. H7019.10012W001classical processing resources and may inform subsequent scheduling decisions, selection of gate layers, or reconfiguration of segments, without requiring a particular specific optimization algorithm.

[0205] In some embodiments, during execution coordination, measurement results obtained from quantum processing nodes may be post-processed by a classical controller using temporal filtering to suppress noise before the results are used for subsequent execution decisions. The temporal filtering may implement a moving-average filter or exponential smoothing to reduce variance in measurement outcomes arising from readout noise, drift, or other disturbances. For example, a filtered measurement value m'i may be computed from a current measurement value mi and a prior filtered value mi— 1 using a relationship such as m'i = Pmi + (l-p)mi-l, where P is a smoothing coefficient.

[0206] Filtered measurement results may be used to support execution control actions, including schedule selection, segment boundary adjustments, calibration updates, routing decisions, and / or error management actions. In some embodiments, the smoothing coefficient P may be adjusted based on observed measurement variance, for example by increasing P when variance is low to improve responsiveness and decreasing P when variance is high to improve robustness.

[0207] The parameter adjustment phase 410 may follow the execution phase 408 and may involve updating variational parameters that control the behavior of quantum gates and operations within the quantum computing architecture. The parameters adjustment phase 410 may enable iterative refinement of quantum circuit performance by modifying rotation angles, coupling strengths, phase offsets, and other adjustable quantities that influence quantum state evolution. The parameters adjustment phase 410 may be performed using gradient-based optimization methods, reinforcement learning techniques, heuristic techniques, or hybrid quantum-classical approaches that combine quantum measurement outcomes with classical computational resources.

[0208] In some embodiments, the gradients computed during the parameters adjustment phase 410 may be aggregated across multiple quantum nodes, segments, or measurement shots to reduce statistical noise and improve the accuracy of parameter updates. The parameters adjustment phase 410 may employ adaptive learning rate schedules, momentum-based optimization, or second-order or quasi-second-order methods that adjust the magnitude and direction of parameter updates based on the history of previous gradient measurements and the curvature of the cost function landscape.Atorney Docket No. H7019.10012W001

[0209] The error correction phase 412 may follow an execution phase and / or be interleaved with execution and may implement quantum error detection and / or correction procedures adapted to the dual-helix quantum architecture. The error correction phase 412 may detect and correct errors that accumulate during quantum circuit execution. In some embodiments, error correction exploits geometric properties of the dual-helix structure to provide efficient syndrome extraction and recovery. Error correction may operate continuously or periodically to maintain logical qubit fidelity above thresholds suitable for fault-tolerant operation.

[0210] In some embodiments, aggregator nodes participate in error detection and correction procedures. For example, an aggregator node may monitor quantum states and / or measurement outcomes received from quantum nodes in a segment to identify error conditions. Monitoring may include parity checks, stabilizer measurements, or comparisons against expected values.

[0211] When an aggregator node detects an error condition associated with a quantum node, the aggregator node may initiate an error handling procedure. The error handling procedure may include requesting re-preparation and / or re-acquisition of a state, invoking quantum error correction codes, flagging the node as degraded, or initiating diagnostic procedures. Aggregator nodes may also perform collective error detection across a segment using stabilizers that span multiple nodes.

[0212] When collective errors are detected, the aggregator node may coordinate corrective actions across multiple quantum nodes. Such actions may include broadcasting correction signals, temporarily suspending execution within a segment, initiating lattice- surgery operations, and / or other remapping procedures triggering segment remapping to isolate degraded resources.

[0213] In some embodiments, ring stabilizers are deployed to perform localized error detection within each helical turn. A ring stabilizer may comprise a parity check operator that measures a collective state of multiple nodes within a 360-degree turn of the helix. For a turn containing nodes {il, i2, ..., in}, a ring stabilizer may be defined for example as Sturn = nj Gturn Zj for phase-flip detection or Sturn = Hj Gturn Xj for bit-flip detection. Syndrome extraction may be performed using controlled operations between nodes and an ancilla qubit, followed by ancilla measurement.

[0214] In some embodiments, helical latice surgery is used to dynamically remap logical qubits away from faulty regions of the dual-helix structure. Lattice surgery may include merge and split operations that redistribute logical qubit support across adjacent turns orAtorney Docket No. H7019.10012W001segments. When an error metric for a segment exceeds a threshold, the system may transfer logical information to an adjacent segment with lower error rates and update execution scheduling accordingly.

[0215] In some embodiments, error rates across segments are monitored to dynamically adjust workload allocation and execution routing. For example, the error correction module 106 may compute a segment-level error metric representing a measure of detected errors within a time window. Segments exceeding a threshold may be flagged as high-noise regions, and scheduling logic may divert execution away from such segments, increase correction frequency, or reroute long-range operations through alternative paths (e.g., different rung couplers or teleportation links). Persistent error histories may be used to identify hardware defects requiring recalibration or repair.

[0216] The convergence / evaluation phase 414 may follow the error correction phase 412. In some embodiments, an evaluation phase 414 determines whether a scheduled circuit execution has achieved one or more a target execution condition. For example, the evaluation phase may assess whether required measurement outcomes have been collected, whether execution has completed required layers, or whether additional execution iterations are needed. When additional execution is needed, the process flow may return to orchestration phase 406 for schedule generation or reconfiguration. In response to no further iterations of parameter updates and / or no further circuit executions being warranted, the process flow 400 may proceed to the inference and output phase 416.

[0217] In some embodiments, evaluation includes monitoring one or more execution metrics such as measurement fidelity, success probability and / or confidence level, timing constraints, and / or error syndrome rates. Such metrics may be used to determine whether additional runs of a circuit (or additional layers) are required and to update scheduling and resource allocation.

[0218] In some embodiments, evaluation includes determining whether a scheduling interval, segment allocation, or gate-layer plan should be modified based on observed execution behavior. For example, if measured error rates or contention exceed one or more thresholds, the system may adjust segment boundaries, revise edge-coloring assignments, or reroute long-range operations.

[0219] An output phase 416 may follow evaluation and may generate output values based on measurement results and / or derived classical post-processing produced during circuit execution. Output values may be stored, transmitted via the classical computing interface 122, and / or used as inputs to subsequent quantum circuit executions.Atorney Docket No. H7019.10012W001

[0220] The output phase 416 may include loading new input data and / or new circuit descriptions or configuration selections for subsequent execution cycles. Input data may be encoded into quantum states using the disclosed multi-dimensional encoding mechanisms and may be assigned to quantum nodes based on angular position and geometric locality.

[0221] In some embodiments, the output phase 416 includes executing a circuit using fixed configuration values for a selected execution interval. Configuration values may include rotation parameters, coupling settings, and / or phase offsets. The circuit may be executed according to a schedule generated by the orchestration phase, and measurement results may be collected for output or subsequent scheduling decisions.

[0222] The process flow 400 illustrated in FIG. 4 may represent one illustrative example embodiment of how quantum computing operations may be organized and executed on the dual-helix quantum architecture described herein. The particular sequence of phases shown in FIG. 4 may be adapted, modified, or reorganized depending on the specific quantum artificial intelligence workload, hardware configuration, or algorithmic requirements. Alternative embodiments may omit one or more of the phases depicted in FIG. 4, may execute phases in a different order, may perform phases concurrently rather than sequentially, or may include additional phases not explicitly shown in FIG. 4. For example, some quantum neural network training workflows may bypass the inference and output phase 416 during iterative training cycles, while some inference-only workloads may omit the parameter adjustment phase 410 and convergence / evaluation phase 414. The process flow 400 may serve as a representative framework for understanding how the dual-helix quantum architecture may support end-to-end quantum-enabled Al computation, but the architecture itself may support a wide variety of computational workflows beyond the specific example illustrated in FIG. 4.ILLUSTRATIVE METHODS

[0223] Figures 5-10 illustrate non-limiting example methods that may be performed using the disclosed architecture. These methods demonstrate how quantum computations may be organized, scheduled, and executed using spatially organized quantum nodes.

[0224] The illustrated methods are non-limiting and may be modified, reordered, combined, or omitted depending on the specific application. The disclosed architecture does not require execution of any particular method unless explicitly claimed.

[0225] FIG. 5 depicts a flowchart of a method 500 for quantum computing, arranged in accordance with at least one embodiment described herein. The method 500 may beAtorney Docket No. H7019.10012W001programmatically performed or controlled by a processor in, e.g., a computer and / or server coupled to the classical computing interface 122. In an example implementation, the method 500 may be performed in whole or in part by the system 100 of FIG. 1 A under the control of a classical processor (coupled to the classical computing interface 122). Some embodiments herein may include a non-transitory computer-readable storage medium that includes computer-executable instructions executable by a processor device to perform or control performance of any operations herein, such as the operations of the method 500 of FIG. 5. The method 500 may include one or more of blocks 502, 504, and / or 506.

[0226] The method 500 may begin at block 502. At block 502, spatial coordinates may be obtained for each of one or more quantum nodes positioned along two intertwined helices of a quantum computing architecture. The spatial coordinates may be based on angular positions of the quantum nodes along the intertwined helices. Each quantum node may be assigned a deterministic spatial coordinate (xi, yi, zi) derived from an angular position 9i according to parametric equations xi = r cos(9i), yi = r sin(9i), and zi = (h / 27t) 9i, where r denotes the helix radius, h denotes the pitch, and 6i = i • A0 represents the angular coordinate of node i. The angular step A9 may determine the node density along each helical strand. The spatial coordinate 0i may function simultaneously as a logical register within a quantum state representation and as a physical address identifying the geometric location of the node within the three-dimensional helical structure.

[0227] The spatial coordinates may be obtained from a configuration file or data structure that stores the geometric parameters of the double-helix architecture. The geometric parameters may include the radius r, the pitch h, and the angular step A0. In some embodiments, the spatial coordinates may be calculated during or prior to initialization time and stored in a lookup table for efficient access during quantum circuit execution. Alternatively, the spatial coordinates may be computed on-demand based on the node index i and the geometric parameters.

[0228] At block 504, a quantum state may be prepared on at least one of the quantum nodes. The quantum state may include a positional mode with a value that corresponds to the spatial coordinate of the at least one of the quantum nodes For example, a positional mode may correspond to angular coordinate 9 and may be embedded into the quantum state via a phase tagging operation. A positional-phase tagging operator such as Upos(k) may be applied to each quantum state, where the operator takes the form Upos(k) = exp(ik9i) for a given spatial frequency parameter k.Atorney Docket No. H7019.10012W001

[0229] At block 506, one or more quantum computations may be performed on the quantum state stored on the at least one of the quantum nodes. The quantum computations may include applying quantum gates, performing measurements, and processing one or more measurement outcomes to generate computational results. The quantum gates may include single-qubit gates and two-qubit gates that transform the quantum states according to unitary operations.

[0230] In some embodiments, neighboring quantum nodes may be selected based on the positional mode of the at least one of the quantum nodes and the neighboring quantum nodes. The selection may preferentially restrict gate connections for the at least one of the quantum nodes to the neighboring quantum nodes. The neighboring quantum nodes may be defined as nodes positioned at adjacent angular coordinates along the same helical strand or nodes positioned on different helical strands but at substantially the same angular position. In some embodiments, operations of the gate connections may be organized in a sublayer of the quantum computations so that no quantum node is involved in more than one gate operation per sublayer of the quantum computing architecture.

[0231] In some embodiments, operations for a plurality of sublayers in the quantum computing architecture may be executed in parallel. The parallel execution may occur when the sublayers correspond to different segments of the helical structure that do not share any common quantum nodes. Each segment may comprise a contiguous group of quantum nodes along one of the helical strands.

[0232] In some embodiments, execution includes configuring one or more control parameter values associated with quantum gate operations. Control parameter values may include rotation angles, coupling strengths, and phase offsets. Control parameter values may be assigned per node and / or shared across nodes within a segment to reduce configuration overhead.

[0233] In some embodiments, a common control parameter value for a segment may be determined based on calibration values, measurement results, or other execution metrics obtained from nodes in the segment. The common control parameter value may be broadcast to nodes within the segment prior to executing a subsequent scheduling interval.

[0234] In some embodiments, the quantum nodes in the segment may each include a plurality of trainable parameter types that are updated. During the quantum computations, the value for each trainable parameter type may be updated to a common value across all the quantum nodes in the segment such that for each trainable parameter type all quantum nodes in the segment are updated to the same value. For example, a first parameter typeAtorney Docket No. H7019.10012W001may control rotation angles for Ry gates, a second parameter type may control rotation angles for Rz gates, and a third parameter type may control coupling strengths for entangling gates. The segment-scoped parameter tying mechanism may be applied independently to each parameter type. For each parameter type, the local gradients for that parameter type may be aggregated across all nodes in the segment to produce a segment-averaged gradient for that parameter type. The segment-averaged gradient may then be used to update the shared parameter value for that parameter type within the segment.

[0235] One skilled in the art will recognize that, for this and other processes and methods disclosed herein, the functions performed in the processes and methods may be implemented in differing order. Further, the outlined steps and operations are only provided as examples, and some of the steps and operations may be optional, combined into fewer steps and operations, or expanded into additional steps and operations without detracting from the essence of the disclosed embodiments.

[0236] FIG. 6 depicts a flowchart of a method 600 for quantum computing, arranged in accordance with at least one embodiment described herein. The method 600 may be programmatically performed or controlled by a processor in, e.g., a computer and / or server coupled to the classical computing interface 122. In an example implementation, the method 600 may be performed in whole or in part by the system 100 of FIG. 1 A under the control of a classical processor (coupled to the classical computing interface 122). Some embodiments herein may include a non-transitory computer-readable storage medium that includes computer-executable instructions executable by a processor device to perform or control performance of any operations herein, such as the operations of the method 600 of FIG. 6.

[0237] At block 602, a quantum neural network with a plurality of network layers may be obtained. The quantum neural network may represent one example of a computational model comprising multiple sequential or interconnected layers that perform quantum operations on input data.

[0238] At block 604, each network layer of the plurality of network layers may be logically assigned to a distinct set of quantum nodes positioned along two intertwined helices of a quantum computing architecture. The assignment may be performed such that adjacent network layers of the plurality of network layers are assigned to sets of quantum nodes on different ones of the intertwined helices. Adjacent network layers may be layers that are consecutive in an ordered sequence of layers in the quantum neural network. TheAtorney Docket No. H7019.10012W001ordered sequence may represent the forward propagation path through the network during inference or the combined forward and backward propagation paths during training.

[0239] The assignment process may begin by determining a number of quantum nodes required for a first network layer. The determination may be based on a width parameter associated with the layer, which may correspond to the number of neurons or quantum processing elements required to represent the layer's computational capacity. A first set of quantum nodes on a first helix of the intertwined helices may be selected, where the number of quantum nodes in the first set equals the determined number of quantum nodes for the first network layer. The first set of quantum nodes may comprise contiguous quantum nodes on the first helix. Contiguous quantum nodes may be positioned at consecutive angular positions along the helical structure without gaps in the angular coordinate sequence.

[0240] For a second network layer adjacent to the first network layer, a number of quantum nodes required for the second network layer may be determined. A second set of quantum nodes on a second helix of the intertwined helices may be selected, where the number of quantum nodes in the second set equals the determined number of quantum nodes for the second network layer. The alternating assignment of consecutive layers between the first helix and the second helix may facilitate efficient inter-layer communication through cross-strand rung connections while maintaining spatial locality within each layer.

[0241] The alternating assignment may be implemented according to a mapping strategy wherein odd-numbered layers are assigned to nodes on the first helix chain while even-numbered layers or stages are assigned to nodes on the second helix chain. Stage 1 may be mapped to a contiguous segment of nodes on helix chain A. Stage 2 may be mapped to a corresponding segment on helix chain B. Stage 3 may return to helix chain A. Stage 4 may return to helix chain B. The alternating pattern may continue for all layers in the network. This mapping is illustrative and may be used to support spatial pipelining in which different stages execute in overlapping time windows subject to scheduling constraints that avoid node contention.

[0242] Quantum connections may be formed between different sets of quantum nodes on different ones of the intertwined helices. These quantum connections may be implemented through rung couplers that provide direct quantum communication channels between nodes on the first helix and nodes on the second helix. In some embodiments, rung couplers may be configured to operate bidirectionally, enabling both forward data flow and backwardAtorney Docket No. H7019.10012W001gradient flow within the same physical interconnect structure. Trainable parameters associated with a network layer of the plurality of network layers may be mapped to quantum connections between quantum nodes of the set of quantum nodes to which the network layer is assigned.

[0243] At block 606, one or more quantum computations may be performed using the quantum computing architecture. The quantum computations may include applying quantum gates to quantum nodes, performing measurements, and collecting results according to the schedules and mappings established during the assignment process. The quantum computations may advantageously leverage the spatial topology of the doublehelix structure to enable parallel execution of quantum operations across multiple segments while maintaining coherence and minimizing errors.

[0244] In some embodiments, quantum computations include applying local operations at one or more quantum nodes and applying inter-node operations between neighboring nodes. Local operations may include single-qubit gates and parameterized rotations. Internode operations may include entangling gates executed between helical neighbors or between cross-strand node pairs coupled by rung couplers. In some embodiments, measurement outcomes are collected and processed by classical control circuitry to support execution coordination, scheduling updates, and / or error management.

[0245] The quantum computations may include two or more logically distinct sets of quantum nodes on a helix of the intertwined helices forming a spatial data pipeline. For example, while a first set of nodes executes a first circuit stage, a second set of nodes may execute a second circuit stage, such that different regions of the dual-helix structure execute different stages concurrently in space. Spatial pipelining may be coordinated using scheduling intervals and segment boundaries to prevent resource conflicts.

[0246] One skilled in the art will appreciate that, for this and other processes and methods disclosed herein, the functions performed in the processes and methods may be implemented in differing order. Further, the outlined steps and operations are only provided as examples, and some of the steps and operations may be optional, combined into fewer steps and operations, or expanded into additional steps and operations without detracting from the scope or spirit of the disclosed embodiments.

[0247] FIG. 7 depicts a flowchart of a method 700 for quantum computing, arranged in accordance with at least one embodiment described herein. The method 700 may be programmatically performed or controlled by a processor in, for example, a computer or server coupled to the classical computing interface 122 of FIG. 1A. In an exampleAtorney Docket No. H7019.10012W001implementation, the method 700 may be performed in whole or in part by the system 100 of FIG. 1A under the control of a classical processor coupled to the classical computing interface 122. Some embodiments herein may include a non-transitory computer-readable storage medium that includes computer-executable instructions executable by a processor device to perform or control performance of any operations herein, such as the operations of the method 700 of FIG. 7.

[0248] The method 700 may begin at block 702. At block 702, similarities may be determined between a plurality of computational elements for quantum computing. The computational elements may include data from a dataset or variables from a computational model. For data-based computational elements, each element may correspond to a feature vector, a data point, or a tensor component from an input dataset. For model-based computational elements, each element may correspond to a weight parameter, a bias term, or a trainable coefficient within a quantum neural network or variational quantum circuit. In some embodiments, relationships may be quantified using a distance metric, correlation metric, dependency metric, or connectivity score representing expected interaction between computational elements during circuit execution. For example, the similarity between computational elements may be quantified using a similarity function that measures the degree of relatedness or correlation between pairs of elements. For data vectors, the similarity function may compute a distance metric such as Euclidean distance, cosine similarity, or kernel -based similarity measures. For model variables, the similarity may be determined by computing connectivity scores that reflect the frequency or strength of interactions between variables during computational operations. The connectivity score for a variable may be calculated by summing the absolute values of coupling coefficients between that variable and all other variables in the model.

[0249] In some embodiments, the determination of similarities may involve constructing a similarity graph where nodes represent computational elements and edges represent similarity relationships exceeding a similarity threshold value. Alternatively or additionally, the determination may involve computing a pairwise similarity matrix where each entry represents the similarity between a pair of computational elements.

[0250] At block 704, the computational elements is preferentially assigned to quantum nodes positioned along two intertwined helices of a quantum computing architecture based on the similarities between the plurality of computational elements. The assignment may be performed such that similar computational elements are assigned to quantum nodes that are closer in physical proximity to one another than quantum nodes assigned to dissimilarAtorney Docket No. H7019.10012W001computational elements. The assignment process may utilize the deterministic spatial coordinates of quantum nodes along the helical structure to assign computational elements to specific quantum nodes based on the spatial coordinate of that node along the helical structure. Alternately or additionally, in some embodiments, elements expected to interact frequently are assigned to quantum nodes having smaller angular separation or to nodes coupled by rung connections to reduce routing overhead during execution.

[0251] In some embodiments, computational elements are ordered prior to assignment so that related elements are assigned to nearby angular positions along a helix. The ordered elements may be mapped sequentially to quantum nodes such that locality of the ordering corresponds to geometric locality of the node topology. For example, the ordering process may arrange elements such that elements with higher mutual similarity are positioned earlier in the sorted sequence.

[0252] In some embodiments, similar computational elements may be assigned to quantum nodes on the same helix of the two intertwined helices. The assignment to a single helix may reduce the physical distance between quantum nodes storing similar computational elements, thereby minimizing the number of cross-helix operations required during quantum computations. For example, the quantum nodes on the first helix chain 102A may store a first subset of computational elements that exhibit high mutual similarity, while the quantum nodes on the second helix chain 102B may store a second subset of computational elements that exhibit high mutual similarity within the second subset but lower similarity to elements in the first subset. In other embodiments, assignment alternates between helices to enable cross-strand entangling operations via rung couplers, depending on circuit structure and scheduling constraints.

[0253] At block 706, one or more quantum computations may be performed using the quantum computing architecture. The quantum computations may include applying quantum gates to quantum nodes, performing measurements, and collecting results according to the schedules and mappings established during the assignment process.

[0254] In some embodiments, measurement results collected during execution are used by a control system to update scheduling decisions, segment allocations, and / or configuration values for subsequent execution intervals. Such updates may be based on measured error rates, fidelity estimates, routing contention indicators, or other execution metrics.

[0255] In some embodiments, segment-level aggregation of measurement results is performed to produce segment-level metrics used to coordinate execution. Segment-levelAtorney Docket No. H7019.10012W001metrics may be combined across segments to produce global execution metrics that inform schedule revision, segment reconfiguration, or error mitigation actions.

[0256] One skilled in the art will appreciate that, for this and other processes and methods disclosed herein, the functions performed in the processes and methods may be implemented in differing order. Further, the outlined steps and operations are only provided as examples, and some of the steps and operations may be optional, combined into fewer steps and operations, or expanded into additional steps and operations without detracting from the essence of the disclosed embodiments.

[0257] FIG. 8 depicts a flowchart of a method 800 for quantum computing using a dualhelix quantum architecture, arranged in accordance with at least one embodiment described herein. The method 800 may be programmatically performed or controlled by a processor in, for example, a computer or server coupled to the classical computing interface 122 of FIG. 1 A. In an example implementation, the method 800 may be performed in whole or in part by the system 100 of FIG. 1 A under the control of a classical processor coupled to the classical computing interface 122. Some embodiments herein may include a non-transitory computer-readable storage medium that includes computer-executable instructions executable by a processor device to perform or control performance of any operations herein, such as the operations of the method 800 of FIG. 8.

[0258] The method 800 may begin at block 802. At block 802, one or more layers of a quantum circuit may be executed on a quantum computing architecture that includes quantum nodes positioned along two intertwined helices. One of the layers may include execution of quantum gates that extend between quantum nodes on different ones of the intertwined helices via rung couplers. In some embodiments, the quantum computing architecture may comprise the dual-helix structure 102 of FIG. 1 A.

[0259] The execution of one or more layers of the quantum circuit may involve applying quantum gates to quantum states stored at the quantum nodes. In some embodiments, only a single quantum operation is performed at each quantum node during execution of any one layer, preventing a node from participating in multiple gate operations simultaneously. In some embodiments, gate operations are organized into sublayers using an edge-coloring algorithm applied to a connectivity graph so that no two gates in a sublayer share a quantum node, enabling parallel execution of all gates in the sublayer.

[0260] In some embodiments, a second layer of the one or more layers may include execution of quantum gates that extend between physically adjacent quantum nodes along the same helix. Physically adjacent quantum nodes may be quantum nodes positioned atAtorney Docket No. H7019.10012W001consecutive angular positions along the helical structure without gaps in the angular coordinate sequence. The second layer may be executed before the one of the layers that includes quantum gates extending between quantum nodes on different helices. In some embodiments, a third layer of the one or more layers may include execution of single qubit gates. The third layer may be executed before the second layer.

[0261] One skilled in the art will appreciate that, for this and other processes and methods disclosed herein, the functions performed in the processes and methods may be implemented in differing order. Further, the outlined steps and operations are only provided as examples, and some of the steps and operations may be optional, combined into fewer steps and operations, or expanded into additional steps and operations without detracting from the essence of the disclosed embodiments.

[0262] FIG. 9 depicts a flowchart of a method 900 for quantum computing using a dualhelix quantum architecture, arranged in accordance with at least one embodiment described herein. The method 900 may be programmatically performed or controlled by a processor in, for example, a computer or server coupled to the classical computing interface 122 of FIG. 1 A. In an example implementation, the method 900 may be performed in whole or in part by the system 100 of FIG. 1 A under the control of a classical processor coupled to the classical computing interface 122. Some embodiments herein may include a non-transitory computer-readable storage medium that includes computer-executable instructions executable by a processor device to perform or control performance of any operations herein, such as the operations of the method 900 of FIG. 9.

[0263] The method 900 may begin at block 902. At block 902, data regarding quantum gates and quantum nodes associated with each quantum gate may be obtained. The quantum gates may form part of a quantum circuit on a quantum computing architecture that includes quantum nodes positioned along two intertwined helices. The quantum computing architecture may comprise the dual-helix structure 102 of FIG. 1A. The quantum nodes may be positioned along the first helix chain 102A and the second helix chain 102B.

[0264] The data regarding quantum gates may include gate type, target node identifiers, control node identifiers, and any parameters associated with each gate. The data regarding quantum nodes may include spatial coordinates, angular positions along a helix, and helix membership. The data may be obtained from a circuit specification and / or produced by a compiler configured to map a logical circuit to the physical topology.

[0265] At block 904, an execution order of the quantum gates may be scheduled based on the data. The scheduling may organize the quantum gates into one or more layers ofAtorney Docket No. H7019.10012W001quantum gate execution. One of the one or more layers may be scheduled to include quantum gates that extend between quantum nodes on different ones of the intertwined helices. The scheduling process may determine the temporal sequence in which quantum gates are executed and may group gates into layers such that gates within a layer may be executed in parallel without conflicts.

[0266] The scheduling process may classify quantum gates based on the physical distance between the quantum nodes involved in each gate operation. For example, single-qubit gates may be assigned to an early layer, two-qubit gates between helical neighbor nodes may be assigned to a second layer, cross-strand rung gates may be assigned to a third layer, and long-range gates requiring multi -hop routing or teleportation may be assigned to a later layer.

[0267] In some embodiments, scheduling incorporates positional information associated with quantum nodes. For example, a positional mode may represent angular coordinate 9i of a node, and gates connecting nodes with similar 9 values may be preferentially scheduled earlier or grouped to reduce routing distance and contention.

[0268] Gates connecting nodes with dissimilar positional modes may be assigned to later layers, and scheduling may further incorporate segment boundaries such that intra-segment gates are scheduled earlier and inter-segment gates are scheduled later, enabling concurrent execution across segments while controlling inter-segment contention.

[0269] Within each layer, an edge-coloring algorithm may be applied to organize gates into sublayers such that no quantum node participates in more than one gate operation per sublayer. For helical neighbor layers, multiple sublayers may be used to support parallel execution while maintaining the single-operation-per-node constraint.

[0270] The scheduling process may incorporate information about segment boundaries when determining gate assignments to layers. The dual-helix structure may be divided into segments, where each segment comprises a contiguous group of quantum nodes along a helical strand and segment boundaries are defined by angular positions along the helix. In some embodiments, gates that connect nodes within a same segment are assigned to earlier layers, and gates that connect nodes in different segments are assigned to later layers, thereby enabling parallel intra-segment execution while controlling inter-segment contention.

[0271] At block 906, the quantum circuit may be executed based on the scheduled execution order of the quantum gates. The execution may involve applying quantum gates to quantum states stored at the quantum nodes according to the scheduled sequence ofAtorney Docket No. H7019.10012W001layers and sublayers. The quantum gates may transform the quantum states according to unitary operations parameterized by the gate parameters specified in the quantum circuit specification.

[0272] In some embodiments, the execution of the first layer may involve applying singlequbit gates to individual quantum nodes. The single-qubit gates may be applied in parallel across all quantum nodes that require such operations. The execution of the second layer may involve applying two-qubit gates between helical neighbor nodes. The execution of the third layer may involve applying cross-strand rung gates between quantum nodes on different helical strands. The execution of the fourth layer may involve implementing long-range gates through quantum teleportation or multi-hop routing.

[0273] The execution of quantum gates may be coordinated by multiple components of the quantum computing system 100. The central control module 108 may coordinate the timing of gate operations across multiple quantum nodes. The task scheduler 110 may determine which quantum nodes execute which gates during each layer. The sensors 114 may monitor the fidelity of gate operations. The error correction module 106 may detect and correct errors that occur during gate execution.

[0274] The scheduling process may incorporate dynamic adjustments based on real-time feedback from the quantum hardware. If a particular quantum node or connection exhibits degraded performance, the scheduling process may dynamically reassign gates involving that node or connection to alternative nodes or connections. The dynamic adjustment may involve re-running the edge-coloring algorithm with updated connectivity information that excludes or deprioritizes the degraded elements.

[0275] One skilled in the art will appreciate that, for this and other processes and methods disclosed herein, the functions performed in the processes and methods may be implemented in differing order. Further, the outlined steps and operations are only provided as examples, and some of the steps and operations may be optional, combined into fewer steps and operations, or expanded into additional steps and operations without detracting from the essence of the disclosed embodiments.

[0276] FIG. 10 illustrates a method 1000 of operating a quantum computing system comprising quantum nodes arranged along two intertwined helices. The method 1000 may be executed by a control system operatively coupled to the quantum computing system. The control system may include one or more processors, memory storing instructions, and interfaces for transmitting control signals to the quantum nodes and receiving measurement data from the quantum nodes. The method 1000 provides an example scheduling andAtorney Docket No. H7019.10012W001execution framework that exploits the geometric properties of the double-helix architecture to reduce circuit depth, minimize routing overhead, and enable parallel execution of quantum gate operations.

[0277] At block 1002, the method 1000 includes logically scheduling quantum gate operations across quantum nodes arranged along two intertwined helices based on angular adjacency. The quantum nodes may be positioned at deterministic spatial coordinates derived from angular positions 9 along the helices.

[0278] The scheduling of quantum gate operations may be based on angular adjacency, meaning that gates are preferentially scheduled between nodes that are close in angular coordinate along the helices.

[0279] The scheduling process may include classifying gates into multiple layers based on the physical distance between the quantum nodes involved in each gate. A first layer (L0) may include single-qubit gates that operate on individual nodes and may be executed in parallel across all nodes. A second layer (LI) may include two-qubit gates between nearest-neighbor nodes, where the physical distance corresponds to adjacent angular positions 9 and 9 ± A9 along the same strand. A third layer (L2) may include cross-rung gates that extend between quantum nodes on different strands, such as gates between nodes (Ai, Bi) connected by a rung coupler. A fourth layer (L3) may include long-range gates between nodes separated by a distance greater than a predefined threshold, which may be implemented using teleportation channels or photonic bus connections.

[0280] Within each layer, the scheduling process may perform edge coloring of the gate connectivity graph to identify conflict-free sublayers. Edge coloring may assign a color to each gate such that no two gates sharing a quantum node receive the same color. Gates assigned the same color may be executed in parallel within a sublayer.

[0281] The scheduling may exploit the helical geometry to minimize the need for SWAP operations. In the double-helix architecture, the rungs connecting strands A and B provide shortcuts that reduce the graph diameter to logarithmic scale. Long-range gates may be assigned to rung connections, allowing quantum states to be transferred between distant nodes in O(log N) hops rather than O(N) hops. This reduction in routing overhead may decrease the circuit depth by by a substantial amount compared to planar architectures.

[0282] The scheduling may also account for segment boundaries. Gates may be scheduled such that operations within a segment execute in parallel, while operations spanning multiple segments are synchronized at segment boundaries.Atorney Docket No. H7019.10012W001

[0283] The scheduling may further incorporate positional phase tagging (PPT). Each quantum node may have a positional phase factor exp(ik9i) applied to its quantum state, where k is a wavenumber and 0i is the angular coordinate of the node. The positional phase may encode spatial information into the quantum state, enabling Fourier-addressable operations.

[0284] At block 1004, the method 1000 includes executing quantum gate operations concurrently on different subsets of the quantum nodes such that no quantum node participates in more than one quantum gate operation during a scheduling interval. A scheduling interval may correspond to a time window during which a set of gates is executed in parallel.

[0285] The concurrent execution may be enabled by the spatial distribution of quantum nodes along the helices. The execution may proceed through the layers and sublayers defined during scheduling. For each sublayer, the control system may activate all gates assigned to that sublayer concurrently. After the gates in a sublayer have been executed, the control system may proceed to the next sublayer. The total execution time for a layer may be proportional to the number of sublayers, which may be minimized through edge coloring. Because the helical geometry provides high connectivity and short physical distances between adjacent nodes, the number of sublayers may be kept small, generally proportional to the neighbor span K.

[0286] The execution may include applying local unitary operations to individual quantum nodes. The execution may further include applying two-qubit entangling gates between adjacent nodes. The execution may also include applying cross-rung gates between nodes on different strands. The execution may include applying long-range gates using teleportation channels or photonic buses. The execution may also include aggregating partial results at aggregator nodes.

[0287] At block 1006, the method 1000 includes transferring quantum states between subsets of quantum nodes using inter-helix quantum couplers. Inter-helix quantum couplers may include rung couplers that connect nodes on strand A to nodes on strand B. The rung couplers may enable quantum state transfer, entanglement generation, and long-range communication between the strands. The transfer of quantum states may be performed as part of the execution of quantum gate operations or as a separate communication step.

[0288] The transfer may include activating a rung coupler to enable quantum state exchange between two nodes. The transfer may include executing a two-qubit gate across the rung. The transfer may include using teleportation channels to transmit quantum statesAtorney Docket No. H7019.10012W001across long distances. The transfer may include maintaining data integrity during transmission. The transfer may include using photonic bus lines to carry quantum states across multiple turns. The transfer may include synchronizing quantum state transfers across multiple rungs. The transfer may include performing hierarchical aggregation using a binary tree structure.

[0289] The method 1000 may further include dividing the quantum nodes into segments and executing quantum gate operations in parallel across different segments. Segments may be assigned to different computational tasks, such as processing different data shards in a data-parallel workload or executing different layers of a quantum neural network in a model-parallel workload. The control system may allocate resources to each segment independently, allowing concurrent execution of tasks without contention.

[0290] The method 1000 may include organizing quantum gate operations into sublayers defined by angular proximity along the helices. Sublayers may be constructed by partitioning the set of gates within a layer into conflict-free subsets.

[0291] The method 1000 may include performing a quantum workload comprising machine learning training, inference, or optimization. For machine learning training, the quantum workload may include executing a variational quantum algorithm, such as a variational quantum eigensolver (VQE) or quantum approximate optimization algorithm (QAOA).

[0292] For instance, the quantum workload may include executing a trained quantum neural network (QNN) on input data to produce predictions. The input data may be encoded into quantum states distributed across the helices, and the QNN layers may be executed sequentially along the z-axis.

[0293] For optimization, the quantum workload may include solving a combinatorial optimization problem, such as a graph partitioning problem, traveling salesman problem, or constraint satisfaction problem. The problem may be encoded as an Ising Hamiltonian or quadratic unconstrained binary optimization (QUBO) formulation, and the quantum nodes may be assigned to represent problem variables.

[0294] The method 1000 may further include aggregating execution results or measurement data at a segment-associated aggregator node and using the aggregated execution results to influence subsequent scheduling decisions.

[0295] The method 1000 may include dynamically redefining at least one segment by reassigning quantum nodes to different segments during execution of a quantum workload based on detected execution conditions. Execution conditions may include error rates,Atorney Docket No. H7019.10012W001performance metrics, or workload imbalance. The control system may monitor error syndromes from ring stabilizers and identify segments with elevated error rates. If a segment is determined to be faulty, the control system may perform lattice surgery to merge the faulty segment with an adjacent healthy segment, effectively remapping logical qubits away from the faulty region. The segment boundaries may be adjusted by changing the angular ranges defined by a start position and a span assigned to each segment. The reassignment may be performed dynamically during execution without interrupting the quantum workload.

[0296] The method 1000 may include modifying a scheduling plan for quantum gate operations based on feedback indicating degraded performance of at least one quantum node or inter-helix quantum coupler. The feedback may be obtained from fidelity measurements, error syndromes, or calibration data. The control system may identify nodes or couplers with fidelity below a threshold and exclude them from the scheduling plan. Gates that would have been assigned to the degraded nodes or couplers may be reassigned to alternative nodes or couplers with higher fidelity.

[0297] The method 1000 may include redirecting execution of at least a portion of a quantum workload away from a segment associated with an error metric exceeding a threshold. The error metric may be a syndrome rate, logical error rate, or gate fidelity. The control system may compare the error metric to a predefined threshold. If the error metric exceeds the threshold, the control system may mark the segment as unreliable and redistribute the workload to other segments.

[0298] The method 1000 may leverage the deterministic spatial coordinates of the quantum nodes to enable efficient scheduling and execution. The angular positions 9i may serve as natural addresses for the quantum nodes, allowing the control system to rapidly identify neighbors, compute distances, and assign gates to couplers. The periodicity of the helical structure may enable the use of frequency-domain or periodicity-aware techniques for scheduling and optimization.HARDWARE AND IMPLEMENTATION VARIANTS

[0299] The quantum computing architecture described herein may be realized through various physical implementations. Different quantum node architectures may be employed depending on the specific application requirements, operational environment, and available fabrication technologies. The choice of implementation may affect parameters such as coherence time, gate fidelity, operating temperature, and scalability, but the fundamentalAtorney Docket No. H7019.10012W001principles of the double-helix topology remain applicable across platforms. Note that the disclosed techniques related to implementing Al on quantum hardware are not limited to any specific hardware platform.

[0300] Furthermore, control systems, such as those described with respect to FIG. 1 A that may be used with dual-helix architecture, may include classical processors, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), or hybrid control systems. Quantum and classical components may communicate using wired or wireless interconnects. Any language directed to a computer includes any suitable combination of computing devices or network platforms, including servers, interfaces, systems, databases, agents, engines, controllers, and modules operating individually or collectively. Computing devices may include a processor configured to execute software instructions stored on a tangible, non-transitory computer-readable medium. Data exchanges among devices may be conducted over one or more networks including the Internet, LAN, WAN, VPN, packet-switched networks, circuit-switched networks, or other suitable networks.GENERAL ADVANTAGES

[0301] The spatial organization and execution framework described herein may provide one or more advantages, including improved scalability, reduced routing overhead, increased parallelism, and flexibility in supporting diverse quantum algorithms. Such advantages may vary depending on the implementation and workload.NON-LIMITING EMBODIMENTS AND COMBINATIONS

[0302] Further, note that features described in connection with one or more embodiments may be omitted, substituted, or combined with features of other embodiments unless the context indicates otherwise. The scope of the disclosure is defined solely by the claims.

[0303] Throughout the specification and claims, the following terms take the meanings explicitly associated herein, unless the context clearly dictates otherwise. The phrase “in one embodiment” as used herein does not necessarily refer to the same embodiment, though it may. Thus, as described below, various embodiments of the disclosure may be readily combined, without departing from the scope or spirit of the invention. As used herein, the term “or” is an inclusive “or” operator and is equivalent to the term “and / or,” unless the context clearly dictates otherwise. The term “based on” is not exclusive and allows for being based on additional factors not described unless the context clearly dictates otherwise.Atorney Docket No. H7019.10012W001

[0304] As used herein, and unless the context dictates otherwise, the term “coupled to” is intended to include both direct coupling (in which two elements that are coupled to each other contact each other) and indirect coupling (in which at least one additional element is located between the two elements). Therefore, the terms “coupled to” and “coupled with” are used synonymously. Within the context of a networked environment where two or more components or devices are able to exchange data, the terms “coupled to” and “coupled with” are also used to mean “communicatively coupled with”, possibly via one or more intermediary devices. The components or devices can be optical, mechanical, and / or electrical devices.

[0305] Although the following description uses terms “first,” “second,” etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, a first sensor could be termed a second sensor and, similarly, a second sensor could be termed a first sensor, without departing from the scope of the various described examples. The first sensor and the second sensor can both be sensors and, in some cases, can be separate and different sensors. In addition, throughout the specification, the meaning of “a”, “an”, and “the” includes plural references, and the meaning of “in” includes “in” and “on”.

[0306] Although some of the various embodiments presented herein constitute a single combination of inventive elements, it should be appreciated that the inventive subject matter is considered to include all possible combinations of the disclosed elements. As such, if one embodiment comprises elements A, B, and C, and another embodiment comprises elements B and D, then the inventive subject matter is also considered to include other remaining combinations of A, B, C, or D, even if not explicitly discussed herein. Further, the transitional term “comprising” means to have as parts or members, or to be those parts or members. As used herein, the transitional term “comprising” is inclusive or open-ended and does not exclude additional, unrecited elements or method steps.

[0307] As used in the description herein and throughout the claims that follow, when a system, engine, server, device, module, or other computing element is described as being configured to perform or execute functions on data in a memory, the meaning of “configured to” or “programmed to” is defined as one or more processors or cores of the computing element being programmed by a set of software instructions stored in the memory of the computing element to execute the set of functions on target data or data objects stored in the memory.Atorney Docket No. H7019.10012W001

[0308] It should be noted that any language directed to a computer should be read to include any suitable combination of computing devices or network platforms, including servers, interfaces, systems, databases, agents, peers, engines, controllers, modules, or other types of computing devices operating individually or collectively. One should appreciate the computing devices comprise a processor configured to execute software instructions stored on a tangible, non-transitory computer readable storage medium (e.g., hard drive, FPGA, PLA, solid state drive, RAM, flash, ROM, or any other volatile or nonvolatile storage devices). The software instructions configure or program the computing device to provide the roles, responsibilities, or other functionality as discussed below with respect to the disclosed apparatus. Further, the disclosed technologies can be embodied as a computer program product that includes a non-transitory computer readable medium storing the software instructions that causes a processor to execute the disclosed steps associated with implementations of computer-based algorithms, processes, methods, or other instructions. In some embodiments, the various servers, systems, databases, or interfaces exchange data using standardized protocols or algorithms, possibly based on HTTP, HTTPS, AES, public-private key exchanges, web service APIs, known financial transaction protocols, or other electronic information exchanging methods. Data exchanges among devices can be conducted over a packet-switched network, the Internet, LAN, WAN, VPN, or other type of packet switched network; a circuit switched network; cell switched network; or other type of network.

[0309] ADDITIONAL EXAMPLES1. A quantum computing system, comprising:a plurality of quantum nodes physically arranged along two intertwined helices extending along a longitudinal axis, each quantum node having a defined angular position that determines a spatial location of the quantum node along a respective helix;inter-helix quantum couplers physically extending between corresponding quantum nodes on different helices, the inter-helix quantum couplers configured to enable quantum-mechanical interaction between the helices; anda control system configured to:identify subsets of the quantum nodes based on angular proximity derived from the defined angular positions,organize quantum gate operations into scheduling intervals in which quantum gate operations are executed concurrently on different subsets of the quantum nodes, andAtorney Docket No. H7019.10012W001prevent execution conflicts by ensuring that no quantum node participates in more than one quantum gate operation during a scheduling interval, wherein the scheduling is geometry-aware with respect to the intertwined helices and reduces routing overhead during execution of a quantum workload.2. The quantum computing system of embodiment 1, wherein the scheduling of quantum gate operations is constrained by angular adjacency and inter-helix connectivity such that the scheduling would require additional routing operations if implemented on a planar nearest-neighbor quantum architecture without increasing circuit depth or routing overhead.3. The quantum computing system of any of embodiments 1-2, wherein the control system is further configured to obtain, based on the defined angular position of each quantum node, a spatial address for scheduling and coordinating quantum gate operations.4. The quantum computing system of any of embodiments 1-3, wherein the plurality of quantum nodes is divided into a plurality of segments, each segment comprising a subset of quantum nodes having adjacent angular positions along at least one helix.5. The quantum computing system of embodiment 4, wherein the control system is configured to execute quantum gate operations in different segments concurrently.6. The quantum computing system of any of embodiments 4-5, wherein quantum nodes within a segment share at least one common control parameter value during execution of the quantum workload.7. The quantum computing system of any of embodiments 4-6, further comprising at least one aggregator node associated with each segment, the aggregator node configured to collect execution data or measurement results from quantum nodes within the segment and provide control feedback to the control system.8. The quantum computing system of any of embodiments 4-7, wherein the control system is further configured to dynamically modify at least one segment boundary by reassigning quantum nodes to different segments during execution of the quantum workload based on at least one of detected error conditions, performance metrics, or execution load.Atorney Docket No. H7019.10012W0019. The quantum computing system of embodiment 8, wherein the control system is configured to migrate execution of at least a portion of the quantum workload away from a segment associated with an error metric exceeding a threshold.10. The quantum computing system of any of embodiments 1-9, wherein the control system is configured to adjust scheduling of quantum gate operations in response to real-time feedback indicating degraded performance of at least one quantum node or inter-helix quantum coupler.11. The quantum computing system of any of embodiments 1-10, wherein the control system is configured to organize quantum gate operations into sublayers such that no quantum node participates in more than one quantum gate operation within a same sublayer.12. The quantum computing system of any of embodiments 1-11, wherein scheduling of quantum gate operations is determined at least in part based on angular adjacency of quantum nodes along the helices.13. The quantum computing system of any of embodiments 1-12, wherein at least one scheduling interval includes quantum gate operations executed between quantum nodes on opposing helices via the inter-helix quantum couplers.14. The quantum computing system of any of embodiments 1-13, wherein a quantum state processed by a quantum node includes positional information derived from the defined angular position corresponding to the spatial position of the quantum node.15. The quantum computing system of embodiment 14, wherein the positional information is encoded as a phase-related component of the quantum state.16. The quantum computing system of any of embodiments 1-15, wherein the quantum workload includes execution of a parameterized quantum algorithm.17. The quantum computing system of any of embodiments 1-16, wherein the control system is configured to aggregate measurement results from quantum nodes in different segments.18. The quantum computing system of any of embodiments 1-17, wherein the quantum nodes comprise photonic qubits, superconducting qubits, trapped ion qubits, spin-based qubits, or any combination thereof.19. A scheduling controller for a quantum computing system comprising quantum nodes arranged along two intertwined helices, the scheduling controller comprising:Atorney Docket No. H7019.10012W001one or more processors; andmemory storing instructions that, when executed, cause the scheduling controller to:receive a quantum circuit specification identifying quantum gate operations and corresponding quantum nodes;determine angular positions of the quantum nodes along the intertwined helices;assign the quantum gate operations into execution layers based on angular adjacency and inter-helix connectivity such that no quantum node participates in more than one quantum gate operation within a same execution layer; and output control signals that cause execution of the quantum gate operations according to the execution layers,wherein the execution layers are defined in a geometry-aware manner that reduces routing overhead relative to a planar quantum architecture.20. A method of operating a quantum computing system, comprising: scheduling quantum gate operations across quantum nodes arranged along two intertwined helices based on angular adjacency;executing quantum gate operations concurrently on different subsets of the quantum nodes such that no quantum node participates in more than one quantum gate operation during a scheduling interval; andtransferring quantum-mechanical interaction between subsets of quantum nodes using inter-helix quantum couplers.21. The method of embodiment 20, further comprising dividing the quantum nodes into segments and executing quantum gate operations in parallel across different segments.22. The method of any of embodiments 20-21, wherein scheduling includes organizing quantum gate operations into sublayers defined by angular proximity along the helices.23. The method of any of embodiments 20-22, wherein a quantum workload being performed comprises machine learning training, inference, or optimization.24. The method of any of embodiments 20-23, further comprising aggregating execution results or measurement data at a segment-associated aggregator node and using the aggregated execution data to influence subsequent scheduling decisions.Attorney Docket No. H7019.10012W00125. The method of any of embodiments 20-24, further comprising dynamically redefining at least one segment by reassigning quantum nodes to different segments during execution of a quantum workload.26. The method of any of embodiments 20-25, further comprising modifying a scheduling plan for quantum gate operations based on feedback indicating degraded performance of at least one quantum node or inter-helix quantum coupler.27. The method of embodiment 26, further comprising redirecting execution of at least a portion of a quantum workload away from a segment associated with an error metric exceeding a threshold.28. A non-transitory computer-readable medium storing instructions that, when executed by a processor, cause performance of the method of any of embodiments 20-27.

Claims

Atorney Docket No. H7019.10012W001CLAIMS1. A quantum computing system, comprising:a plurality of quantum nodes physically arranged along two intertwined helices extending along a longitudinal axis, each quantum node having a defined angular position that determines a spatial location of the quantum node along a respective helix;inter-helix quantum couplers physically extending between corresponding quantum nodes on different helices, the inter-helix quantum couplers configured to enable quantum-mechanical interaction between the helices; anda control system configured to:identify subsets of the quantum nodes based on angular proximity derived from the defined angular positions,organize quantum gate operations into scheduling intervals in which quantum gate operations are executed concurrently on different subsets of the quantum nodes, andprevent execution conflicts by ensuring that no quantum node participates in more than one quantum gate operation during a scheduling interval, wherein the scheduling is geometry-aware with respect to the intertwined helices and reduces routing overhead during execution of a quantum workload.

2. The quantum computing system of claim 1, wherein the scheduling of quantum gate operations is constrained by angular adjacency and inter-helix connectivity such that the scheduling would require additional routing operations if implemented on a planar nearest-neighbor quantum architecture without increasing circuit depth or routing overhead.

3. The quantum computing system of claim 1, wherein the control system is further configured to obtain, based on the defined angular position of each quantum node, a spatial address for scheduling and coordinating quantum gate operations.

4. The quantum computing system of claim 1, wherein the plurality of quantum nodes is divided into a plurality of segments, each segment comprising a subset of quantum nodes having adjacent angular positions along at least one helix.Atorney Docket No. H7019.10012W0015. The quantum computing system of claim 4, wherein the control system is configured to execute quantum gate operations in different segments concurrently.

6. The quantum computing system of claim 4, wherein quantum nodes within a segment share at least one common control parameter value during execution of the quantum workload.

7. The quantum computing system of claim 4, further comprising at least one aggregator node associated with each segment, the aggregator node configured to collect execution data or measurement results from quantum nodes within the segment and provide control feedback to the control system.

8. The quantum computing system of claim 4, wherein the control system is further configured to dynamically modify at least one segment boundary by reassigning quantum nodes to different segments during execution of the quantum workload based on at least one of detected error conditions, performance metrics, or execution load.

9. The quantum computing system of claim 8, wherein the control system is configured to migrate execution of at least a portion of the quantum workload away from a segment associated with an error metric exceeding a threshold.

10. The quantum computing system of claim 1, wherein the control system is configured to adjust scheduling of quantum gate operations in response to real-time feedback indicating degraded performance of at least one quantum node or inter-helix quantum coupler.

11. The quantum computing system of claim 1, wherein the control system is configured to organize quantum gate operations into sublayers such that no quantum node participates in more than one quantum gate operation within a same sublayer.

12. The quantum computing system of claim 1, wherein scheduling of quantum gate operations is determined at least in part based on angular adjacency of quantum nodes along the helices.Atorney Docket No. H7019.10012W00113. The quantum computing system of claim 1, wherein at least one scheduling interval includes quantum gate operations executed between quantum nodes on opposing helices via the inter-helix quantum couplers.

14. The quantum computing system of claim 1, wherein a quantum state processed by a quantum node includes positional information derived from the defined angular position corresponding to the spatial position of the quantum node.

15. The quantum computing system of claim 14, wherein the positional information is encoded as a phase-related component of the quantum state.

16. The quantum computing system of claim 1, wherein the quantum workload includes execution of a parameterized quantum algorithm.

17. The quantum computing system of claim 1, wherein the control system is configured to aggregate measurement results from quantum nodes in different segments.

18. The quantum computing system of claim 1, wherein the quantum nodes comprise photonic qubits, superconducting qubits, trapped ion qubits, spin-based qubits, or any combination thereof.

19. A scheduling controller for a quantum computing system comprising quantum nodes arranged along two intertwined helices, the scheduling controller comprising:one or more processors; andmemory storing instructions that, when executed, cause the scheduling controller to:receive a quantum circuit specification identifying quantum gate operations and corresponding quantum nodes;determine angular positions of the quantum nodes along the intertwined helices;assign the quantum gate operations into execution layers based on angular adjacency and inter-helix connectivity such that no quantum node participates in more than one quantum gate operation within a same execution layer; andAtorney Docket No. H7019.10012W001output control signals that cause execution of the quantum gate operations according to the execution layers,wherein the execution layers are defined in a geometry-aware manner that reduces routing overhead relative to a planar quantum architecture.

20. A method of operating a quantum computing system, comprising: scheduling quantum gate operations across quantum nodes arranged along two intertwined helices based on angular adjacency;executing quantum gate operations concurrently on different subsets of the quantum nodes such that no quantum node participates in more than one quantum gate operation during a scheduling interval; andtransferring quantum-mechanical interaction between subsets of quantum nodes using inter-helix quantum couplers.

21. The method of claim 20, further comprising dividing the quantum nodes into segments and executing quantum gate operations in parallel across different segments.

22. The method of claim 20, wherein scheduling includes organizing quantum gate operations into sublayers defined by angular proximity along the helices.

23. The method of claim 20, wherein a quantum workload being performed comprises machine learning training, inference, or optimization.

24. The method of claim 20, further comprising aggregating execution results or measurement data at a segment-associated aggregator node and using the aggregated execution data to influence subsequent scheduling decisions.

26. The method of claim 20, further comprising dynamically redefining at least one segment by reassigning quantum nodes to different segments during execution of a quantum workload.Attorney Docket No. H7019.10012W00127. The method of claim 20, further comprising modifying a scheduling plan for quantum gate operations based on feedback indicating degraded performance of at least one quantum node or inter-helix quantum coupler.

29. The method of claim 26, further comprising redirecting execution of at least a portion of a quantum workload away from a segment associated with an error metric exceeding a threshold.

30. A non-transitory computer-readable medium storing instructions that, when executed by a processor, cause performance of the method of claim 20.

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