Chip interposer

Abstract

An interposer chip includes a substrate and a plurality of through-vias extending from a first side of the substrate to a second side of the substrate. Each through-via includes an electrical conductor extending between the first and second sides. A plurality of first electrically conducting pads is disposed on the first side, where each first electrically conducting pad is coupled to a respective electrical conductor and has a first size. A plurality of second electrically conducting pads is disposed on the second side, where each second electrically conducting pad is coupled to a respective electrical conductor and has a second size. The second size of the second electrically conducting pads is greater than the first size of the first electrically conducting pads. The interposer chip facilitates electrical connectivity between components while suppressing microwave crosstalk and parasitic capacitance in applications such as quantum computing systems.

Description

Attorney Docket Number: 56113-0681WO1CHIP INTERPOSER BACKGROUND

[0001] Quantum computing takes advantage of quantum effects, such as superposition of basis states and entanglement to perform certain computations more efficiently than a classical digital computer. In contrast to a digital computer, which stores and manipulates information in the form of bits (e.g., a “1” or “0”), quantum computing systems can manipulate information using qubits. A qubit can refer to a quantum circuit element that enables the superposition of multiple states (e.g., data in both the “0” and “1” state) and / or to the superposition of data, itself, in the multiple states. A quantum computing system may also manipulate qudits, in which a qudit is a generalization of a qubit and refers to a quantum circuit element that can enables the superposition of d states and / or to the superposition of the d states, where d is an integer greater than 2. In accordance with conventional terminology, the superposition of a “0” and “1” state in a quantum system may be represented, e.g., as a | 0> + 0 | 1>. The “0” and “1” states of a digital computer are analogous to the | 0> and | 1> basis states, respectively of a qubit. The value | a |2represents the probability that a qubit is in | 0> state, whereas the value | 0 |2represents the probability that a qubit is in the | 1> basis state.SUMMARY

[0002] This disclosure relates to an interposer for establishing electrical connectivity between components, such as between a quantum computing chip and external interfaces. The interposer includes a substrate having a first side and an opposite second side. A plurality of through-vias is disposed within the substrate, where each through-via includes an electrical conductor extending from the first side to the second side. A plurality of first electrically conducting pads is positioned on the first side of the substrate, with each first electrically conducting pad coupled to a respective electrical conductor of a through-via. These first electrically conducting pads are characterized by a first size. A plurality of second electrically conducting pads is positioned on the second side of the substrate, with each second electrically conducting pad coupled to a respective electrical conductor of a through-via. These second electrically conducting pads are characterized by a second size that is greater than the first size.Attorney Docket Number: 56113-0681WO1

[0003] The interposer facilitates reliable electrical coupling while managing electromagnetic effects that can impact signal integrity. By utilizing first electrically conducting pads with a smaller surface area on the first side, the interposer can interface with high-density circuit elements while reducing parasitic capacitance and suppressing microwave crosstalk. Conversely, the larger second size of the second electrically conducting pads on the second side provides an expanded surface area to facilitate alignment and bonding with larger-scale external contacts or connectors.

[0004] In some implementations, the electrical conductors within the through-vias comprise a superconducting material, enabling low-loss signal transmission suitable for cryogenic environments. The first and second electrically conducting pads may also comprise superconducting materials. The substrate can be formed from a dielectric material, such as single crystal silicon, and may have a thickness between 100 microns and 1 mm. The through-vias can be characterized by a first feature size, such as an opening width, between 20 microns and 200 microns. To further enhance signal isolation, the interposer may include ground contacts and ground vias. For instance, a first ground contact on the first side and a second ground contact on the second side can be coupled by a subset of through-vias to provide electrical shielding. In certain configurations, a layer of indium is disposed on the first electrically conducting pads to facilitate superconducting bump bonding to an adjacent chip. These features may be integrated into a quantum computing device to support the routing of microwave signals to and from quantum circuit elements.BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Fig. 1 A is a top view of an example interposer.

[0006] Fig. IB is a cross-sectional view of the interposer of FIG. 1A.

[0007] Fig. 1C is a bottom view of the interposer of FIG. 1 A

[0008] Fig. 2 is a top view of an example interposer illustrating an arrangement of contact pads and ground contacts.

[0009] Fig. 3 is a cross-sectional view of an example interposer that includes bump bonds.

[0010] Fig. 4 is a cross-sectional view of an example interposer coupled to a quantum computing chip.Attorney Docket Number: 56113-0681WO1DETAILED DESCRIPTION

[0011] In general, in some implementations, quantum computing systems may employ multiple chips in a stacked arrangement. At least one of the chips may include, but is not limited to, quantum computing circuit elements, such as qubits. Another at least one of the chips may include, but is not limited to, circuit elements configured to control the quantum computing circuit elements. Adjacent chips in the stack may be electrically and communicatively coupled to one another through bump bonds. The bump bonds between the stacks may be positioned between contact pads formed on the adjacent chips.

[0012] To assist with alignment and reliability of connections between adjacent chips and / or to facilitate connection to external contacts (including connectors such as spring-loaded electrical contacts), the contact pads may be formed with a relatively large surface area. For instance, in some cases, the contact pads may have surface areas that are at least 150,000 pm2. For quantum computing systems, control and data signals are typically in the microwave range, e.g., between about 1 GHz to about 10 GHz or higher frequencies. As connection pad sizes increase, the connection pads may increasingly function as antennas. For instance, the larger surface area of the connection pads becomes comparable in size to the wavelengths of quantum computing signals, making the contact pads more efficient at radiating or receiving such signals. Larger electrically conductive layers can support resonant modes that efficiently couple with incident microwaves, enhancing radiation or reception through constructive interference. Additionally, in some implementations, larger connection pads are associated with an increase in parasitic capacitance.

[0013] Both the unintended transmission of microwave signals and parasitic capacitance can be detrimental to the design and operation of quantum computing systems. For example, these effects may result in unwanted crosstalk between signal lines and qubits. Alternatively or in addition, they can lead to energy loss and decoherence, resulting in shortened time scales for reliable quantum computing operations. In some cases, these effects can cause unwanted frequency shifts and instability in quantum circuit element (e.g., qubit) resonance frequencies.

[0014] To reduce the impact of the foregoing adverse effects, the connection pads may be reduced in size. However, smaller connection pads render alignment of connections to contactsAttorney Docket Number: 56113-0681WO1more difficult, resulting in diminished fabrication throughput. To address these challenges, certain designs attempt to integrate shielding or complex routing structures, such as through-silicon vias (TSVs), directly into the chip containing the active circuit elements. However, incorporating such features into a chip that already contains sensitive quantum circuit elements significantly increases the complexity of the fabrication process. This complexity can lead to reduced yields and introduces additional design constraints that may limit the performance or scalability of the system.

[0015] The present disclosure relates to an interposer that can be used to address the foregoing issues, by allowing improved alignment with larger contact pads, while suppressing microwave crosstalk and parasitic capacitance. The interposer can include a first set of contact pads on a first side of the interposer, in which the contact pads of the first set each have a first size. The interposer can further include a second set of contact pads on a second side of the interposer, in which the contact pads of the second set each have a second size that is smaller than the first size. The contact pads of the first set can be electrically coupled to the contact pads of the second set, e.g., using through-vias within the interposer.

[0016] FIGS. 1A-1C are schematics that illustrate an example of an interposer 100 according to the present disclosure. FIG. 1A illustrates a first surface 102 (e.g., atop) of the interposer 100, FIG. IB illustrates a cross-section of the interposer 100, and FIG. 1C illustrates a second surface 106 (e.g., bottom) of the interposer 100, where the second surface 106 is an opposite side of the interposer 100 from the first surface 102. The interposer 100 can be used, in some implementations, to provide electrical connections to and / or from one one or more chips. For instance, in some cases, contacts on the first surface 102 of the interposer 100 can be used to electrically connect to a computing chip, such as a quantum computing chip that includes qubits, while contacts on the second surface 106 of the interposer of the interposer 100 can connect to external components or another chip, such as another quantum computing chip.

[0017] As shown in FIG. 1A, the first surface 102 includes a first contact pad 110. Although only a single contact pad 110 is shown for ease of viewing, the first surface 102 can include multiple first contact pads. When multiple first contact pads 110 are used, the pads 110 can be arranged in an array across the first surface 102 of the interposer 100. Each first contact pad 110 has a first size. The first size may be designed to be large enough to allow a reliable connection,Attorney Docket Number: 56113-0681WO1e ., through bump bonding, to contacts of another chip, such as a quantum computing chip, but small enough that the first contact pads 110 provide adequate signal fidelity without substantially functioning as antennas and / or inducing crosstalk between adjacent contact pads. For example, the first size of the first contact pads 110 can be between 100 square microns and 10,000 square microns, such as 2,500 square microns. A length of each side of the first contact pad can be, for example, between 10 microns and 1,000 microns. Although the first contact pad 110 is shown as square in shape, the contact pads 110 can have any other shape, such as circular, rectangular or other polygonal geometries.

[0018] The first surface 102 further includes a ground plane 130. As shown in FIG. 1A, the ground plane 130 extends around the periphery of the first surface 102, substantially surrounding the first contact pad 110. The design of the ground plane 130 is configured to define an electrical boundary around the first contact pad 110 to provide shielding of signals to and from the first contact pad 110. Although shown as extending around the periphery of the chip 100, the ground plane 130 may have other configurations.

[0019] Each of the first contact pad 110 and the ground plane 130 are formed from electrically conducting material. In particular, in certain implementations, the first contact pad 110 and the ground plane 130 include a superconducting material, such as a aluminum, niobium, or titanium nitride.

[0020] Each of the first contact pad 110 and the ground plane 130 are coupled to a respective electrical conductor of a respective through-via. For example, as shown in FIG. 1 A, the first contact pad 110 is coupled to a respective through-via 120, and the ground plane 130 is coupled to multiple respective ground vias 140 (indicated by dashed line circles). In the present example, first contact pad 110 is shown as laterally spaced apart from through-via 120, but still electrically connected to the through-via 120 via an elongated conductive trace 104, whereas ground plane 130 is formed directly over and in contact with the respective ground vias 140. Alternative designs are also possible. For instance, in some implementations, the first contact pad 110 may be formed directly over the through-via 120.

[0021] FIG. IB illustrates a cross-sectional view of the interposer 100 taken along the line A-A shown in FIG. 1A. The interposer 100 includes a substrate 150 having a first side (e.g., firstAttorney Docket Number: 56113-0681WO1surface 102) and a second side (e.g., second surface 106). In some implementations, the substrate 150 is formed from a dielectric material, such as single crystal silicon. The thickness of the substrate 150 between the first surface 102 and the second surface 106 can be, e.g., between 100 microns and 1 millimeter.

[0022] As illustrated in FIG. IB, the through-via 120 extends through the substrate 150, providing an electrical path between the first contact pad 110 on the first surface 102 and a second contact pad 160 on the second surface 106. Similarly, ground vias 140 extend through the substrate 150 to electrically couple the ground plane 130 on the first surface 102 to a ground plane 170 on the second surface 106. Each through-via 120, 140 can be characterized by a first feature size corresponding to the width or diameter of the opening of the via. For example, the first feature size can be between 20 microns and 200 microns. The through-vias 120, 140 are filled with an electrical conductor, such as a superconducting material (e.g., aluminum, niobium, or titanium nitride), enabling the transport of signals and currents between the opposite sides of the interposer 100.

[0023] FIG. 1C illustrates a second surface 106 (e.g., a bottom surface) of the interposer 100. The second surface 106 includes a second contact pad 160. While a single second contact pad 160 is illustrated, the second surface 106 can include a plurality of second contact pads 160 arranged, for example, in an array that corresponds to the arrangement of the first contact pads 110 on the first surface 102. The second contact pad 160 is electrically coupled to the through-via 120, which in turn couples the second contact pad 160 to the first contact pad 110 through the substrate 150. In this illustration, the second contact pad 160 is positioned directly over the through-via 120 (represented by the dashed circle within the boundary of the second contact pad 160), though other designs are also possible where the pad is laterally offset and connected via a trace or other conductive lead.

[0024] The second contact pad 160 is characterized by a second size. In some implementations, the second size is greater than the first size of the first contact pad 110. For instance, the second contact pad 160 can have a larger surface area than the first contact pad 110 to facilitate easier alignment with external components, such as spring-loaded electrical contacts, or larger pitch bump bonds. As an example, the surface area of the second contact pad 160, as viewed facing the second surface 106, can be between 40,000 square microns and 1 square millimeter, such asAttorney Docket Number: 56113-0681WO1150,000 square microns. A length of each side of the second contact pad 160 can be between, e.g., 200 microns and 1000 microns. Although the second contact pad 160 is illustrated as having a rectangular or square shape, the second contact pad 160 can take other shapes, such as circular, hexagonal, or other polygonal geometries.

[0025] The second surface 106 also includes a ground plane 170. As shown in FIG. 1C, the ground plane 170 can extend around a portion of the second surface 106 and is electrically coupled to the ground vias 140. This ground plane 170 provides an electrical boundary and shielding for the signals transmitted to and from the second contact pad 160. The ground plane 170 and the second contact pad 160 are formed from electrically conducting materials. In certain implementations, these features comprise superconducting materials, such as aluminum, niobium, or titanium nitride.

[0026] While FIGS. 1A-1C illustrate a specific configuration of pads, vias, and ground planes, other designs are also possible. For example, the number, density, and layout of the through-vias 120, 140 and their associated contact pads 110, 160 can be varied to suit specific integration requirements. The substrate 150, while described as single crystal silicon, could also be formed from other dielectric or semiconducting materials suitable for quantum computing environments. Additionally, the relative positions of the through-vias and the pads can be modified, such as by using redistribution layers or different routing geometries on either the first surface 102 or the second surface 106.

[0027] FIG. 2 illustrates an example of an interposer 200 featuring multiple first contact pads 110. In this implementation, the first contact pads 110 are arranged in an array, such as the illustrated 6x5 matrix, to facilitate multiple electrical connections across the substrate. While an array configuration is shown, other designs for the arrangement and density of the first contact pads 110 are possible to accommodate specific routing requirements or chip architectures. Each first contact pad 110 is coupled to a respective second contact pad on the second surface of the interposer 100 by means of a respective through-via formed within the substrate. The through-vias may be located directly under the respective first contact pads to which they are connected. Alternatively, in some implementations, one or more through-vias may be positioned laterally away from the first contact pads such that the first contact pads do not directly overlap the through-via. Similarly, the second contact pads may be positioned laterally away from theAttorney Docket Number: 56113-0681WO1respective through-vias to which they connect such that the second contact pads do not directly overlap the through-via. In some implementations, each second contact pad has a second size that is larger than the first size of the first contact pad 110 to which it is coupled. This configuration can facilitate easier alignment and connection to external components while maintaining a smaller footprint on the first surface 102 for coupling to high-density circuit elements. In some implementations, the first contact pads 110 are arranged with a specific lateral spacing to optimize signal integrity and reduce electromagnetic coupling. For example, the distance between the centers of adjacent first contact pads 110 can be between 100 microns and 2 millimeters, such as 250 microns, 500 microns, 700 microns, 1 mm, or 1.25 mm. The first contact pads 110 can be organized in various grid configurations depending on the layout of the chip 400. While a 6x5 matrix is illustrated in FIG. 2, other grid configurations include 8x8, 10x12, 16x16, 20 x 20, or 24 x 24 arrays. The overall size of the grid formed by the plurality of first contact pads 110 can vary to match the size of the active region of a quantum computing chip. For instance, the grid can have a total length per side between 1 millimeter and 10 millimeters, such as a grid area of between approximately 1 square millimeters or 100 square millimeters, and more particularly between 25 square millimeters and 30 square millimeters

[0028] The first surface 102 also includes the ground plane 130. As depicted in FIG. 2, the ground plane 130 is designed to be positioned between adjacent first contact pads 110. By interspersing the ground plane 130 between the first contact pads 110, the ground plane 130 provides electrical shielding for each pad. This configuration can suppress microwave crosstalk and electromagnetic interference between signal lines coupled to the first contact pads 110, thereby improving signal fidelity within the interposer 100.

[0029] FIG. 3 illustrates a cross-sectional view of an example of an interposer 300. Similar to FIG. IB, the interposer 300 includes a substrate 150 having a first side and a second side. In contrast to the interposer 100 of FIGS. 1 A-1C, multiple first contact pads 110 are disposed on the first side of the substrate 150, and each first contact pad 110 is coupled to a respective through-via 120 that extends through the substrate 150 to the second side. The through-vias 120 are arranged such that they are electrically coupled to respective second contact pads 160 on a second surface of the interposer 300. In this manner, the through-vias 120 provide electrical paths between the first contact pads 110 and the second contact pads 160.Attorney Docket Number: 56113-0681WO1

[0030] The interposer 300 further includes multiple ground vias 140 extending through the substrate 150. The ground vias 140 electrically couple a first ground plane 130 on the first side of the substrate 150 to a second ground plane 170 on the second side of the substrate 150. The first ground plane 130 can be positioned between adjacent first contact pads 110 to provide electromagnetic shielding and reduce crosstalk between signal lines.

[0031] A bump bond material 302 is formed on each of the first contact pads 110. The bump bond material 302 is configured to facilitate electrical and mechanical coupling between the interposer and another component, such as a quantum computing chip. In some implementations, the bump bond material 300 comprises a superconducting material. For example, the bump bond material 302 can include a layer of indium. The use of a superconducting material for the bump bond material 302 enables low-loss electrical connections suitable for cryogenic operations in quantum computing environments. The bump bond material 302 may be deposited or formed on the first contact pads 110 using fabrication techniques such as evaporation, sputtering, or electroplating.

[0032] FIG. 4 illustrates a cross-sectional view of an assembly including the interposer 100 coupled to a chip 400. The chip 400 can include a quantum computing chip having qubits (e.g., transmons, flux qubits, phase qubits, among others) and / or other quantum circuit elements including, but not limited to, qubit couplers, qubit measurement circuits, Josephson junctions, and control lines. In some implementations, the chip 400 includes a substrate 402 and one or more distribution layers 404. The distribution layers 404 can include one or more dielectric layers 408 and one or more redistribution conductor layers 406 configured to route signals within the chip 400 and positioned among and / or on the dielectric layers 408. In some implementations, the substrate 402 of the chip 400 comprises a dielectric material. For instance, the substrate 402 can be formed from single crystal silicon, which provides a suitable low-loss material for the fabrication of quantum circuit elements. The redistribution conductors 406 and other conductive features within the distribution layers 404, such as traces, pads, or electrically conductive vias, can comprise electrically conducting materials. In certain cases, these electrically conductive features comprise superconducting materials to support low-loss signal transmission at cryogenic temperatures. Examples of such superconducting materials include aluminum, niobium, titanium nitride, among other superconducting materials. The dielectrics 408 within the distribution layersAttorney Docket Number: 56113-0681WO1404 can comprise various insulating materials, such as silicon oxide, silicon nitride, or hydrogenated silicon, which serve to electrically isolate different layers of the redistribution conductors 406. The specific materials for the chip 400 can be selected to match or complement the thermal and electrical properties of the interposer 100, such as the coefficient of thermal expansion of the substrate 150.

[0033] The interposer 100 is coupled to the chip 400 through a bump bond 300. As shown in FIG. 4, the bump bond 300 provides an electrical and mechanical connection between a contact pad 407 of the chip 400 and a first contact pad 110 of the interposer 100. The first contact pad 110 is sized to be large enough to allow a reliable connection through the bump bond 300 to the contact pad 407 of the chip 400 but small enough that the first contact pad 110 provides adequate signal fidelity without substantially functioning as antennas and / or inducing crosstalk between adjacent contact pads. Though not shown in FIG. 4 (for ease of viewing other features), the interposer 100 may also include a ground plane on the same side of the substrate 150 as the first contact pad 110 to provide electromagnetic shielding to and / or from the first contact pad 110. The second contact pad 160, which is located on the opposite surface of the substrate 150, has a larger surface area than a surface area of the first contact pad 110, and is sized to be large enough to allow for reliable connections to external electrical connections, such as spring-loaded electrical contacts, or other external connectors. This configuration allows the interposer 100 to serve as a routing interface between the high-density connections of a quantum computing chip 400 and larger-scale electrical interfaces. As described herein, the interposer 100 one or more through-vias 140 extend through the substrate 150 to electrically connect the first contact pad 110 to the second contact pad 160. In some implementations, the interposer 100 can be bonded to another component, such as another chip, through the second contact pads 160.

[0034] Fabrication of the interposers described herein and their integration with other components, such as the chip 400, can be achieved through various semiconductor and quantum hardware manufacturing processes. For example, the substrate 150 can be processed using deep reactive ion etching (DRIE), such as a Bosch process, to form high-aspect-ratio openings for the through-vias 120 and ground vias 140. In some implementations, following the formation of these openings, an insulating liner, such as silicon oxide or silicon nitride, can be deposited along the sidewalls using chemical vapor deposition (CVD) or atomic layer deposition (ALD) toAttorney Docket Number: 56113-0681WO1electrically isolate the vias from the substrate 150. The openings can then be filled with electrically conducting materials, including superconductors like aluminum, niobium, or titanium nitride, among others, using techniques such as sputtering, electroplating, or chemical vapor deposition. In some instances, a seed layer is first deposited to facilitate the subsequent growth or deposition of the superconducting material. Excess conductive material on the surfaces of the substrate 150 can be removed or planarized using chemical mechanical polishing (CMP) to provide a smooth surface for the subsequent formation of the first contact pads 110 and the second contact pads 160.

[0035] The first contact pads 110, second contact pads 160, and ground planes 130, 170 can be patterned using photolithography combined with etching or lift-off processes. For example, a layer of superconducting material can be deposited across a surface of the substrate 150 and then selectively removed through dry etching to define the pad geometries. To facilitate the coupling of the interposer 100 to another chip, the bump bond material 302 can be applied to the first contact pads 110. This application can involve thermal evaporation of indium through a shadow mask or using a lift-off resist pattern.

[0036] The combination of the interposer 100 with one or more other chips, such as a quantum computing chip, can be performed using flip-chip bonding. In this process, the chips are aligned using a sub-micron precision flip-chip bonder, and a controlled amount of pressure and / or heat is applied to form a mechanical and electrical connection through the bump bonds 300. For superconducting applications, the bonding process is often performed at room temperature or low temperatures to prevent damage to sensitive quantum circuit elements and to ensure the integrity of the superconducting interfaces. In some implementations, the interposer 100 can be integrated into a larger multi-chip module (MCM) or a system-on-a-package (SoP) architecture, where multiple interposers and chips are tiled or stacked to scale the number of available qubits and control lines. The use of these fabrication and assembly techniques allows for the independent optimization of the quantum computing chip and the interposer 100, supporting the high yields and signal fidelities required for quantum information processing.

[0037] A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made. Elements of one or more implementations may be combined, deleted, modified, or supplemented to form further implementations. In yet anotherAttorney Docket Number: 56113-0681WO1example, the logic flows depicted in the figures do not require the particular order shown, or sequential order, to achieve desirable results. In addition, other steps may be provided, or steps may be eliminated, from the described flows, and other components may be added to, or removed from, the described systems. Accordingly, other implementations are within the scope of the following claims.

Claims

Attorney Docket Number: 56113-0681WO1What is claimed is:

1. An interposer chip comprising:a substrate;a plurality of through-vias within the substrate, wherein each through-via of the plurality of through-vias extends from a first side of the substrate to a second side of the substrate, wherein each through-via comprises an electrical conductor that extends from the first side of the substrate to the second side of the substrate;a plurality of first electrically conducting pads on the first side of the substrate, wherein each first electrically conducting pad is coupled to a respective electrical conductor of the plurality of through-vias, wherein each first electrically conducting pad has a first size;a plurality of second electrically conducting pads on the second side of the substrate, wherein each second electrically conducting pad is coupled to a respective electrical conductor of the plurality of through-vias, wherein each second electrically conducting pad has a second size,wherein the second size is greater than the first size.

2. The interposer chip of claim 1, wherein the electrical conductor of each through-via comprises a superconductor.

3. The interposer chip of claim 1, wherein the plurality of first electrically conducting pads comprise superconductor pads, and wherein the plurality of second electrically conducting pads comprise superconductor pads.

4. The interposer chip of claim 1, wherein the substrate comprises a dielectric.

5. The interposer chip of claim 1, wherein the substrate comprises single crystal silicon.

6. The interposer chip of claim 1, wherein a thickness of the substrate between the first side and the second side is between 100 microns to 1 millimeter.Attorney Docket Number: 56113-0681WO17. The interposer chip of claim 1, wherein each through-via of the plurality of through-vias comprises a first feature size characterizing an extend of an opening of the through-via, and wherein the first feature size is between 20 microns and 200 microns.

8. The interposer chip of claim 1, wherein a surface area of each first electrically conducting pad, as viewed facing the first side of the substrate, is between 100 square microns and 10,000 square microns.

9. The interposer chip of claim 1, wherein a surface area of each second electrically conducting pad, as viewed facing the second side of the substrate, is between 40,000 square microns and 1 square millimeter.

10. The interposer chip of claim 1, wherein the plurality of through-vias comprise a first subset of through-vias arranged in a central portion of the substrate and a second subset of through-vias arranged in an outer portion of the substrate, wherein the outer portion surrounds the central portion.

11. The interposer chip of claim 10, comprising:a first ground contact extending around the outer portion of the substrate on the first side of the substrate; anda second ground contact extending around the outer portion of the substrate on the second side of the substrate, wherein the electrical conductor of each through-via of the second subset of through vias is coupled to the first ground contact on the first side of the substrate and to the second ground contact on the second side of the substrate.

12. The interposer chip of claim 1 comprising, on each first electrically conducting pad, a layer of indium.

13. A quantum computing device comprising any of the interposers of statements 1-12 above.Attorney Docket Number: 56113-0681WO114. The quantum computing device of claim 13, comprising:a quantum computing chip coupled to the interposer, wherein the quantum computing chip comprises a qubit device; andbump bonds between the quantum computing chip and the interposer, wherein each bump bond couples a respective first contact pad of the interposer to a respective quantum computing chip contact pad of the quantum computing chip.

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