Low energy wafer biasing method and apparatus

Abstract

Methods and apparatus of biasing a substrate during a plasma deposition process. One example method includes delivering a pulsed voltage (PV) waveform to an electrode disposed in a substrate support, where delivering the PV waveform includes a first substrate biasing operation that involves (i) delivering the PV waveform at a first substrate bias by delivering a series of voltage pulses having amplitudes that extend from a first positive voltage to a first negative voltage, and (ii) coupling, by use of a switch, a shunt capacitance to an output of the PV waveform source, and a second substrate biasing operation, that involves (i) delivering the PV waveform at a second substrate bias by delivering a series of voltage pulses having amplitudes that extend from a second positive voltage to a second negative voltage, and (ii) decoupling, by use of the switch, the shunt capacitance from the output.

Description

PATENTAttorney Docket No.: 44025873WO01LOW ENERGY WAFER BIASING METHOD AND APPARATUS BACKGROUNDField

[0001] Embodiments of the present disclosure generally relates to substrate processing methods and apparatus. More specifically, embodiments of the present disclosure relate to an apparatus and methods of biasing a substrate during plasma processing.Description of the Related Art

[0002] Reliably producing high aspect ratio features is one of the key technology challenges for the next generation of semiconductor devices. One method of forming high aspect ratio features uses a plasma-assisted deposition and etching processes to bombard a material formed on a surface of a substrate during processing to improve a deposited film properties, form features in the deposited film, and / or reshape portions of the deposited film layer formed on a surface of a substrate.

[0003] Processes used to form the next generation of semiconductor devices will include physical vapor deposition (PVD), plasma enhanced atomic layer deposition (PEALD), or plasma enhanced chemical vapor deposition (PECVD) techniques to deposit thin films of various metals and metal alloys within the various high aspect ratio features. Conventional processes have typically used high voltage substrate biases during portions of the deposition process to etch and / or reshape the deposited layer formed on the surface of the substrate. However, moderate to large substrate biases (e.g., >0.2kV) provided during the PEALD, PECVD and PVD deposition processes can cause damage to the deposited layer and underlying layers of the substrate, particularly when high-energy ions are used to enhance the deposition rate and / or morphology of the deposited film. This damage can lead to poor step coverage and other defects, which can compromise the performance and reliability of the device. Moreover, in PVD deposition applications, high energy ions that are delivered to the surface of the substrate can lead to poor deposition bottom coverage due the ballistic nature of the interaction of the high energy ions with the surface of the substrate. To minimize the amount of damage and poor bottom coverage issues it isPATENTAttorney Docket No.: 44025873WO01often desirable to reduce the substrate bias voltage during portion of the plasma process to reduce the energy of the ions formed in the plasma. In one example, low ion energies are often desired during plasma processing to prevent damage to some of the underlying fragile materials (e.g., low-k materials) and fragile device structures formed on exposed regions of the substrate. However, it has been found that conventional substrate biasing hardware are not able to control the substrate bias voltage applied at low voltages (e.g., <0.2kV) during processing. The lack of control of the substrate bias voltage at low bias voltages can lead to substrate-to-substrate deposited film property characteristic(s) and film morphology variability.

[0004] Moreover, while reducing the amount of damage created in a substrate when providing a low voltage substrate bias, it has been found that an “overhang” of a PVD deposited material will form at the entrance of features formed in the surface of a substrate. Therefore, there is a need for a process that can provide good bottom coverage and also includes processes that can reduce the formation of a material overhang at the entrance of a feature formed on the substrate.

[0005] Accordingly, there is a need in the art for a method and apparatus that solves the problems described above.SUMMARY

[0006] To the accomplishment of the foregoing and related ends, the one or more embodiments comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the appended drawings set forth in detail certain illustrative features of the one or more embodiments. These features are indicative, however, of but a few of the various ways in which the principles of various embodiments may be employed.

[0007] Embodiments of the present disclosure are directed to a method of biasing a substrate during a plasma deposition process. The method generally includes forming a plasma within a processing region of a plasma processing chamber; delivering a pulsed voltage (PV) waveform to an electrode disposed in a substrate support within the processing region of the plasma processing chamber, where delivering the PV waveform includes: ( / ') a first substrate biasing operation, including: delivering the PV waveform at a first substrate bias, by use of a PV waveform source,PATENTAttorney Docket No.: 44025873WO01by delivering a series of voltage pulses having amplitudes that extend from a first positive voltage to a first negative voltage; and coupling, by use of a first switch, a shunt capacitance to an output of the PV waveform source, where the shunt capacitance is coupled between the output of the PV waveform source and a reference potential node; and ( / ' / ) a second substrate biasing operation, including: delivering the PV waveform at a second substrate bias, by use of the PV waveform source, by delivering a series of voltage pulses having amplitudes that extend from a second positive voltage to a second negative voltage; and decoupling, by use of the first switch, the shunt capacitance from the output of the PV waveform source.

[0008] Embodiments of the present disclosure provide a non-transitory computer-readable medium including computer-executable instructions that, when executed by one or more processors of a system controller, cause the system controller to perform a method. The method generally includes forming a plasma within a processing region of a plasma processing chamber, delivering a pulsed voltage (PV) waveform to an electrode disposed in a substrate support within the processing region of the plasma processing chamber, where delivering the PV waveform includes: ( / ') a first substrate biasing operation, including: delivering the PV waveform at a first substrate bias, by use of a PV waveform source, by delivering a series of voltage pulses having amplitudes that extend from a first positive voltage to a first negative voltage; and coupling, by use of a first switch, a shunt capacitance to an output of the PV waveform source, where the shunt capacitance is coupled between the output of the PV waveform source and a reference potential node; and ( / ' / ) a second substrate biasing operation, including: delivering the PV waveform at a second substrate bias, by use of the PV waveform source, by delivering a series of voltage pulses having amplitudes that extend from a second positive voltage to a second negative voltage; and decoupling, by use of the first switch, the shunt capacitance from the output of the PV waveform source.

[0009] Embodiments of the present disclosure provide a plasma processing assembly. The plasma processing assembly generally includes a plasma processing chamber that includes a processing region, an electrode disposed in a substrate support within the plasma processing chamber, and a system controller. The system controller generally includes one or more processors configured to deliver a pulsedPATENTAttorney Docket No.: 44025873WO01voltage waveform to the electrode by: ( / ') performing a first substrate biasing operation, including: delivering the PV waveform at a first substrate bias, by use of a PV waveform source, by delivering a series of voltage pulses having amplitudes that extend from a first positive voltage to a first negative voltage; and coupling, by use of a first switch, a shunt capacitance to an output of the PV waveform source, where the shunt capacitance is coupled between the output of the PV waveform source and a reference potential node; and ( / ' / ) performing a second substrate biasing operation, including: delivering the PV waveform at a second substrate bias, by use of the PV waveform source, by delivering a series of voltage pulses having amplitudes that extend from a second positive voltage to a second negative voltage; and decoupling, by use of the first switch, the shunt capacitance from the output of the PV waveform source.

[0010] Embodiments of the present disclosure provide a plasma processing assembly. The plasma processing assembly generally includes an electrode, a PV waveform source coupled to the electrode, where the PV waveform source is configured to deliver a series of asymmetric voltage pulses, a capacitive element including a first terminal coupled to the PV waveform source and the electrode via a first switch and including a second terminal coupled to a reference potential node, and an inductive element including a first terminal coupled to the PV waveform source via a second switch and including a second terminal coupled to the electrode.

[0011] Embodiments of the present disclosure are directed to a method of biasing a substrate during a plasma deposition process. The method generally includes forming a plasma within a processing region of a plasma processing chamber; and delivering a PV waveform to an electrode disposed in a substrate support within the processing region of the plasma processing chamber, where delivering the PV waveform includes: a first substrate biasing operation that includes: delivering the PV waveform at a first substrate bias, by use of a PV waveform source, by delivering a series of voltage pulses having amplitudes that extend from a first positive voltage to a first negative voltage; and coupling, by use of a first switch, a shunt capacitance to an output of the PV waveform source, where the shunt capacitance is coupled between the output of the PV waveform source and a reference potential node.PATENTAttorney Docket No.: 44025873WO01

[0012] Embodiments of the present disclosure provide a non-transitory computer-readable medium including computer-executable instructions that, when executed by one or more processors of a system controller, cause the system controller to perform a method. The method generally includes forming a plasma within a processing region of a plasma processing chamber; and delivering a PV waveform to an electrode disposed in a substrate support within the processing region of the plasma processing chamber, where delivering the PV waveform includes: a first substrate biasing operation that includes: delivering the PV waveform at a first substrate bias, by use of a PV waveform source, by delivering a series of voltage pulses having amplitudes that extend from a first positive voltage to a first negative voltage; and coupling, by use of a first switch, a shunt capacitance to an output of the PV waveform source, where the shunt capacitance is coupled between the output of the PV waveform source and a reference potential node.BRIEF DESCRIPTION OF THE DRAWINGS

[0013] So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of its scope, and may admit to other equally effective embodiments.

[0014] Figure 1A illustrates a cross-sectional view of a processing chamber, according to one or more embodiments described herein.

[0015] Figures 1B and 1C are functionally equivalent circuit diagrams of pulsed voltage (PV) biasing circuits that can be used to provide a PV waveform to an electrode within a plasma process chamber, according to one or more embodiments described herein.

[0016] Figure 2A shows a voltage waveform that may be applied to an electrode of a processing chamber, according to one or more embodiments described herein.PATENTAttorney Docket No.: 44025873WO01

[0017] Figure 2B shows a voltage waveform that is established on a substrate due to a voltage waveform applied to an electrode of a processing chamber, according to one or more embodiments described herein.

[0018] Figure 3 is a flow diagram illustrating a method for delivering a PV waveform to an electrode disposed in a substrate support, according to one or more embodiments described herein.

[0019] Figure 4 is a timing diagram illustrating operations performed during the performance of the method illustrated in Figure 3, according to one or more embodiments described herein.

[0020] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.DETAILED DESCRIPTION

[0021] Embodiments of the present disclosure generally relate to plasma processing techniques, such as metal deposition and etching processes. More specifically, embodiments of the present disclosure relate to delivering configurable pulsed voltage (PV) waveforms to an electrode during deposition and etching substrate processing. In some embodiments, a PV waveform is applied to an electrode disposed within a substrate support disposed within a processing region of a plasma processing chamber. The PV waveform is configured to alter a substrate bias voltage and voltage formed across a plasma sheath formed over a surface of a substrate during at least one portion of a plasma processing operation. Altering the plasma sheath voltage (e.g., sheath thickness) during at least one portion of a plasma processing operation is used to prevent the generation of ion energies that will damage a deposited layer or underlying layers during one or more phases of a plasma process. Ions having low ion energies are used for use in various PVD processes, such as PVD processes that include the deposition of a material on a fragile material (e.g., low-k material) and / or fragile device structures formed on a substrate. Moreover, as described above, during PVD deposition processes, the creation of high energy ions that are delivered to the surface of the substrate during PVD depositionPATENTAttorney Docket No.: 44025873WO01processes can lead to poor bottom and / or step coverage due the ballistic nature of the high energy ions interacting with the feature containing surfaces of a substrate. However, it has been found that some substrate biasing hardware and methods are not able to control the substrate bias voltage applied at low voltages (e.g., <0.2kV) during plasma processing to provide minimal substrate damage and variability in a deposited film’s properties and morphology.

[0022] When applying a substrate bias voltage (also referred to herein as a DC bias voltage) to a substrate in a plasma processing chamber, plasma ion flux, created by the plasma interaction with a surface of a substrate, drives the electrically floating substrate voltage to a voltage that is equal to the generated plasma potential. If a constant substrate bias voltage is applied to a substrate during plasma processing, the continuous plasma interaction during plasma processing will reduce the generated sheath voltage from an initial first DC biasing voltage to a second DC bias voltage, which is less than the initial first DC bias voltage. The reduction in the generated sheath voltage, which is often referred to herein as a “pulse voltage waveform droop,” leads to a wide ion energy spread during the application of the substrate bias due to the changing sheath voltage over the application of the substrate bias (e.g., TON period of a voltage pulse). The spread in substrate voltage and thus sheath voltage during the applied substrate bias period leads to a spread in the angular distribution of ions that strike or bombard the surface of the substrate and also energies of the ions that strike or bombard the surface of the substrate. Therefore, there is a desire for an apparatus and a method of controlling the substrate bias voltage at low substrate bias voltages that has a minimal variation in the generated sheath voltage, or, in other words, a reduced pulse voltage waveform droop.Processing Chamber Examples

[0023] Figure 1A illustrates a cross-sectional view of a processing chamber 100. The processing chamber 100 includes an upper process assembly 102, a process kit 104, and a pedestal assembly 106, which are all configured to process a substrate 108 disposed in a processing region 110. The process kit 104 includes a grounded shield 112, a deposition ring 114, and a cover ring 116. In Figure 1 A, the processing chamber 100 includes a sputtering chamber (also called a physical vapor depositionPATENTAttorney Docket No.: 44025873WO01(PVD) chamber), capable of depositing a single or multi-compositional material from a sputtering target 120 on the substrate 108. The processing chamber 100 may also be used to deposit aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), hafnium (Hf), silver (Ag), chrome (Cr), gold (Au), molybdenum (Mo), silicon (Si), ruthenium (Ru), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), lanthanum (La), alumina (AIOx), lanthanum oxides (LaOx), nickel platinum alloys (NiPt), and titanium (Ti), or a combination thereof.

[0024] The processing chamber 100 includes a chamber body 122 having sidewalls 124, a bottom wall 126, and the upper process assembly 102 that enclose the processing region 110 (e.g., plasma zone). The chamber body 122 may be fabricated from welded plates of stainless steel or a unitary block of aluminum. In some embodiments, the sidewalls include aluminum and the bottom portion of the chamber includes one or more walls that are formed from a stainless steel plate. The sidewalls 124 generally contain a slit valve (not shown) to provide for entry and egress of a substrate 108 from the processing chamber 100. Components in the upper process assembly 102 of the processing chamber 100 in cooperation with the grounded shield 112, pedestal assembly 106, and cover ring 116 confine the plasma formed in the processing region 110 to the region above the substrate 108.

[0025] The pedestal assembly 106 is supported from the bottom wall 126 of the processing chamber 100. The pedestal assembly 106 supports the deposition ring 114 along with the substrate 108 during processing. The pedestal assembly 106 is coupled to the bottom wall 126 of the processing chamber 100 by a lift mechanism 128, which is configured to move the pedestal assembly 106 between an upper processing position and lower transfer position. Additionally, in the lower transfer position, lift pins 130 are moved through the pedestal assembly 106 to position the substrate a distance from the pedestal assembly 106 to facilitate the exchange of the substrate with a substrate transfer mechanism disposed exterior to the processing chamber 100, such as a single blade robot (not shown). A bellows 132 may be disposed between the pedestal assembly 106 and the bottom wall 126 to isolate the processing region 110 from the interior of the pedestal assembly 106 and the exterior of the chamber.PATENTAttorney Docket No.: 44025873WO01

[0026] The pedestal assembly 106 generally includes a substrate support 134 sealingly coupled to a platform housing 136. The platform housing 136 may be fabricated from a metallic material such as stainless steel or aluminum. A cooling plate (not shown) may be disposed within the platform housing 136, enabling thermal regulation of the substrate support 134.

[0027] The substrate support 134 may include aluminum or ceramic. The substrate support 134 has a substrate receiving surface 138 that receives and supports the substrate 108 during processing, the substrate receiving surface 138 being substantially parallel to a sputtering surface 140 of the sputtering target 120. The substrate support 134 may be an electrostatic chuck, a ceramic body, a heater, or a combination thereof. In some embodiments, the substrate support 134 is an electrostatic chuck that includes a dielectric body with an electrode 142 embedded therein. The dielectric body may be fabricated from a high thermal conductivity dielectric material such as pyrolytic boron nitride, aluminum nitride, silicon nitride, alumina or an equivalent material. Other embodiments of the pedestal assembly 106 and substrate support 134 are further described below. In one embodiment, the electrode 142 is configured so that when a DC voltage is applied to the electrode 142, a substrate 108 disposed on the substrate receiving surface 138 will be electrostatically chucked thereto to improve the heat transfer between the substrate 108 and the substrate support 134. In some embodiments, a PV waveform circuit 143 that may include a PV waveform source 144 is electrically coupled to the electrode 142, and is configured to generate a PV signal that includes a PV waveform so that a PV signal can be provided to the substrate 108 during processing to affect and control the plasma interaction with the surface of the substrate 108. The PV waveform source 144 will include a PV generator (e.g., DC power supply) and one or more electrical components, such as high repetition rate switches, capacitive elements (not shown), inductive elements (not shown), fly back diodes (not shown), power transistors (not shown) and / or resistors (not shown), that are configured to provide a PV waveform to an output node that is coupled to electrode 142.

[0028] The substrate support 134 may be coupled to a high voltage DC supply 145 that supplies a chucking voltage thereto. The high voltage DC supply 145 may be coupled to the bias electrode 142. In one configuration, a static DC voltage is betweenPATENTAttorney Docket No.: 44025873WO01about -5000V and about +5000V, and is delivered to the electrode from the high voltage DC supply 145 to electrostatically “chuck” a substrate 108 to the substrate receiving surface 138 of the substrate support 134 during plasma processing.

[0029] A program (or computer instructions) readable by a system controller 146 determines which tasks are performable on a substrate. In some embodiments, the system controller 146 includes a computing device having one or more processors, memory, and storage. The one or more processors can include central processing units, graphics processing units, accelerators, etc. The memory includes main memory for storing instructions for the one or more processors to execute or data for the one or more processors to operate on. For example, the memory includes random access memory (RAM). The storage includes mass storage for data or instructions. For example, the storage may include a removable disk drive, flash memory, an optical disc, a magneto-optical disc, magnetic tape, or a Universal Serial Bus drive or two or more of these. The storage may include removable or fixed media and may be internal or external to the computing device. The storage may include any suitable form of non-volatile, solid-state memory, or read-only memory. The system controller 146 includes a non-transitory computer readable medium or media. The non-transitory computer readable medium or media may include one or more semiconductor-based or other integrated circuits (ICs) (such, as for example, field-programmable gate arrays or application-specific ICs), hard disk drives, hybrid hard drives, optical discs, optical disc drives, magneto-optical discs, magneto-optical drives, solid-state drives, RAM drives, any other suitable non-transitory computer readable storage medium / media, or any suitable combination. The non-transitory computer readable medium or media may be volatile, non-volatile, or a combination of volatile and non-volatile.

[0030] In some cases, the program is software readable by the system controller 146 that includes code to perform tasks relating to monitoring, execution, and control of the movement and various process recipe tasks and recipe steps being performed in the processing chamber 100. For example, the program can include program code that includes a substrate positioning instruction set to operate the pedestal assembly 106; a gas flow control instruction set to operate gas flow control valves to set a flow of sputtering gas to the processing chamber 100; a gas pressure control instructionPATENTAttorney Docket No.: 44025873WO01set to operate a throttle valve or gate valve to maintain a pressure in the processing chamber 100; a temperature control instruction set to control a temperature control system (not shown) in the pedestal assembly 106 or sidewalls 124 to set temperatures of the substrate 108 or sidewalls 124, respectively; and a process monitoring instruction set to monitor the process in the processing chamber 100.

[0031] The upper process assembly 102 may also include an RF source 148, a direct current (DC) source 150, an adaptor 152, a motor 154, and a lid assembly 156. The lid assembly 156 may include the sputtering target 120, and a magnetron system 158. The upper process assembly 102 is supported by the sidewalls 124 when in a closed position, as shown in Figure 1A. A ceramic target isolator 160 is disposed between the isolator ring assembly 118, the sputtering target 120, and the adaptor 152 of the lid assembly 156 to prevent vacuum leakage there between. The adaptor 152 is sealably coupled to the sidewalls 124, and is configured to help with the removal of the upper process assembly 102 and isolator ring assembly 118.

[0032] When in the processing position, the sputtering target 120 is disposed adjacent to the adaptor 152, and is exposed to the processing region 110 of the processing chamber 100. The sputtering target 120 contains material that is deposited on the substrate 108 during a PVD, or sputtering, process. The isolator ring assembly 118 is disposed between the sputtering target 120 and the shield 112 and the chamber body 122 electrically isolating the sputtering target 120 from the shield 112 and chamber body 122.

[0033] During processing, the sputtering target 120 is biased relative to a grounded region of the processing chamber 100 (e.g., the chamber body 122 and the adaptor 152) by a power source disposed in the RF source 148 and / or the direct current (DC) source 150. It is believed that by delivering RF energy and / or DC power to the sputtering target 120 during a high pressure PVD process, significant process advantages can be achieved over low pressure DC plasma processing techniques when used in conjunction with sputtering materials such as titanium, copper, nickel, ruthenium, aluminum, tantalum, molybdenum, tungsten, and other materials. In one embodiment, the RF source 148 includes an RF power source and an RF match (not shown) that are configured to efficiently deliver RF energy to the sputtering target 120.PATENTAttorney Docket No.: 44025873WO01In some examples, the RF power source is capable of generating RF currents at a frequency of between about 13.56 MHz and about 228 MHz at powers between about 0.1 and about 5 kW. In one or more examples, a DC power supply included in the DC source 150 is capable of delivering between about 0.1 and about 50 kW of DC power.

[0034] During processing, a gas, such as argon, is supplied to the processing region 110 from a gas source 162 via conduits 164. The gas source 162 may include an inert gas such as argon, krypton, helium or xenon, which is capable of energetically impinging upon and sputtering material from the sputtering target 120 and / or surface of the substrate 108 based on a bias applied which may be applied by the PV waveform source 144. The gas source 162 may also include a reactive gas, such as one or more of an oxygen-containing gas or a nitrogen-containing gas, which is capable of reacting with the sputtering material to form a layer on a substrate. Spent process gas and byproducts are exhausted from the processing chamber 100 through exhaust ports 166 that receive spent process gas and direct the spent process gas to an exhaust conduit having an adjustable position gate valve (not shown) to control the pressure in the processing region 110 in the processing chamber 100. The exhaust conduit is connected to one or more exhaust pumps 168, such as a cryopump. In some cases, the pressure of the sputtering gas in the processing chamber 100 during processing is set to sub-atmospheric levels, such as a vacuum environment, for example, a pressure of about 0.6 mTorr to about 300 mTorr. In some embodiments, the processing pressure is set to about 20 mTorr to about 100 mTorr.

[0035] In some embodiments, a first electromagnet assembly 170 includes a first current source 170A configured to bias a first magnetic coil assembly 170B. The first magnetic coil assembly 170B may be positioned near the sputtering target 120 and may be configured to modulate an upper region of the formed plasma 172. A second electromagnet assembly 174 may include a second current source 174A and may be configured to bias a second magnetic coil assembly 174B. The second magnetic coil assembly 174B may be positioned in the central part of the chamber and may be configured to modulate a central portion of the plasma 172. The plasma 172 may be formed between the substrate 108 and the sputtering target 120 from the gas. A portion of ions within the plasma 172 may be accelerated toward the sputtering targetPATENTAttorney Docket No.: 44025873WO01120 and cause material to become dislodged from the sputtering target 120. The dislodged target material may be deposited on the substrate 108.

[0036] A lid enclosure 178 may include a conductive wall 180, a center feed 182, and shielding (not shown). In this configuration, the conductive wall 180, the center feed 182, the sputtering target 120, and a portion of the motor 154 may enclose and form a back region 184. The back region 184 is a sealed region disposed on the backside of the sputtering target 120 and may be filled with a flowing liquid during processing to remove the heat generated at the sputtering target 120 during processing. In some embodiments, the conductive wall 180 and the center feed 182 may be configured to support the motor 154 and magnetron system 158, so that the motor 154 can rotate the magnetron system 158 during processing. In one or more embodiments, the motor 154 may be electrically isolated from the RF or DC power delivered from the power supplies by use of a dielectric layer, such as Delrin, G10, or Ardel. The shielding (not shown) may include one or more dielectric materials that are positioned to enclose and prevent the RF energy delivered to the sputtering target 120 from interfering with and affecting other processing chambers. In some embodiments, the shielding may include a Delrin, G10, Ardel, or other similar material and / or a thin-grounded sheet metal RF shield.

[0037] To provide efficient sputtering, a magnetron system 158 may be positioned behind the sputtering target 120 in the upper process assembly 102 to create a magnetic field in the processing region 110 adjacent the sputtering surface 140 of the sputtering target 120, which generates the magnetron-controlled plasma 172. A magnetic field generated by the magnetron system 158 may trap electrons and ions to increase the plasma density over one or more regions of the sputtering target 120, and to increase target utilization, control deposition uniformity and the sputtering rate. In some embodiments, the magnetron system 158 may include a source magnetron assembly (not shown) that includes an outer pole (not shown) and an inner pole (not shown). The magnetron system 158 may be rotated about a central axis of the processing chamber 100 by use of the motor 154. In some embodiments, a “closed loop” magnetron configuration is formed within the magnetron system 158 such that the outer pole (not shown) of the magnetron surrounds the inner pole (not shown) of the magnetron forming a gap between the poles that is a continuous loop. In thePATENTAttorney Docket No.: 44025873WO01closed loop configuration, the magnetic fields that emerge and reenter through a surface of the sputtering target form a “closed loop” pattern can be used to confine electrons near the surface of the sputtering target in a closed pattern, which is often called a “racetrack” type pattern. A closed loop, as opposed to the open loop, magnetron configuration may be able to confine electrons and generate a high density plasma near the sputtering surface 140 of the sputtering target 120 to increase the sputtering yield. In some other embodiments, an “open loop” magnetron configuration may be formed within the magnetron system 158 such that the outer pole of the magnetron may surround the inner pole of the magnetron forming a gap between the poles that is a continuous loop. In an open loop magnetron configuration, the electrons trapped between the inner and outer poles may migrate, leak out, and escape from the B-fields created at open ends of the magnetron, thus only holding the electrons for a short period of time during the sputtering process due to the reduced confinement of the electrons. It has been found that the use of an open loop magnetron configuration can provide significant step coverage improvements and provide an improved material composition uniformity across the substrate surface, when used in conjunction with the RF and DC sputtering of multi-compositional targets described herein.

[0038] As will be discussed further below, in order to generate ion energies in the desired substrate bias voltage range the one or more processors of the system controller 146 may execute instructions that cause the one or more processors to control portions of PV waveform biasing circuit that is used to alter characteristics of the voltage pulses provided in a PV waveform generated by the PV waveform source 144. In one example, the one or more processors may adjust the voltage pulse amplitudes created within the PV waveform source 144.Pulsed Voltage Biasing Circuit

[0039] Figures 1 B and 1 C are schematic illustrations of pulsed voltage (PV) biasing circuits 190B and 190C (which may both be referred to herein as “190”) that can be used to provide a PV waveform to an electrode within a plasma process chamber, according to one or more embodiments described herein. The PV biasing circuit 190 may include a low energy mode (LEM) circuits 161 B and 161 C (which may both bePATENTAttorney Docket No.: 44025873WO01referred to herein as “161”) that are positioned between the output of the PV waveform source 144 (included in a PV waveform circuits 143B and 143C, which may both be referred to herein as “143”) and the electrode 142. The electrode 142 may be coupled to a complex load 192 and a ground reference (e.g., electrical ground, also referred to herein as a reference potential node) through an electrostatic chuck capacitance CE. In general, a parallel plate-like structure may be formed by the biasing electrode 142 and a layer of a dielectric material disposed on the surface of the substrate support 134 that has an effective electrostatic chuck capacitance CE, which may be in the nano-Farad (nF) range (e.g., 5 nF - 50 nF). A stray capacitance CSTRAY may be formed between one or more of the PV biasing circuit 190 components (e.g., electrode 142) and the ground reference.

[0040] The complex load 192 is shown in Figure 1 B as a standard electrical plasma model that represents the processing plasma 172 as three series elements. The first element being an electron-repelling cathode sheath (i.e., “plasma sheath 173”) adjacent to the substrate 108. The cathode sheath is represented by a three-part circuit element that includes: (a) the diode DSH, which when open represents the sheath collapse phase, (b) the current source li, representing the ion current flowing to the substrate in the presence of the sheath, and (c) the capacitive element CSH, which represents the sheath for the main portion of the biasing cycle (i.e., ion current phase of the PV waveform), during which the ions are accelerated towards the substrate 108. The second element being the plasma 172, which is represented by a single resistor Rpiasma. The third element being an electron-repelling wall sheath forming at the chamber walls. The wall sheath is likewise represented by a three-part circuit element that includes: (a) the diode Dwaii, (b) the current source Iwaii representing the ion current to the wall, and (c) the capacitive element Cwaii, which represents the wall sheath primarily during the ESC recharging phase of the PV waveform.

[0041] The low energy mode (LEM) circuit 161 includes a shunt capacitance leg 163 that is attached between the output port 144A of the PV waveform source 144 and the biasing electrode 142 and the ground reference. The shunt capacitance leg 163 within the LEM circuit 161 includes a shunt capacitive element Cs and a switch SW1. In some embodiments, the shunt capacitive element Cs is a variable capacitivePATENTAttorney Docket No.: 44025873WO01element, such as mechanically controlled variable capacitive element, digital variable capacitive element, or other type of variable capacitive element, which is, along with the switch SW1, controlled by command signals provided from the system controller 146. The ability to adjust the capacitance of the shunt capacitive element Cs and / or selectively couple a set or fixed capacitance in the shunt capacitance leg 163 to the ground reference, by use of the switch SW1 , is used to alter and / or adjust the effective capacitance of the PV biasing circuit 190 in an effort to adjust the substrate bias during plasma processing.

[0042] In some embodiments, the LEM circuit 161 may also include a shunt inductance leg 165 with an inductive element Ls and a switch SW2 that is coupled between the output port 144A of the PV waveform source 144 and the biasing electrode 142 (through the inductive element (labeled “Lune”)) and the ground reference, as shown in the PV biasing circuit 190B of Figure 1B. As shown in Figure 1 B, the inductive element Ls and the switch SW2 may form a shunt path.

[0043] In other embodiments, the LET circuit 161 may not include the shunt inductance leg 165 and the PV biasing circuit 190C may include an inductance leg 167 with an inductive element Ls and the switch SW2 and may be coupled in parallel with the inductive element Lune, as shown in Figure 1C. The inductive element Lune may represent the internal inductance between the LEM circuit 161 and the biasing electrode 142. As shown in Figure 1 C, the switch SW2 and the inductive element Ls may be coupled in parallel with the inductive element Lune between the output port 144A of the PV waveform source 144 and the biasing electrode 142. In this manner, the inductance between the output port 144A of the PV waveform source 144 and the biasing electrode 142 may be switched between the inductance of the inductive element Lune and the inductive element Ls (e.g., by coupling and decoupling the inductive element Ls between the PV waveform source 144 and the biasing electrode 142.

[0044] In some embodiments, the inductive element Ls is a fixed or variable inductive element, which is, along with the switch SW2, controlled by command signals provided from the system controller 146. The ability to selectively couple a set or fixed inductance (L) in the inductance leg 165, by use of the switch SW2, isPATENTAttorney Docket No.: 44025873WO01used to alter and / or adjust the effective impedance provided by the LEM circuit 161 in an effort to adjust the substrate bias during plasma processing. In some cases, the inductance in the PV biasing circuit 190 may be reduced (e.g., by decoupling the inductive element Ls and / or by varying the inductance of the inductive element Ls) to reduce the off time (TOFF) of the PV waveform delivered by the PV waveform source 144 (thereby increasing pulse on time, TON). In other cases, the inductance in the PV biasing circuit 190 may be increased (e.g., by coupling the inductive element Ls and / or by varying the inductance of the inductive element Ls) to increase the off time (TOFF) of the PV waveform delivered by the PV waveform source 144 (thereby decreasing pulse on time, TON).

[0045] In some cases, one of the switch SW1 , the shunt capacitive element Cs, the switch SW2, or the inductive element Ls may be disposed inside the PV waveform source 144, whereas in other cases, one or more of the switch SW1, the shunt capacitive element Cs, the switch SW2, or the inductive element Ls may be disposed outside the PV waveform source 144. The switching control provided to the switch SW1 and / or the switch SW2 may be mechanical, or provided by one or more processors included in the PV waveform source 144, by the system controller 146, or by the PV waveform source 144 through any communication protocol.Pulsed Voltage Waveform Examples

[0046] Figure 2A illustrates a voltage waveform that may be established at an electrode of a processing chamber, such as electrode 142, according to one or more embodiments described herein. Figure 2B illustrates an example 200 of different types of non-sinusoidal voltage waveforms 225 and 230 established at a substrate surface due to different voltage waveforms provided from a pulsed voltage (PV) biasing circuit 190 coupled to the PV waveform source 144, similar to the voltage waveform shown in Figure 2A, which are separately established at an electrode (e.g., bias electrode 142) within the processing chamber, according to one or more embodiments described herein. The waveforms include two stages: an ion current stage and a sheath collapse stage 210, as shown. At the beginning of the ion current stage, a drop of substrate voltage creates a high voltage sheath 173 (Figure 1A) above the substrate, accelerating positive ions to the substrate. The positive ions thatPATENTAttorney Docket No.: 44025873WO01bombard the surface of the substrate during the ion current stage deposit a positive charge on the substrate surface, which if uncompensated for causes a gradual increase in the substrate voltage positively during the ion current stage, as illustrated by voltage waveform 225 in Figure 2B. To minimize the amount of pulse voltage waveform droop experienced during the ion current stage, the sheath collapse stage 210 is provided to remove or reset the charge accumulated on the surface of the substrate so that the substrate bias voltage can then be reapplied at a desired substrate bias voltage during the subsequent ion current stage of a subsequent voltage pulse.

[0047] The waveforms 225 and 230 (and any voltage or PV waveforms described herein) may be considered and / or referred to as asymmetric waveforms because the ion current stage of the waveforms 225 and 230 is different in time (e.g., has a different length in time or a different duration) than the sheath collapse stage. For example, and as illustrated in Figure 2B, the ion current stage of each of the waveforms 225 and 230 may be longer in time than the sheath collapse stage. In addition, and in some cases, the waveforms 225 and 230 (and any voltage or PV waveforms described herein) may be considered and / or referred to as non-sinusoidal waveforms (e.g., waveforms that do not follow the shape of a sine wave).

[0048] The ion flux received by a substrate during the ion current stage, which needs to be compensated for to avoid PV waveform droop, can be described by the equation EQ1:where “I” is the ion current, “Q” is charge, “V” is voltage, “C” is the total capacitance, and “t” is time.

[0049] However, the uncontrolled accumulation of positive charge on the substrate surface undesirably gradually discharges the sheath and chuck capacitive elements, slowly decreasing the sheath voltage drop and bringing the substrate potential closer to zero, as illustrated by voltage waveform 225. The accumulation of positive charge results in the voltage drop (e.g., voltage becoming less negative (i.e., “pulse voltagePATENTAttorney Docket No.: 44025873WO01waveform droop”)) in the voltage waveform established at the substrate surface (Figure 2B). However, in some PV waveform delivery processes, a voltage waveform that is established at the electrode that has a negative slope during the ion current stage is provided, as shown in Figure 2A, so as to establish a square shaped region (e.g., near zero slope) for an established substrate voltage waveform, as shown by voltage waveform 230 in Figure 2B. Implementing the slope in the PV waveform established at the electrode during the ion current stage may be referred to as current compensation. The voltage difference between the beginning and end of the ion current stage determines an ion energy distribution function (IEDF) width. The greater the voltage difference during the ion current stage, the wider the IEDF width. To achieve mono-energetic ions and a narrower IEDF width, operations are performed to flatten the substrate voltage waveform in the ion current stage using current compensation.

[0050] In an effort to control IEDF, by reducing the pulse voltage waveform droop, different methods have been used, such as a pulse voltage waveform frequency control and step-wise voltage control. In frequency control applications, the frequency (i.e., frequency = 1 / (pulse period Tp)) of the delivered voltage pulse is adjusted to achieve a desired or minimal amount of pulse voltage waveform droop. However, the length of the sheath collapse stage 210 (TOFF) within the pulse period Tp may have a fixed length that is set and / or limited by the reactive elements in the PV biasing circuit. Therefore, an increase in the frequency of the voltage pulses to reduce the amount of pulse voltage waveform droop will cause a direct reduction in the time (TON) the substrate bias is applied to the substrate during the pulse period Tp and a reduction in the duty cycle (TON / TP) of the applied substrate bias. In some embodiments, the PV biasing circuit 190 (or the PV waveform source 144) may include (or utilize) switching circuitry (not shown) to adjust the frequency of delivered voltage pulses (e.g., that form the PV waveform) during the operations described herein. In other embodiments, the PV biasing circuit 190 (or the PV waveform source 144) may not include the switching circuitry.

[0051] At low substrate bias voltages, “dV” in EQ1 is small, when used in a ion current compensation scheme that utilizes the adjustment in the frequency of the voltage pulses, since it is difficult for the PV waveform source 144 within the PVPATENTAttorney Docket No.: 44025873WO01biasing circuit 190 to provide enough current to compensate for ion flux current, and the control of the ion energy therefore energy spread control is IEDF is difficult. Low substrate bias voltages can be in a range between 10 volts (V) and 250 V, such as between 10 V and 200 V.

[0052] It has also been found that when low substrate bias voltages (e.g., small dV in EQ1) are required, a generator using frequency adjustment to compensate the ion current, the biasing duty cycle, which controls the total ion flux passing through the plasma sheath, would be too small to be useful.

[0053] In some embodiments, the LEM circuit 161 is used to increase or maintain high pulse voltage waveform duty cycle in a frequency compensated ion current control scheme by changing the effective capacitance of the PV biasing circuit 190 to maintain constant current that is used to compensate for the plasma generated ion current (I).

[0054] In a frequency compensated ion current control scheme, the ion flux received by a substrate during the ion current stage can be generally described by the equation EQ2:where “I” is the ion current, “f” is frequency, “AV” is the change in voltage (V), “C” is the total capacitance, “k” is proportional coefficient, and “t” is time.

[0055] By changing / varying total capacitance C by a proportional coefficient (k), specifically by increasing the PV biasing circuit 190’s capacitance by adding in the shunt capacitance leg 163 by closing the switch SW1, the needed pulse frequency can be proportionally decreased by (1 / k) and pulse period increased by (k) times. The decreased pulse frequency, which allows a longer pulse period to be used, and therefore increases the on-duty cycle of plasma ion extraction in a biasing pulse.

[0056] In a separate fixed pulse frequency ion current compensation scheme, changing the pulse frequency by switching to variable or fixed frequency control modules, can also proportionally boost the effective voltage needed to maintain compensation current. In the fixed pulse frequency ion current compensationPATENTAttorney Docket No.: 44025873WO01scheme, the ion flux received by a substrate during the ion current stage can be generally described by the equation EQ3:where “I” is the ion current, “f” is frequency, “AV” is the change in voltage (V), “C” is the total capacitance, “k” is proportional coefficient, and “t” is time. By changing / varying the delivered pulsed frequency f by a proportional coefficient (k), specifically by decreasing f, the effective voltage can be boosted by k to provide the needed compensation current. The boosted effective voltage (k V) could improve generator waveform shape control in low voltage (low energy regime) to provide useful high ion energy spread control.Plasma Process Examples

[0057] Figure 3 is a process flow diagram illustrating a method 300 for delivering a pulsed voltage (PV) waveform to an electrode disposed in a substrate support during a plasma process, according to one or more embodiments described herein. Figure 4 is a timing diagram illustrating operations performed during the performance of method 300, according to one or more embodiments described herein.

[0058] At operation 302, a deposition process is performed on a surface of a substrate. The deposition process can include a PVD deposition process that includes a substrate biasing operation that is performed by use of the PV biasing circuit 190 that is configured to bias the substrate by delivering PV waveform to the electrode 142 disposed in the substrate support while a plasma is formed in the PVD deposition chamber. As illustrated in Figure 4, the deposition process is performed between times to and ti. The PV waveform provided during operation 302 is configured to include a low substrate bias voltage (Vi) during the ion current phase of the of the PV waveform by increasing the effective capacitance of the PV biasing circuit 190 by adding the shunt capacitance Cs by closing the switch SW1 to couple the output of the PV waveform source 144 and shunt capacitance Cs to the ground reference. In some embodiments, the shunt capacitance Cs is set to a fixed capacitance during the duration of the deposition operation 302. In some other embodiments, the shunt capacitance Cs capacitance value is adjusted by signalsPATENTAttorney Docket No.: 44025873WO01provided from the system controller 146 during the deposition operation 302 to compensate for differing ion fluxes created by adjusting the substrate bias applied to the substrate during at least a portion of the deposition process.

[0059] In some embodiments of operation 302, the PV waveform provided during operation 302 also includes adding an inductance to adjust the impedance of the PV biasing circuit 190 by adding the inductance Ls by closing the switch SW2 to couple the output of the PV waveform source 144 and inductive element Ls to the ground reference. The addition of the inductance Ls to the PV biasing circuit 190 can be provided while the shunt capacitance Cs is also coupled to the ground reference.

[0060] At operation 304, a deposited layer shaping or etching process is performed on a surface of a substrate. In some embodiments, the process performed during operation 304 does not include a PVD target sputtering operation, and thus does not include additional deposition of a layer on the surface of the substrate. However, in other embodiments, operation 304 does include sputtering of the PVD target during operation 304, but at a different sputter rate than the sputtering process performed during operation 302.

[0061] Operation 304 will include a substrate biasing operation that is configured to bias the substrate by delivering a higher pulse bias voltage (V2) during the ion current phase of the PV waveform to the electrode 142 disposed in the substrate support while a plasma is formed in the PVD deposition chamber. As illustrated in Figure 4, the deposited layer shaping or etching process is performed between times ti and t2. The PV waveform provided during operation 304 is configured to include a high substrate bias voltage (V2) by removing the shunt capacitance Cs from the PV biasing circuit 190 by opening the switch SW1 to decouple the shunt capacitance leg 163 from the PV biasing circuit 190.

[0062] Operations 302 and 304 may be completed two or more times on the same substrate to form a deposited layer that has a desired thickness and layer morphology (e.g., desired bottom coverage, sidewall coverage, reduced overhang, etc.) within features formed in the surface of the substrate. In some cases, operation 302 is performed a second time, as shown during times t2 and ts in Figure 4, and operation 304 is performed a second time, as shown during times te and t4 in Figure 4.PATENTAttorney Docket No.: 44025873WO01Additional Considerations

[0063] While this specification contains many specific implementation details, these should not be construed as limitations on the scope of what may be claimed, but rather as descriptions of features that may be specific to particular implementations. Certain features that are described in this specification in the context of separate implementations may also be implemented, in combination, in a single implementation. Conversely, various features that are described in the context of a single implementation may also be implemented in multiple implementations, separately, or in any suitable sub-combination. Moreover, although previously described features may be described as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination may, in some cases, be excised from the combination, and the claimed combination may be directed to a sub-combination or variation of a sub-combination.

[0064] Particular implementations of the subject matter have been described. Other implementations, alterations, and permutations of the described implementations are within the scope of the following claims as will be apparent to those skilled in the art. While operations are depicted in the drawings or claims in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed (some operations may be considered optional) to achieve desirable results. In certain circumstances, multitasking or parallel processing (or a combination of multitasking and parallel processing) may be advantageous and performed as deemed appropriate. While the various steps in an embodiment method or process are presented and described sequentially, one of ordinary skill in the art will appreciate that some or all of the steps may be executed in different order, may be combined, or omitted, and some or all of the steps may be executed in parallel. The steps may be performed actively or passively. The method or process may be repeated or expanded to support multiple components or multiple users within a field environment. Accordingly, the scope should not be considered limited to the specific arrangement of steps shown in a flowchart or diagram.PATENTAttorney Docket No.: 44025873WO01

[0065] Furthermore, any claimed implementation is considered to be applicable to at least a computer-implemented method; a non-transitory, computer-readable medium storing computer-readable instructions to perform the computer-implemented method; and a computer system including a computer memory interoperability coupled with a hardware processor configured to perform the computer-implemented method or the instructions stored on the non-transitory, computer-readable medium.

[0066] As used herein, “a CPU”, “controller”, “a processor”, “at least one processor”, or “one or more processors”, generally refers to a single processor configured to perform one or multiple operations or multiple processors configured to collectively perform one or more operations. In the case of multiple processors, performance the one or more operations could be divided amongst different processors, though one processor may perform multiple operations, and multiple processors could collectively perform a single operation. Similarly, “a memory”", at least one memory”, or “one or more memories”, generally refers to a single memory configured to store data and / or instructions, multiple memories configured to collectively store data and / or instructions.

[0067] As used herein, “gas” and “fluid” may be used interchangeable with either term generally referring to elements, compounds, materials, etc., having the properties of a gas, a fluid, or both a gas and a fluid.

[0068] Unless defined otherwise, all technical and scientific terms used have the same meaning as commonly understood by one of ordinary skill in the art to which these systems, apparatuses, methods, processes and compositions belong.

[0069] In this disclosure, the terms “top”, “bottom”, “side”, “above”, “below”, “up”, “down”, “upward”, “downward,” “horizontal,” “vertical,” and the like do not refer to absolute directions. Instead, these terms refer to directions relative to a nonspecific plane of reference. This non-specific plane of reference may be vertical, horizontal, or other angular orientation.

[0070] The singular forms “a”, “an”, and “the”, include plural referents, unless the context clearly dictates otherwise. Within a claim, reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, butPATENTAttorney Docket No.: 44025873WO01rather “one or more”. Unless specifically stated otherwise, the term “some” refers to one or more.

[0071] Embodiments of the present disclosure may suitably “comprise”, “consist”, or “consist essentially of”, the limiting features disclosed, and may be practiced in the absence of a limiting feature not disclosed. As used here and in the appended claims, the words “comprise”, “has”, and “include”, and all grammatical variations thereof are each intended to have an open, non-limiting meaning that does not exclude additional elements or steps.

[0072] “Optional” and “optionally” means that the subsequently described material, event, or circumstance may or may not be present or occur. The description includes instances where the material, event, or circumstance occurs and instances where it does not occur.

[0073] “Coupled” and “coupling” means that the subsequently described material is connected to previously described material. The connection may be a direct, or indirect connection, and may, or may not, include intermediary components such as plumbing, wiring, fasteners, mechanical power transmission, electrical communication, wired and / or wireless transmission, etc., which may suitable to affect operation of the components.

[0074] As used, the term “determining” encompasses a wide variety of actions. For example, “determining” may include calculating, computing, processing, deriving, investigating, looking up, for example, looking up in a table, a database, or another data structure, and ascertaining. In addition, “determining” may include receiving, for example, receiving information, and accessing, for example, accessing data in a memory. In addition, “determining” may include resolving, selecting, choosing, and establishing.

[0075] When the word “approximately” or “about” are used, this term may mean that there may be a variance in value of up to ±10%, of up to 5%, of up to 2%, of up to 1%, of up to 0.5%, of up to 0.1%, or up to 0.01%.

[0076] Ranges may be expressed as from about one particular value to about another particular value, inclusive. When such a range is expressed, it is to bePATENTAttorney Docket No.: 44025873WO01understood that another embodiment is from the one particular value to the other particular value, along with all particular values and combinations thereof within the range.

[0077] As used, terms such as “first” and “second” are arbitrarily assigned and are merely intended to differentiate between two or more components of a system, an apparatus, or a composition. It is to be understood that the words “first” and “second” serve no other purpose and are not part of the name or description of the component, nor do they necessarily define a relative location or position of the component. Furthermore, it is to be understood that that the mere use of the term “first” and “second” does not require that there be any “third” component, although that possibility is envisioned under the scope of the various embodiments described.

[0078] Although only a few example embodiments have been described in detail, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the disclosed scope as described. Accordingly, all such modifications are intended to be included within the scope of this disclosure as defined in the following claims. In the claims, means-plus-function clauses are intended to cover the structures described as performing the recited function and not only structural equivalents, but also equivalent structures. It is the express intention of the applicant not to invoke 35 U.S.C. § 112(f), for any limitations of any of the claims, except for those in which the claim expressly uses the words ‘means for’ together with an associated function.

[0079] The following claims are not intended to be limited to the embodiments provided but rather are to be accorded the full scope consistent with the language of the claims.

Claims

PATENTAttorney Docket No.: 44025873WO01What is claimed is:

1. A method of biasing a substrate during a plasma deposition process, the method comprising:forming a plasma within a processing region of a plasma processing chamber; anddelivering a pulsed voltage (PV) waveform to an electrode disposed in a substrate support within the processing region of the plasma processing chamber, wherein delivering the PV waveform comprises:a first substrate biasing operation, comprising:delivering the PV waveform at a first substrate bias, by use of a PV waveform source, by delivering a series of voltage pulses having amplitudes that extend from a first positive voltage to a first negative voltage; andcoupling, by use of a first switch, a shunt capacitance to an output of the PV waveform source, wherein the shunt capacitance is coupled between the output of the PV waveform source and a reference potential node; anda second substrate biasing operation, comprising:delivering the PV waveform at a second substrate bias, by use of the PV waveform source, by delivering a series of voltage pulses having amplitudes that extend from a second positive voltage to a second negative voltage; anddecoupling, by use of the first switch, the shunt capacitance from the output of the PV waveform source.

2. The method of claim 1, wherein the shunt capacitance is set to a first capacitance value during a duration of the delivery of the PV waveform at the first substrate bias.

3. The method of claim 1 , wherein the shunt capacitance is adjusted between a first capacitance value and a second capacitance value during the delivering of the PV waveform at the first substrate bias.PATENTAttorney Docket No.: 44025873WO014. The method of claim 1, wherein the first positive voltage within the first substrate biasing operation and the second positive voltage within the second substrate biasing operation are substantially the same.

5. The method of claim 1, wherein the first negative voltage within the first substrate biasing operation and the second negative voltage within the second substrate biasing operation are substantially the same.

6. The method of claim 1 , wherein at least one of the first substrate biasing operation or the second substrate biasing operation further comprises coupling, by use of a second switch, an inductance to the output of the PV waveform source, wherein the inductance and the second switch are coupled between the output of the PV waveform source and the electrode.

7. The method of claim 1 , wherein at least one of the first substrate biasing operation or the second substrate biasing operation further comprises decoupling, by use of a second switch, an inductance to the output of the PV waveform source, wherein the inductance and the second switch are coupled between the output of the PV waveform source and the electrode.

8. The method of claim 1 , wherein at least one of:the first substrate biasing operation comprises adjusting during the delivery of the PV waveform at the first substrate bias, a frequency of the PV waveform; or the second substrate biasing operation comprises adjusting during the delivery of the PV waveform at the second substrate bias, a frequency of the PV waveform.

9. A non-transitory computer-readable medium comprising computer-executable instructions that, when executed by one or more processors of a system controller, cause the system controller to perform a method, the method comprising:forming a plasma within a processing region of a plasma processing chamber; andPATENTAttorney Docket No.: 44025873WO01delivering a pulsed voltage (PV) waveform to an electrode disposed in a substrate support within the processing region of the plasma processing chamber, wherein delivering the PV waveform comprises:a first substrate biasing operation that includes:delivering the PV waveform at a first substrate bias, by use of a PV waveform source, by delivering a series of voltage pulses having amplitudes that have a first negative voltage; andcoupling, by use of a first switch, a shunt capacitance to an output of the PV waveform source, wherein the shunt capacitance is coupled between the output of the PV waveform source and a reference potential node.

10. The non-transitory computer-readable medium of claim 9, wherein the shunt capacitance is adjusted between a first capacitance value and a second capacitance value during the delivering of the PV waveform at the first substrate bias.

11. The non-transitory computer-readable medium of claim 9, whereinthe shunt capacitance is adjusted between a first capacitance value and a second capacitance value during the delivery of the PV waveform at the first substrate bias, anddelivering the PV waveform further comprises a second substrate biasing operation that includes:delivering the PV waveform at a second substrate bias, by use of the PV waveform source, by delivering a series of voltage pulses having amplitudes that have a second negative voltage; anddecoupling, by use of the first switch, the shunt capacitance from the output of the PV waveform source.

12. The non-transitory computer-readable medium of claim 9, whereinthe shunt capacitance is set to a first capacitance value during the delivery of the PV waveform at the first substrate bias, anddelivering the PV waveform further comprises a second substrate biasing operation that includes:PATENTAttorney Docket No.: 44025873WO01delivering the PV waveform at a second substrate bias, by use of the PV waveform source, by delivering a series of voltage pulses having amplitudes that have a second negative voltage; anddecoupling, by use of the first switch, the shunt capacitance from the output of the PV waveform source.

13. The non-transitory computer-readable medium of claim 12, wherein the first negative voltage within the first substrate biasing operation and the second negative voltage within the second substrate biasing operation are substantially the same.

14. The non-transitory computer-readable medium of claim 12, wherein at least one of the first substrate biasing operation or the second substrate biasing operation further comprises coupling, by use of a second switch, an inductance to the output of the PV waveform source, and wherein the inductance and the second switch are coupled between the output of the PV waveform source and the electrode.

15. The non-transitory computer-readable medium of claim 12, wherein at least one of the first substrate biasing operation or the second substrate biasing operation further comprises decoupling, by use of a second switch, an inductance to the output of the PV waveform source, and wherein the inductance and the second switch are coupled between the output of the PV waveform source and the electrode.

16. The non-transitory computer-readable medium of claim 12, wherein at least one of:the first substrate biasing operation comprises adjusting during the delivery of the PV waveform at the first substrate bias, a frequency of the PV waveform; or the second substrate biasing operation comprises adjusting during the delivery of the PV waveform at the second substrate bias, a frequency of the PV waveform.

17. A plasma processing assembly, comprising:an electrode;a pulsed voltage (PV) waveform source coupled to the electrode, wherein the PV waveform source is configured to deliver a series of asymmetric voltage pulses;PATENTAttorney Docket No.: 44025873WO01a capacitive element including a first terminal coupled to the PV waveform source and the electrode via a first switch and including a second terminal coupled to a reference potential node; andan inductive element including a first terminal coupled to the PV waveform source via a second switch and including a second terminal coupled to the electrode.

18. The plasma processing assembly of claim 17, wherein the capacitive element is adjustable.

19. The plasma processing assembly of claim 17, further comprising:a plasma processing chamber; anda substrate support disposed in the plasma processing chamber, wherein the electrode is disposed in the substrate support.

20. The plasma processing assembly of claim 17, further comprising a system controller that includes one or more processors configured to deliver a pulsed voltage waveform to the electrode by:performing a first substrate biasing operation, comprising:delivering a PV waveform at a first substrate bias, by use of the PV waveform source, by delivering a series of voltage pulses having amplitudes that extend from a first positive voltage to a first negative voltage; and coupling, by use of the first switch, a shunt capacitance to an output of the PV waveform source, wherein the shunt capacitance is coupled between the output of the PV waveform source and the reference potential node; and performing a second substrate biasing operation, comprising:delivering the PV waveform at a second substrate bias, by use of the PV waveform source, by delivering a series of voltage pulses having amplitudes that extend from a second positive voltage to a second negative voltage; anddecoupling, by use of the first switch, the shunt capacitance from the output of the PV waveform source.

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