Processor-based circuit interrupting device having noise tolerance

Abstract

A circuit interrupting device includes a grounded neutral (GN) fault detection circuit and a controller. The grounded neutral (GN) fault detection circuit is configured to provide a first signal in response to a GN fault on a neutral conductor, where the first signal has a frequency in a predetermined frequency range above a power line frequency. The controller is configured to perform: detecting a second signal while the GN fault detection circuit is enabled, where the second signal has a frequency within the predetermined frequency range above the power line frequency; causing the GN fault detection circuit to be disabled; and based on detecting no frequency in the predetermined frequency range above the power line frequency while the GN fault detection circuit is disabled, causing a load to be disconnected.

Description

PATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT) PROCESSOR-BASED CIRCUIT INTERRUPTING DEVICEHAVING NOISE TOLERANCECROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to and the benefit of the filing date of U.S. Provisional Application No. 63 / 749,157, filed on January 24, 2025, which is hereby incorporated by reference herein in its entirety.TECHNICAL FIELD

[0002] The present disclosure relates to processor-based circuit interrupting devices, and more particularly, to microcontroller-based circuit interrupting devices having noise tolerance.BACKGROUND

[0003] A category of line monitors, such as power line monitors, includes the ground-fault circuit interrupter (GFCI). A GFCI should preferably be able to pass industry standards, such as Underwriter's Laboratory (UL) standards. UL standard UL934 has requirements for GFCIs that relate to 60 Hz operations. Under UL standard ULI 01, appliances are allowed to produce significant high frequency currents. The UL standards may coexist in a way that allows undesirable conditions to exist, even while UL standards are satisfied. There is continuing interest in improving GFCIsSUMMARY

[0004] In accordance with aspects of the present disclosure, a circuit interrupting device includes: a grounded neutral (GN) fault detection circuit configured to provide a first signal in response to a GN fault on a neutral conductor, where the first signal has a frequency in a predetermined frequency range above a power line frequency; and a controller. The controller is configured to perform: detecting a second signal while the GN fault detection circuit is enabled, where the second signal has a frequency within the predetermined frequency range above the power line frequency; causing the GN fault detection circuit to be disabled; and based on detecting no frequency within the predetermined frequency range above the power line frequency while the GN fault detection circuit is disabled, causing a load to be disconnected.

[0005] In accordance with aspects of the present disclosure, a method in a circuit interrupting device includes: causing a grounded neutral (GN) fault detection circuit to be enabled, where the GN fault detection circuit configured to provide a first signal in response to a GN fault on a neutralPATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT) conductor, where the first signal has a frequency in a predetermined frequency range above a power line frequency; detecting a second signal while the GN fault detection circuit is enabled, where the second signal has a frequency in the predetermined frequency range above the power line frequency; causing the GN fault detection circuit to be disabled; and based on detecting no frequency in the predetermined frequency range above the power line frequency while the GN fault detection circuit is disabled, causing a load to be disconnected.

[0006] Any of the embodiments and / or aspects disclosed above or below herein may be combined with one or more or embodiments and / or aspects disclosed herein. All combinations of embodiments and / or aspects are contemplated to be within the scope of the present disclosure. Examples of embodiments provided at the end of the detailed description are hereby incorporated by reference into this section.

[0007] The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the techniques described in this disclosure will be apparent from the description and drawings, and from the claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0008] A detailed description of embodiments of the disclosure will be made with reference to the accompanying drawings, wherein like numerals designate corresponding parts in the figures:

[0009] FIG. l is a block diagram of example portions of GFCI circuitry, in accordance with aspects of the present disclosure;

[0010] FIG. 2 is a diagram of an example components of a controller, in accordance with aspects of the present disclosure;

[0011] FIG. 3 is a diagram of an example circuit for providing a voltage reference, in accordance with aspects of the present disclosure;

[0012] FIG. 4 is a diagram of yet another example circuit for providing a voltage reference, in accordance with aspects of the present disclosure;

[0013] FIG. 5 is a flow diagram of an example operation in a GFCI device, in accordance with aspects of the present disclosure;

[0014] FIG. 6 is a flow diagram of another example operation in a GFCI device, in accordance with aspects of the present disclosure; andPATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT)

[0015] FIG. 7 is a flow diagram of an example operation for adjusting sensitivity of a GFCI device, in accordance with aspects of the present disclosure.DETAILED DESCRIPTION

[0016] In the following description, certain specific details are set forth in order to provide a thorough understanding of disclosed aspects. However, one skilled in the relevant art will recognize that aspects may be practiced without one or more of these specific details or with other methods, components, materials, etc. In other instances, well-known structures associated with transmitters, receivers, or transceivers have not been shown or described in detail to avoid unnecessarily obscuring descriptions of the aspects.

[0017] Reference throughout this specification to “one aspect” or “an aspect” means that a particular feature, structure, or characteristic described in connection with the aspect is included in at least one aspect. Thus, the appearances of the phrases “in one aspect” or “in an aspect” in various places throughout this specification are not necessarily all referring to the same aspect. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more aspects.

[0018] A ground fault circuit interrupter (GFCI) is a device, e.g., in a circuit breaker, in a receptacle, or otherwise (e g., in right angle, in-line, plug-in, or panel mount circuit interrupt devices), that operates to disconnect electrical power in the event of an electrical fault. As persons skilled in the art will understand, an electrical fault means and refers to a condition in which electrical current does not follow an intended path within an electrical device and may, instead, be diverted to undesirable paths, such as to a path to a person. Since the advent of GFCI devices, the number of fatalities from electrocution has decreased significantly.

[0019] A GFCI device must be reliable in detecting electrical faults and must also be useful. If a GFCI falsely trips its circuit breaker often and unnecessarily, electrical power to the load becomes unnecessarily interrupted and will cause users to be confused and frustrated. Modem appliances and lights, however, among other devices and equipment, may use power supplies that generate significant high frequency ground currents. When such loads are connected to a GFCI device, the significant high frequency ground currents may create fault-like conditions in a GFCI device. At the same time, actual electrical faults may also involve high frequency signals. Accordingly, it is important for a GFCI device to distinguish high frequencies signals associatedPATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT) with an actual electrical fault, which require circuit interruption, from high frequency signals caused by a load, which do not require circuit interruption.

[0020] A GFCI device having a controller is disclosed. As explained in further detail below, the controller can process signals to detect one or more electrical fault conditions, such as ground fault or grounded neutral (G / N) conditions, and can also process signals to distinguish actual faults from G / N-like conditions caused by high frequency signals from a load.

[0021] The controller of the GFCI device can be or include a processor, a microcontroller, a digital signal processor, a system on chip (SOC), and / or a field programmable gate array (FPGA), among other possibilities. In various embodiments, the controller is provided as a single integrated circuit (1C) chip which can be mounted on a single printed circuit board (PCB). In various embodiments, the various circuit components, including, for example, the controller, are provided as one or more integrated circuit chips. That is, the various circuit components are located on one or more integrated circuit chips.

[0022] In accordance with aspects of the present disclosure, the controller executes instructions (e.g., firmware) to determine whether a real electrical fault may be occurring or whether an electrical fault is not occurring but G / N-like conditions, e.g., high frequency ground noise from appliances that are within allowed levels, are present. As mentioned above, modem appliances and lights may use power supplies that generate significant high frequency ground currents, which may generate a high frequency ground fault and which can be misinterpreted as grounded neutral conditions and cause false tripping of GFCIs. The present disclosure decreases false tripping in a GFCI by identifying high frequency signals from loads that are not related to an actual electrical fault.

[0023] Referring now to FIG. 1, there is shown a block diagram of an example of a GFCI device that includes a controller 140. The GFCI device senses a variety of electrical faults associated with signals on a phase conductor 101 and a neutral conductor 103, which are connected between a power source 104 (e.g., 120 VAC) and a load 106. The power signals provided by the power source 104 may, for example, be power signals provided by a utility company or power signals provided to a portion of a residential or commercial electrical system, such as via a branch circuit.

[0024] The GFCI device includes a differential current transformer 112 and a grounded neutral (G / N) transformer 114. The differential transformer 112 detects or senses an imbalance betweenPATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT) current flowing through the phase conductor 101 and the neutral conductor 102, which is indicative of a ground fault condition. When an imbalance is detected, the differential transformer 112 outputs a differential signal having a voltage (referred to herein as a differential voltage) that corresponds to the sensed difference between the currents flowing through the phase and neutral conductors 101, 103. When a ground fault condition occurs, the differential signal has a first frequency that corresponds to the frequency of the signals flowing through the phase and neutral conductors, e.g., a power signal frequency of about 60 Hz. A signal, which is based on the differential signal, is provided to an operational amplifier (OP A0) 116, which effectively operates to amplify the differential voltage and output a signal OPAO out that corresponds to an amplified differential voltage.

[0025] The grounded neutral transformer 114 and the differential transformer 112 are arranged or configured to be in a proper electrical phase relationship with respect to each other. This may be achieved in any suitable manner, such as, for example, physically positioning or arranging the grounded neutral transformer 114 and the differential transformer 112 in a particular orientation with respect to each other such that the direction of current flow in one transformer is along a particular direction with respect to the direction of current flow of the other transformer. A resonant circuit 120 may include a capacitor having a selected capacitive value that will create resonance upon inductance of the grounded neutral transformer 114. The resonant circuit 120 will be discussed more below.

[0026] In accordance with aspects of the present disclosure, output of the op-amp OP A0 116 is connected to a low pass filter 121 and to a high pass filter and op-amp (OPA1) 122. The low pass filter 121 is configured to extract the power line frequency component from the OPAO out signal for use in detecting “traditional” power line ground faults which exhibit the power line frequency (e.g., 60 Hz, or another power line frequency). As shown in FIG. 1, the extracted power line component is denoted as an LPF out signal. The power line frequency component may be referred to herein as a first frequency component. Persons skilled in the art will understand how to detect a traditional ground fault using the OPAO out signal and / or the LPF out signal. For example, techniques described in U.S. Patent No. 9,276,393 may be employed. The entire contents of U.S. Patent No. 9,276,393 are hereby incorporated by reference herein.

[0027] In accordance with aspects of the present disclosure, the high pass filter and OPA1 122 are configured to remove a low frequency component from the OPAO out signal and leave a highPATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT) frequency component that may be indicative of either a G / N-fault or high frequency noise from the load 106, and to amplify that high frequency component. In various embodiments, the high frequency component may, for example, have a frequency between 3 kHz - 10 kHz, or another frequency range. The high frequency component may be referred to herein as a second frequency component and is explained in more detail below.

[0028] The output of the op-amp OP Al 122 is a signal denoted as OPAl out and is connected through a resonant circuit 120 to the grounded neutral transformer 114. The OP Al 122 is in a proper electrical phase relationship with the differential transformer 112 such that OPA1 122 oscillates upon the occurrence of a grounded neutral condition at a second frequency. When a grounded neutral condition is present, the grounded neutral transformer 114 injects or outputs a signal which creates an imbalance in the currents passing through differential transformer 112, which causes the differential transformer 112 to output a differential signal that has the second frequency component.

[0029] Specifically, the grounded neutral transformer 114, the differential transformer 112, the resonant circuit 120, OP A0 116, and OPA1 122 cooperate to achieve positive feedback when a grounded neutral fault condition exists. The resonant circuit 120 may include a capacitor having a selected capacitance value that will result in resonance upon inductance of the grounded neutral transformer 114. When a grounded neutral fault occurs, the resonant circuit 120 is configured to oscillate at its resonant frequency (i.e., the second frequency), and a current in the neutral conductor 103 is detected by the differential transformer 112. When no such grounded neutral fault is detected, the resonant circuit 120 acts simply as a load and does not affect operation of the differential transformer 112. An example of positive feedback is described in U.S. Patent No.9,276,393, which was incorporated by reference above.

[0030] Persons skilled in the art will understand other approaches for implementing proper phase relationship between a grounded neutral transformer and an amplifier to achieve positive feedback when an actual grounded neutral fault occurs. Such other approaches and embodiments are contemplated to be within the scope of the present disclosure.

[0031] As mentioned above, high frequency signals from the load 106 may appear as a G / N-like condition if the high frequency signals are in the range of the second frequency, i.e., in the range of the resonant frequency of the resonant circuit 120 when an actual grounded neutral fault occurs. In accordance with aspects of the present disclosure, a controller 140 may operate toPATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT) distinguish actual grounded neutral faults from such high frequency signals from the load by enabling and disabling the grounded neutral transformer 114 and determining whether the high frequency signals are present during both enabled and disabled periods of the grounded neutral transformer 114. That is, if the high frequency signals are present when the grounded neutral transformer 114 is enabled and also when the grounded neutral transformer 114 is disabled, the controller may conclude that the G / N-like condition is caused by high frequency signals from the load 106 (or by another cause) rather than caused by an actual grounded neutral fault. In the illustration of FIG. 1, the grounded neutral transformer 114 may be disabled by closing a switch 130 to shunt the transformer and may be enabled by opening the switch 130. In various embodiments, the switch 130 may be implemented by a transistor external to a controller 140. In various embodiments, the switch 130 may be implemented by a pin of the controller 140 switching between hi-impedance state and low output. Because high frequency signals from external sources or from a grounded neutral fault can appear or disappear in the middle of a measuring interval, the procedure of enabling and disabling the grounded neutral transformer 114 core procedure should be repeated more than once, such as twice or more than twice. Such operations will be described in more detail in connection with FIGS. 2 and FIG. 6.

[0032] Further, in various embodiments, if it is determined that the high frequency component is not a grounded neutral fault, the controller 140 and the peak detector / averaging block 142, or digital sampling by the controller 140, can determine the level of the high frequency component based on frequency measurements and decide whether to trigger the circuit interrupt.

[0033] In accordance with aspects of the present disclosure, in the example of FIG. 1, the frequency of the high frequency component signal OPAl out may be determined using a comparator 123 and a counter 125. The comparator 123 may operate to provide a particular indicationfor each cycle of a signal, and the counter 125 operates to track the number ofindications provided by the comparator 123. The comparator 123 may be set on a certain threshold to generate a transition when the signal at the output of OPA1 is changing. A voltage measurement block 144 in the controller 140 may measure the transitions, and the counter 125 counts these transitions. The controller 140 periodically reads and clear the counter 125 to determine whether there is any high frequency component and, if so, determine the frequency value of the high frequency component. Other types of comparators are contemplated to be within the scope of the present disclosure. In various embodiments, if a controller has sufficiently high processing capability and is capable ofPATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT) sampling OPAl_out at the Nyquist rate or higher (e.g., 6-20 kHz sampling rate), then the controller 140 may sample OPAl out and determine the frequency of OPAl out without the use of a comparator 123.

[0034] With continuing reference to FIG. 1, a controller 140 may reset the counter 125 periodically and read the value in the counter 125 on a timed basis to determine the number of cycles in the OPAl out signal over time and, thus, determine the frequency of the high frequency component signal OPAl out. For example, a 3-10 kHz signal has one cycle about every 0.1 to 0.333 milliseconds. In various embodiments, a controller may, for example, read and reset the counter 125 with power line frequency half-cycles or cycles, i.e., every 8.33 milliseconds or every 16.67 milliseconds. During each 8.33 millisecond period, a 3 kHz signal would exhibit 25 cycles and a 10 kHz signal would exhibit 83 cycles. Other timing for resetting the counter 125 are contemplated to be within the scope of the present disclosure.

[0035] Such an implementation for determining frequency of OPA 1 out is merely an example. Other embodiments are contemplated to be within the scope of the present disclosure. For example, in various embodiments, op amp OPAO 116 may be connected to a filter / peak detector / av eraging block 142 in the controller 140. In such embodiments, such functionalities would be provided in the controller 140, and the controller 140 may detect high frequency electrical faults. To illustrate such possible embodiments, FIG. 1 shows a dashed line connecting the op amp OPAO 116 and the block 142.

[0036] If the OPA0_out signal (having power line frequency component) is directly connected to an input of op-amp OPA1, there may be difficulty detecting higher frequency oscillations using the comparator 123 in the presence of a standing ground fault below the trip threshold (e.g., 4-6 mA). For example, a grounded neutral condition may occur when a ground fault below 4 mA exists. In this case, the comparator 123 may not correctly detect the output signal OPA0_out with the standing ground fault and a high frequency component on top of it. To minimize the effect of a standing fault on GN fault detection, a high pass filter or a bi-pass filter can be used to remove the low frequency component. In the simplest case, this may be a capacitor between the output of OPAO and the input of OPAl.

[0037] The GFCI device of FIG. 1 also includes a voltage reference circuit 118 that generates a voltage Vref. The voltage reference circuit 118 receives an input voltage signal having voltage Vdd from the power source 104 and includes one or more electrical components (e.g., shown inPATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT) 3-5) for generating Vref as function of Vdd. In various embodiments, Vref = Vdd / 2. In various embodiments, the voltage reference circuit 118 may provide Vref = 1.2V or Vref=1.35V, within the range 0 < Vref < Vdd. Examples of various embodiments will be described in connection with FIGS. 3-5. For now, it is sufficient to note that the power source 104 may be a source of power line disturbances, and it is beneficial to use a voltage regulator for the voltage reference circuit 118. A voltage regulator provides a stable voltage that is not dependent on Vdd deviations compared to a resistive divider, and the voltage reference comes up faster while the controller 140 is in reset (because it can be set to a voltage below the reset voltage of the controller 140). This alleviates some problems associated with power up transitions (e g., a GFCI in certain cases has to react to electrical faults in less the 24 milliseconds).

[0038] The block diagram of FIG. 1 is merely illustrative, and persons skilled in the art will recognize that the GFCI devices includes other components not shown in FIG. 1 or may include components different from those shown in FIG. 1. For example, certain components are illustrated in FIGS. 2-5. Also, certain components are described in U.S. Patent No. 9,276,393, which persons skilled in the art will understand, such as, without limitation, circuitry for circuit interruption (including a trip coil / solenoid) and various test, trip, and reset circuitry. Circuit interruption involves an actuator, such as a silicon controlled rectifier (SCR), Triac, or bipolar transistors, or MOSFETs. In various embodiments, the solenoid may be implemented as a holding relay. In various embodiments, the GFCI device may have a test button for initiating a manual test and for tripping the GFCI device in case of a successful test. In various embodiments, the GFCI device can be implemented with a reset lockout feature, in which the test button opens contact mechanically, and when the reset button is activated, a manual test is performed and contacts are closed only when the manual test is successful. In various embodiments, with a single-chip microcontroller solution, a GFCI device can be used with a holding relay, and the contacts can be closed on the holding relay only after a self-test or a manual test is successful. For example, a microcontroller GFCI can be used with contacts that are controlled by a solenoid. A solenoid opens contacts in case of an electrical fault, and closing the contacts again requires a manual “mechanical” input. There are different class of GFCIs - portable GFCIs: plug-in or panel mount GFCIs, such as Leviton Cat. Nos. GSRA1 or GSPA2. Such GFCIs have a holding relay. Those GFCIs, when plugged-in (e.g. powered), initiate a self-test, and close the contacts only if this selftest is successful, as described in U.S. Patent Application Publication No. US20220216687A1,PATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT) which is hereby incorporated by reference herein in its entirety. However, instead of using a two chip solution, as described in U.S. Patent Application Publication No. US20220216687A1, a single microcontroller GFCI can be used, such as a solution in accordance with aspects of the present disclosure.

[0039] Additionally, some of the blocks shown in FIG. 1 may be implemented by discrete electrical components (e.g., discrete capacitors) and some components may be implemented in a controller. For example, the op-amps OP AO and OPA1 may not be discrete components and may be provided within the controller 140. The op-amps OP A0 and OPA1 may have analog gain circuits, which persons skilled in the art will recognize.

[0040] Therefore, in accordance with the description above, a ground fault detection circuit may be implemented by the differential transformer 112, the op amp 116, and other components connecting such devices. The controller 140 may process a signal of the ground fault detection circuit (e.g., OPAO out) to detect a ground fault. The differential transformer is just one example component of a ground fault detection circuit. A grounded neutral fault detection circuit may be implemented by the differential transformer 112, the op amp 116, the high pass filter / op amp 122, the resonant circuit 120, the grounded neutral transformer 114, and other components connecting such devices. The controller 140 may process a signal of the grounded neutral fault detection circuit (e.g., OPAl out) to detect a grounded neutral fault. The grounded neutral transformer is just one example component of a grounded neutral fault detection circuit. Other implementations of a ground fault detection circuit and / or of a grounded neutral fault detection circuit, as well as other corresponding implementations of the feedback loop, are contemplated. In various embodiments, if it is desirable to detect high frequency ground faults, which at high levels are dangerous to the human body, OPAl out may be filtered using filters representative of human body models, and that output may be processed / conditioned with analog averaging / peak detection circuits, and then that output may be digitized by an ADC converter, and then a controller 140 may use the digitized samples to determine whether the high frequency signals are a high frequency ground fault that is dangerous based on the frequency indicated by the digitized samples. Such and other variations will be understood by persons skilled in the art and are within the scope of the present disclosure.

[0041] FIGS. 2-5 will now be described below. Generally, FIG. 2 shows an example of a controller, and FIGS. 3-5 show examples of the voltage reference circuit 118 of FIG. 1.PATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT)

[0042] Referring to FIG. 2, there is shown a diagram of an example of a controller 200 that may be used in the GFCI device (e.g., controller 140 of FIG. 1). In various embodiments, the controller 200 may be a microcontroller from Texas Instruments, Inc. identified by numbers MSPM0L13xx, where xx may be 03, 04, 05, or 06. Information on such microcontrollers are available at: https: / / www.ti.com / microcontrollers-mcus-processors / arm-based-microcontrollers / arm-cortex-mO-mcus / products.html. The data sheets of all such controllers are hereby incorporated by reference herein in their entirety. In various embodiments, the controller 200 may not be a Texas Instruments, Inc. microcontroller and may be any other controller.

[0043] In FIG. 2, the illustrated controller is not shown with pin labels, but pin labels are shown in FIG. 1 and in FIGS. 3-5. Some examples of PIN labels include, without limitation, OPA0 1N+, OPAO IN-, OP AO OUT, OPA1 IN+, OPA1 IN-, OPA1 OUT, C0MP IN+, COMP IN-, COMP OUT, LINE MONITOR, TEST GFCI, BUTTON, TRIP, and SCR FIRE, among other possible pin labels. The appearance of a pin label in such figures indicates that they are connected to a corresponding pin in the controller 200 of FIG. 2.

[0044] Generally, the controller 200 may include one or more analog-to-digital converters (ADC) that sample and convert analog signals to digital values. For example, in various embodiments, the controller 200 may include ADCs for sampling the Vref signal, the LPF out signal, and the OPAl out signal in FIG. 1. The controller 200 may also include one or more opamps. For example, in various embodiments, the controller 200 may include both op-amp OP AO 116 and op-amp OPA1 122 of FIG. 1. In various embodiments, the controller 200 may implement digital filters for the low pass filter 121 and the high pass filter in block 122 of FIG. 1.

[0045] The controller 200 may perform other operations relating to GFCI operation, which persons skilled in the art will recognize. For example, some operations are described in U.S. Patent No. 9,276,393, which was incorporated by reference above. Various aspects and operations the controller 200 are described below.

[0046] In various embodiments, the controller 200 may include a processing unit 202; at least one memory unit 204, which may include one more types of memory, such as RAM, ROM, flash memory, EEPROM, etc.; a plurality of input / output pins 206; a clock unit CLK 208; op-amp(s) 116, 122; ADC(s) 227; and software or firmware modules 220 which include a series of programmable instructions that are executable by the processing unit 202. The series of programmable instructions can be stored on a processor-readable medium accessible by thePATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT) processing unit 202, such as memory unit 204, for performing the functions disclosed herein and to achieve a technical effect in accordance with the disclosure.

[0047] In accordance with aspects of the present disclosure, the controller 200 may include a voltage measurement circuit (e.g., 144, FIG. 1) that measures voltage levels and zero cross timing. Measured voltage levels can be used to calculate simulated test fault current used for self-test or manual test of the GFCI device (discussed below), so that a test fault threshold can be adjusted for, e.g., low voltage operations or when the GFCI device is used with a generator that goes into “sleep” mode when a load is not present. Such adjustments prevent test failures during low voltage operations or when the GFCI device is used with a generator that goes into “sleep” mode when a load is not present. Measuring zero crossing timing can also be used to detect “sleep” modes of generators and be used to adjust measurements based on real power line frequencies other than 60 Hz. In various embodiments, the controller 200 may perform periodic self-test by applying a simulated fault and measuring the response on the output of OP A0. Because operating voltage can vary significantly (for example, in generators going to sleep mode when load is not present), measuring the operating voltage allows for adjustments to avoid self-test failures due to low operating voltage conditions. In various embodiments, when operating voltage decreases below the trip solenoid capabilities, the self-test can be temporarily stopped.

[0048] The software / firmware modules 220 include several modules that may be discrete from one another or integrated together. The modules include a sampler module 224, a gain determination module 226, a test routine control module 228, an op-amp offset compensation module 230, an op-amp saturation compensation module 232, a reference voltage Vref correction module 234, an RMS determination module 236, and a fault determination module 238.

[0049] The sampler module 224 consults CLK 208 and controls sampling measured values, such as Vref, LPF out, and OPAl out, among others. In various embodiments, the sampling module 222 controls sampling to occur approximately every 255 jus, or approximately 32 times per 60 Hz half cycle. In various embodiments, the sampling module 222 may control sampling to occur at or above a Nyquist rate of the expected frequency of OPAl out, e.g., at least 12-14 kHz sampling rate.

[0050] The gain determination module 226 receives a digitized form of output from the output terminal of op-amp 116 and performs a gain calculation in software by applying one or more equations that use one or more gain constants. The gain determination module 226 is calibrated byPATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT) adjusting the one or more gain constants for the calculation to achieve the requisite sensitivity, as per requirements set by regulations, e.g., UL Standards, to sense ground faults within a predetermined range, which in the present example is 4-6 mA. The required sensitivity is achieved by selection of resistor components in a gain circuit (which persons skilled in the art will understand) and selection of the software gain constants. The software gain constants are stored in memory unit 224, e.g., in flash memory or EEPROM. Examples of gain circuits and resistor components are described in U.S. Patent No. 9,276,393.

[0051] Accordingly, by combining software calculations with the use of analog components in a gain circuit, adjustments for achieving the required sensitivity may be made to the software gain constants without adjusting any hardware components. The calibration of the software gain constants may be performed at predetermined intervals or in response to an event, by performing an automatic diagnostic routine.

[0052] Test routine control module 228 may initiate a test routine or be activated by an external event, such as activation of test button. When a test routine is initiated by manual activation of test button, the op-amp offset compensation module 226 may be activated. Operational amplifiers typically have an associated input offset voltage which is amplified along with the input signal, causing an error that is significant in the GFCI device because of the small differential voltage that is being amplified. Input offset voltage may further be influenced by ambient temperature. The opamp offset compensation module 230 compensates for the input offset voltage by measuring the differential voltage during a test routine that was initiated by activation of test button which opens contacts and excludes the possibility of an actual fault condition.

[0053] When op-amp 116 is saturated (which may be indicated when ADC 227 reads a maximum or minimum value), op-amp saturation compensation module 232 compensates by a predetermined factor. For smaller ground fault signals, this will accelerate response of the GFCI device to fault conditions without compromising noise immunity, with the ability to satisfy timing requirements for interrupting the circuit.

[0054] Vref correction module 234 may implement compensation for power source disturbances, which will be described below in connection with FIG. 4. For now, it is sufficient to note that if Vref is not constant and may meaningfully vary, then computations involving or based on Vref should take such variances into account. For example, Vref may be sampled at the same time and the same timing as other signals, and the sampled values of Vref may be used toPATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT) compensate the sampled values of the other signals. Further details are described in connection with FIG. 4.

[0055] RMS determination module 236 determines an RMS value for measured signal properties for a signal, such as, for example, the OPAl out signal and / or a signal output of the differential transformer 112. The software modules 220 may determine RMS values that correspond to measured values and / or threshold values when performing calculations and making determinations, e.g., instead of average rectified current values, etc. UL requirements specify trip levels based on RMS rather than average current, thus providing guidelines that can be used by devices for a wide variety of applications in which power line voltage is not necessarily provided as a sine wave, such as in electrical power conversion applications. Conventionally, a GFC1 device must be specially calibrated for use with such applications, because a conventional GFCI device is designed to measure average or peak current due to the power line voltage being a sine wave. RMS determination module 236, however, can determine the RMS value for an input wave of any shape by applying an appropriate algorithm without the need for calibration. That is, the RMS determination module 236 applies RMS calculated values to the input signal. In accordance with aspects of the present disclosure, the RMS determination module 236 may determine average or real RMS values of various signals (e.g., LPF out signal, OPAl out signal) for use in determining presence of ground faults and / or grounded neutral faults. Such an approach may ensure proper trip levels when the GFCI device is used in noise environments or with non-sinusoidal power (e.g., generated by power converters).

[0056] Circuit interruption is triggered by fault determination module 238. As mentioned above, persons skilled in the art will understand how to implement fault determination. An example is disclosed in U.S. Patent No. 9,276,393, which was incorporated by reference above. Furthermore, the fault determination module 238 may perform the operations of the present disclosure for distinguishing an actual grounded neutral fault from high frequency signals generated by a load. In accordance with aspects of the present disclosure, such operations include causing the controller 200 to enable and disable the grounded neutral fault detection circuit (e.g., by opening and closing switch 130) and to determine whether the OPAl_out signal includes high frequency signals when the grounded neutral fault detection circuit is enabled and when it is disabled. In various embodiments, a controller 200 may disable the grounded neutral fault detection circuit by closing a switch (130, FIG. 1) to shunt the grounded neutral transformer 114.PATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT) The switch may be controlled by a pin of the controller 200. In various embodiments, a controller 200 may enable the grounded neutral fault detection circuit by opening the switch 130 and disengaging the shunt. In the simplest case, the switch may be a transistor, such as a MOSFET, which persons skilled in the art will recognize. In various embodiments, the controller 200 may enable and disable the grounded neutral detection circuit by disconnecting the OPA1 output or the resonant circuit output in the positive feedback loop. In various embodiments, the controller 200 may enable and disable the grounded neutral transformer 114 based on the timing of a power line frequency, e.g., 60 Hz, such as based on the power line frequency, a multiple of the power line frequency (e.g., 120 Hz), or a fraction of the power line frequency (e.g., 30 Hz). For example, the controller 200 may alternate enabling the differential transformer 112 for one cycle and disabling the grounded neutral transformer 114 for one cycle. As another example, the controller 200 may alternate enabling the grounded neutral transformer 114 for one half-cycle and disabling the grounded neutral transformer 114 for one half-cycle. Further details are described in connection with FIG. 5.

[0057] The various constants for algorithms stored in the GFCI device can be calibrated during manufacturing. The constants can be stored within the controller 200, such as, for example, within flash memory or an EEPROM of the controller 200, and / or may be stored within non-volatile memory (not shown) outside the controller 200. The constants can be used to compensate for example, for differences in permeability of the magnetic core and / or number of turns of one or both of the transformers 112, 114, as well as variations in passive components. It is contemplated that calibration is performed for different temperatures and the corresponding constants for various temperatures in a particular temperature range stored in the GFCI device.

[0058] The GFCI device may be tested via a manually initiated test or an automatically initiated self-test. When performing a self-test, the test routine control module 228 controls a test circuit to generate a simulated ground fault. Persons skilled in the art will understand a test circuit, and an example is described in U.S. Patent No. 9,276,393. If the simulated ground fault is sensed, the GFCI device continues normal operation. However, if the simulated ground fault is not sensed, the GFCI device remains in a tripped condition or triggers a tripped condition so that power will not be provided to the load 106, and / or triggers an alarm. For a manual test, test button is actuated and a BUTTON signal is transmitted. Test routine control module 228 receives the BUTTON signal and transmits a control signal to activate test circuit for generating a simulated ground fault.PATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT)

[0059] FIG. 2 is merely illustrative and variations are contemplated to be within the scope of the present disclosure.

[0060] FIG. 3 and FIG. 4 show examples of a voltage reference circuit and will now be described. In various embodiments, the voltage reference circuit of FIG. 3 and FIG. 4 implements the voltage reference circuit 118 of FIG. 1. In various embodiments, the voltage reference circuit may be an internal module of the controller of FIG. 1 or FIG. 2 or may be implemented by a field-programmable gate array (FPGA).

[0061] Referring now to FIG. 3, there is shown an example of a voltage reference circuit that is implemented using a low-dropout (LDO) regulator 310. The example of FIG. 3 may be used for the voltage reference circuit 118 of FIG. 1. In various embodiments, the LDO regulator 310 may be a component from Texas Instruments, Inc. or may be a component from other integrated circuit (IC) providers. The voltage reference circuit of FIG. 3 may provide a stable 1 ,2V reference voltage, as shown in FIG. 3. In various embodiments, the voltage reference circuit of FIG. 3 may provide other reference voltages, such as 1.35V, for example. A voltage reference produced by a LDO regulator is more stable and is less susceptible to power source disturbances.

[0062] Referring now to FIG. 4, there is shown an example of a voltage reference circuit that is implemented using a resistor divider with some degree of protection for higher frequency power source disturbances. In comparison to the LDO regulator of FIG. 3, the resistor divider is cheaper to implement but is more susceptible to power source disturbances. The capacitor C22 has an impedance that is lower for higher frequencies and serves as a shunt to ground for higher frequency disturbances in the power source voltage Vdd. The voltage reference circuit of FIG. 4 may be susceptible to power source disturbances at certain frequencies. Accordingly, if the resistor divider is used to provide a reference voltage, the GFCI device would need to account for such power source disturbances. For example, if power source disturbances introduce an undesirable frequency signal into the reference voltage, the undesirable frequency signal could also affect the OPAl out signal and could be misinterpreted as a grounded neutral fault. In accordance with aspects of the present disclosure, to address this disturbance, an ADC may sample the Vref signal of FIG. 4 at the same time and the same timing (e.g., same sampling rate) that OPAl_out is sampled, and may compensate the OPAl out samples by subtracting (or otherwise compensating for) the Vref samples. Similarly, for any other signals that may be affected by variations in Vref due to power source disturbances, Vref may be sampled at the same time and the same timing that such otherPATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT) signals are sampled, and the Vref sample values may be used to compensate the other signal samples.

[0063] The voltage reference circuits of FIGS. 3 and 4 are merely examples. Other voltage reference circuits are contemplated to be within the scope of the present disclosure.

[0064] Accordingly, example components and circuitry for a GFCI device have been described above. As described above, a controller may distinguish an actual grounded neutral fault from high frequency signals generated by loads.

[0065] FIG. 5 shows a flow diagram of example operations of a GFCI device. The operations of FIG. 5 may be performed by the controller 200 of FIG. 2.

[0066] At block 510, the operation involves causing a grounded neutral (GN) fault detection circuit to be enabled, where the GN fault detection circuit is configured to provide a first signal in response to a GN fault on a neutral conductor, and where the first signal has a frequency above a power line frequency (e.g., 60 Hz). For example, the grounded neutral fault detection circuit may include the grounded neutral transformer 114 of FIG. 1, and the first signal provided by the grounded neutral fault detection circuit may be the resonant signal in the windings of the grounded neutral transformer 114. The resonant signal may have a frequency in the range of 3-10 kHz, for example, or in another frequency range above the power line frequency. The grounded neutral fault detection circuit (e.g., grounded neutral transformer, etc.) may be enabled in the manner described above herein, e.g., opening the switch 130, FIG. 1.

[0067] At block 520, the operation involves detecting a second signal while the GN fault detection circuit is enabled, where the second signal has a frequency in a predetermined frequency range above the power line frequency. For example, the OPAl out signal (the second signal) may have a frequency above the power line frequency, such as in the 3-10 kHz range, or in another frequency range above the power line frequency. Thus, the predetermined frequency range may be a frequency range indicative of a grounded neutral fault, such as 3-10 kHz, or greater than 3 kHz, or another frequency range indicative of a grounded neutral fault.

[0068] At block 530, the operation involves causing the GN fault detection circuit to be disabled. The grounded neutral fault detection circuit (e.g., grounded neutral transformer, etc.) may be disabled in the manner described above herein, e.g., closing the switch 130, FIG. 1.

[0069] At block 540, the operation involves, based on detecting no frequency in the predetermined frequency range above the power line frequency while the GN fault detection circuitPATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT) is disabled, causing a load to be disconnected. As described above herein, if the OPAl_out signal has a frequency in the predetermined frequency range (above the power line frequency) while the grounded neutral fault detection circuit is enabled and while the grounded neutral fault detection circuit is disabled, then it can be determined that the amplified signal is caused by high frequency noise from a load. But if the OPAl out signal has a frequency in the predetermined frequency range (above the power line frequency) while the grounded neutral fault detection circuit is enabled but not while the grounded neutral fault detection circuit is disabled, then it can be determined that the amplified signal is caused by an actual grounded neutral fault. The grounded neutral fault detection circuit (e.g., grounded neutral transformer, etc.) may be enabled and disabled in the manner described above herein, e.g., opening or closing the switch 130, FIG. 1.

[0070] FIG. 5 is illustrative, and variations are contemplated to be within the scope of the present disclosure. For example, in various embodiments, the operations may include operations other than those shown in FIG. 5. In various embodiments, the operations may not include every operation shown in FIG. 5. In various embodiments, the operations may have a different order than those shown in FIG. 5. Such and other embodiments are contemplated to be within the scope of the present disclosure.

[0071] FIG. 6 shows a flow diagram of another example of operations of a GFCI device. The operations of FIG. 6 may be performed by the controller 200 of FIG. 2.

[0072] At block 610, the operation involves obtaining an amplified signal in a positive feedback loop, where the feedback loop includes (i) a grounded neutral transformer configured to provide a first signal in response to a grounded neutral fault on a neutral conductor where the first signal has a first frequency range, and (ii) an amplifier configured to amplify a second signal in the positive feedback loop to provide the amplified signal. The feedback loop may be the feedback loop described in connection with FIG. 1. For example, the grounded neutral fault detection circuit may include the grounded neutral transformer 114 of FIG. 1, and the first signal provided by the grounded neutral fault detection circuit may be the resonant signal in the windings of the grounded neutral transformer 114. The resonant signal may have a frequency in the range of 3-10 kHz, for example, or in another frequency range. The frequency range of the resonant signal would be the first frequency range. The amplifier may be the op-amp OPA1 of FIG. 1, and the amplified signal may be OPAl out. The feedback loop is not limited to the example of FIG. 1, however, and other implementations are within the scope of the present disclosure.PATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT)

[0073] At block 620, the operation involves determining whether the amplified signal has an amplified-signal frequency in the first frequency range while the grounded neutral fault detection circuit is enabled and while the grounded neutral fault detection circuit is disabled. For example, the OPAl out signal may have a frequency in the first frequency range, such as 3-10 kHz, or another frequency range. As described above herein, if the OPAl out signal has a frequency in the first frequency range while the grounded neutral fault detection circuit is enabled and while the grounded neutral fault detection circuit is disabled, then it can be determined that the amplified signal is caused by high frequency noise from a load. But if the OPAl out signal has a frequency in the first frequency range while the grounded neutral fault detection circuit is enabled but not while the grounded neutral fault detection circuit is disabled, then it can be determined that the amplified signal is caused by an actual grounded neutral fault. The grounded neutral fault detection circuit (e.g., grounded neutral transformer, etc.) may be enabled and disabled in the manner described above herein, e.g., opening or closing the switch 130, FIG. 1.

[0074] At block 630, the operation involves, based on determining that the amplified signal has an amplified-signal frequency in the first frequency range while the GN fault detection circuit is enabled but not while the GN fault detection circuit is disabled, causing an interrupter to interrupt current flow through the neutral conductor.

[0075] FIG. 6 is illustrative, and variations are contemplated to be within the scope of the present disclosure. For example, in various embodiments, the operations may include operations other than those shown in FIG. 6. In various embodiments, the operations may not include every operation shown in FIG. 6. In various embodiments, the operations may have a different order than those that shown in FIG. 6. Such and other embodiments are contemplated to be within the scope of the present disclosure.

[0076] FIG. 7 shows a flow diagram of an example of various operations of a GFCI device. The operations of FIG. 7 address situations where external radio frequency (RF) or electromagnetic interference (EMI) may subject the circuitry of FIG. 1 to high frequency noise. The operations of FIG. 5 and FIG. 6 detect an actual grounded neutral (GN) fault based on detecting no frequency in a predetermined frequency range above the power line frequency while the GN fault detection circuit is disabled (FIG. 5, 540) or based on determining that an amplified signal (e.g., FIG. 1, OPAl out) has an amplified-signal frequency in the first frequency range while the grounded neutral fault detection circuit is enabled but not while the grounded neutralPATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT) fault detection circuit is disabled (FIG. 6, 630). When the circuitry of FIG. 1 is subject to high frequency noise from external RF or EMI, the operations of FIG. 5 and FIG. 6 may not be able to detect grounded neutral (GN) faults because high frequency signals (caused by the external RF interference or EMI) may be present in the circuitry when the GN fault detection circuit is enabled and when the GN fault detection circuit is disabled. The operations of FIG. 7 address interference from external RF or EMI. The operations of FIG. 7 may be performed by the controller 200 of FIG. 2.

[0077] Blocks 510-530 of FIG. 7 are the same as blocks 510-530 of FIG. 5. They are repeated below for completeness. In various embodiments, the operations of FIG. 6 may be implemented in the operation of FIG. 7 instead of blocks 510-530.

[0078] In FIG. 7, at block 510, the operation involves causing a grounded neutral (GN) fault detection circuit to be enabled, where the GN fault detection circuit is configured to provide a first signal in response to a GN fault on a neutral conductor, and where the first signal has a frequency above a power line frequency (e.g., 60 Hz). For example, the grounded neutral fault detection circuit may include the grounded neutral transformer 114 of FIG. 1, and the first signal provided by the grounded neutral fault detection circuit may be the resonant signal in the windings of the grounded neutral transformer 114. The resonant signal may have a frequency in the range of 3-10 kHz, for example, or in another frequency range above the power line frequency. The grounded neutral fault detection circuit (e.g., grounded neutral transformer, etc.) may be enabled in the manner described above herein, e.g., opening the switch 130, FIG. 1.

[0079] At block 520, the operation involves detecting a second signal while the GN fault detection circuit is enabled, where the second signal has a frequency above the power line frequency. For example, the OPAl out signal (the second signal) may have a frequency above the power line frequency, such as in the 3-10 kHz range, or in another frequency range above the power line frequency.

[0080] At block 530, the operation involves causing the GN fault detection circuit to be disabled. The grounded neutral fault detection circuit (e.g., grounded neutral transformer, etc.) may be disabled in the manner described above herein, e g., closing the switch 130, FIG. 1.

[0081] At block 740, the operation involves adjusting a sensitivity used for both (i) detecting oscillations in the second signal while the GN fault detection circuit is enabled, and (ii) detecting noise above the power line frequency while the GN fault detection circuit is disabled. A highPATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT) sensitivity can better detect oscillations in the second signal (in a predetermined frequency range) while the GN fault detection circuit is enabled, but will also more easily detect noise frequency (in the predetermined frequency range) above the power line frequency while the GN fault detection circuit is disabled, leading to an inability or reduced ability to distinguish between noise and a grounded neutral fault. In contrast, a low sensitivity can reduce or avoid detection of noise frequency (in the predetermined frequency range) above the power line frequency while the GN fault detection circuit is disabled, but will also reduce or miss detection of oscillations (in the predetermined frequency range) in the second signal while the GN fault detection circuit is enabled. By adjusting the sensitivity to an appropriate level, it is possible to achieve desirable detection of oscillations (in the predetermined frequency range) in the second signal while the GN fault detection circuit is enabled, as well as avoid detection of noise frequency (in the predetermined frequency range) above the power line frequency while the GN fault detection circuit is disabled. As mentioned above, this operation addresses situations where external radio frequency (RF) or electromagnetic interference (EMI) may subject the circuitry of FIG. 1 to high frequency noise such that high frequency signals (caused by the external RF interference or EMI) may be present in the circuitry when the GN fault detection circuit is disabled. The adjusting the sensitivity may be performed by blocks 742 and 744.

[0082] At block 742, the operation involves decreasing the sensitivity based on detecting, while the GN fault detection circuit is disabled, noise frequency in the predetermined frequency range above the power line frequency. For example, while the GN fault detection circuit is disabled at block 530, if noise frequency in the predetermined frequency range above the power line frequency is detected, then the operation of block 742 can decrease sensitivity to attenuate detection of noise above the power line frequency.

[0083] At block 744, the operation involves increasing the sensitivity based on, while the GN fault detection circuit is enabled, not detecting any oscillations in the predetermined frequency range in the second signal. Although the operation of block 742 operates to decrease sensitivity for detecting noise, the decreased sensitivity also decreases sensitivity for detecting oscillations in the second signal (e.g., OPAl_out signal) while the GN fault detection circuit is enabled. The operation of block 744 operates to increase sensitivity if no oscillations in the predetermined frequency range are detected in the second signal while the GN fault detection circuit is enabled (e.g., enabled at block 510.)PATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT)

[0084] The operations shown in FIG. 7 may be repeated. In embodiments, in repeating the operations of FIG. 7, the operation of block 742 may be performed to decrease sensitivity as long as noise frequency in the predetermined frequency range above the power line frequency is detected when the GN fault detection circuit is disabled (e.g., at block 530). In embodiments, in repeating the operations of FIG. 7, the operation of block 744 may be performed to increase sensitivity as long as oscillations in the predetermined frequency range are not detected in the second signal when the GN fault detection circuit is enabled (e.g., at block 510). By cooperating together, the operations at block 742 and 744 will balance detecting oscillations while the GN fault detection circuit is enabled with attenuating detection of noise while the GN fault detection circuit is disabled. The following will describe examples of scenario.

[0085] A first scenario relates to situations when there is no GN fault, but there is external radio frequency (RF) or electromagnetic interference (EMI) that subjects the circuitry of FIG. 1 to high frequency noise such that high frequency signals (caused by the external RF interference or EMI) are present in the circuitry while the GN fault detection circuit is disabled and while the GN fault detection circuit is enabled. In this scenario, the operation of block 742 will decrease the sensitivity. During the time when the noise frequency in a predetermined frequency range is still detectable, the noise frequency will be present in the second signal while the GN fault detection circuit is enabled, so the operation of block 744 will not increase the sensitivity. Therefore, the operation of block 742 will operate to decrease the sensitivity until such point when the noise frequency in the predetermined frequency range is no longer detected while the GN fault detection circuit is disabled. At that point, the operation of block 744 will no longer detect the noise frequency in the predetermined frequency range in the second signal while the GN fault detection circuit is enabled and, therefore, will increase the sensitivity. At that point, the operations of blocks 742 and 744 will successively decrease and increase the sensitivity, respectively.

[0086] A second scenario relates to a GN fault that occurs after the first scenario. After the first scenario, after the operation of block 742, the sensitivity is decreased such that the noise frequency in a predetermined frequency range (due to external RF / EMI) will not be detected while the GN fault detection circuit is enabled. In the second scenario, because of amplification (e.g., by OPA1), it is assumed that the amplitude of the oscillations, in the predetermined frequency range in the second signal (caused by the GN fault), are greater than the amplitude of the noise caused by the external RF / EMI. Therefore, when the GN fault occurs, the oscillation in the predeterminedPATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT) frequency range in the second signal (caused by the GN fault) will be detected while the GN fault detection circuit is enabled, and operation 744 will not increase the sensitivity. When the GN fault detection circuit is disabled, the sensitivity is still at a level that will not detect the noise frequency in the predetermined frequency range. Therefore, the controller would determine that a GN fault has occurred based on detection of oscillations in the predetermined frequency range in the second signal while the GN fault detection circuit is enabled but not while the GN fault detection circuit is disabled.

[0087] A third scenario relates to a GN fault that beings at the same time that external RF or EMI subjects the circuitry of FIG. 1 to high frequency noise. Again, because of amplification (e.g., by OPA1), it is assumed that the amplitude of the oscillations, in a predetermined frequency range in the second signal (caused by the GN fault), are greater than the amplitude of the noise caused by the external RF / EMI. In the third scenario, because the GN fault is occurring, the oscillation in the predetermined frequency range in the second signal (caused by the GN fault) will be detected while the GN fault detection circuit is enabled, and operation 744 will not increase the sensitivity. During the time when the noise frequency in the predetermined frequency range is still detected while the GN fault detection circuit is disabled, the operation of block 742 will operate to decrease the sensitivity until such point when the noise frequency in the predetermined frequency range is no longer detectable. At that point, the third scenario would turn into the second scenario.

[0088] In operations 742 and 744, the sensitivity may be adjusted (increased or decreased) in various ways, such as, for example, by adjusting a gain of an amplifier (e.g., OPA1 of FIG. 1), adjusting a threshold of a comparator (e.g., comparator 123, FIG. 1), adjusting a parameter of a filter (e.g., high pass filter or bi-pass filter 122, FIG. 1) , adjusting a parameter of a resonant circuit (e.g., resonant circuit 120, FIG. 1), or switching number of turns in a neutral core (e.g., neutral core in transformer 114, FIG. 1). Such and other ways of adjusting sensitivity are contemplated to be within the scope of the present disclosure.

[0089] FIG. 7 is illustrative, and variations are contemplated to be within the scope of the present disclosure. For example, in various embodiments, the operations may include operations other than those shown in FIG. 7. In various embodiments, the operations may not include every operation shown in FIG. 7. In various embodiments, the operations may have a different order than those that shown in FIG. 7. Such and other embodiments are contemplated to be within the scope of the present disclosure.PATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT)

[0090] Various aspects and / or embodiments are now described below.

[0091] In various aspects and / or embodiments, an input of the microcontroller (e.g., a pin) may be used for enabling and disabling Grounded Neutral (GN) oscillation. For example, a pin of the controller can be configured to enable and disable the GN fault detection circuit. In various aspects of embodiments, the pin of the controller may be configured to disable the GN fault detection circuit by, at least one of: directly shorting a GN core, indirectly shorting the GN core by using an intermediate circuit, directly disconnecting the GN core from the GN fault detection circuit, or indirectly disconnecting the GN core from the GN fault detection circuit by using an intermediate circuit.

[0092] In various aspects and / or embodiments, when there is noise on a branch circuit, an adaptive GAIN on OPA1 can be implemented to be adaptive using the controller options (e.g., options available in TI MSPM0L parts, or with external components if the amplifier is external). When feedback is disabled by disabling (e.g., shorting the GN core, e.g., using a controller pin, or with external transistor / MOSFET) the a high frequency signal can still be detected. The gain of OPA1 can be reduced to eliminate external high frequency noise while enabling GN detection. For example, a controller can be configured to, in response to noise within a predetermined frequency range on a branch circuit, perform adjustments to an adaptive gain of an amplifier, where the adjustments are configured to: permit determining whether an amplified signal has an amplified-signal frequency within the predetermined frequency range above the power line frequency while the GN fault detection circuit is enabled, and reduce, while the GN fault detection circuit is enabled, noise effects resulting from the noise on the branch circuit.

[0093] In various aspects and / or embodiments, when a circuit interrupter is used as equipment protection device (e.g., GFPE) or as the part of an arc fault circuit interrupt (AFCI), it has higher level of detection threshold, for example, 30 ma (milliamps). To test those devices, a higher level of the test current may be needed. If such current is derived from power line using a resistor, the resistor should have a higher power rating. In addition, the power supply would need to have higher capacity. These higher requirements may be drawbacks and may be avoided by changing the gain on OP A0 under control of a controller. During a manual test, the gain can be increased and a small current can be used for a manual test. Another approach is to use a small current boost gain on OPA1 and measure the test response on output of OPA1. For example, a circuit interrupting device can be an equipment protection device (GFPE) or an arc-fault circuit interrupting (AFCI) device,PATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT) and a controller can be configured to, in response to a manual test of the circuit interrupting device, use a smaller test current for the manual test by performing at least one of: increase the gain of the second amplifier during the manual test, or use a small-current boost gain of the second amplifier during the manual test and measuring a test response on the second amplified signal.

[0094] In various aspects and / or embodiments, an adaptive gain can be used to keep a printed circuit board (PCB) and components for both GFCI and GFPE devices the same, and the functionality can be configured during manufacturing. For example, a circuit interrupting device can be an equipment protection device (GFPE) or a ground-fault circuit interrupting (GFCI) device, and by implementing adaptive gain in an amplifier, components of the circuit interrupting device are the same whether the circuit interrupting device is a GFPE or a GFCI device.

[0095] In various aspects and / or embodiments, a bandpass filter can be introduced between OP A0 and OPAl. To measure the ground fault signal output of OPA1 connected to the low pass filter, the output of the low pass filter is sampled by a controller to identify ground fault value. In addition, the output of the OP A0 connected to the bandpass filter serves several purposes. At low frequences, it filters out the power line frequency signal, which helps the comparator with the DC threshold to correctly react to the high frequency signals. The high frequency part of the bandpass filter filters out the switching noise of OP A0 (when switching amplifier is used) and filters out the high frequency noise outside of the possible band of GN oscillations. When the amplifier is inside the controller, the bandpass filter can have original implementation and does not jeopardize gain control adaptive feature of OPAl . For example, a circuit interrupting device may include: a ground fault detection circuit configured to provide a third signal in response to a first signal and in response to a ground fault on a phase conductor and the neutral conductor; a second amplifier configured to amplify a fourth signal to provide a second amplified signal, where the fourth signal is based on the third signal; and a bandpass filter connected between an output of the second amplifier and an input of the first amplifier. The bandpass filter may be configured to: filter out power line frequency, filter out switching noise of the second amplifier, and filter out the high frequency noise outside of the predetermined frequency range above the power line frequency.

[0096] In various aspects and / or embodiments, a controller can be configured to calculate rootmean-square (RMS) of a ground fault signal rather than average of crossing some threshold values. Instead of having a threshold based on lowest voltage level, a device can provide constant test signal. When the device measures power line voltage and adjusts the acceptance for test signalPATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT) based on current value of voltage, the function can be linear. This improves reliability and quality of testing / self-testing. For example, a controller, in response to a manual test of the circuit interrupting device, can be configured to calculate root mean square (RMS) voltage of a second signal to provide a constant test signal.

[0097] Further aspects and / or embodiments are shown in the following examples.

[0098] Example 1.1. A circuit interrupting device comprising:a grounded neutral (GN) fault detection circuit configured to provide a first signal in response to a GN fault on a neutral conductor, the first signal having a frequency in a predetermined frequency range above a power line frequency; anda controller configured to perform:detecting a second signal while the GN fault detection circuit is enabled, the second signal having a frequency within the predetermined frequency range above the power line frequency;causing the GN fault detection circuit to be disabled; andbased on detecting no frequency within the predetermined frequency range above the power line frequency while the GN fault detection circuit is disabled, causing a load to be disconnected.

[0099] Example 1.2. The circuit interrupting device of Example 1.1,wherein the GN fault detection circuit comprises an amplifier arranged to form a positive feedback loop within the GN fault detection circuit, the amplifier configured to amplify a signal in the positive feedback loop to provide an amplified signal as the second signal,wherein the controller is further configured to perform:determining whether the amplified signal has an amplified-signal frequency within the predetermined frequency range above the power line frequency while the GN fault detection circuit is enabled and while the GN fault detection circuit is disabled.

[0100] Example 1.3. The circuit interrupting device of Example 1.2, wherein in the determining whether the amplified signal has an amplified-signal frequency in the predetermined frequency range above the power line frequency while the GN fault detection circuit is enabled and while the GN fault detection circuit is disabled, the controller is configured to perform: causing the GN fault detection circuit to be enabled;PATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT) detecting a first frequency of the amplified signal while the GN fault detection circuit is enabled;causing the GN fault detection circuit to be disabled; anddetecting a second frequency of the amplified signal while the GN fault detection circuit is disabled.

[0101] Example 1.4. The circuit interrupting device of Example 1.3, wherein in the determining whether the amplified signal has an amplified-signal frequency in a predetermined frequency range above the power line frequency while the GN fault detection circuit is enabled and while the GN fault detection circuit is disabled, the controller is configured to, at least twice, cause the GN fault detection circuit to be enabled, detect the first frequency, cause the GN fault detection circuit to be disabled, and detect the second frequency.

[0102] Example 1.5. The circuit interrupting device of any one of Example 1.2- Example 1.4, further comprising:a comparator configured to provide an indication corresponding to each cycle of the amplified signal; anda counter configured to count the indication corresponding to each cycle of the amplified signal,wherein the controller is configured to read and reset the counter to determine the amplified-signal frequency.

[0103] Example 1.6. The circuit interrupting device of any one of Example 1.2- Example 1.5, further comprising:a ground fault detection circuit configured to provide a third signal in response to:the first signal, anda ground fault on a phase conductor and the neutral conductor;a second amplifier configured to amplify a fourth signal to provide a second amplified signal, wherein the fourth signal is based on the third signal; anda high pass filter connected between an output of the second amplifier and an input of the first amplifier.

[0104] Example 1.7. The circuit interrupting device of any one of Example 1.2- Example 1.6, further comprising:a voltage reference circuit configured to provide a reference voltage,PATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT) a first analog-to-digital converter (ADC), anda second ADC,the controller further configured to perform:sampling, by the first ADC, the amplified signal to provide first signal samples, wherein the sampling occurs at a sampling rate, andsampling, by the second ADC, the reference voltage to provide reference voltage samples, wherein the sampling by the second ADC occurs at the sampling rate.

[0105] Example 1.8. The circuit interrupting device of Example 1.9, wherein the controller is further configured to perform:compensating the first signal samples based on the reference voltage samples.

[0106] Example 1.9. The circuit interrupting device of any one of Example 1.2- Example 1.8, wherein the controller is further configured to perform:based on determining that the amplified signal has an amplified-signal frequency in the predetermined frequency range above the power line frequency while the GN fault detection circuit is enabled and while the GN fault detection circuit is disabled, repeat, for another iteration, the determining whether the amplified signal has an amplified-signal frequency in the predetermined frequency range above the power line frequency while the GN fault detection circuit is enabled and while the GN fault detection circuit is disabled.

[0107] Example 1.10. The circuit interrupting device of any one of claims Example 1.2-Example 1.9, wherein the controller is further configured to perform:adjusting a sensitivity for detecting oscillations in a predetermined frequency range in the second signal while the GN fault detection circuit is enabled, and for detecting noise frequency in the predetermined frequency range above the power line frequency while the GN fault detection circuit is disabled.

[0108] Example 1.11. The circuit interrupting device of Example 1.10, wherein in the adjusting the sensitivity, the controller is configured to perform:decreasing the sensitivity based on detecting noise frequency in the predetermined frequency range above the power line frequency while the GN fault detection circuit is disabled; andincreasing the sensitivity based on not detecting any oscillations in the predetermined frequency range in the second signal while the GN fault detection circuit is enabled.PATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT)

[0109] Example 1.12. The circuit interrupting device of Example 1.10 or Example 1.11, wherein the sensitivity is adjusted by one or more of:adjusting a gain of an amplifier,adjusting a threshold of a comparator,adjusting a parameter of a filter,adjusting a parameter of a resonant circuit, orswitching number of turns in a neutral core.

[0110] Example 1.13. The circuit interrupting device of any one of the preceding Examples, wherein the controller is configured to repeatedly alternate causing:the GN fault detection circuit to be enabled for one cycle of the power line frequency, andthe GN fault detection circuit to be disabled for one cycle of the power line frequency.

[0111] Example 1.14. The circuit interrupting device of any one of the preceding Examples, wherein the controller is configured to repeatedly alternate causing:the GN fault detection circuit to be enabled for one half-cycle of the power line frequency, andthe GN fault detection circuit to be disabled for one half-cycle of the power line frequency.

[0112] Example 1.15. The circuit interrupting device of any one of the preceding Examples, wherein a pin of the controller is configured to enable and disable the GN fault detection circuit.

[0113] Example 1.16 The circuit interrupting device of Example 1.15, wherein the pin of the controller is configured to disable the GN fault detection circuit by, at least one of:directly shorting a GN core,indirectly shorting the GN core by using an intermediate circuit,directly disconnecting the GN core from the GN fault detection circuit, orindirectly disconnecting the GN core from the GN fault detection circuit by using an intermediate circuit.

[0114] Example 1.17. The circuit interrupting device of any one of Example 1.2- Example 1.12, wherein the controller is further configured to, in response to noise within the predetermined frequency range on a branch circuit, perform adjustments to an adaptive gain of the amplifier, the adjustments configured to:PATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT) permit the determining whether the amplified signal has an amplified-signal frequency within the predetermined frequency range above the power line frequency while the GN fault detection circuit is enabled, andreduce, while the GN fault detection circuit is enabled, noise effects resulting from the noise on the branch circuit.

[0115] Example 1.18. The circuit interrupting device of Example 1.6,wherein the circuit interrupting device is an equipment protection device (GFPE) or an arc-fault circuit interrupting (AFCI) device,wherein the controller is configured to, in response to a manual test of the circuit interrupting device, use a smaller test current for the manual test by performing at least one of:increase the gain of the second amplifier during the manual test, or use a small-current boost gain of the second amplifier during the manual test and measuring a test response on the second amplified signal.

[0116] Example 1.19. The circuit interrupting device of any one of Example 1.2- Example 1.12,wherein the circuit interrupting device is an equipment protection device (GFPE) or a ground-fault circuit interrupting (GFCI) device,wherein, by implementing adaptive gain in the amplifier, components of the circuit interrupting device are the same whether the circuit interrupting device is a GFPE or a GFCI device.

[0117] Example 1.20. The circuit interrupting device of any one of Example 1.2- Example 1.5, wherein the amplifier is a first amplifier, the circuit interrupting device further comprising:a ground fault detection circuit configured to provide a third signal in response to the first signal and in response to a ground fault on a phase conductor and the neutral conductor;a second amplifier configured to amplify a fourth signal to provide a second amplified signal, wherein the fourth signal is based on the third signal; anda bandpass filter connected between an output of the second amplifier and an input of the first amplifier,wherein the bandpass filter is configured to:filter out power line frequency,filter out switching noise of the second amplifier, andPATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT) filter out the high frequency noise outside of the predetermined frequency range above the power line frequency.

[0118] Example 1.21. The circuit interrupting device of any one of the preceding Examples, wherein the controller, in response to a manual test of the circuit interrupting device, is further configured to calculate root mean square (RMS) voltage of the second signal to provide a constant test signal.

[0119] Example 2.1. A method in a circuit interrupting device comprising:causing a grounded neutral (GN) fault detection circuit to be enabled, the GN fault detection circuit configured to provide a first signal in response to a GN fault on a neutral conductor, the first signal having a frequency in a predetermined frequency range above a power line frequency;detecting a second signal while the GN fault detection circuit is enabled, the second signal having a frequency in the predetermined frequency range above the power line frequency;causing the GN fault detection circuit to be disabled; andbased on detecting no frequency in the predetermined frequency range above the power line frequency while the GN fault detection circuit is disabled, causing a load to be disconnected.

[0120] Example 2.2. The method of Example 2.1,wherein the GN fault detection circuit comprises an amplifier,wherein the amplifier is arranged to form a positive feedback loop within the GN fault detection circuit, the amplifier configured to amplify a signal in the positive feedback loop to provide an amplified signal,the method further comprising:determining whether the amplified signal has an amplified-signal frequency in the predetermined frequency range above the power line frequency while the GN fault detection circuit is enabled and while the GN fault detection circuit is disabled.

[0121] Example 2.3. The method of Example 2.2, wherein the determining whether the amplified signal has an amplified-signal frequency in the predetermined frequency range above the power line frequency while the GN fault detection circuit is enabled and while the GN fault detection circuit is disabled comprises:causing the GN fault detection circuit to be enabled;PATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT) detecting a first frequency of the amplified signal while the GN fault detection circuit is enabled;causing the GN fault detection circuit to be disabled; anddetecting a second frequency of the amplified signal while the GN fault detection circuit is disabled.

[0122] Example 2.4. The method of Example 2.3, where the determining whether the amplified signal has an amplified-signal frequency in the predetermined frequency range above the power line frequency while the GN fault detection circuit is enabled and while the GN fault detection circuit is disabled comprises:at least twice, causing the GN fault detection circuit to be enabled, detecting the first frequency, causing the GN fault detection circuit to be disabled, and detecting the second frequency.

[0123] Example 2.5. The method of any oneofExample 2.2- Example 2.4, further comprising:providing an indication corresponding to each cycle of the amplified signal; counting the indication corresponding to each cycle of the amplified signal to provide a count; andreading and resetting the count to determine the amplified-signal frequency.

[0124] Example 2.6. The method of any one of Example 2.2- Example 2.5, wherein the amplifier is a first amplifier, wherein the positive feedback loop further comprises:a ground fault detection circuit configured to provide a third signal in response to the first signal and in response to a ground fault on a phase conductor and the neutral conductor;a second amplifier configured to amplify a fourth signal to provide a second amplified signal, wherein the fourth signal is based on the third signal; anda high pass filter connected between an output of the second amplifier and an input of the first amplifier.

[0125] Example 2.7. The method of any one of Example 2.2- Example 2.6, further comprising:sampling, by a first analog-to-digital converter (ADC), the amplified signal to provide first signal samples, wherein the sampling occurs at a sampling rate, andsampling, by a second ADC, a reference voltage to provide reference voltage samples, wherein the sampling by the second ADC occurs at the sampling rate.PATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT)

[0126] Example 2.8. The method of Example 2.7, further comprising:compensating the first signal samples based on the reference voltage samples.

[0127] Example 2.9. The method of any one of Example 2.2- Example 2.8, further comprising:based on determining that the amplified signal has an amplified-signal frequency in the predetermined frequency range above the power line frequency while the GN fault detection circuit is enabled and while the GN fault detection circuit is disabled, repeating, for another iteration, the determining whether the amplified signal has an amplified-signal frequency in the predetermined frequency range above the power line frequency while the GN fault detection circuit is enabled and while the GN fault detection circuit is disabled.

[0128] Example 2.10. The method of any one of Example 2.2- Example 2.9, further comprising:adjusting sensitivity for detecting oscillations in the second signal while the GN fault detection circuit is enabled, and for detecting noise above the power line frequency while the GN fault detection circuit is disabled.

[0129] Example 2.11. The method of Example 2.10, wherein the adjusting the sensitivity comprises:decreasing the sensitivity based on detecting noise frequency in the predetermined frequency range above the power line frequency while the GN fault detection circuit is disabled; andincreasing the sensitivity based on not detecting any oscillations in the predetermined frequency range in the second signal while the GN fault detection circuit is enabled.

[0130] Example 2.12. The method Example 2.10 or Example 2.11, the adjusting the sensitivity comprises one or more of:adjusting a gain of an amplifier,adjusting a threshold of a comparator,adjusting a parameter of a filter,adjusting a parameter of a resonant circuit, orswitching number of turns in a neutral core.

[0131] Example 2.13. The method of any one of Example 2.1- Example 2.12, further comprising repeatedly alternate causing:PATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT) the GN fault detection circuit to be enabled for one cycle of the power line frequency, andthe GN fault detection circuit to be disabled for one cycle of the power line frequency.

[0132] Example 2.14. The method of any one of Example 2.1- Example 2.13, further comprising repeated alternate causing:the GN fault detection circuit to be enabled for one half-cycle of the power line frequency, andthe GN fault detection circuit to be disabled for one half-cycle of the power line frequency.

[0133] Example 2.15. The method of any one of Example 2.1- Example 2.14, wherein a pin of a controller is configured to cause the GN fault detection circuit to be enabled and disabled.

[0134] Example 2.16 The method of Example 2.15, wherein the pin of the controller is configured to cause the GN fault detection circuit to be disabled by, at least one of:directly shorting a GN core,indirectly shorting the GN core by using an intermediate circuit,directly disconnecting the GN core from the GN fault detection circuit, orindirectly disconnecting the GN core from the GN fault detection circuit by using an intermediate circuit.

[0135] Example 2.17. The method of any one of Example 2.2- Example 2.12, further comprising performing, in response to noise within the predetermined frequency range on a branch circuit, adjustments to an adaptive gain of the amplifier, the adjustments configured to:permit the determining whether the amplified signal has an amplified-signal frequency within the predetermined frequency range above the power line frequency while the GN fault detection circuit is enabled, andreduce, while the GN fault detection circuit is enabled, noise effects resulting from the noise on the branch circuit.

[0136] Example 2.18. The method of Example 2.6,wherein the GN fault detection circuit in a circuit interrupting device, wherein the circuit interrupting device is an equipment protection device (GFPE) or an arc-fault circuit interrupting (AFC I) device,PATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT) the method further comprising, in response to a manual test of the circuit interrupting device, using a smaller test current for the manual test by performing at least one ofincrease the gain of the second amplifier during the manual test, or use a small-current boost gain of the second amplifier during the manual test and measuring a test response on the second amplified signal.

[0137] Example 2.19. The method of any one of Example 2.2- Example 2.12,wherein the GN fault detection circuit in a circuit interrupting device, wherein the circuit interrupting device is an equipment protection device (GFPE) or a ground-fault circuit interrupting (GFCI) device,wherein, by implementing adaptive gain in the amplifier, components of the circuit interrupting device are the same whether the circuit interrupting device is a GFPE or a GFCI device.

[0138] Example 2.20. The method of any one of Example 2.2- Example 2.5, wherein the amplifier is a first amplifier, wherein the GN fault detection circuit is in a circuit interrupting device, the circuit interrupt device further comprising:a ground fault detection circuit configured to provide a third signal in response to the first signal and in response to a ground fault on a phase conductor and the neutral conductor,a second amplifier configured to amplify a fourth signal to provide a second amplified signal, wherein the fourth signal is based on the third signal, anda bandpass filter connected between an output of the second amplifier and an input of the first amplifier,wherein the bandpass filter is configured to:filter out power line frequency,filter out switching noise of the second amplifier, andfilter out the high frequency noise outside of the predetermined frequency range above the power line frequency.

[0139] Example 2.21. The method of any one of Example 2.1- Example 2.20, further comprising, in response to a manual test of the circuit interrupting device, calculating root mean square (RMS) voltage of the second signal to provide a constant test signal.

[0140] The embodiments disclosed herein are examples of the disclosure and may be embodied in various forms. For instance, although certain embodiments herein are described asPATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT) separate embodiments, each of the embodiments herein may be combined with one or more of the other embodiments herein. Specific structural and functional details disclosed herein are not to be interpreted as limiting, but as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the present disclosure in virtually any appropriately detailed structure. Like reference numerals may refer to similar or identical elements throughout the description of the figures.

[0141] The phrases “in an embodiment,” “in embodiments,” “in various embodiments,” “in some embodiments,” or “in other embodiments” may each refer to one or more of the same or different embodiments in accordance with the present disclosure. A phrase in the form “A or B” means “(A), (B), or (A and B) ” A phrase in the form “at least one of A, B, or C” means “(A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C) ”

[0142] Any of the herein described methods, programs, algorithms, or codes may be converted to, or expressed in, a programming language or computer program. The terms “programming language” and “computer program,” as used herein, each include any language used to specify instructions to a computer, processor, or controller, and include (but is not limited to) the following languages and their derivatives: Assembler, Basic, Batch files, BCPL, C, C+, C++, Delphi, Fortran, Java, JavaScript, machine code, operating system command languages, Pascal, Perl, PL1, scripting languages, Visual Basic, metalanguages which themselves specify programs, and all first, second, third, fourth, fifth, or further generation computer languages. Also included are database and other data schemas, parameters and / or variables, and any other meta-languages. No distinction is made between languages which are interpreted, compiled, or use both compiled and interpreted approaches. No distinction is made between compiled and source versions of a program. Thus, reference to a program, where the programming language could exist in more than one state (such as source, compiled, object, or linked) is a reference to any and all such states. Reference to a program may encompass the actual instructions, variables, and parameters, and / or the intent of those instructions, variables, and parameters.

[0143] The systems described herein may also utilize one or more controllers to receive various information and transform the received information to generate an output. The controller may include any type of computing device, computational circuit, or any type of processor or processing circuit capable of executing a series of instructions that are stored in a memory. The controller may include multiple processors and / or multicore central processing units (CPUs) andPATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT) may include any type of processor, such as a microprocessor, digital signal processor, microcontroller, programmable logic device (PLD), field programmable gate array (FPGA), or the like. The controller may also include a memory to store data and / or instructions that, when executed by the one or more processors, causes the one or more processors to perform one or more methods and / or algorithms.

[0144] It should be understood that the foregoing description is only illustrative of the present disclosure. Various alternatives and modifications can be devised by those skilled in the art without departing from the disclosure. Accordingly, the present disclosure is intended to embrace all such alternatives, modifications, and variations. The embodiments described with reference to the attached drawing figures are presented only to demonstrate certain examples of the disclosure. Other elements, steps, methods, and techniques that are insubstantially different from those described above and / or in the appended claims are also intended to be within the scope of the disclosure.

Claims

PATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT) What is Claimed is:

1. A circuit interrupting device comprising:a grounded neutral (GN) fault detection circuit configured to provide a first signal in response to a GN fault on a neutral conductor, the first signal having a frequency in a predetermined frequency range above a power line frequency; anda controller configured to perform:detecting a second signal while the GN fault detection circuit is enabled, the second signal having a frequency within the predetermined frequency range above the power line frequency;causing the GN fault detection circuit to be disabled; andbased on detecting no frequency within the predetermined frequency range above the power line frequency while the GN fault detection circuit is disabled, causing a load to be disconnected.

2. The circuit interrupting device of claim 1,wherein the GN fault detection circuit comprises an amplifier arranged to form a positive feedback loop within the GN fault detection circuit, the amplifier configured to amplify a signal in the positive feedback loop to provide an amplified signal as the second signal,wherein the controller is further configured to perform:determining whether the amplified signal has an amplified-signal frequency within the predetermined frequency range above the power line frequency while the GN fault detection circuit is enabled and while the GN fault detection circuit is disabled.

3. The circuit interrupting device of claim 2, wherein in the determining whether the amplified signal has an amplified-signal frequency in the predetermined frequency range above the power line frequency while the GN fault detection circuit is enabled and while the GN fault detection circuit is disabled, the controller is configured to perform:causing the GN fault detection circuit to be enabled;detecting a first frequency of the amplified signal while the GN fault detection circuit is enabled;PATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT) causing the GN fault detection circuit to be disabled; anddetecting a second frequency of the amplified signal while the GN fault detection circuit is disabled.

4. The circuit interrupting device of claim 3, wherein in the determining whether the amplified signal has an amplified-signal frequency in a predetermined frequency range above the power line frequency while the GN fault detection circuit is enabled and while the GN fault detection circuit is disabled, the controller is configured to, at least twice, cause the GN fault detection circuit to be enabled, detect the first frequency, cause the GN fault detection circuit to be disabled, and detect the second frequency.

5. The circuit interrupting device of claim 2, further comprising:a comparator configured to provide an indication corresponding to each cycle of the amplified signal; anda counter configured to count the indication corresponding to each cycle of the amplified signal,wherein the controller is configured to read and reset the counter to determine the amplified-signal frequency.

6. The circuit interrupting device of claim 2, wherein the amplifier is a first amplifier, the circuit interrupting device further comprising:a ground fault detection circuit configured to provide a third signal in response to:the first signal, anda ground fault on a phase conductor and the neutral conductor;a second amplifier configured to amplify a fourth signal to provide a second amplified signal, wherein the fourth signal is based on the third signal; anda high pass filter connected between an output of the second amplifier and an input of the first amplifier.

7. The circuit interrupting device of claim 2, further comprising:a voltage reference circuit configured to provide a reference voltage,PATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT) a first analog-to-digital converter (ADC), anda second ADC,the controller further configured to perform:sampling, by the first ADC, the amplified signal to provide first signal samples, wherein the sampling occurs at a sampling rate, andsampling, by the second ADC, the reference voltage to provide reference voltage samples, wherein the sampling by the second ADC occurs at the sampling rate.

8. The circuit interrupting device of claim 7, wherein the controller is further configured to perform:compensating the first signal samples based on the reference voltage samples.

9. The circuit interrupting device of claim 2, wherein the controller is further configured to perform:based on determining that the amplified signal has an amplified-signal frequency in the predetermined frequency range above the power line frequency while the GN fault detection circuit is enabled and while the GN fault detection circuit is disabled, repeat, for another iteration, the determining whether the amplified signal has an amplified-signal frequency in the predetermined frequency range above the power line frequency while the GN fault detection circuit is enabled and while the GN fault detection circuit is disabled.

10. The circuit interrupting device of claim 2, wherein the controller is further configured to perform:adjusting a sensitivity for detecting oscillations in a predetermined frequency range in the second signal while the GN fault detection circuit is enabled, and for detecting noise frequency in the predetermined frequency range above the power line frequency while the GN fault detection circuit is disabled.

11. The circuit interrupting device of claim 10, wherein in the adjusting the sensitivity, the controller is configured to perform:PATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT) decreasing the sensitivity based on detecting noise frequency in the predetermined frequency range above the power line frequency while the GN fault detection circuit is disabled; andincreasing the sensitivity based on not detecting any oscillations in the predetermined frequency range in the second signal while the GN fault detection circuit is enabled.

12. The circuit interrupting device of claim 10, wherein the sensitivity is adjusted by one or more of:adjusting a gain of an amplifier,adjusting a threshold of a comparator,adjusting a parameter of a filter,adjusting a parameter of a resonant circuit, orswitching number of turns in a neutral core.

13. The circuit interrupting device of claim 1, wherein the controller is configured to repeatedly alternate causing:the GN fault detection circuit to be enabled for one cycle of the power line frequency, andthe GN fault detection circuit to be disabled for one cycle of the power line frequency.

14. The circuit interrupting device of claim 1, wherein the controller is configured to repeatedly alternate causing:the GN fault detection circuit to be enabled for one half-cycle of the power line frequency, andthe GN fault detection circuit to be disabled for one half-cycle of the power line frequency.

15. The circuit interrupting device of claim 1, wherein a pin of the controller is configured to enable and disable the GN fault detection circuit.PATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT) 16. The circuit interrupting device of claim 15, wherein the pin of the controller is configured to disable the GN fault detection circuit by, at least one of:directly shorting a GN core,indirectly shorting the GN core by using an intermediate circuit,directly disconnecting the GN core from the GN fault detection circuit, orindirectly disconnecting the GN core from the GN fault detection circuit by using an intermediate circuit.

17. The circuit interrupting device of claim 2, wherein the controller is further configured to, in response to noise within the predetermined frequency range on a branch circuit, perform adjustments to an adaptive gain of the amplifier, the adjustments configured to:permit the determining whether the amplified signal has an amplified-signal frequency within the predetermined frequency range above the power line frequency while the GN fault detection circuit is enabled, andreduce, while the GN fault detection circuit is enabled, noise effects resulting from the noise on the branch circuit.

18. The circuit interrupting device of claim 6,wherein the circuit interrupting device is an equipment protection device (GFPE) or an arc-fault circuit interrupting (AFCI) device,wherein the controller is configured to, in response to a manual test of the circuit interrupting device, use a smaller test current for the manual test by performing at least one of:increase a gain of the second amplifier during the manual test, oruse a small-current boost gain of the second amplifier during the manual test and measuring a test response on the second amplified signal.

19. The circuit interrupting device of claim 2,wherein the circuit interrupting device is an equipment protection device (GFPE) or a ground-fault circuit interrupting (GFCI) device,PATENT APPLICATION Attorney Docket No. PA-02966 ORIG-2 WO (1640-114 II PCT) wherein, by implementing adaptive gain in the amplifier, components of the circuit interrupting device are the same whether the circuit interrupting device is a GFPE or a GFCI device.

20. The circuit interrupting device of claim 2, wherein the amplifier is a first amplifier, the circuit interrupting device further comprising:a ground fault detection circuit configured to provide a third signal in response to the first signal and in response to a ground fault on a phase conductor and the neutral conductor;a second amplifier configured to amplify a fourth signal to provide a second amplified signal, wherein the fourth signal is based on the third signal; anda bandpass filter connected between an output of the second amplifier and an input of the first amplifier,wherein the bandpass filter is configured to:filter out power line frequency,filter out switching noise of the second amplifier, andfilter out high frequency noise outside of the predetermined frequency range above the power line frequency.

21. The circuit interrupting device of claim 1, wherein the controller, in response to a manual test of the circuit interrupting device, is further configured to calculate root mean square (RMS) voltage of the second signal to provide a constant test signal.

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