Oscillator measurement system and method with flicker noise suppression

Abstract

An oscillator measurement system and method to measure phase noise, amplitude noise, and Allan deviation with reduced close-to-carrier noise floor by digitizing a device-under-test (DUT) signal and a reference signal together with first and second synthesized signals. In embodiments, a first digitizer time-referenced to a clock samples the DUT signal and the first synthesized signal, and a second digitizer time-referenced to the clock samples the reference signal and the second synthesized signal. Digital down-converters demodulate the digital signals to generate demodulated outputs. Differential circuits scale and subtract the outputs of the demodulated synthesized signals from the corresponding outputs of the demodulated DUT and reference signals, and further subtract the resulting difference signals to generate an output corresponding to noise of the DUT signal referenced to the reference signal while canceling or suppressing correlated converter-induced noise. The output is suitable for spectral or time-domain analysis and supports multi-channel configurations.

Description

PATENT Client Ref. 2025-021-03 Attorney Docket No. UOCO.P2113WO / 00676028OSCILLATOR MEASUREMENT SYSTEM AND METHOD WITH FLICKER NOISE SUPPRESSIONRELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Patent Application No.63 / 748,774, filed January 23, 2025, and U.S. Provisional Patent Application No. 63 / 813,972, filed May 29, 2025, each of which is incorporated herein by reference in its entirety.STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[0002] This invention was made with government support under grant number 70NANB23H027, awarded by the National Institute of Standards and Technology (NIST). The government has certain rights in the invention.BACKGROUND

[0003] Direct-digital measurement systems for characterizing oscillators can be limited by intrinsic close-to-carrier noise contributions introduced by the digitizers, including flicker noise, voltage-reference noise, and aperture-jitter effects, which can constrain achievable phase-noise, amplitude-noise, and stability measurement floors.SUMMARY

[0004] The present embodiments include an oscillator measurement system and method for measuring phase noise, amplitude noise, Allan deviation, or a combination thereof with improved intrinsic noise performance by digitizing a device-under-test (DUT) signal and a reference signal together with first and second synthesized signals generated by a frequency source. In embodiments, the DUT signal and a first synthesized signal are sampled with a first digitizer time-referenced to a clock, and the reference signal and a second synthesized signal are sampled with a second digitizer time-referenced to the clock. Digital down-converters (DDCs) demodulate the resulting digital signals to generate demodulated outputs that represent fluctuations due to noise associated with the corresponding carrier signals and may include both phase-noise and amplitude-noise information. Differential circuits generate differential signals by scaling and subtracting the outputs of the demodulated synthesized signals from the corresponding outputs of the demodulated DUT and reference signals, and by further1LEGALU 12447633\6PATENT Atorney Docket No. UOCO.P2113WO / 00676028 subtracting the resulting differential signals to generate an output that corresponds to a noise measurement of the DUT signal as referenced to the reference signal.

[0005] The present embodiments utilize the fact that two carrier signals traveling through the same device will experience the same flicker phase modulation (PM) and amplitude modulation (AM) noise introduced by that device. Therefore, an additional signal is introduced on the DUT and reference paths, and this additional signal may be used to measure the flicker AM and PM noise affecting both paths so that correlated close-to-carrier noise contributions introduced by the digitizers may be canceled or suppressed by the foregoing demodulation and differencing operations.

[0006] In some embodiments, the frequency source that generates the synthesized signals is referenced to the clock and may include one or more of a frequency divider, a direct digital synthesizer, a phase-locked loop, or a frequency multiplier. The disclosed systems and methods support configurations with multiple measurement channels without performance degradation, including configurations useful for timescale applications, by enabling suppression of correlated converter-induced impairments (including flicker-related limitations) in a manner that remains effective across channels.

[0007] The present embodiments include systems and methods for reducing close-to-the-carrier noise floors in direct digital measurement systems. For a 100 MHz carrier signal, with respect to previous state-of-the-art direct digital measurement systems, a noise floor reduction of over 35 dB in the flicker region for both phase and amplitude noise is achieved, together with greater than a factor of 20 improvement in Allan deviation. At 100 MHz for a single channel, a single sideband residual phase noise floor of £(1 Hz) = —147 dBc / Hz with a flicker comer of about 0.03 Hz is achieved, and a single-channel residual Allan deviation noise floor of less than 1.3 X 10-16at 1 second averaging time with a 0.5 Hz bandwidth is achieved. Further improvement may be achieved with cross-correlation techniques.

[0008] The present embodiments may directly measure ultra-low-noise oscillators, including optical-clock-derived signals after conversion to the RF domain, as well as the residual noise of RF components, and enable the creation of timescales based on modern optical atomic clocks, which are used to define the second.BRIEF DESCRIPTION OF THE FIGURES

[0009] FIG. 1 shows an oscillator measurement system, in accordance with some of the present embodiments.

[0010] FIG. 2 shows a direct-digital measurement system to measure phase noise and2LEGALM 12447633\6PATENT Atorney Docket No. UOCO.P2113WO / 00676028 amplitude noise originating from a device-under-test (DUT) oscillator.

[0011] FIG. 3 shows an oscillator measurement system that is one example of the oscillator measurement system of FIG. 1.

[0012] FIG. 4 shows an oscillator measurement system that is one example of the oscillator measurement system of FIG. 1.

[0013] FIG. 5 shows a block diagram of a single-channel FSDD noise measurement system which is one example of the oscillator measurement system of FIG. 1.

[0014] FIG. 6 is a plot of residual phase noise at a 100 MHz carrier with a synthesized signal near the carrier frequency, illustrating close-to-carrier noise-floor reduction relative to a conventional direct-digital configuration.

[0015] FIG. 7 is a plot of residual amplitude noise at a 100 MHz carrier with a synthesized signal near the carrier frequency, illustrating close-to-carrier noise-floor reduction relative to a conventional direct-digital configuration.

[0016] FIG. 8 is a plot of residual Allan deviation at a 100 MHz carrier with a synthesized signal near the carrier frequency, illustrating improved time-domain stability performance relative to a conventional direct-digital configuration.

[0017] FIG. 9 is a plot of residual phase noise at a 100 MHz carrier with a synthesized signal placed farther from the carrier frequency, illustrating the effect of synthesized-signal placement on residual phase-noise performance.

[0018] FIG. 10 is a plot of residual amplitude noise at a 100 MHz carrier with a synthesized signal placed farther from the carrier frequency, illustrating the effect of synthesized-signal placement on residual amplitude-noise performance.

[0019] FIG. 11 is a plot of residual Allan deviation at a 100 MHz carrier with a synthesized signal placed farther from the carrier frequency, illustrating the effect of synthesized-signal placement on time-domain stability performance.DETAILED DESCRIPTION

[0020] The present embodiments relate to direct-digital measurement systems for characterizing oscillators, including high-performance devices under test such as atomic clocks. As described herein, conventional direct-digital architectures are fundamentally limited by residual close-to-carrier noise originating in the analog-to-digital converters (ADCs), including flicker-phase noise in the ADCs and noise contributions arising from the ADC’s voltage reference noise and aperture jitter. These limitations create a noise floor that constrains achievable phase-noise, amplitude-noise, and Allan-deviation performance, particularly when3LEGALM 12447633\6PATENT Atorney Docket No. UOCO.P2113WO / 00676028 measuring ultra-low-noise oscillators, where it could take days of cross-correlation averaging to achieve the necessary close-to-the-carrier noise floor.

[0021] The present embodiments address this problem by introducing an additional correction signal and associated digital-signal-processing chain (including multiple ADC channels and digital down-converters) that enable the system to effectively reduce the noise floor, particularly in the flicker noise region. By exploiting the shared nature of flicker noise and other correlated ADC impairments, the disclosed systems and methods suppress these contributions in a feed-forward manner, thereby providing substantially improved phase- and amplitude-noise measurement sensitivity and yielding single-channel residual instabilities on the order of 1.3 X 10-16at 1 second averaging time. In summary, the present embodiments provide measurement systems and methods that overcome the intrinsic flicker-noise and jitter limitations of prior direct-digital approaches by using coordinated ADC sampling paths and DDC-based signal extraction to suppress converter-induced noise and enable ultra-low-noise metrology.

[0022] FIG. 1 shows an oscillator measurement system 100, in accordance with some of the present embodiments. The oscillator measurement system 100 includes a clock 102, a frequency source 104, a first digitizer 106, and a second digitizer 108. The clock 102 outputs a clock signal 103 having a clock frequency vc. The frequency source 104 generates a first synthesized signal 114 and a second synthesized signal 124, each having the same synthesized frequency v5. A device-under-test (DUT) generates a DUT signal 110 having a DUT frequency vDand a reference source generates a reference signal 112 having a reference frequency vR.

[0023] The first digitizer 106 and the second digitizer 108 convert analog signals (e.g., the DUT signal 110, the first synthesized signal 114, the second synthesized signal 124, and the reference signal 112) into digital signals. The first digitizer 106 includes one or more ADC cores and is time-referenced to the clock 102 such that the first digitizer 106 (i) generates a first digital signal 116 by sampling the DUT signal 110 at the clock frequency vcand (ii) generates a second digital signal 126 by sampling the first synthesized signal 114 at the clock frequency vc. Similarly, the second digitizer 108 includes one or more ADC cores and is time-referenced to the clock 102 such that the second digitizer 108 (i) generates a third digital signal 118 by sampling the second synthesized signal 124 at the clock frequency vcand (ii) generates a fourth digital signal 128 by sampling the reference signal 112 at the clock frequency vc.

[0024] The oscillator measurement system 100 further includes a first digital downconverter (DDC) 120, a second DDC 122, a third DDC 130, and a fourth DDC 132. The first4LEGALM 12447633\6PATENT Atorney Docket No. UOCO.P2113WO / 00676028 DDC 120 demodulates the first digital signal 116 by the DUT frequency vDto generate a first demodulated signal 136. The second DDC 122 demodulates the second digital signal 126 by the synthesized frequency v5to generate a second demodulated signal 146. The third DDC demodulates the third digital signal 118 by the synthesized frequency v5to generate a third demodulated signal 138. The fourth DDC demodulates the fourth digital signal 128 by the reference frequency vRto generate a fourth demodulated signal 148. In each case, demodulation by the DDCs generates signals in baseband (i.e., centered at or near zero frequency) representing the fluctuations due to noise associated with the corresponding carrier signals. Accordingly, the resulting demodulated outputs may include both phase-noise and amplitude-noise information associated with the underlying DUT, synthesized, or reference carrier signals. For clarity, each such DDC output may be referred to as a “demodulated phase-noise signal” or a “demodulated amplitude-noise signal,” depending on the component of interest.

[0025] The oscillator measurement system 100 further includes a first differential circuit 140, a second differential circuit 150 and a third differential circuit 160. The first differential circuit 140 generates a first differential signal 156 by subtracting the second demodulated signal 146 from the first demodulated signal 136 (i.e., the first differential signal 156 equals the first demodulated signal 136 minus the second demodulated signal 146). The second differential circuit 150 generates a second differential signal 158 by subtracting the third demodulated signal 138 from the fourth demodulated signal 148 (i.e., the second differential signal 158 equals the fourth demodulated signal 148 minus the third demodulated signal 138). The third differential circuit 160 generates a third differential signal 170 by subtracting the second differential signal 158 from the first differential signal 156.

[0026] In some embodiments, the second demodulated signal 146 and the third demodulated signal 138 are scaled by one or more scaling coefficients before being subtracted from the first demodulated signal 136 and the fourth demodulated signal 148, respectively. Although FIG. 1 depicts the differential circuits 140, 150, and 160 as including a particular configuration of adder and subtracter units (circled “+” and “) and multiplier units (circled “X”), other embodiments may employ arithmetic units (including add, subtract, multiply, and divide units) arranged differently, or distributed across one or more processing stages, to obtain the same results without departing from the scope herein.

[0027] Similar to the demodulated signals, the differential signals generated by the differential circuits represent differences of the fluctuations due to noise present in the5LEGALM 12447633\6PATENT Atorney Docket No. UOCO.P2113WO / 00676028 corresponding demodulated signals. As a result, each differential signal may include differences of phase-noise information or differences of amplitude-noise information. For clarity, such differential signals may therefore be referred to as “phase-difference signals” or “amplitude-difference signals,” depending on the component of interest.

[0028] In some of the embodiments, the oscillator measurement system 100 includes a spectrum analyzer 180. The third differential signal 170 may include phase-noise information, amplitude-noise information, or both. When the demodulated outputs convey phase-noise information, the third differential signal 170 functions as a phase-difference signal, and when the demodulated outputs convey amplitude-noise information, the third differential signal 170 functions as an amplitude-difference signal. Thus, the third differential signal 170 represents the measurement of interest, namely, the noise characteristics of the DUT signal 110 referenced to the reference signal 112. The spectrum analyzer 180 processes the third differential signal 170 to produce a noise signal 182 that characterizes the DUT signal 110 in the phase-noise domain and the amplitude-noise domain, and may also be used for time-domain stability analysis. The noise signal 182 may also be referred to as a noise-measurement signal.

[0029] In some of the embodiments, the first and second synthesized signals 114 and 124 are derived from the clock 102. For example, the frequency source 104 may be a frequency divider that divides the clock frequency vcby an integer N, such that the generated first and second synthesized signals 114 and 124 have a synthesized frequency v5= vc / N. In other examples, the frequency source 104 may include a phase-locked loop, a direct digital synthesizer, or a frequency multiplier. In some of the embodiments, the reference signal 112 is supplied from a reference clock that is different from the clock 102.

[0030] In some embodiments, the oscillator measurement system 100 includes any number of filters. For example, one or more of the digital signals may be filtered with a bandpass filter having a bandwidth that overlaps the corresponding frequency before being fed into the respective DDC. As another example, the second demodulated signal 146 may be filtered using a low-pass filter prior to being fed into the first differential circuit 140, and the third demodulated signal 138 may be filtered using a low-pass filter prior to being fed into the second differential circuit 150. Other filters applied to other signals may be included in the oscillator measurement system 100 without departing from the scope herein.

[0031] In some embodiments, the oscillator measurement system 100 includes one or more amplifiers and attenuators to condition one or more of the DUT signal 110, the reference signal 112, the first synthesized signal 114, or the second synthesized signal 124 prior to digitization. For example, a first amplifier may amplify the first synthesized signal 114 and a 6LEGALM 12447633\6PATENT Atorney Docket No. UOCO.P2113WO / 00676028 second amplifier may amplify the second synthesized signal 124 prior to being digitized. Additionally or alternatively, one or more attenuators may be utilized to reduce a power of one or more of the first and second synthesized signals 114 and 124. In some embodiments, amplifiers or attenuators are included to condition the DUT signal 110 or the reference signal 112. In these embodiments, the amplifiers and attenuators may be used to adjust the signal amplitudes delivered to the digitizer inputs so the digitizers operate within their input range during sampling and so the available digitizer input range is used effectively.

[0032] In some embodiments, the oscillator measurement system 100 includes one or more digital amplifiers and digital attenuators to condition one or more demodulated signals and differential signals. For example, one or more digital amplifiers may be configured to output a scaled demodulated signal by multiplying a demodulated signal generated by a DDC by a scaling coefficient prior to subtraction in a corresponding differential circuit, such that a phase-difference signal or an amplitude-difference signal is generated using the scaled demodulated signal. In further examples, one or more digital amplifiers may be configured to output a scaled phase-difference signal or a scaled amplitude-difference signal by multiplying a phase-difference signal or an amplitude-difference signal by a scaling coefficient prior to subtraction in the third differential circuit 160. In these embodiments, digital attenuation may be implemented by selecting a scaling coefficient having magnitude less than one (or by other digital scaling operations), and the digital scaling may be applied to any of the demodulated signals 136, 146, 138, and 148 and any of the differential signals 156, 158, and 170 to accommodate signals at different frequencies, to adjust relative signal levels, to keep intermediate values within a desired numerical range and reduce quantization effects in subsequent digital processing, or to apply a selected weighting among measurement cores, without departing from the scope herein.

[0033] FIG. 2 shows a direct-digital measurement system 200 to measure phase noise and amplitude noise originating from a device-under-test (DUT) oscillator. The direct-digital measurement system 200 includes an ADC system 298 and a DDC 220. The ADC system 298 is similar to the first digitizer 106 and the second digitizer 108 of FIG. 1. The ADC system 298 is time-referenced to a clock 202 such that the ADC system 298 samples a DUT signal 210 at instants determined by a defined timing event of a clock signal 203 generated by the clock 202 and having a clock frequency vc. In the depicted system, sampling occurs at the positive zero-crossings of the clock signal 203.

[0034] In the context of FIG. 2, the ADC system 298 may be understood as a model of a single ADC channel (or “ADC path”) that is time-referenced to the clock 202 and that 7LEGALM 12447633\6PATENT Atorney Docket No. UOCO.P2113WO / 00676028 includes the functional circuitry associated with sampling and conversion, such as an input buffer, a clock buffer, a voltage reference, and an ADC core. By contrast, a digitizer (e.g., the first digitizer 106 or the second digitizer 108 of FIG. 1) may include one or more such ADC systems (i.e., one or more ADC channels) that share a common timing reference and that collectively provide one or more analog inputs and one or more digital outputs. Accordingly, each ADC channel within a digitizer may be modeled by a corresponding ADC system as shown in FIG. 2, and noise terms attributed herein to an “ADC system” are intended to refer to noise associated with the corresponding ADC channel of the digitizer rather than to quantization behavior of the ADC core itself. Alternatively, in some implementations, the digitizer may include only the ADC core, and one or more of the input buffer, the clock buffer, and the voltage reference may be external to the digitizer. In any of these cases, an “ADC system” or “ADC channel” associated with a digitizer refers to the corresponding ADC channel that supports sampling and conversion for that digitizer, including any internal and external circuitry used to implement that channel.

[0035] The DUT signal 210 and the clock signal 203 are analog electrical signals whose time-varying voltage may be expressed as << where the DUT signal 210 has signal amplitude AD, fractional amplitude noise aD, and phase noise To- Similarly, the clock signal 203 has signal amplitude Ac, fractional amplitude noise ac, and phase noise cpc.

[0036] After sampling, the ADC system 298 outputs a digital signal 216 that is a digital sequence of samples. Because the ADC system 298 is triggered by the positive zero crossing of the clock signal 203, the output sequence is largely independent of Acand ac(t), while the phase fluctuations of the clock signal 203 project into the sampled sequence (e.g., the digital signal 216) with a corresponding frequency scaling. If the ADC system 298 is noise-free, the kthsample of the digital signal 216 may be written as< where tksolves2nvctk+ <pc(tfc) = 2TT C,for every integer k. Equivalently, the digital signal 216 may be rewritten as8LEGALM 12447633\6PATENT Attorney Docket No. UOCO.P2113WO / 00676028where aD, pD, and <pcdenote the instantaneous values of the corresponding noise processes at the sampling instants. The DDC 220 then demodulates the digital signal 216 by the DUT frequency vDto generate a demodulated signal 236 of the form< <with the top entry representing the phase component and the bottom entry representing the amplitude component.

[0037] In conventional implementations, the ADC system 298 includes an ADC inputbuffer circuit 292, a clock-buffer circuit 294, a voltage-reference circuit 296, and an ADC core 290. The non-ideal behavior of these circuits introduce residual noise terms. In one noise model, the ADC input-buffer circuit 292 contributes flicker phase and amplitude noise< C<-AXF)as wellaswhite phase and amplitude noise (cp^w , AxWy), where the subscript Axdenotes terms associated with a specific ADC system and the subscript Wydenotes the whitenoise terms associated with signals having a frequency vy. The clock-buffer circuit 294 contributes aperture-jitter noise ((pAx]), which scales with carrier frequency, and the voltage-reference circuit 296 contributes fractional amplitude noise

[0038] With this ADC noise model, the demodulated signal 236 generated by the DDC 220 may be expressed as<where the subscript A1denotes noise associated with the ADC system 298.

[0039] FIG. 3 shows an oscillator measurement system 300 that is one example of the oscillator measurement system 100 of FIG. 1. The oscillator measurement system 300 implements a first digitizer 306 which is one example of the first digitizer 106 of FIG. 1, and a second digitizer 308 which is one example of the second digitizer 108 of FIG. 1.

[0040] The first digitizer 306 includes a first combiner 310 and a first ADC core 390. The first combiner 310 combines the DUT signal 110 and the first synthesized signal 114 to generate a first combined signal 320. The first ADC core 390 samples the first combined signal9LEGALU 12447633\6PATENT Atorney Docket No. UOCO.P2113WO / 00676028 320 at the clock frequency vcto generate a first intermediate signal 322. Subsequently, the first DDC 120 demodulates the first digital signal 116 as the first intermediate signal 322, and the second DDC 122 demodulates the second digital signal 126 as the first intermediate signal 322. In this example, the first and second digital signals 116 and 126 carry the same information as the intermediate signal 322.

[0041] Similarly, the second digitizer 308 includes a second combiner 312 and a second ADC core 392. The second combiner 312 combines the reference signal 112 and the second synthesized signal 124 to generate a second combined signal 330. The second ADC core 392 samples the second combined signal 330 at the clock frequency vcto generate a second intermediate signal 332. Subsequently, the third DDC 130 demodulates the third digital signal 118 as the second intermediate signal 332, and the fourth DDC 132 demodulates the fourth digital signal 128 as the second intermediate signal 332. In this example, the third and fourth digital signals 118 and 128 carry the same information as the second intermediate signal 332.

[0042] In some of the embodiments, the first ADC core 390 is electrically connected to the first and second DDCs 120 and 122 via separate electrical traces or input paths with no digital replication, buffering, or other active signal-processing operation required to generate two copies of the waveform. Rather, both DDCs receive the same sequence of ADC-generated samples directly from a digital output of the first ADC core 390, such that each DDC processes an identical digital representation of the first intermediate signal 322 notwithstanding their physically distinct electrical connections. The same applies to the second intermediate signal 332 generated by the second ADC core 392, which may likewise be directed (without any digital copying operations) to the third and fourth DDCs 130 and 132 via distinct physical routing paths.

[0043] In other embodiments, the oscillator measurement system 300 may include one or more active devices to generate multiple instances of the intermediate signal 322 for delivery to the respective DDCs. For example, a digital splitter, fan-out buffer, or other replication circuit may be interposed between the first ADC core 390 and the inputs of the first and second DDCs 120 and 122. Such components may receive the intermediate signal 322 from a digital output of the first ADC core 390 and actively generate two or more digital replicas thereof, each replica being electrically distinct and independently routed to a corresponding DDC. In these configurations, the duplication is performed deliberately by active digital logic devices rather than by passive branching of an existing signal path. A corresponding arrangement may be implemented for the second intermediate signal 332 output by the second ADC core 392,10LEGALM 12447633\6PATENT Attorney Docket No. UOCO.P2113WO / 00676028 allowing active duplication of the intermediate signal 332 for delivery to the third and fourth DDCs 130 and 132.

[0044] The first DDC 120 demodulates the first digital signal 116 (as the first intermediate signal 322) by the DUT frequency vDto generate the first demodulated signal 136 which may be expressed as (see discussion of FIG. 2)< < <where the subscript A corresponds to the ADC channel (i.e., the ADC channel or ADC system as described in FIG. 2) implemented using the first ADC core 390 to generate the first intermediate signal 322, (pDdenotes the phase noise of the DUT signal 110, (pcdenotes the phase noise of the clock signal, (pAiFdenotes the flicker phase noise, (pAwDdenotes the white phase noise associated with the DUT frequency vD, (pAiJdenotes the jitter phase noise (i.e., phase noise due to aperture jitter), ADdenotes the amplitude of the DUT signal 110, aDdenotes the fractional amplitude noise of the DUT signal 110, O^R denotes the flicker amplitude noise, C<-AWDdenotes the white amplitude noise associated with the DUT frequency vD, and aA1Rdenotes the voltage-reference amplitude noise.

[0045] Similarly, the second DDC 122 demodulates the second digital signal 126 (as the first intermediate signal 322) by the synthesized frequency v5to generate the second demodulated signal 146 which may be expressed as< <where (psldenotes the phase noise of the first synthesized signal 114, AS1denotes the amplitude of the first synthesized signal 114, and asldenotes the fractional amplitude noise of the first synthesized signal 114. Note that the jitter phase noise scales as a ratio of the synthesized and DUT frequencies, vs / vD.

[0046] The first differential circuit 140 then scales and subtracts the second demodulated signal 146 from the first demodulated signal 136 (e.g., scaling and subtracting Eqn. 2 from Eqn. 1) to generate the first differential signal 156 as follows,11LEGALU 12447633\6PATENT Attorney Docket No. UOCO.P2113WO / 00676028< < <where the symbol O designates an element-wise product. Eqn. 3 shows that the jitter phase noise (pA1Jand the clock phase noise cpccancel out, while the flicker phase noise (pA1Fis suppressed by a factor which depends on a ratio of the DUT frequency vDand the synthesized frequency v5. Advantageously, the flicker amplitude noise aA Fand the voltage-reference amplitude noise aA Rcancel out in Eqn. 3.

[0047] Similarly, the third DDC 130 demodulates the third digital signal 118 (as the second intermediate signal 332) by the synthesized frequency v5to generate the third demodulated signal 138 and the fourth DDC 132 demodulates the fourth digital signal 128 (as the second intermediate signal 332) by the reference frequency vRto generate the fourth demodulated signal 148. Subsequently, the second differential circuit 150 scales and subtracts the third demodulated signal 138 from the fourth demodulated signal 148 to generate the second differential signal 158 in the following way,< <where the subscript A2corresponds to the ADC channel (i.e., the ADC channel or ADC system as described in FIG. 2) implemented using the second ADC core 392 to generate the second intermediate signal 332, <pS2denotes the phase noise of the second synthesized signal 124, AS2denotes the amplitude of the second synthesized signal 124, and aS2denotes the fractional amplitude noise of the second synthesized signal 124.

[0048] The third differential circuit 160 scales and subtracts the second differential signal 158 from the first differential signal 156 to generate a third differential signal 170 which may be expressed as,LEGALU 12447633\6PATENT Atorney Docket No. UOCO.P2113WO / 00676028< < << <where the equality asl= aS2was used because the first and second synthesized signals 114 and 124 derive from the same frequency source 104 such that this equality is an appropriate assumption.

[0049] Eqn. 5 shows that the third differential signal 170 corresponds to noise of the DUT signal 110 referenced to the reference signal 112, while suppressing or canceling noise contributions that are common to the sampled and demodulated signals. In particular, because the DUT signal 110 and the first synthesized signal 114 are sampled with the same ADC core 390 and are processed by respective DDCs, converter-related effects that are common to those two demodulated outputs are reduced in the first differential signal 156. Likewise, because the reference signal 112 and the second synthesized signal 124 are sampled with the same ADC core 392 and are processed by respective DDCs, converter-related effects that are common to those two demodulated outputs are reduced in the second differential signal 158. Subtracting the second differential signal 158 from the first differential signal 156 in the third differential circuit 160 thereby yields the third differential signal 170 in which the remaining terms correspond predominantly to the relative noise behavior of the DUT signal 110 and the reference signal 112, while residual contributions associated with the digitizers and the synthesized signals are canceled or suppressed as reflected by Eqn. 5.

[0050] Accordingly, the third differential signal 170 provides an output suitable for subsequent spectral and time-domain processing to characterize the DUT signal 110 relative to the reference signal 112, including phase-noise and amplitude-noise characterization, and further including stability analysis such as Allan deviation, as described above with respect to FIG. 1. Additionally or alternatively, one or more scaling operations and filtering operations may be applied at one or more points in the processing chain (including to one or more demodulated signals and one or more differential signals) to accommodate different signal frequencies, to adjust relative signal levels, or to maintain intermediate values within a desired numerical range, without departing from the scope herein.

[0051] FIG. 4 shows an oscillator measurement system 400 that is one example of the oscillator measurement system 100 of FIG. 1. The oscillator measurement system 40013LEGALM 12447633\6PATENT Atorney Docket No. UOCO.P2113WO / 00676028 implements a first digitizer 406 which is one example of the first digitizer 106 of FIG. 1, and a second digitizer 408 which is one example of the second digitizer 108 of FIG. 1.

[0052] The first digitizer 406 includes a first ADC core 490 and a second ADC core 492 co-located on a first multi-channel chip. The first ADC core 490 samples the DUT signal 110 at the clock frequency vcto generate the first digital signal 116. The second ADC core 492 samples the first synthesized signal 114 at the clock frequency vcto generate the second digital signal 126. Similarly, the second digitizer 408 includes a third ADC core 494 and a fourth ADC core 496 co-located on a second multi-channel chip. The third ADC core 494 samples the second synthesized signal 124 at the clock frequency vcto generate the third digital signal 118. The fourth ADC core 496 samples the reference signal 112 at the clock frequency vcto generate the fourth digital signal 128.

[0053] The oscillator measurement system 400 functions similarly to what is explained in FIG. 3 above. In the oscillator measurement system 300 of FIG. 3, the DUT signal 110 and the first synthesized signal 114 are combined prior to sampling such that a single ADC core samples a combined waveform and the resulting digital samples are used by multiple DDCs to extract the respective demodulated outputs. By contrast, in the oscillator measurement system 400, the DUT signal 110 and the first synthesized signal 114 are sampled with distinct first and second ADC cores 490 and 492, and the reference signal 112 and the second synthesized signal 124 are sampled with distinct third and fourth ADC cores 496 and 494, with each pair of ADC cores co-located on a corresponding multi-channel ADC chip. This arrangement avoids combining multiple analog signals for delivery to a single ADC input and permits signal levels for the DUT, reference, and synthesized signals to be set independently at the respective digitizer inputs. In addition, co-locating the paired ADC cores on a common multi-channel ADC chip may improve matching and correlation of converter-related effects between the paired channels, thereby supporting effective suppression of such effects by the subsequent demodulation and differencing operations, without departing from the scope herein.Flicker-Suppressed Direct-Digital Measurements of Phase and Amplitude Noise

[0054] Measuring phase and amplitude noise of local oscillators and two-port devices is often critical for many applications such as telecommunication [1, 2] and radar [3], Since their first commercial introduction, direct digital techniques [4] have been widely used in time and frequency metrology offering numerous advantages. These include the ability to utilize asynchronous reference (REF) and device-under-test (DUT) frequencies, eliminating the need for phase-locking, simplified near-to-the-carrier measurements, simultaneous phase and14LEGALM 12447633\6PATENT Atorney Docket No. UOCO.P2113WO / 00676028 amplitude noise detection, and Allan deviation measurement, all without the need for sensitivity calibration [4-8],

[0055] State-of-the-art performance is achieved using two-input high-performance analog-to-digital converters (ADC) [9] to suppress common noise sources such as aperture jitter and the voltage reference. In multi -input applications, such as timescales, the performance could be degraded due to the limited common mode noise suppression between ADCs distributed over independent devices. During Allan deviation measurements, low measurement bandwidths (BW) are generally used, meaning that the measurement system’s noise floor is often limited by residual flicker phase noise in the ADCs. To overcome these noise floor limitations, the most commonly used technique in commercial instruments is cross-correlation averaging [8-10], However, when ultra-low noise devices or the best optical atomic clocks are measured, it may take days of cross-correlation averaging to achieve the necessary close-to-the-carrier noise floor. Moreover, when using cross-correlation, noise floor improves as the square root of averaging time, and because of limitations in channel isolation and practical measurement time, enhancements over an order of magnitude are hardly achieved in Allan deviation.

[0056] In a previously developed direct-digital measurement system [9], a singlechannel 10 MHz single-sideband phase-noise floor of £(1 Hz) = —143 dBc / Hz was demonstrated, together with a single-channel residual frequency stability of 3.2 x 10-15at an averaging time of T = 1 s. Building on that architecture, the present embodiments further describe a multi-channel system that incorporates a flicker-suppressed direct-digital (FSDD) technique to improve measurement performance, as described in

[0011] , The FSDD technique significantly reduces the residual flicker-noise floor and delivers consistent results for differential measurements, whether the differential measurement is performed between the two input channels of a common dual-channel ADC device (i.e., two ADC cores co-located on the same multi-channel ADC chip or module) or between input channels implemented using different ADC devices. For 100 MHz carriers, the residual single-channel phase-noise floor without FSDD is £(1 Hz) = —124 dBc / Hz when the two inputs of the same dual-channel ADC device are used, and £(1 Hz) = —111 dBc / Hz when the inputs are directed to ADC channels implemented on different ADC devices. In both cases, the single-channel noise floor is limited by flicker phase noise. On the other hand, when FSDD is implemented, we observe over 35 dB lower residual flicker with the measurement being mostly white-noise limited for both phase and amplitude noise. For the same 100 MHz carriers, single-channel Allan deviation15LEGALM 12447633\6PATENT Atorney Docket No. UOCO.P2113WO / 00676028 residual noise demonstrates more than a factor of 20 improvement when FSDD is used. These already record-breaking results may be further improved with the use of cross-spectrum and cross-variance

[0010] techniques, bringing the instrument noise floor to as low as 10-17@ T = 1 or better. In a live timescale application, where cross-correlation cannot be used, FSDD theoretically supports some of the best optical atomic clocks after converting their outputs into the RF domain [12, 13],Flicker-Suppressed Direct-Digital

[0057] FIG. 5 shows a schematic of a single-channel FSDD noise measurement system 500 which is one example of the oscillator measurement system 100 of FIG. 1. A correction signal (CORR) (e.g., the first and second synthesized signals 114 and 124) is injected into the DUT (e.g., the DUT signal 110 of FIG. 1) and REF (e.g., the reference signal 112 of FIG. 1) paths. For ADC0 (e.g., the ADC system 298 of FIG. 2), two DDCs extract DUT and CORR phase-noise fluctuations, whereas for ADC1 (e.g., the ADC system 298 of FIG. 2), two DDCs extract REF and CORR phase-noise fluctuations. The phase noise information is then scaled and subtracted. The correction signal may be an independent source, or a scaled frequency of the clock (also referred to as the ADC clock) such as a frequency divider, a direct digital synthesizer (DDS), or a programmable phase-locked loop (PLL). The symbol s denotes differentiation, and the scaling constants kxare described in Eqn. 10.

[0058] The most intuitive way to understand the FSDD technique is by superposition: if the blocks outlined with dashed lines in FIG. 5 are removed, the system performs a conventional direct digital measurement as already implemented in previous work [9] (see, for example, FIG. 2), which will include the system noise floor. On the other hand, if DUT and REF are removed, the correction signal (CORR) performs a residual system noise floor measurement. Because both measurements, conventional and residual, are performed simultaneously and share the same noise floor, subtracting their measured phase-noise fluctuations reduces the noise floor, particularly in the flicker noise region.

[0059] In the noise model used in this study, the ADC core itself is considered ideal, meaning that quantization noise is negligible and therefore excluded from further analysis (see, for example, FIG. 2). Three main noise sources for each ADC device (e.g., each ADC system 298 of FIG. 2) are indicated as follows:• A buffer at the clock port.• A voltage reference.16LEGALM 12447633\6PATENT Atorney Docket No. UOCO.P2113WO / 00676028 • A buffer at the input port.Both white and flicker noise of the clock buffer will introduce aperture jitter cpAxj for the specific ADCX(e.g., a specific ADC system like the ADC system 298 of FIG. 2), and it will be by definition a time modulation (x(t) type of noise). This aperture jitter will scale according to a ratio of the DUT carrier and CORR carrier frequencies. On the other hand, the voltage reference will introduce amplitude noise for a particular ADCX, and since its fluctuations will change the gain of the ADC core, it may be defined as C<AXR- Finally, the residual noise of the input buffer has been divided into two components: flicker noise and white noise for both phase and amplitude. The white-noise components q>AxwyandaAxwywill be independent for each ADCXand carrier frequency vy, while the flicker-noise componentsandaAxF will be independent for each ADCX, but the same for each carrier frequency vy. Flicker noise is a nearDC process, and because of non-linearities in a device, flicker noise is up-converted when a carrier signal passes through an active device

[0014] , Therefore, since the source of flicker noise is common to two or more carrier signals passing through the same device simultaneously, each signal will experience the same flicker modulation

[0015] , Up-converted flicker noise ideally does not scale with carrier frequency or power

[0014] , suggesting thatisaphase modulation (cp(t) type of noise). Similar reasoning may be applied for amplitude noise, and therefore aAxFwill be the same for all carrier signals passing through a particular device simultaneously.

[0060] DUT and CORR signals are sampled through ADCO. In the digital domain, two DDCs extract the phase and amplitude noise for the DUT carrier (vD) and for the CORR carrier (vs). The details of the DDCs are described in previous work [9], The DDC dedicated to the DUT will measure:< < <while the second DDC for v5will generate:< < <><LEGAL\112447633\6PATENT Attorney Docket No. UOCO.P2113WO / 00676028The top and bottom rows of the matrices contain the phase and amplitude noise terms, respectively. <pDandare the DUT and CORR phase noise respectively, cpcis the phase noise of the ADC clock, and vcis the clock frequency. For the amplitude components, ADand are the amplitudes of the DUT and CORR carriers respectively, while aDand asare their amplitude index fluctuations.

[0061] By scaling and subtracting Eqns. 6 and 7,<The symbol O designates the element-wise product. From Eqn. 8 one can see that the DUT is measured against CORR, the aperture jitter and ADC clock phase noise cancels, and the input buffer flicker noise is suppressed by a factor which depends on the DUT to CORR frequency ratio (i.e., 1 — ^). On the other hand, for amplitude noise, input buffer flicker noise and voltage-reference noise cancel.

[0062] Similarly, for the REF path:where cpRand aRare the REF phase and amplitude noise, respectively. ARis the REF signal amplitude and vRis the REF signal frequency.

[0063] Finally, Eqn. 9 may be scaled by the DUT to REF frequency ratio and subtracted from Eqn. 8. The final result is then18LEGALU 12447633\6PATENT Attorney Docket No. UOCO.P2113WO / 00676028< < < <

[0064] Eqn. 10 shows that the DUT noise is measured against the scaled REF noise, as expected. In contrast to the traditional direct-digital technique, ADC aperture jitter is removed and the flicker phase noise from both ADCs are suppressed, however, additional new white noise components are present. The final measurement equations do not contain terms from the phase and amplitude noise introduced by the correction signal, clock aperture jitter, or clock phase noise. The amount of ADC flicker reduction and white noise degradation may be controlled with the frequency ratio between DUT, REF, and the correction signal.

[0065] From a practical point of view, white noise is further deteriorated by the limited ADC dynamic range. In fact, if the available dynamic range is split in half to accommodate the correction signal, a 6 dB increase in ADC residual white noise is expected in both phase and amplitude noise. Power levels for DUT, REF, and CORR, and v5may be optimized to maximize flicker suppression, or to limit white noise degradation.

[0066] To recover some white noise performance at high-frequency offsets, FIG. 5 shows two digital low-pass filters for the v5paths. These filters, however, will compromise aperture jitter and voltage reference noise suppression above their cut-off frequency.

[0067] The CORR frequency must be different enough from the DUT and the REF frequencies to not compromise the measurement with a specific bandwidth, and analog filters may be needed to prevent the CORR’s phase and amplitude noise sidebands from overlapping with the DUT and REF noise sidebands, and vice versa. Aliasing caused by the sampling must also be considered when utilizing more than one Nyquist region.

[0068] Finally, to avoid the necessity of requiring an additional source for the correction signal, it may be conveniently derived from the ADC clock with the use of one or more of programmable phase-locked loops (PLL), direct digital synthesizers (DDSs), frequency dividers, and multipliers. The residual noise of these components may be considered part of <Ps and as, and will suppress according to the equations shown above. Moreover, the model in FIG. 2 demonstrates that noise introduced on the ADC clock paths may be considered as aperture jitter, and therefore will be suppressed; while flicker noise introduced by components on the ADC system input path may be considered as input-buffer noise, and19LEGALM 12447633\6PATENT Atorney Docket No. UOCO.P2113WO / 00676028 therefore will partially suppress according to Eqn. 10. This result enables the use of buffers and amplifiers on the clock and input ADC system ports with minimal performance degradation. Also, since time modulation (x(t) noise) is greatly suppressed, cable length variations are compensated for from the points of injection of the correction signal to the ADCs.Experimental Results

[0069] A. Hardware

[0070] This flicker suppression system and method has been implemented and evaluated on a prototype which is composed of three main parts:• Input module.• Backplane.• ZCU102 evaluation board.

[0071] The input module is the most critical part, and features the AD9652 16-bit dual ADC from Analog Devices, and all the electronics and power regulation to support the ADC. The input conditioning is implemented with a simple unbalanced-balanced transformer able to accept frequencies from 1 MHz to 400 MHz, and the module presents an adjustable low-noise voltage reference, and a loosely locked PLL as described in a previous article [9], The input module also features an Artix-7 field programmable gate array (FPGA) to implement the DDCs, and a high-speed serial communication link that sends the phase and amplitude data stream to the ZCU102 evaluation board for processing. These modules also have a temperature controller capable of maintaining constant temperatures of the ADC, voltage reference, and input conditioning circuits. The temperature controller, however, has not been used during the measurements presented.

[0072] The backplane, capable of hosting up to four input ADC modules, provides power conditioning, communication with the ZCU102 computation engine, and the system clock resources. The system clock includes a 1 GHz oscillator, a programmable PLL that generates the ADC clocking frequency, and a AD9912 DDS that produces the correction signal. The system clock may be steered, and it is frequency locked to one or an ensemble of the input signals to avoid moving spurs during the measurement.

[0073] The ZCU102 evaluation board controls and monitors the custom system, and implements decimation chains, Fourier, and Allan deviation analysis pipeline similar to the previous prototype [9], This evaluation board is a temporary solution, and these tasks will eventually be performed by a custom-made plug-in module in a future version.20LEGALM 12447633\6PATENT Atorney Docket No. UOCO.P2113WO / 00676028

[0074] B. Measurement Setup

[0075] Two input modules (four ADC inputs) placed in the first and fourth slots of the backplane are used to evaluate the effectiveness of FSDD. Three main residual measurements are performed at 100 MHz using a NEL O-CDFE Series OCXO oscillator. The first evaluation is performed without the use of FSDD as a reference point, and the input signal power is maximized to cover the full dynamic range of the AD9652 (see plots in FIGS. 6-11). The second evaluation also incorporates a 104.2 MHz correction signal. To maximize the effectiveness of FSDD, and to minimize white noise degradation, the ADC dynamic range is divided equally to accommodate both the 100 MHz and correction carriers (FIGS. 6, 7, and 8). Due to the narrow frequency spacing between the test and correction signals, analog filters are not used, causing the noise sidebands of both signals to overlap. The third and final evaluation has been executed with the correction in the third Nyquist region at 307.25 MHz (FIGS. 9, 10, and 11). According to Eqn. 10, in this last configuration the input buffer flicker-noise suppression is less effective, and it is possible to identify improvements due to aperture jitter and voltage-reference noise removal. Moreover, in this case, band pass filters are used to avoid noise sidebands overlap and the power levels are adjusted to minimize white noise degradation for phase noise.

[0076] In all measurement setups, the ADCs are clocked at 288.312 MHz, the measurement bandwidths are kept constant, and residual phase and amplitude noise are evaluated between inputs of the same modules P1-P0 (Al -A0) and P7-P6 (A7-A6), and inputs from different modules P6-P0 (A6-A0) and P7-P0 (A7-A0). The P indicates phase analysis, while A is for amplitude. The number indicates the input channel number, and inputs from 2 to 5 are missing since the center two slots of the backplane are unpopulated. Finally, the measurements using inputs of the same modules are also cross-correlated. These types of measurements enable the evaluation of the residual performance of the prototype when used as a noise analyzer (cross-correlation and cross-spectrum averaging), or for timescale applications (different input combinations without cross-correlation). To avoid moving spurs during measurements, the system clock is frequency locked to an ensemble of DUT and REF such that the vectors in the 100 MHz dedicated DDCs rotate at 60 Hz. The constant rotation generates a spur, and this frequency has been chosen since a 60 Hz power network spur is expected anyway. The signal is distributed to the four inputs using four two-way Wilkinson power splitter / combiners. The first device is used to combine the 100 MHz carrier with the correction signal (correction port terminated in the first measurement), and the other three are used to split the combined signal in a symmetrical tree fashion. Isolation of the power splitters and 21LEGALM 12447633\6PATENT Atorney Docket No. UOCO.P2113WO / 00676028 impedance matching are important for cross-correlation and cross-spectrum averaging improvements.

[0077] C. 100 MHz Residual Noise

[0078] FIGS. 6, 7, and 8 show the significant advantage of the FSDD technique. Residual phase noise without FSDD measured at 1 Hz offsets £(1 Hz) = —123.7 dBc / Hz when inputs from the same ADC are used, and £(1 Hz) = — 111 dBc / Hz otherwise. Similarly, for residual single-sideband amplitude noise, (1 Hz) = —126.0 dBc / Hz and (1 Hz) = —115.5 dBc / Hz. For both phase and amplitude noise, FSDD suppresses flicker noise by over 35 dB when the correction frequency is very close to the measured signal of 100 MHz. Moreover, all input combinations show similar residual performance within the cut-off frequency (~1 kHz) of the digital low-pass filters on the correction paths. Using FSDD, the system reached phase-noise floors of £(1 Hz) = —147 dBc / Hz with a flicker corner of about 0.03 Hz for all input combinations, and these results may be further improved with the use of cross-spectrum averaging. Single-channel white noise degradation with respect to the non-FSDD case is clearly visible due to the shared ADC dynamic range (above the digital filter cutoff frequency), and also due to correction (below the digital filter cut-off frequency). Crossspectrum averaging also unveils numerous far-from-the-carrier spurs. Due to the presence of two carriers and their harmonics, inter-modulation products, and aliasing, it is difficult to find an ADC clock frequency that yields spur-free spectra when FSDD is used. Moreover, the two carriers’ sidebands overlap due to the lack of analog filters, and because of the limited singlechannel isolation, the ultimate noise floor achieved with cross-spectrum averaging results are limited. The small discrepancy in performance between single channels in the 10-3to 10-2frequency offsets area is suspected to be caused by different temperature coupling between input ports on the same or different modules. By taking advantage of the fact that a dual-input ADC presents highly correlated aperture jitter and voltage-reference noise, the FSDD technique presented may be modified, such that the correction signal may be fed to one of the inputs while DUT or REF is measured on the other (see, for example, the oscillator measurement system 400 of FIG. 4). In this way, white noise and spectral purity performance may be preserved, and different ADC chips will present similar flicker-noise performance to a single chip.

[0079] The residual Allan deviation also shows significant improvements. At 1 s averaging times, the residual frequency stability improved from 3.0 X 10-15and 1.3 X 10-14for inputs on the same module or different modules respectively, to 1.3 x 10-16in both cases22LEGALM 12447633\6PATENT Atorney Docket No. UOCO.P2113WO / 00676028 with a better behavior. More than a factor of 20 improvement in the single-channel noise floor is achieved when FSDD is enabled, and these results may still be further improved with the Groslambert covariance (GCov), as shown in FIG. 8.

[0080] FIGS. 9-11 show results from a measurement setup where the correction frequency has been moved to 307.25 MHz and its power level has been decreased to about of the ADC’s dynamic range, leaving more room for the 100 MHz test signal. FIG. 9 shows that FSDD is less effective for residual phase noise, even though it yields slightly better white-noise performance. Far from the carrier and above the digital low-pass filters’ cut-off frequency the system demonstrates an average below —180 dBc / Hz, while inside the ~1 kHz cut-off frequency the single-channels approach —150 dBc / Hz and the cross-spectrum is instead limited by the poor isolation at the correction signal’s frequency. Close to the carrier, a steeper than flicker behavior is observed and has been attributed to temperature fluctuations causing cp(t)-type disturbances. The residual Allan deviation measurement (FIG. 11) confirms that the system performs identically at 1 -second intervals. However, for some input combinations, it exhibits a plateau between 100 and 1000 seconds, which is a typical range for thermal time constants. Above approximately 400 seconds, the two-sample covariance also reveals correlations between (P1-P0) and (P7-P6).

[0081] The correction signal’s low power causes highly degraded white-noise performance below the digital filters’ cut-off frequency for residual amplitude noise (FIG. 10), and limited improvements in the flicker region. All input combinations show similar residual noise around 1 Hz offset and the residual noise between different modules shows almost 20 dB lower flicker, suggesting that the voltage-reference noise has been successfully corrected for.Conclusions

[0082] The flicker-noise suppression technique advantageously and significantly improves close-to-the-carrier performance in direct-digital measurement systems for both phase and amplitude noise. Time-domain measurements are also significantly improved with this method.

[0083] By evaluating the flicker-suppression technique with correction signals both close and far from the DUT and REF carrier frequencies, the behavior predicted as predicted in Eqn. 10 has been confirmed for phase noise. According to the theory, and confirmed by the presented results, FSDD is more effective when the correction frequency is placed closer to the test carrier (FIG. 4 vs. FIG. 7). However, the amplitude noise model presented in FIG. 2 appears incomplete, as it predicts that improvements in amplitude flicker noise due to the correction23LEGALM 12447633\6PATENT Atorney Docket No. UOCO.P2113WO / 00676028 signal should be independent of frequency and power levels, whereas the experimental results demonstrate a clear frequency dependence (FIG. 5 vs. FIG. 8). A possible cause of this response is the strong dependency of residual amplitude flicker to carrier frequency and power.

[0084] Nevertheless, the prototype built to test the FSDD technique shows, for 100 MHz carriers, a residual single channel Allan deviation of 1.3 x 10-16at 1 second averaging times regardless of which inputs are used, opening the door to multi-channel measurement systems with state-of-the-art performance and capable of measuring and potentially ensembling the current best optical atomic clocks [16, 17], The high effectiveness of FSDD shown in FIG. 4 suggests that residual fractional frequency performance metrics are expected to further improve at higher DUT carrier and ADC clock frequencies. Additionally, single-channel residual Allan deviation in the low 10-17at 1 s intervals for 1 GHz carriers is expected. Unfortunately, the current prototype available does not support these frequencies.

[0085] The high inherent close-to-the-carrier noise of the ADCs limits the use of conventional digital measurement systems to far-from-the-carrier measurements of two-port devices, crystal, and RF oscillators. The FSDD method, with its improved flicker response, enables improvements in close-to-the-carrier noise measurements of two-port components, saving time that would otherwise have been needed for cross-spectrum averaging or the setup of advanced techniques such as carrier suppression [18-20], The absolute phase noise of optical cavities or optical atomic clocks may be measured directly after converting the signals to the RF domain.

[0086] Changes may be made in the above methods and systems without departing from the scope hereof. It should thus be noted that the matter contained in the above description or shown in the accompanying drawings should be interpreted as illustrative and not in a limiting sense. The following claims are intended to cover all generic and specific features described herein, as well as all statements of the scope of the present method and system, which, as a matter of language, might be said to fall therebetween.References[1] G. Colavolpe, “Communications over phase-noise channels: A tutorial review,” 2012, doi: 10.1109 / ASMS-SPSC.2012.6333095.[2] A. Spalvieri, “Non-parametric phase tracking in demodulation and decoding of QAM signals affected by phase noise,” 2017, pp. 1-5. doi: 10.1109 / TSSA.2017.8272900.[3] K. Siddiq, R. J. Watson, S. R. Pennock, P. Avery, R. Poulton, and B. Dakin-Norris, “Phase noise analysis in FMCW radar systems,” 2015, pp. 501-504. doi:24LEGALM 12447633\6PATENT Attorney Docket No. UOCO.P2113WO / 00676028 10.1109 / EuRAD.2015.7346347.[4] J. Grove, J. Hein, J. Retta, P. Schweiger, W. Solbrig, and S. R. Stein, “Direct-digital phase-noise measurement,” 2004, pp. 287-291. doi: 10.1109 / FREQ.2004.1418466.[5] T. Imaike, “Full digital phase noise measurement by using two reference oscillators and multichannel ADCs,” 2017, pp. 583-586. doi: 10.1109 / FCS.2017.8088964.[6] D. A. Howe, A. Hati, C. W. Nelson, and D. Lirette, “PM-AM correlation measurements and analysis,” 2012, pp. 1-5. doi: 10.1109 / FCS.2012.6243729.[7] C. W. Nelson and D. A. Howe, “A Sub-Sampling Digital PM / M Noise Measurement System,” Sep. 2012, doi: 10.1080 / 19315775.2012.11721610.[8] P.-Y. Bourgeois, G. Goavec-Merou, J.-M. Friedt, and E. Rubiola, “A fully-digital realtime SoC FPGA based phase noise analyzer with cross-correlation,” 2017, pp. 578- 582. doi: 10.1109 / FCS.2017.8088963.[9] M. Pomponio, A. Hati, and C. Nelson, “Direct Digital Simultaneous Phase-Amplitude Noise and Allan Deviation Measurement System,” 2024, doi: 10.1109 / OJUFFC.2024.3487147.

[0010] D. Fest, J. Groslambert, and J.-J. Gagnepain, “Individual characterization of an oscillator by means of cross-correlation or cross-variance method,” 1983, doi: 10.1109 / TIM.1983.4315105.

[0011] M. Pomponio, “Oscillator measurement system and method with flicker-noise suppression, provisional patent #63 / 748,774,” 2025.

[0012] M. W. et al. Schioppo M. Brown R., “Ultrastable optical clock with two cold-atom ensembles,” 2017, doi: https: / / doi.org / 10.1038 / nphoton.2016.231.

[0013] Z. Zhiqiang, K. J. Arnold, R. Kaewuam, and M. D. Barrett, “176Lu+clock comparison at the IO"18level via correlation spectroscopy,” 2023, doi: 10.1126 / sciadv.adgl971.

[0014] R. Boudot and E. Rubiola, “Phase noise in RF and microwave amplifiers,” 2012, doi:10.1109 / TUFFC.2012.2502.

[0015] D. L. Creedon, M. E. Tobar, E. N. Ivanov, and J. G. Hartnett, “High-resolution flicker- noise-free frequency measurements of weak microwave signals,” 2011, doi: 10.1109 / TMTT.2011.2125798.

[0016] J. Yao et al., “Optical-clock-based time scale,” Oct. 2019, doi:10.1103 / PhysRev Applied.12.044069.

[0017] C. E. Calosso, “The digital revolution, also for time scales.” 2023. Available:https: / / arxiv.org / abs / 2307.03751

[0018] K. H. Sann, “The Measurement of Near-Carrier Noise in Microwave Amplifiers,” Sep.25LEGALU 12447633\6PATENT Attorney Docket No. UOCO.P2113WO / 00676028 1968, doi: 10.1109 / TMTT.1968.1126783.

[0019] E. N. Ivanov, M. E. Tobar, and R. A. Woode, “Microwave interferometry: Application to precision measurements and noise reduction techniques,” Nov. 1998, doi: 10.1109 / 58.738292.

[0020] A. Hati, M. Pomponio, and C. W. Nelson, “Ultralow PM and AM Noise Generation With an Ensemble of Phase-Coherent Oscillators,” Feb. 2024, doi: 10.1109 / TUFFC.2023.3341726.LEGALU 12447633\6

Claims

PATENT Atorney Docket No. UOCO.P2113WO / 00676028 CLAIMSWhat is claimed is:

1. An oscillator measurement system, comprising:a clock configured to output a clock signal having a clock frequency vc;a frequency source configured to generate first and second synthesized signals, the first and second synthesized signals both having a synthesized frequency v5that is different from the clock frequency vc;a first digitizer time-referenced to the clock, the first digitizer having one or more analog-to-digital-converter (ADC) cores, the first digitizer being configured to (i) generate a first digital signal by sampling a device-under-test (DUT) signal at the clock frequency vc, the DUT signal having a DUT frequency vDand (ii) generate a second digital signal by sampling the first synthesized signal at the clock frequency vc;a second digitizer time-referenced to the clock, the second digitizer having one or more ADC cores, the second digitizer being configured to (i) generate a third digital signal by sampling the second synthesized signal at the clock frequency vcand (ii) generate a fourth digital signal by sampling a reference signal at the clock frequency vc, the reference signal having a reference frequency vR; a first digital down-converter (DDC) configured to demodulate the first digital signal by the DUT frequency vDto generate a first demodulated phase-noise signal; a second DDC configured to demodulate the second digital signal by the synthesized frequency v5to generate a second demodulated phase-noise signal;a third DDC configured to demodulate the third digital signal by the synthesized frequency v5to generate a third demodulated phase-noise signal; a fourth DDC configured to demodulate the fourth digital signal by the reference frequency vRto generate a fourth demodulated phase-noise signal;a first differential circuit configured to generate a first phase-difference signal by subtracting the second demodulated phase-noise signal from the first demodulated phase-noise signal;27LEGALM 12447633\6PATENT Attorney Docket No. U0C0.P2113WO / 00676028 a second differential circuit configured to generate a second phase-difference signal by subtracting the third demodulated phase-noise signal from the fourth demodulated phase-noise signal; anda third differential circuit configured to output a third phase-difference signal by subtracting the second phase-difference signal from the first phase-difference signal.

2. The oscillator measurement system of claim 1, further comprising a spectrum analyzer configured to process the third phase-difference signal to output a noisemeasurement signal.

3. The oscillator measurement system of claim 1, wherein:the first digitizer comprises:a first combiner configured to combine the first synthesized signal with the DUT signal to generate a first combined signal; and a first ADC core configured to generate a first intermediate signal by sampling the first combined signal;the second digitizer comprises:a second combiner configured to combine the second synthesized signal with the reference signal to generate a second combined signal; and a second ADC core configured to generate a second intermediate signal by sampling the second combined signal;the first DDC demodulates the first intermediate signal as the first digital signal; the second DDC demodulates the first intermediate signal as the second digital signal; the third DDC demodulates the second intermediate signal as the third digital signal;andthe fourth DDC demodulates the second intermediate signal as the fourth digital signal.

4. The oscillator measurement system of claim 1, wherein:the first digitizer comprises:28LEGALU 12447633\6PATENT Attorney Docket No. U0C0.P2113WO / 00676028 a first ADC core configured to generate the first digital signal by sampling the DUT signal; anda second ADC core configured to generate the second digital signal by sampling the first synthesized signal;the second digitizer includes:a third ADC core configured to generate the third digital signal by sampling the second synthesized signal; anda fourth ADC core configured to generate the fourth digital signal by sampling the reference signal.

5. The oscillator measurement system of claim 4, wherein:the first ADC core and the second ADC core are co-located on a first multi-channel ADC chip; andthe third ADC core and the fourth ADC core are co-located on a second multi-channel ADC chip.

6. The oscillator measurement system of claim 1, wherein the frequency source is referenced to the clock.

7. The oscillator measurement system of claim 6, wherein the frequency source comprises a phase-locked loop, a direct-digital synthesizer, a frequency divider, or a frequency multiplier.

8. The oscillator measurement system of claim 1, further comprising:a first digital amplifier configured to output a scaled second demodulated phase-noise signal by multiplying the second demodulated phase-noise signal byVD / VS, wherein the first phase-difference signal comprises the scaled second demodulated phase-noise signal subtracted from the first demodulated phasenoise signal;a second digital amplifier configured to output a scaled third demodulated phase-noise signal by multiplying the third demodulated phase-noise signal byVR / VS, wherein the second phase-difference signal comprises the scaled third29LEGALU 12447633\6PATENT Atorney Docket No. UOCO.P2113WO / 00676028 demodulated phase-noise signal subtracted from the fourth demodulated phase-noise signal; anda third digital amplifier configured to output a scaled second phase-difference signal by multiplying the second phase-difference signal byVD / VR, wherein the third phase-difference signal comprises the scaled second phase-difference signal subtracted from the first phase-difference signal.

9. The oscillator measurement system of claim 1, wherein:the first DDC is configured to demodulate the first digital signal by the DUT frequency vDto generate a first demodulated amplitude-noise signal; the second DDC is configured to demodulate the second digital signal by the synthesized frequency v5to generate a second demodulated amplitude-noise signal;the third DDC is configured to demodulate the third digital signal by the synthesized frequency v5to generate a third demodulated amplitude-noise signal; the fourth DDC is configured to demodulate the fourth digital signal by the reference frequency vRto generate a fourth demodulated amplitude-noise signal; and the oscillator measurement system further comprises:a fourth differential circuit configured to generate a first amplitude-difference signal by subtracting the second demodulated amplitude-noise signal from the first demodulated amplitude-noise signal;a fifth differential circuit configured to generate a second amplitude-difference signal by subtracting the third demodulated amplitude-noise signal from the fourth demodulated amplitude-noise signal; anda sixth differential circuit configured to output a third amplitude-difference signal by subtracting the second amplitude-difference signal from the first amplitude-difference signal.

10. The oscillator measurement system of claim 9, wherein:the DUT signal has a DUT amplitude dD;the reference signal has a reference amplitude AR,30LEGALM 12447633\6PATENT Attorney Docket No. UOCO.P2113WO / 00676028 the first synthesized signal has a first synthesized amplitude AS1;the second synthesized signal has a second synthesized amplitude AS2; and the oscillator measurement system further comprises:a fourth digital amplifier configured to output a scaled second demodulated amplitude-noise signal by multiplying the second demodulated amplitude-noise signal by ^D / A wherein the first amplitudedifference signal comprises the scaled second demodulated amplitudenoise signal subtracted from the first demodulated amplitude-noise signal;a fifth digital amplifier configured to output a scaled third demodulated amplitude-noise signal by multiplying the third demodulated amplitude-noise signal by R / , wherein the second amplitude- ' S2difference signal comprises the scaled third demodulated amplitudenoise signal subtracted from the fourth demodulated amplitude-noise signal; anda sixth digital amplifier configured to output a scaled second amplitudedifference signal by multiplying the second amplitude-difference signal by wherein the third amplitude-difference signalcomprises the scaled second amplitude-difference signal subtracted from the first amplitude-difference signal.

11. The oscillator measurement system of claim 1, further comprising:a first amplifier configured to amplify the first synthesized signal; anda second amplifier configured to amplify the second synthesized signal.

12. The oscillator measurement system of claim 1, wherein:the first synthesized signal has a first signal power;the second synthesized signal has a second signal power; andthe oscillator measurement system further comprises:a first attenuator configured to reduce the first signal power; and31LEGALU 12447633\6PATENT Atorney Docket No. UOCO.P2113WO / 00676028 a second attenuator configured to reduce the second signal power.

13. The oscillator measurement system of claim 1, further comprising:a first band-pass filter configured to output a first filtered digital signal by filtering the first digital signal, the first band-pass filter having a first bandwidth that overlaps the DUT frequency vD, wherein the first filtered digital signal is fed into the first DDC;a second band-pass filter configured to output a second filtered digital signal by filtering the second digital signal, the second band-pass filter having a second bandwidth that overlaps the synthesized frequency vs, wherein the second filtered digital signal is fed into the second DDC;a third band-pass filter configured to output a third filtered digital signal by filtering the third digital signal, the third band-pass filter having a third bandwidth that overlaps the synthesized frequency vs, wherein the third filtered digital signal is input into the third DDC; anda fourth band-pass filter configured to output a fourth filtered digital signal by filtering the fourth digital signal, the fourth band-pass filter having a fourth bandwidth that overlaps the reference frequency vR, wherein the fourth filtered digital signal is fed into the fourth DDC.

14. The oscillator measurement system of claim 1, further comprising:a first low-pass filter configured to generate a filtered second demodulated phasenoise signal by filtering the second demodulated phase-noise signal, wherein the filtered second demodulated phase-noise signal is fed into the first differential circuit; anda second low-pass filter configured to generate a filtered third demodulated phasenoise signal by filtering the third demodulated phase-noise signal, wherein the filtered third demodulated phase-noise signal is fed into the second differential circuit.

15. An oscillator measurement method, comprising:generating, with a clock, a clock signal having a clock frequency vc;32LEGALM 12447633\6PATENT Attorney Docket No. U0C0.P2113WO / 00676028 generating, with a frequency source, first and second synthesized signals both having a synthesized frequency v5that is different from the clock frequency vc; outputting, with a first digitizer, (i) a first digital signal by sampling a device-under- test (DUT) signal at the clock frequency vcand (ii) a second digital signal by sampling the first synthesized signal at the clock frequency vc, the DUT signal having a DUT frequency vD;outputting, with a second digitizer, (i) a third digital signal by sampling the second synthesized signal at the clock frequency vcand (ii) a fourth digital signal by sampling a reference signal at the clock frequency vc, the reference signal having a reference frequency vR;demodulating, with a first digital down-converter (DDC), the first digital signal by the DUT frequency vDto generate a first demodulated phase-noise signal; demodulating, with a second DDC, the second digital signal by the synthesized frequency v5to generate a second demodulated phase-noise signal; demodulating, with a third DDC, the third digital signal by the synthesized frequency v5to generate a third demodulated phase-noise signal;demodulating, with a fourth DDC, the fourth digital signal by the reference frequency vRto generate a fourth demodulated phase-noise signal;generating, with a first differential circuit, a first phase-difference signal by subtracting the second demodulated phase-noise signal from the first demodulated phase-noise signal;generating, with a second differential circuit, a second phase-difference signal by subtracting the third demodulated phase-noise signal from the fourth demodulated phase-noise signal; andgenerating, with a third differential circuit, a third phase-difference signal by subtracting the second phase-difference signal from the first phase-difference signal.

16. The oscillator measurement method of claim 15, further comprising processing the third phase-difference signal with a spectrum analyzer to output a noise-measurement signal.33LEGALU 12447633\6PATENT Attorney Docket No. UOCO.P2113WO / 00676028 17. The oscillator measurement method of claim 16, wherein:said outputting the first digital signal and the second digital with the first digitizer comprises:combining, with a first combiner, the first synthesized signal with the DUT signal to generate a first combined signal; andgenerating, with a first ADC core, a first intermediate signal by sampling the first combined signal;said outputting the third digital signal and the fourth digital with the second digitizer comprises:combining, with a second combiner, the second synthesized signal with the reference signal to generate a second combined signal; and generating, with a second ADC core, a second intermediate signal by sampling the second combined signal;said demodulating, with the first DDC, the first digital signal includes demodulating the first intermediate signal as the first digital signal;said demodulating, with the second DDC, the second digital signal includes demodulating the first intermediate signal as the second digital signal; said demodulating, with the third DDC, the third digital signal includes demodulating the second intermediate signal as the third digital signal; andsaid demodulating, with the fourth DDC, the fourth digital signal includes demodulating the second intermediate signal as the fourth digital signal.

18. The oscillator measurement method of claim 15, wherein:said outputting the first digital signal and the second digital with the first digitizer comprises:sampling the DUT signal with a first ADC core to generate the first digital signal; andsampling the first synthesized signal with a second ADC core to generate the second digital signal;34LEGALU 12447633\6PATENT Attorney Docket No. UOCO.P2113WO / 00676028 said outputting the third digital signal and the fourth digital with the second digitizer comprises:sampling the second synthesized signal with a third ADC core to generate the third digital signal; andsampling the reference signal with a fourth ADC core to generate the fourth digital signal.

19. The oscillator measurement method of claim 18, wherein:the first ADC core and the second ADC core are co-located on a first multi-channel ADC chip; andthe third ADC core and the fourth ADC core are co-located on a second multi-channel ADC chip.

20. The oscillator measurement method of claim 15, further comprising:outputting, with a first digital amplifier, a scaled second demodulated phase-noise signal by multiplying the second demodulated phase-noise signal byVD / VS, wherein the first phase-difference signal comprises the scaled second demodulated phase-noise signal subtracted from the first demodulated phasenoise signal;outputting, with a second digital amplifier, a scaled third demodulated phase-noise signal by multiplying the third demodulated phase-noise signal byVR / VS, wherein the second phase-difference signal comprises the scaled third demodulated phase-noise signal subtracted from the fourth demodulated phase-noise signal; andoutputting, with a third digital amplifier, a scaled second phase-difference signal by multiplying the second phase-difference signal byVD / VR, wherein the third phase-difference signal comprises the scaled second phase-difference signal subtracted from the first phase-difference signal.

21. The oscillator measurement method of claim 15, wherein:said demodulating, with the first DDC, the first digital signal by the DUT frequency vDalso generates a first demodulated amplitude-noise signal;35LEGALU 12447633\6PATENT Atorney Docket No. UOCO.P2113WO / 00676028 said demodulating, with the second DDC, the second digital signal by the synthesized frequency v5also generates a second demodulated amplitude-noise signal; said demodulating, with the third DDC, the third digital signal by the synthesized frequency v5also generates a third demodulated amplitude-noise signal; said demodulating, with the fourth DDC, the fourth digital signal by the reference frequency vRalso generates a fourth demodulated amplitude-noise signal; and the oscillator measurement further comprises:generating, with a fourth differential circuit, a first amplitude-difference signal by subtracting the second demodulated amplitude-noise signal from the first demodulated amplitude-noise signal;generating, with a fifth differential circuit, a second amplitude-difference signal by subtracting the third demodulated amplitude-noise signal from the fourth demodulated amplitude-noise signal; and generating, with a sixth differential circuit, a third amplitude-difference signal by subtracting the second amplitude-difference signal from the first amplitude-difference signal.

22. The oscillator measurement method of claim 21, wherein:the DUT signal has a DUT amplitude dD;the reference signal has a reference amplitude AR;the first synthesized signal has a first synthesized amplitude AS1;the second synthesized signal has a second synthesized amplitude AS2; and the oscillator measurement method further comprises:outputting, with a fourth digital amplifier, a scaled second demodulated amplitude-noise signal by multiplying the second demodulated amplitude-noise signal by wherein the first amplitudedifference signal comprises the scaled second demodulated amplitudenoise signal subtracted from the first demodulated amplitude-noise signal;36LEGALM 12447633\6PATENT Attorney Docket No. UOCO.P2113WO / 00676028 outputting, with a fifth digital amplifier, a scaled third demodulated amplitudenoise signal by multiplying the third demodulated amplitude-noise signal byAr / As2, wherein the second amplitude-difference signal comprises the scaled third demodulated amplitude-noise signal subtracted from the fourth demodulated amplitude-noise signal; and outputting, with a sixth digital amplifier, a scaled second amplitude-difference signal by multiplying the second amplitude-difference signal byAd / A, wherein the third amplitude-difference signal comprises the scaled second amplitude-difference signal subtracted from the first amplitude-difference signal.

23. An oscillator measurement system, comprising:a local clock;a frequency source;a first digitizer having one or more analog-to-digital-converter (ADC) cores that are referenced to the local clock, the one or more ADC cores of the first digitizer having one or more analog inputs and one or more digital outputs, the one or more analog inputs of the first digitizer being electrically connected to both a device-under-test (DUT) and the frequency source;a second digitizer having one or more ADC cores that are referenced to the local clock, the one or more ADC cores of the second digitizer having one or more analog inputs and one or more digital outputs, the one or more analog inputs of the second digitizer being electrically connected to both a reference clock and the frequency source;a first digital down-converter (DDC) having a first DDC input that is electrically connected to one of the one or more digital outputs of the first digitizer; a second DDC having a second DDC input that is electrically connected to one of the one or more digital outputs of the first digitizer;a third DDC having a third DDC input that is electrically connected to one of the one or more digital outputs of the second digitizer;LEGALU 12447633\6PATENT Atorney Docket No. UOCO.P2113WO / 00676028 a fourth DDC having a fourth DDC input that is electrically connected to one of the one or more digital outputs of the second digitizer;a first differential circuit having (i) a first input electrically connected to an output of the first DDC and (ii) a second input electrically connected to an output of the second DDC;a second differential circuit having (i) a first input electrically connected to an output of the third DDC and (ii) a second input electrically connected to an output of the fourth DDC; anda third differential circuit having (i) a first input electrically connected to an output of the first differential circuit and (ii) a second input electrically connected to an output of the second differential circuit.

24. The oscillator measurement system of claim 23, further comprising a spectrum analyzer electrically connected to an output of the third differential circuit.

25. The oscillator measurement system of claim 23, the frequency source being referenced to the local clock.

26. The oscillator measurement system of claim 23, further comprising the reference clock.

27. The oscillator measurement system of claim 23, wherein:the first digitizer further comprises a first combiner having a first combiner input and a first combiner output, the first combiner input being electrically connected to the DUT and the frequency source, the first combiner output being electrically connected to the one or more analog inputs of the first digitizer; and the second digitizer further comprises a second combiner having a second combiner input and a second combiner output, the second combiner input being electrically connected to the reference clock and the frequency source, the second combiner output being electrically connected to the one or more analog inputs of the second digitizer.

28. The oscillator measurement system of claim 23, wherein:38LEGALM 12447633\6PATENT Attorney Docket No. U0C0.P2113WO / 00676028 the one or more ADC cores of the first digitizer includes a first ADC core and a second ADC core, wherein:the first ADC core includes a first analog input electrically connected to the DUT;the first ADC core includes a first digital output electrically connected to the first DDC input of the first DDC;the second ADC core includes a second analog input electrically connected to the frequency source; andthe second ADC core includes a second digital output electrically connected to the second DDC input of the second DDC;the one or more ADC cores of the second digitizer includes a third ADC core and a fourth ADC core, wherein:the third ADC core includes a third analog input electrically connected to the frequency source;the third ADC core includes a third digital output electrically connected to the third DDC input of the third DDC;the fourth ADC core includes a fourth analog input electrically connected to the reference clock; andthe fourth ADC core includes a fourth digital output electrically connected to the fourth DDC input of the fourth DDC.

29. The oscillator measurement system of claim 28, wherein:the first ADC core and the second ADC core are co-located on a first multi-channel ADC chip; andthe third ADC core and the fourth ADC core are co-located on a second multi-channel ADC chip.39LEGALU 12447633\6

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