Power supply for reversible logic

Abstract

A reversible logic system comprises a physically rigid structure, a reversible logic circuit configured on the physically rigid structure, and an energy-recycling power supply configured on the physically rigid structure, the energy-recycling power supply being electrically connected to the reversible logic circuit via power-clocks.

Description

Attorney Docket No. DEBEN-1003PCTPATENT APPLICATION POWER SUPPLY FOR REVERSIBLE LOGICCROSS REFERENCE TO RELATED PATENT APPLICATIONS

[0001] The present application claims the priority and benefit under 35 U. S. C. §119(e) of U. S. Provisional Patent Application Serial No. 63 / 749,639 filed January 26, 2025, titled “POWER SUPPLY FOR REVERSIBLE LOGIC.” U. S. Provisional Patent Application Serial Number 63 / 749,639 is herein incorporated by reference in its entirety.

[0002] The present application also claims the priority and benefit under 35 U. S. C. §119(e) of U. S. Provisional Patent Application Serial No. 63 / 765,396 filed February 28, 2025, titled “POWER SUPPLY FOR REVERSIBLE LOGIC.” U. S. Provisional Patent Application Serial Number 63 / 765,396 is herein incorporated by reference in its entirety.TECHNICAL FIELD

[0003] Embodiments are generally related to the field of electronics. Embodiments are also related to the field of computing systems. Embodiments are further related to the field of cold electronics. Embodiments further relate to the fields of reversible and adiabatic logic, cryogenic electronics, superconducting inductors, and computing systems, including quantum computing systems.BACKGROUND

[0004] Reversible logic and computing originated in the 1960s and 1970s as a physicsbased theory aimed at understanding the minimum dissipation of logic circuits, which at the time included vacuum tubes and discrete transistors. The original goal was to test the theory by driving a logic gate with benchtop signal generators and measuring the heat rise.

[0005] Around 1990, DARPA funded R& D to use reversible logic concepts to improve the energy efficiency of computers — a potentially utilitarian use. To date, about a dozen R& DAttorney Docket No. DEBEN-1003PCTPATENT APPLICATIONprograms have fabricated “adiabatic CMOS” test chips. Many of these succeeded at the circuit level, but none have shown promise for competing with CMOS. These projects developed circuit design techniques and circuit families such as 2LAL, S2LAL, RERL, and buses. A reversible logic system may include multiple energy-recycling power supplies operating at different frequencies.

[0006] Understanding the background requires identifying what is missing. Energy flow in a potential utilitarian reversible computer should follow the operational pattern of an electric car. Both use energy from a power source to perform something of value to the user, i.e., logic or turning wheels. Both recycle energy, through reversible logic or the motor running in reverse as a generator. Due to inadequate battery technology, the quest for electric cars was stuck at golf carts for decades. Likewise, the prior art for reversible computers presents a vision of replacing CMOS, but the energy-recycling power supply is only adequate for test circuits.

[0007] While energy-recycling power supplies have little prior art, mathematical expressions for inductance are well understood.

[0008] Independently, High Kinetic Inductance (HKI) material was developed for quantum computing. For example, kinetic inductors from a specific low- Tcsuperconducting foundry are defined by parameters: L□= 8.5 pH / □, w= 0.8 pm minimum wire width, s = 1 pm minimum wire spacing and from a high- Tcfoundry with a Q factor of 1172 and critical current Ic= 2,133.33 A / m.

[0009] The prior art includes multi-layer ( Z-layer) 3D semiconductor fabrication capabilities that can multiply the capability of an integrated circuit by a factor of N. Layered fabrication must be accompanied by a process that can access specific buried layers. One such process, called stair-step etching, creates connection patterns applicable to 3D flash memory.

[0010] The prior art for quantum computing contains cryo-CMOS qubit controllers. These 4 K-class circuits have been successful for few-qubit test circuits, yet some of the reported obstacles for continued scale up include dissipation and noise. Ultra-steep slope transistors are relevant, while other references suggest the additional concern that qubit gates areAttorney Docket No. DEBEN-1003PCTPATENT APPLICATIONsensitive to noise from CMOS transistors.

[0011] Accordingly, there is a need in the art for converting a CMOS design into a functionally equivalent reversible redesign as disclosed herein.Attorney Docket No. DEBEN-1003PCTPATENT APPLICATION SUMMARY

[0012] The following summary is provided to facilitate an understanding of some of the innovative features unique to the embodiments disclosed and is not intended to be a full description. A full appreciation of the various aspects of the embodiments can be gained by taking the entire specification, claims, drawings, and abstract as a whole.

[0013] It is, therefore, one aspect of the disclosed embodiments to provide a method, system, and apparatus for improved electronics.

[0014] It is an aspect of the disclosed embodiments to provide methods and systems for computing.

[0015] It is an aspect of the disclosed embodiments to provide methods and systems for supercomputing applications.

[0016] It is an aspect of the disclosed embodiments to provide methods and systems for quantum computing applications.

[0017] It is an aspect of the disclosed embodiments to provide methods and systems for control systems.

[0018] The aforementioned aspects and other objectives and advantages can now be achieved as described herein.

[0019] Aspects of the embodiments disclosed herein reconceptualize reversible logic as a key part of a computer system that beats CMOS on utilitarian applications — including a scale-up path compatible with Moore’s Law.

[0020] Adiabatic logic uses AC power-clock waveforms. The disclosure illustrates sine waves for reasons explained herein. These AC waveforms vary between ground (henceforth GND) and VR, where VR corresponds to dd in CMOS. As expected, energy flows from the power supply into the circuit when the waveform moves away from its midpoint voltage. In adiabatic logic, energy returns to the supply as the waveform retracts toward its midpoint.Attorney Docket No. DEBEN-1003PCTPATENT APPLICATIONEmbodiments may recycle 90-99% of this energy, significantly lowering heat dissipation in the chip and reducing demand from the power source.

[0021] As provided herein, some disclosures can be applied independently of others; for some use cases, utilitarian reversible logic may be possible using a subset of the disclosures.

[0022] Energy-recycling power supplies can include two-element inductor-capacitor (LC) circuits, henceforth referred to as “tanks.” This disclosure includes inductors that may be fabricated of superconductors and HKI material. In this disclosure, the capacitor is the effective wire-to-wire and gate capacitance of the adiabatic logic circuits.

[0023] Independently, embodiments may also include novel use of a LC network called 4LC (Four-Inductor-Capacitor) that generates power-clocks with automatic phase control and no in-line switches, simultaneously increasing energy efficiency and reducing system complexity. The term “LC network” can refer to both tanks and the 4LC circuit.

[0024] Embodiments may further include integrated inductor variants where energy storage location can be within microns of the logic circuit that uses the energy, thus minimizing resistive losses. This disclosure also includes novel integration methods that apply to larger distances.

[0025] To achieve utilitarian reversible logic, this disclosure includes the CMOS conversion process that transforms a conventional CMOS chip design into a reversible redesign— defined as the integration of an energy-recycling power supply and an adiabatic logic chip, where the resulting chip is functionally equivalent to the original CMOS chip. CMOS conversion includes a replication step where the 4LC or four tanks are transformed into a chip power grid that efficiently distributes power through many electrical connections.

[0026] Another aspect of the embodiments is a method of using HKI material in energyrecycling power supplies. Kinetic inductors have the mathematical behavior of inductors E = ½LI2, but store energy in the E = ½mv2kinetic energy of charge carriers of mass m moving at velocity v. Such inductors currently exist at both low- and high- Tc. Kinetic inductors are essentially composed of HKI superconducting wire, so they have very large Q factors,Attorney Docket No. DEBEN-1003PCTPATENT APPLICATIONaddressing a key limitation of normal metal inductors in energy recycling power supplies.

[0027] One or two kinetic inductance layers may be suitable for qubit controllers, leading to an immediately actionable utilitarian use case. However, the ability to create A / -layer kinetic inductors leads to an important opportunity. HKI layers must be very thin — 40 nm in current processes — and they store energy within their material. This allows kinetic inductors to be layered, multiplying their energy density per unit volume by N. This disclosure includes a process for fabricating N-layer kinetic inductors using a stair-step process and then using the inductors for reversible logic.

[0028] Aspects of the embodiments may also include a scaling process based on fabricating AZ-layer 3D kinetic inductors that will accommodate increasing speeds and power densities needed to compete with CMOS over time. Essentially, semiconductor advances driven by Moore’s Law would be accommodated by increasing the number of HKI layers.

[0029] The hybrid structure also enables reusable reversible logic layouts, which is essentially an extension of circuit design libraries based on “IP blocks.”

[0030] Embodiments thus include the elusive energy-recycling power supply necessary for utilitarian reversible logic. Embodiments may be applicable cryogenic applications with lower power densities — such as quantum computer control systems. Embodiments may also be effective at higher temperatures and for increasingly dense, high-power applications.Attorney Docket No. DEBEN-1003PCTPATENT APPLICATION BRIEF DESCRIPTION OF THE FIGURES

[0031] The accompanying figures, in which like reference numerals refer to identical or functionally similar elements throughout the separate views and which are incorporated in and form a part of the specification, further illustrate the embodiments and, together with the detailed description, serve to explain the embodiments disclosed herein.

[0032] FIG. 1 depicts an overall architecture of a reversible redesign that integrates an adiabatic logic chip with an energy-recycling power supply, in accordance with the disclosed embodiments;

[0033] FIG. 2A depicts steps associated with the CMOS conversion process, which starts with a CMOS conversion base and produces a reversible logic system comprising an energyrecycling power supply and a reversible logic circuit, in accordance with the disclosed embodiments;

[0034] FIG. 2B illustrates aspects of the CMOS conversion process, in accordance with the disclosed embodiments;

[0035] FIG. 3 depicts ramped power-clock waveforms used in reversible logic systems, specifically for four-phase and eight-phase clocking, in accordance with the disclosed embodiments;

[0036] FIG. 4 depicts sinusoidal power-clock waveforms, which provide equivalent energy efficiency while being easier and more efficient to generate using the disclosed power supply, in accordance with the disclosed embodiments;

[0037] FIG. 5 depicts energy flow in a CMOS chip and compares it to reversible logic under sinusoidal and ramped power-clock waveforms, showing how energy is stored and recycled during clock cycles, in accordance with the disclosed embodiments;

[0038] FIG. 6 depicts a schematic of the 4LC circuit, which generates four sine waves with automatic 90-degree phase shifts, enabling full-phase power-clocks in a single, integratedAttorney Docket No. DEBEN-1003PCTPATENT APPLICATIONresonant structure, in accordance with the disclosed embodiments;

[0039] FIG. 7 presents simulation results of the 4LC circuit powering a reversible logic circuit, demonstrating proper operation using stored power for a short time and continuous proper operation when the stored power continually recharges, in accordance with the disclosed embodiments;

[0040] FIG. 8 depicts a rigid structure comprising an adiabatic logic chip and superconducting chip (e.g., YBCO), where the latter has a ground plane on one side and inductors on the other, minimizing magnetic coupling and enabling efficient integration with semiconductor chips, in accordance with the disclosed embodiments;

[0041] FIG. 9A depicts a process flow for fabricating multilayer kinetic inductors using a stair-step etching technique, with alternating layers carrying equal and opposite currents to avoid magnetic flux saturation in superconductors, in accordance with the disclosed embodiments;

[0042] FIG. 9B depicts the stair-step fabrication process for kinetic inductors, in accordance with the disclosed embodiments;

[0043] FIG. 10 shows a top-down cross-sectional view of a multi-layer kinetic inductor, illustrating the geometry of parallel wire segments, insulating gaps, turn regions, and contact points that enable high inductance with minimal area, in accordance with the disclosed embodiments;

[0044] FIG. 11 depicts a scalable array of 4LC circuits arranged in a square or checkerboard configuration, showing how multiple power-supply regions can be integrated to support high-performance, distributed reversible logic systems, in accordance with the disclosed embodiments;

[0045] FIG. 12A depicts the four-to-eight phase converter circuit, which generates eight phase power-clocks from four-phase inputs using a tick-selector and connection matrix, enabling compatibility with other reversible logic families, in accordance with the disclosed embodiments;Attorney Docket No. DEBEN-1003PCTPATENT APPLICATION

[0046] FIG. 12B depicts the reversible converter synthesis, applicable when A / is a multiple of four, in accordance with the disclosed embodiments;

[0047] FIG. 12C depicts the generalized reversible converter synthesis, applicable for any N, in accordance with the disclosed embodiments;

[0048] FIG. 13 depicts detailed implementation of the tick-selector circuit using a 2LAL register stage, illustrating how phase selection is generated over eight ticks and how the resulting waveforms are used to drive reversible logic, in accordance with the disclosed embodiments;

[0049] FIG. 14 depicts a reversible logic system including input from the power source, CMOS that co-exists on the same chip, and recharging options for 4LC — as well as the energy-recycling power supply and reversible logic, in accordance with the disclosed embodiments;

[0050] FIG. 15 depicts a reusable, standardized chip power grid for reversible logic IP, showing power-clock ports at fixed locations with defined capacitance and phase relationships, enabling modular and scalable design of reversible logic circuits, in accordance with the disclosed embodiments;

[0051] FIG. 16 depicts power-clock ports centered on the four-corner intersection point of reversible logic IP regions, in accordance with the disclosed embodiments.Attorney Docket No. DEBEN-1003PCTPATENT APPLICATION DETAILED DESCRIPTION

[0052] The particular values and configurations discussed in the following non-limiting examples can be varied, and are cited merely to illustrate one or more embodiments, and are not intended to limit the scope thereof.

[0053] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which illustrative embodiments are shown. The embodiments disclosed herein can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the embodiments to those skilled in the art. Like reference numerals refer to like elements throughout.

[0054] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and / or “comprising,” a used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0055] Throughout the specification and claims, terms may have nuanced meanings suggested or implied in context beyond an explicitly stated meaning. Likewise, the phrase “in one embodiment” as used herein does not necessarily refer to the same embodiment and the phrase “In another embodiment” as used herein does not necessarily refer to a different embodiment. It is intended, for example, that claimed subject matter include combinations of example embodiments in whole or in part.

[0056] Unless otherwise defined, all terms (including technical and scientific terms) usedAttorney Docket No. DEBEN-1003PCTPATENT APPLICATIONherein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0057] It is contemplated that any embodiment discussed in this specification can be implemented with respect to any method, kit, reagent, or composition of the invention, and vice versa. Furthermore, compositions of the invention can be used to achieve methods of the invention.

[0058] It will be understood that particular embodiments described herein are shown by way of illustration and not as limitations. The principal features can be employed in various embodiments without departing from the scope disclosed herein. Those skilled in the art will recognize, or be able to ascertain, using no more than routine experimentation, numerous equivalents to the specific procedures described herein. Such equivalents are considered to be within the scope of the disclosed embodiments and are covered by the claims.

[0059] The use of the word “a” or “an” when used in conjunction with the term “comprising in the claims and / or the specification may mean “one,” but it is also consistent with the meaning of “one or more,” at “at least one,” and “one or more than one.” The use of the term “or” in the claims is used to mean “and / or” unless explicitly indicated to refer to alternatives only or the alternatives are mutually exclusive, although the disclosure supports a definition that refers to only alternatives and “and / or.” Throughout this application, the term “about” is used to indicate that a value includes the inherent variation of error for the device, the method being employed to determine the value, or the variation that exists among the study subjects.

[0060] As used in this specification and claim(s), the words “comprising” (and any form of comprising, such as “comprise” and “comprises”), “having” (and any form of “having,” such as “have” and "has”), “including” (and any form of “including,” such as “includes” and “include”) or “containing” (and any form of “containing,” such as “contains” and “contain”) areAttorney Docket No. DEBEN-1003PCTPATENT APPLICATIONinclusive or open-ended and do not exclude additional, un-recited elements or method steps.

[0061] All of the compositions and / or methods disclosed and claimed herein can be made and executed without undue experimentation in light of the present disclosure. While the compositions and methods have been described in terms of preferred embodiments, it will be apparent to those of skill in the art that variations may be applied to the compositions and / or methods and in the steps, or in the sequence of steps, of the method described herein without departing from the concept, spirit and scope of the disclosed embodiments. All such similar substitutes and modifications apparent to those skilled in the art are deemed to be within the spirit, scope and concept as defined by the appended claims.

[0062] Utilitarian as used in this disclosure should be understood to suggest something capable of producing useful results without undue experimentation.

[0063] Embodiments disclosed herein can comprise a reversible redesign 130 comprising an adiabatic logic chip 132 and an energy-recycling power supply 131, wherein the adiabatic logic chip and the energy-recycling power supply are incorporated into a physically rigid structure that electrically connect the adiabatic logic chip and the energy-recycling power supply via power-clocks, wherein the energy-recycling power supply powers the reversible redesign. In an embodiment, the energy-recycling power supply generates power-clocks comprising four or more clock signals, each divided into four or more ticks. In an embodiment, the power-clocks generated by the energy-recycling power supply have sinusoidal waveforms. In an embodiment, the reversible redesign and the energy-recycling power supply are co-fabricated on a single substrate, and the rigid structure comprises vias interconnecting metal layers. In an embodiment, the adiabatic logic chip and the energyrecycling power supply are physically separated and physically and electrically connected by one or more of die stacking, hybrid bonding, chiplets, through-silicon vias (TSVs), microbumps, package-on-package, interposers, high- or low-temperature co-fired ceramic structures, or other physical structures for filling the space between elements. In an embodiment, the energy-recycling power supply comprises one or more inductors that resonate with the circuit capacitance of the reversible redesign, forming an LC network that generates sinusoidal power-clocks. In an embodiment, the LC network is configured as aAttorney Docket No. DEBEN-1003PCTPATENT APPLICATION4LC circuit that simultaneously produces four sine-wave power-clocks with 90-degree phase shifts between them. In an embodiment, the energy-recycling power supply includes at least one superconducting inductor. In an embodiment, the energy-recycling power supply includes at least one high-Tcsuperconducting inductor. In an embodiment, the energyrecycling power supply includes at least one kinetic inductor. In an embodiment, the kinetic inductor comprises two layers of HKI material separated by an insulator, the two layers identically formed into an inductor. At one end of the inductor, the layers are shorted together, and at the other end of the inductor the two layers become the two terminals of the inductor.

[0064] In an embodiment an / V-layer multilayer kinetic inductor is disclosed, where N is three or more, and with electrical contacts A and B, comprising N layers of HKI material interleaved with N-1 insulating layers, where all 2N layers are patterned into an inductor shape with terminals named first and second, where all the layers are shorted together at the first terminal, the even-numbered layers are shorted together at the second terminal and form contact A, and odd-numbered layers are shorted together at the second terminal and form contact B.

[0065] In an embodiment, an energy-recycling system comprises a region on the surface of an integrated circuit, power-clock port positions in the region, one or more logic blocks comprising layout geometry for one or more logic circuits within the region and connecting to the power-clock port positions, one or more power blocks comprising layout geometry for an energy-recycling power supply within the region and connecting to the power-clock port positions, wherein every combination of one logic block and one power block, performs the repeating cycle of: transferring energy E in the energy-recycling power supply to the logic circuits, powering their performance of logic functions, transferring energy E back to the energy-recycling power supply. In an embodiment, the number of logic blocks plus the number of power blocks is three or more, and the combination of all logic blocks and power blocks forms a library of layout geometry that can combined to perform logic functions, where the combination is correct by construction. In an embodiment, each logic block i has an associated capacitance Ci, each power block j has an associated inductance Lj, and there exists a frequency equation Ffor the clock rate of a combination as a function of Lj x Cr. F(Lj x Ci), a set of at least two target clock rates { f1f2… } are provided, every logic blocks canAttorney Docket No. DEBEN-1003PCTPATENT APPLICATIONfunction at every frequency, thereby creating a set of logic blocks that can function at any frequency in a specified set based on selecting the appropriate power block. In an embodiment, each 90-degree rotation of the logic block layout geometry causes each powerclock 0i to be remapped to 0( / +i)mod4, wherein a single optimized logic block may be used in any clock phase. In an embodiment the region is within a chip power grid that has the structure of a checkerboard, with the region being designated as black and white depending on its position, each power block is available two forms corresponding to black and white squares on a checkerboard, and the power block circuit is of the form corresponding to the black and white designation. In an embodiment, the system includes one or more other blocks where the layout geometry is based on non-reversible technology including CMOS, non-CMOS logic circuits (e.g., nMOS), analog electronics, non-transistor electronics (e.g., Josephson junctions), or semiconductor electronics augmented with unconventional components (e.g., memristors).

[0066] In an embodiment, a method of creating a four phase-to-specified AAtick waveform converter circuit, comprises (step 1) providing an A / -symbol code word, where the symbols are chosen from the set comprising GND, VR, the four four-phase energy-recycling powerclocks 0o to 03, and “no connection,” where the code word specifies the desired waveform, and an output wire, (step 2) outputting a tick generator circuit with repetition factor N, (step 3) repeating steps 4 to 6 for each symbol / of the code word from symbol 0 to symbol N-1 unless symbol / specifies “no connection,” (step 4) outputting a transmission gate from the source specified by symbol / to the output wire, where the transmission gate connects to both rails of tick selection waveform / , (step 5) if a transmission gate was added in step 4 and symbol / specifies VR, deleting the n-channel FET from the transmission gate just added in step 4, (step 6) if a transmission gate was added in step 4 and symbol / specifies GND, deleting the n-channel FET from the transmission gate just added in step 4 wherein the output now comprises a circuit design that is ready for detailed electrical design and fabrication. In an embodiment, all circuits created by the process, such that the code word used in the process obeys the grammar and semantics defined in the specification, and wherein the resulting structures are capable of generating a waveform suitable for driving reversible logic in a system with four or more phases.Attorney Docket No. DEBEN-1003PCTPATENT APPLICATION

[0067] In an embodiment, a method of converting a CMOS design into a functionally equivalent reversible redesign, comprises (step a) receiving CMOS parameters for power (Pc), clock rate (fc), and supply voltage (Vc), (step b) receiving an architectural description of the CMOS chip, (step c) receiving a floorplan of the CMOS chip, (step d) receiving a gatelevel or register-transfer-level description of the CMOS logic, (step e) converting the gatelevel or register-transfer-level description from CMOS gates to a partially reversible gatelevel description using known reversible logic mappings (e.g., AND-OR-NOT to Toffoli gates, CNOT gates, and retractile cascades), (step f) receiving reversible logic parameters for supply voltage (VR) and clock rate (fR), (step g) receiving correction factors (δleak, δdark, δsize, and δqtr) to account for leakage, dark silicon, gate count, and the four phases of the clocks, (step h) using correction factors to estimate the CMOS capacitance (CR) and the area of the reversible redesign (AR), (step i) computing the required number of layers (Nk) or Q factor (QRtype) for the energy-recycling power supply based on the scaling equations in the specification, (step j) selecting the most suitable option, or deciding no option is suitable, (step k) generating layout geometry for the reversible gates and the energy-recycling power supply. In an embodiment, the CMOS design is part of a problem-solving system, and further comprises simulating the layout geometry to assess the effect of load and process variations under realistic operating conditions, iteratively refining the design based on simulation results, fabricating the layout geometry to create a physical implementation of the reversible redesign called a reversible chip, and integrating the reversible chip into the problem-solving system to achieve reduced power consumption.

[0068] Given CMOS’s dominant position, utilitarian reversible logic will need to match CMOS in function while exceeding CMOS in some way — such as energy efficiency or low noise. Performing CMOS conversion on a utilitarian CMOS chip would assure that the reversible redesign performs a useful function. In contrast, CMOS conversion of test circuits would not create utilitarian reversible logic because test circuits are not utilitarian to start with.

[0069] FIG. 1 depicts overall architecture of a reversible logic system that integrates an adiabatic logic chip with an energy-recycling power supply, illustrating a core aspect of the present embodiments in enabling scalable, efficient reversible computing.Attorney Docket No. DEBEN-1003PCTPATENT APPLICATION

[0070] FIG. 1 illustrates rectangular AC power-clock waveforms 100, DC voltage R 101 (equivalent to dd), sinusoidal power-clocks 110, 4LC circuit 120, reversible redesign 130 energy-recycling power supply 131, and adiabatic logic chip 132.

[0071] Adiabatic logic uses AC power-clock waveforms 100, although the disclosure uses sine waves for reasons explained below. These AC waveforms vary between ground (henceforth GND) and DC voltage VR 101 (equivalent to Vdd in CMOS). As expected, energy flows from the power supply into the circuit when the waveform moves away from its midpoint voltage. In adiabatic logic, energy returns to the supply as the waveform retracts toward its midpoint.

[0072] Embodiments can include a novel LC network called the 4LC circuit 120 that generates power-clocks with automatic phase control and no in-line switches, simultaneously increasing energy efficiency and reducing system complexity.

[0073] Aspects of the embodiments further include integrated inductor variants where energy storage location (i.e. the energy-recycling power supply 131) can be within microns of the circuit that uses the energy in the adiabatic logic chip 132, thus minimizing resistive losses in the reversible redesign 130.

[0074] CMOS conversion

[0075] Fig. 2A depicts the input to, and output of, the CMOS conversion process, where the input comprises the design of a CMOS chip 203 and produces a functionally equivalent reversible redesign comprising an energy-recycling power supply 210 and a reversible logic of adiabatic logic chip 220.

[0076] FIG. 2A further illustrates elements of a Computer system 200, including a power source 201, Network 202, CMOS chip 203, Other chips 204, AND gate 205, functional blocks for processing 206, other services 207, busses 208, cylinders 209, Energy recycling power supply 210, qtr-scale 4LC circuit 215, shrunken 4LC circuit 216, electrical connections 217, Adiabatic logic chip 220, smaller-diameter cylinders 221, position 222, Toffoli gate 225,Attorney Docket No. DEBEN-1003PCTPATENT APPLICATIONfunctional blocks for processing 226, other services 227, busses 228, and cylinders 229.

[0077] Fig. 2B depicts the CMOS conversion process. The method proceeds as follows:• Step 230: Obtain CMOS power (Pc), clock rate (fc), and supply voltage (Vb);• Step 231: Obtain the CMOS an architectural description;• Step 232: Obtain the CMOS floorplan;• Step 233: Obtain the gate-level or register-transfer-level (RTL) description of the CMOS logic;• Step 234: Convert the gate-level description to a partially reversible form using established algorithms (e.g., AND-OR-NOT to Toffoli gates, CNOT gates, and retractile cascades;• Step 235: Determine reversible logic parametersfor supply voltage (VR) and clock rate (fa);• Step 236: Apply correction factors 5 to reconcile CMOS and reversible logic differences;• Step 237: Compute CMOS capacitance (OR) and the area of the reversible redesign (AR);• Step 238: Compute required resources (e.g., number of HKI layers A / k) or minimum performance figures (Q or energy reduction factor) from presented equations;• Step 239: Select the most suitable configuration or reject all options as unsuitable;• Step 240: Generate layout geometry, fabricate the reversible redesign to produce a reversible chip, and replace the CMOS chip in the problem-solving system to realize substantial energy savings.

[0078] This disclosure defines a reversible logic system as CMOS conversion applied to a CMOS chip 203 in a computer system 200, where the reversible redesign, fabricated as a reversible logic chip, replaces the CMOS chip 203. The computer system draws energy from a power source 201, connects to a network interface 202 for receipt of problems and delivery of solutions, and houses a suite of other chips 204 such as auxiliary memory and storage devices. Problem solving proceeds through universal Boolean logic — such as an AND gate 205 — embedded in functional blocks for processing 206 and other services 207, all linked byAttorney Docket No. DEBEN-1003PCTPATENT APPLICATIONbuses 208.

[0079] Reversible logic can deliver energy efficiencies far beyond CMOS. Energy recycling is extraordinarily sensitive to small energy losses. As a result, the architecture illustrated in FIG. 2A integrates the concept of “computer architecture” with a power-system architecture. Thus, utilitarian reversible logic can be integrated into a reversible logic computer along with CMOS, DRAM, etc.

[0080] The CMOS conversion process is illustrated in FIG. 2B. The process illustrated in FIG. 2B turns a CMOS chip design into a reversible redesign. This disclosure emphasizes that the critical missing piece is the energy-recycling power supply 210. Therefore, this disclosure defines the reversible redesign as the integration of an adiabatic logic chip 220 with a realizable energy-recycling power supply 210, as needed for a fully utilitarian reversible logic system.

[0081] The first step 230 in transforming a CMOS chip into an energy-efficient reversible redesign is to obtain the chip’s datasheet, followed by step 231 where its architectural description (e.g. the arrangement of processing 206, other services 207, and busses 208) is obtained. At step 232 the floorplan can also be obtained. This preserves engineering knowledge from the original design and provides a fair basis for quantitative performance comparison. It should be appreciated that the method implicitly applies to entirely new designs, where steps 230-240 are based on planning documents.

[0082] A typical chip datasheet specifies the power supply voltage dd = Vc, where the subscript C henceforth denotes “CMOS,” clock frequency fc, power dissipation Pc, and chip area Ac. Using the familiar power formula, P = CV2f, one can calculate Cc, an equivalent CMOS capacitance relevant for power consumption of the CMOS circuitry.

[0083] Then at step 233, the method includes obtaining a netlist or register-transfer-level (RTL) description. The floorplan maps each gate 205 onto the die surface. Gates are powered through Vc and GND voltages 209.

[0084] Because both CMOS and reversible logic use Boolean gates, CMOS conversionAttorney Docket No. DEBEN-1003PCTPATENT APPLICATIONmay preserve the overall architecture and floorplan. Specifically, the configuration of CMOS AND gate 205, functional blocks for processing 206, other services 207, and buses 208 are mapped to reversible Toffoli gate 225, functional blocks for processing 226, other services 227, and buses 228.

[0085] In the next step 234 CMOS gates are replaced with reversible logic gates using localized transformations. For example, an AND gate 205 may be replaced by a Toffoli gate 225; however, the mapping is not strictly one-to-one. Intermediate signals may need to be reversed or decomputed. Although full reversibility imposes considerable overhead, embodiments can include partial reversibility, which delivers sufficient energy savings while substantially reducing design complexity. The transformation changes the chip area 211.

[0086] The phrase partial reversibility is used in the sense of “reversing the operations of a portion of the gates to reclaim energy, while allowing the remainder to proceed irreversibly because the marginal benefit is negligible.”

[0087] A straightforward, yet highly inefficient, approach to designing the energy-recycling power supply would entail full simulation of the reversible circuit, calculation of each gate’s electrical and thermal load under typical operating conditions, and then crafting a component to meet those detailed demands. Instead, the disclosed embodiments present a scalingbased method that matches the energy-recycling power supply to circuit area through a set of analytic equations.

[0088] Starting in step 235, CMOS chip parameters are used to determine initial reversible logic parameters AR, PR, CR, VR, and / R, where the subscript R henceforth denotes “reversible,” including step 236 for applying multiplicative or additive corrections. In step 237, rescaling equations are used to replicate the qtr-scale 4LC circuit 215 into a chip power grid comprised of an array of shrunken 4LC circuits 216, by computing an area AR for each region. The equations reveal required inductor properties and may demand the use of a metal with conductivity orders of magnitude greater than copper, motivating the adoption of superconducting inductors.

[0089] In step 238, spreadsheet-ready mathematical expressions are used compute theAttorney Docket No. DEBEN-1003PCTPATENT APPLICATIONparameters and performance metrics for various design options, such as legacy approaches and different superconducting inductor styles. In step 239, the designer selects the preferred option.

[0090] In the final step 240, layout geometry for the reversible logic elements including Toffoli gate 225, functional blocks for processing 226, other services 227, and busses 228, and the energy-recycling power supply is generated, the reversible redesign is fabricated, and the system is integrated into the problem-solving computer system 200.

[0091] Ramps, sinusoidal waves, and physics

[0092] In the 1960s, physicists proposed a fundamental lower limit on the order of kT for irreversible logic gates, where k is Boltzmann’s constant, Tis absolute temperature, and kT equals 4.11 x 10’21J at room temperature. Signal generators are envisioned to operate using four-phase power-clocks 300, originally based on ramp waveforms, illustrated in Fig. 3.

[0093] FIG. 3 depicts four-phase power-clocks 300, rectangular power-clock AC waveform 301, ticks 0-3 302, VR DC voltage, equivalent to Vdd 303, GND 304, eight-phase powerclocks 310, eight phase rectangular power-clock 311, and ticks 0-7312.

[0094] Likewise, FIG. 4 depicts four-phase sinusoidal power-clocks 400, sinusoidal powerclock 401, ticks 0-3 402, Vp DC voltage, equivalent to Vdd 403, GND 404, eight-phase sinusoidal power-clocks 410, an eight phase sinusoidal power-clock 411, and ticks 0-7412

[0095] Although reversible logic circuits require DC voltages for ancillary functions such as substrate bias, reset signals, and I / O, they primarily draw power from AC waveforms, such as rectangular power-clock AC waveform 301, that varies between R 303 and GND 304. In ramped clocks, each flat or sloped region is referred to as a “tick,” such as tick 0-3 302, or tick 0-7312.

[0096] Utilitarian deployment of reversible logic, as disclosed herein, requires accounting for power dissipation in both the adiabatic logic chip 132 and the benchtop signal generator, which was renamed an energy-recycling power supply 131 because of its new role. The prior art is ambiguous on whether “adiabatic logic” includes the energy-recycling power supply orAttorney Docket No. DEBEN-1003PCTPATENT APPLICATIONtreats it as a separate subsystem; in this disclosure, the term “adiabatic logic” refers to logic without the energy-recycling power supply.

[0097] Generating the original four-phase power-clocks 300 and eight-phase power-clocks 310 in FIG. 3 requires complex subsystems that achieve percentage efficiencies no higher than the mid-nineties. Therefore, this disclosure exploits the fact that the rectangular powerclock AC waveforms 301 in FIG. 3, resemble four sine waves shifted progressively in increments of 90 degrees or quadrature. This disclosure demonstrates that replacing ramped four-phase power-clocks 300 with four-phase sinusoidal power-clocks 400 has negligible impact on the energy efficiency of the adiabatic logic chip 220, while potentially increasing waveform generation efficiency enough to reach the utilitarian threshold.

[0098] The difference between the waveforms is that ramped clocks include extra time that allows transistors to turn off fully — reducing leakage-related energy loss and making it more likely that an experiment will reach the kT limit. Sinusoidal clocks eliminate such gaps, enabling higher-frequency operation and thus greater throughput for the same number of transistors, bringing the system closer to the “utilitarian” threshold.

[0099] Energy issues in CMOS conversion

[0100] A careful look at energy requirements shows that the path to a utilitarian reversible logic system is not obvious. To further explore CMOS conversion, FIG. 5 illustrates how to convert Pc = Cc Vc2fc into an expression for PR, the power dissipation of the converted system. Energy loss in CMOS arises primarily from charging and discharging the capacitance of signal nodes (Csignai) as they transition between 0 and 1. Since CMOS conversion does not change the semiconductor process, the Csignai values for both technologies are about the same

[0101] FIG. 5 illustrates DC voltage 501, 0-to-1 transition 502, half in Csignai 503, heat 504, graph 510 showing energy flow in reversible logic powered by sine wave clocks reversible wire transition power flow, power flow of the sinusoidal power-clock 513, same time 516, graph 520, power flow of the ramped waveforms 523, alternate 526, φ₀ 511, d / dt φ₀ 512, power waveform 513, from power supply 514, controllable fraction εR 515, andAttorney Docket No. DEBEN-1003PCTPATENT APPLICATIONtimeline 516.

[0102] FIG. 5 illustrates a CMOS energy flow 500, where wire transitions dissipate an average of Esignal= ½CsignalVC2, where Csignai is the node’s capacitance and Vc is the DC voltage 501. A 0-to-1 transition 502 charges Csignai from 0 to Vc, drawing energy Esignai = Csignai c2from the power supply into the chip, shown with a downward arrow to indicate downward flow into the chip consistent with the layout illustrated in FIG. 2. CMOS charges capacitors from a DC source, which is 50% efficient, so this transition dissipates half the energy as heat and stores the other half in Csignal503, indicated by a shorter line ending in a different symbol. The 1-to-0 transition converts stored energy in Csignalinto heat 504. Averaging energy over both transitions yields Esignal= ½CsignalVC2.

[0103] FIG. 5 further illustrates reversible wire transition power flow 510 when driven by sinusoidal power-clocks. (For simplicity, vertical axis labels have been removed, so no subscripts appear on voltages or capacitances.) Since φ₀ 511 is a voltage sine wave (sin t), its derivative d / dt φ₀ 512 is a current cosine wave (cos t), and their product is a power waveform 513 of twice the frequency (sin 2t), representing the power drawn from the energyrecycling power supply.

[0104] When a reversible logic signal transitions from 0-to-1, ½CsignalVR2is drawn from the power supply 514 (indicated by a downward arrow). The 1-to-0 transition recovers most of this energy, returning a controllable fraction εR 515 to the power supply (indicated by an upward arrow). The return fraction can be engineered, though it becomes increasingly difficult as εR approaches 100%. Typical values are εR = 90–99%.

[0105] So far, FIG. 5 illustrates only one clock phase. When four copies of the timelines for energy from the power supply 514 and the controllable fraction εR 515 returned are shifted by 90 degrees, the result is timeline 516, which shows that the four sinusoidal power-clocks continuously deliver and recycle energy.

[0106] The average energy (P= CV2f) entering both CMOS and reversible logic circuits is identical, up to minor corrections. For CMOS, energy enters through large wires, drawn as cylinders 209 approximately to scale. The power supply connections to the reversible chipAttorney Docket No. DEBEN-1003PCTPATENT APPLICATIONcarry the same energy, and are represented by cylinders 229 of equal diameter. These cylinders are drawn off to the side because this disclosure replaces them with one or more innovations (allocated in position 222). In CMOS, energy leaves as heat, whereas εR = 90–99% of reversible logic energy is recycled. This means power source consumption is 10–1% of that in CMOS. Consequently, the power supply connections above the energy-recycling power supply are drawn with smaller-diameter cylinders 221.

[0107] The discussion above reveals the limitations of the prior art. Some energy-recycling power supplies in the prior art show a single pin — which is not the right picture for reaching the utilitarian threshold. Approximately half of the pins on current CMOS chips are devoted to Vddand GND, meaning a 1,000-pin CMOS chip has about 250 Vddand 250 GND pins — drawn as cylinders 209. The previous paragraph showed that power flow between the energy-recycling power supply and the adiabatic logic chip is about the same as between the power source and the CMOS chip — drawn as cylinders 229. Thus, the baseline expectation is that the CMOS conversion of a utilitarian chip would have on the order of 500 pins devoted to the power-clocks.

[0108] Fig. 5 provides a graph 520 that is the equivalent of graph 510 for ramped waveforms. Note that the power flow of the sinusoidal power-clock 513 is smoother than the power flow of the ramped waveforms 523. Observe that sinusoidal clocks are always supplying and recovering energy at the same time 516 while ramped clocks alternate 526. Smoother operation reduces noise and peak current. In a non-integrated system, reducing peak current would reduce concerns about overcurrent in pins. It would also reduce peak current in superconducting wires and inductors, where the limit is defined as peak current / c.

[0109] The following provides exemplary embodiments for the adiabatic logic chip 220 and the energy-recycling power supply 210.

[0110] In an embodiment of a reversible logic system comprising an adiabatic logic chip 220 and an energy-recycling power supply 210, where the adiabatic logic chip 220 and the energy-recycling power supply 210 are incorporated into a physically rigid structure in position 222 that electrically connects the two via power-clocks, powering the reversible redesign of adiabatic logic chip 220. The rigid structure in position 222 can comprise anAttorney Docket No. DEBEN-1003PCTPATENT APPLICATIONabutment of two components (in which case position 222 has zero volume and essentially does not exist) such as conductors on the surfaces of the energy-recycling power supply 210 and adiabatic logic chip 220, or may include additional rigid structures in position 222 that electrically connect the power-clocks to form a rigid structure comprising three component types such as energy-recycling power supply 210, rigid structures in position 222, and the adiabatic logic chip 220. Physical rigidity ensures consistent geometry, making simulation results valid and reducing mechanical misalignment during operation. The rigid electrical connections enable low latency electrical connections between the power supply and the logic circuit, limiting phase shift from long wires. This minimizes energy loss and is essential for accurate operation of reversible logic gates.

[0111] In an embodiment, aspects include further specifying that the energy-recycling power supply generates power-clocks comprising four or more clock signals, each divided into four or more ticks such as ticks 0-3 302, and ticks 0-7 312. With four ticks, this embodiment supports universal logic with no intermediate components or switching losses, thereby minimizing overhead that adds complexity or causes energy loss. This makes direct use of four-tick power-clocks ideal for accelerators. For eight ticks, this embodiment allows use of other reversible logic that include intermediate components and switching losses but can hold data when its clock is turned off (i.e., 0 Hz), resulting in lower dissipation — a feature that may make it preferable for data storage. Six-tick power-clocks and retractile cascade power-clocks have other advantages. Multiple reversible logic families may be used simultaneously, making the energy-recycling power supply in this disclosure a universal solution.

[0112] In an embodiment, aspects include further specifying that the energy-recycling power supply generates four-phase sinusoidal power-clocks 400 and eight-phase sinusoidal power-clocks 410. With sinusoidal waveforms the energy efficiency of adiabatic logic chip 220 is substantially the same as with ramped clocks, but the power-clocks can be generated by the energy-recycling power supply 210 with no switching losses. In this embodiment, analog LC networks may power universal four-phase logic with no intermediate components, thereby minimizing overhead that adds complexity and energy loss. Using the reversible converter synthesis method, sine wave power-clocks become a universal set of reversibleAttorney Docket No. DEBEN-1003PCTPATENT APPLICATIONclocks. Smoother power flow of the sinusoidal power-clocks 513 vs. power flow of the ramped waveforms 523 reduces peak current and noise. In a non-integrated system, this would reduce peak current through hundreds of pins, alleviating concerns about overcurrent in pins. It would also reduce peak current in superconducting wires and inductors, where the limit is defined as peak current / c. This embodiment would be preferred for high-density accelerators where energy efficiency is paramount. It would also be preferred for qubit control where minimization of noise is paramount.

[0113] In an embodiment, aspects include further specifying that the adiabatic logic chip and the energy-recycling power supply are co-fabricated on a single substrate, and the electrical connections 217 comprise vias interconnecting metal layers. This structure has the highest performance due to the small vertical extent of vias leading low resistance, capacitance, and inductance while high horizontal density leads to high current capacity (note that due to artistry, the figure illustrates electrical connections 217 as a large number of vertical lines — and each line appears tall due to the “exploded” view). The embodiment described above is defined as co-fabrication on the same side of the substrate, other embodiments can include co-fabrication on the backside with connection using through-silicon vias (TSVs). Half the pins may be devoted to Vdd and GND for the CMOS chip 203; these embodiments potentially free up those pins for other functions, allowing more pins for logic and hence improved performance for new reversible logic designs. This embodiment can make use of superconducting materials such as niobium nitride (NbN), which offer high kinetic inductance and low losses, as described below.

[0114] In an embodiment aspects include further specifying that the adiabatic logic chip and the energy-recycling power supply are physically separated but physically and electrically connected by at least four additional rigid conductive structures in position 222 to form a rigid structure of at least six components including power supply 210, 4 rigid conductive structures in position 222, and reversible logic of adiabatic logic chip 220. For example, the additional rigid structures could comprise, but are not limited to, die stacking, chiplets, through-silicon vias (TSVs), microbumps, package-on-package, interposers, higher low-temperature co-fired ceramic structures in position 222 and filling the space between power supply 210 and reversible logic of adiabatic logic chip 220. This approach permitsAttorney Docket No. DEBEN-1003PCTPATENT APPLICATIONindependent optimization of each component — for example, but not limited to, updating the logic to mitigate new cyber security vulnerabilities or adjusting the energy-recycling power supply to reduce current crowding. The embodiment is enabled by the feasibility of stacking superconducting inductor layers atop semiconductor wafers, as shown in FIG. 8 and FIG. 9. Leveraging existing packaging technologies ensures compatibility with current semiconductor supply chains and reduces time-to-market.

[0115] Sine waves in quadrature and 4LC

[0116] Embodiments include the 4LC circuit, which generates all four power-clocks in a single circuit, automatically maintaining correct phase relationships while using only four inductors and no switches. Analysis in the preceding section shows that, without this embodiment, the current in a power-clock cylinder 229 would be high, leading to significant energy loss.

[0117] Maintaining a near-90 degree phase relationship between independent powerclocks introduces substantial issues. Aspects of the prior art include adding a complex, active control circuit that continuously adjusts frequencies to maintain proper phase alignment.

[0118] FIG. 6 illustrate a lumped element transmission line 600, 4LC 610 (as a cyclic four-element transmission line), symmetry revealing the parasitic mode 620, line of symmetry 621, connection P0-P2622, and connection P1- 3623

[0119] The 4LC circuit 610 of FIG. 6, is an LC network of four identical L’s and four identical C’s arranged as a lumped-element transmission line 600 of four stages. The four stages are arranged in a cycle 610 with the junctions between inductors labeled points P₀–P₃. As a transmission line, the circuit propagates a sinusoidal power-clock, producing four-phase sinusoidal power-clocks 400 in quadrature at points P₀–P₃. Symmetry analysis reveals both operational and parasitic modes.

[0120] If all L’s have the same values and likewise for C’s, the oscillation frequencies of a tank, the 4LC mode used for power-clocks, and the 4LC parasitic mode differ, as shown in Table 1 below:Attorney Docket No. DEBEN-1003PCTPATENT APPLICATION TABLE 1 / Lc = 1 / (2TT VLC) Standard expression for the resonant frequency of a tank√2 fLC Frequency of the 4LC mode used for power-clocks2 fLC Frequency of the parasitic mode

[0121] The √2 fLC mode produces four sine waves with a 90-degree phase relationship — previously termed “automatic.” Solving the matrix differential equations for the 4LC schematic with identical L and C values yields vector oscillation modes that contain all four voltages in quadrature. If the L and C values differ by a few percent, the phase relationship may deviate slightly (e.g., to 89 degrees or 91 degrees), and the frequency shifts marginally. However, this deviation is uniform across all four power-clocks and would not cause failure like a ¼ Hz drift in one tank relative to the others causing two clock phases to become identical after 1 second.

[0122] Demonstration of sinusoidal power-clocks

[0123] FIG. 7 show a 15KQ plot 700, sine wave overlay 701, generated clocks 702, (fails due to inadequate power) time 703, 5 KQ plot 710, sine wave overlay 711, and generated clocks 712.

[0124] For each 15 kQ plot 700 and 5 kQ plot 710 of FIG. 7, the 4LC circuit was simulated with initial conditions that produced waveforms propagating in the correct direction for four-phase sinusoidal power-clocks 401. Each simulation generated four sine wave overlays 701, and four sine wave overlays 711 that resemble the intended four-phase sinusoidal powerclocks 401. The 2LAL reversible logic circuit described in FIG. 12 and FIG. 13, can be connected to these signals. The resulting generated clocks 702, and generated clocks 712 were correct for the first half of the simulation. The circuit produced eight-phase sinusoidal power-clocks 410, which appear clean in the first half of the chart.

[0125] In an embodiment, an aspect includes further specifying that the energy-recycling power supply 131 comprises one or more inductors that resonate with the circuit capacitance of the adiabatic logic chip 132, forming an LC network that generates sinusoidal power-Attorney Docket No. DEBEN-1003PCTPATENT APPLICATIONclocks. This embodiment implicitly includes capacitance adjustment by adding a Ctrimcapacitor to the reversible logic 132. This configuration leverages the natural energyrecycling properties of LC networks, where energy oscillates between inductor and capacitor with losses defined by resistance R. The energy-recycling power supply provides the inductance; the close proximity of wires to each other and transistor gate capacitances in the reversible logic circuit provide the capacitance. Simulation produces sine wave overlay 711 in FIG. 7, demonstrating sustained, stable oscillation when the inductance and chip capacitance are tuned to resonance and are compatible with the recharging circuit introduced below. This embodiment supports the invention’s utility by enabling on-chip energy recycling.

[0126] In an embodiment, aspects include further specifying that the LC network is configured as a 4LC circuit 120 that simultaneously produces four sine-wave power-clocks with 90-degree phase shifts. Four independent tanks contain four inductors and four capacitors — exactly matching the component count of a 4LC circuit. Both four independent tanks and the 4LC circuit produce four sine waves, but only the 4LC circuit automatically generates them in a 90-degree phase relationship (though it operates at ^2 times the frequency for the same component values). As described in FIG. 6, the 4LC circuit achieves automatic frequency and phase control simply by wiring devices differently, whereas four independent tanks would require a separate control subsystem. The 4LC design directly drives 4-phase 2LAL and supports the reversible converter synthesis method and the four-to-eight phase converter circuit, enabling many other logic families. Thus it provides a “universal” energy-recycling technology for scalable, efficient digital system operation.

[0127] Recharging

[0128] A theoretically lossless 4LC circuit would oscillate indefinitely. However, reversible logic circuits contain transistors with losses and crosstalk, causing total energy to decay in both simulation and reality.

[0129] If the inductors and capacitors have low loss, the simulation can sustain power to the reversible logic for a limited time based on the energy supplied by the simulation’s initial conditions. In the sine wave overlay 701, two curves are shown: the 4LC output values Pnand a simulator-generated reference. The Pnamplitudes decline over time. The circuit failsAttorney Docket No. DEBEN-1003PCTPATENT APPLICATIONdue to inadequate power 703 due to insufficient power available to the 2LAL logic, resulting in a DC voltage. The remedy is to externally recharge the desired oscillation mode while draining energy from unwanted modes.

[0130] FIG. 14 illustrates Energy recycling system 1400 including, conventional electronics 1401, CMOS for reset and other functions 1402, energy recycling circuit 1403, p 1404, Equivalent capacitor 1405, reversible logic 1406, redesign 1407, GND 1408, and drive waveform 1409.

[0131] One method to recharge the 4LC circuit uses conventional electronics to generate four drive waveforms that match the desired power-clocks and inject each through a resistor, as depicted in FIG. 14 as resistor 1410, resistor 1411, and the pair of resistors 1412. The principle is that the resistor transfers energy into or out of each oscillating mode until the amplitude and phase match the drive waveform. In the first 15KQ plot 700, four 15 kQ drive resistors 1410-1412 are too weak, and the circuit failed due to inadequate power 703. In the second 5 kQ plot 710, all four resistors 1410-1412 are a stronger 5 kQ 1410-1412, adequately recharging the circuit, producing a consistent sine wave overlay 711 and generated clocks 712 across the entire chart.

[0132] Alternative implementations may reduce the number of external connections to the power source 221. First consider a single-connection setup, such as a connection through one resistor 1410. As described, the 4LC circuit is based on a bidirectional transmission line. In FIG. 7 15KQ plot 700 and 5KQ plot 710 show simulated initial conditions to create a rightward-propagating wave. However, a single-point drive would produce a superposition of leftward- and rightward-propagating waves, leading to improper operation. Thus, the recharging circuit must favor one direction.

[0133] Reducing the number of sine-wave generators and resistors from four to two by deleting two resistors 1412 and retaining the remaining two, resistor 1410 and resistor 1411, connecting the second generator to an adjacent phase provides the required directionality, recharging the rightward-propagating mode while draining from other modes.

[0134] Building on the alternative above, the two sine wave generators can be replacedAttorney Docket No. DEBEN-1003PCTPATENT APPLICATIONwith three DC voltages (GND, R / 2, and VR). A high-Q resonant circuit does not require continuous drive; it can be briefly connected to recharge the desired mode and discharge others. This additional alternative would apply drive only when the power-clock is within a few millivolts of GND, VR / 2, or VR. Since these deviations are negligible, analog generators can be eliminated and only GND, VR / 2, or VRfrom a DC supply through resistor 1410 and resistor 1411 are needed. This alternative may simplify battery-operated (DC) systems.

[0135] In an embodiment, aspects include further specifying that the LC network is recharged by applying non-recycling drive waveforms to points P₀–P₃ through resistors. This embodiment includes three variants, driving all four points, driving two adjacent points, and driving two adjacent points periodically from DC voltages.

[0136] Q factor and 10x principle

[0137] This section shows that a reversible logic system powered by a 4LC or four tanks can be modeled as an RLC network. This major simplification allows the Q factor to reflect the energy efficiency gain of the reversible logic system.

[0138] The basic operation of reversible logic transfers stored energy Estored between an inductor and the equivalent capacitance Ciogic of the reversible circuit with losses in both the inductor and the reversible circuit. These losses are modeled as the resistance Rsystem= Rinductor+ Rlogic, where Rinductoris the equivalent series resistance of the inductors and Rlogicis the average “on” resistance of transistors when charging capacitive loads, plus the wire resistance in the reversible circuit comprising adiabatic logic chip 220.

[0139] Two equivalent definitions of Q factor exist:Q= 1 / R x yj(LJC) at resonance (1)Q = Estored / Edissipated per cycle = 1 / S. (2)

[0140] Define:Attorney Docket No. DEBEN-1003PCTPATENT APPLICATION

[0141] Qlogicas the Q of the adiabatic logic chip 220;

[0142] Qinductoras the Q of the energy-recycling power supply 210;

[0143] Qsystemas the Q of the reversible redesign of adiabatic logic chip 220 and energy-recycling power supply 210.

[0144] From equation (1):Qsystem= 1 / Rsystem× √(Linductor / CR) (3)

[0145] From the equation (2), subject to corrections:Qsystem= 1 / εsystem= PC / PR(4)

[0146] representing the energy efficiency improvement from reversible logic.

[0147] The “10x better principle” states that a commercial offering must be at least ten times superior to competitors to achieve commercial success. We use Qsystem > 10 as a threshold requirement for a utilitarian reversible logic system.

[0148] For reference, Q factors combine like resistors in parallel: Q1|| Q2= 1 / (1 / Q1+ 1 / Q2).

[0149] Thus:Qsystem= Qlogic|| Qinductor, (5)

[0150] evaluated at the resonant frequency fRusing Linductorand CR.

[0151] If a reversible system has Rsystem= Rinductor+ Rlogic, the Qinductorand Qlogiccan be computed independently from resistances, and the overall superiority factor, Qsystem, can be determined.

[0152] Explaining the CMOS Conversion Process Using an ExampleAttorney Docket No. DEBEN-1003PCTPATENT APPLICATION

[0153] The following sections explain CMOS conversion using a narrative based on a series of equations with exemplary numerical values. The narrative first sets up the problem through a series of equations and then divides the single qtr-scale 4LC circuit 215 into regions containing a shrunken 4LC circuit 216. The regions are analyzed for different inductor types and different use cases. The numerical part of the narrative uses parenthetical expressions containing an equal sign and the numerical value, like Pi(= 3.1415). The equations are then reapplied with alternative parameters to show the benefit of various innovations. The equations can be entered into a spreadsheet to construct a roadmap or parameter sweep using the “plot” function. This is meant to be exemplary, and it should be appreciated that in other embodiments, other values are possible.

[0154] Say the CMOS design being converted has area Ac (= 1 cm2), power supply voltage Vc = Vdd (= 1 V), clock rate fc (= 1 GHz), power dissipation Pc (= 100 W), and other properties listed below.

[0155] Using the standard CMOS power equation (P = y^CV2 / ), the effective capacitance of the CMOS circuit is:CC= 2PC / (VC2fC) (= 0.2 μF), (6)

[0156] where Cc is the equivalent capacitance of the CMOS circuit for power purposes.

[0157] The following corrections are pertinent:• δleak(= 0.8) leakage current overestimates CCby 20%;• δdark(= 2) 50% dark silicon underestimates CCby a factor of 2;• δsize(= 1) reversible logic uses more gates than CMOS per equivalent function; • δqtr(= ¼) one clock phase.

[0158] Applying the corrections yields:Aqtr = Ac X 5qtr (= 0.25 cm2), (7)Cqtr= δleak× δdark× δsize× δqtr× CC(= 0.08 μF) (8)Attorney Docket No. DEBEN-1003PCTPATENT APPLICATION

[0159] where the subscript qtr henceforth describes a variable that applies to one clock phase of the reversible logic chip, where Aqtris the reversible logic area pro-rated to one clock phase, and Cqtris the CMOS capacitance for one clock phase after corrections that reverse CMOS effects not applicable to reversible logic.

[0160] Integrated inductors and scaling to a specific frequency

[0161] Embodiments include reversible-logic systems that integrate the qtr-scale 4LC circuit’s 215 inductors directly into the adiabatic logic chip 220. The shrunken 4LC circuit 216 is replicated a specific number of times to tune the resonant frequency to a user-specified clock rate. Using the resonance directly avoids high-power switching components and creates a chip power grid where many electrical connections 217 deliver and recycle energy very close to where it is used, minimizing phase shift and resistive loss. The following sections develop these considerations for various inductor types and materials.

[0162] Kinetic inductors. The following parameters could be representative of low- Tcsuperconducting kinetic inductors.L□(= 8.5 pH / □)w (= 0.8 μm) minimum wire widths (= 1 μm) minimum wire spacing (9)

[0163] Fig. 10 depicts the contacted kinetic inductor shape 1010 that approaches the asymptotic limit of energy density. The core section 1011 includes parallel wire segments of width wat minimum spacing s, connected in series by an outer turn region and contact areas 1013-1016. The turn region reverses current flow; the wires in the turn must be wider and have a minimum radius to mitigate current crowding that would exceed the critical current / c. To provide enough room for the minimum radius turn, the wire pitch must increase, which is accomplished by tilting the core wires relative to the turn region.

[0164] The turn and contact regions occupy negligible space in the asymptotic limit as device size increases. The core region then comprises Aqtr / (w x (w+s)) sub-regions each containing a w x w square and an insulating gap of s × w. The total wire length equals Aqtr / (w x (w+s)) (= 17.4 M) squares. These expressions apply for any wgreater than the minimumAttorney Docket No. DEBEN-1003PCTPATENT APPLICATIONwidth.

[0165] Thus the inductance is:Lk= L□× Aqtr / (w × (w+s)) (= 148 μH), (10)

[0166] where the subscript k henceforth denotes “kinetic.”

[0167] Since Lkscales linearly with area, the scaling exponent is Σk= 1.

[0168] Meander inductors. For normal metal and non-kinetic superconductors, the approximate monomial formula is used:Lm= 0.0026 a0.0603h0.4429N0.954d0.606W0.173(11)

[0169] Where the subscript m henceforth denotes “meander,” a is lead length, h is meander height, N is number of meanders, d is meander spacing, IV is wire width, and s = 0.

[0170] This disclosure uses an asymptotically dense square geometry where a = d / 2, l = len = h + W, and W = d. Under these conditions, Lm(= 144 nH) based on previous parameters.Lmscales as A0.4681for fixed N, so Σm= 0.4681 (12)

[0171] Spiral inductors. Spiral inductors — of both normal metal and non-kinetic superconductors — are approximated by:Ls= 0.635 μ0N2davg[ln(2.07 / ρ) + 0.18ρ + 0.13ρ2] (13)

[0172] where the subscript s henceforth denotes “spiral.” This disclosure uses an asymptotically dense geometry with davg= 0.635 and ρ = 1. Thus, Ls(= 63 nH), and Lsscales as A½for fixed N so Σs= ½.

[0173] Scaling area and frequency. The resonant frequency of the inductance computedAttorney Docket No. DEBEN-1003PCTPATENT APPLICATIONabove and the capacitance Cqtrwill generally differ from the user specified fR. To shift the frequency to fR, this disclosure subdivides Aqtrinto regions. As the area of a region shrinks, both capacitance and inductance shrink, raising the resonant frequency. The initial frequency is:fqtrjype = V2 I (2TT V(LtypeCqtr)), (14)

[0174] where “type” in a subscript henceforth denotes the inductor type (k, m, or s), Zqtrjype is the resonant frequency when the area of the inductor and capacitor is Aqtr, and the 2 factor is due to the 4LC circuit and should be removed when the formula is applied to four tanks.

[0175] The critical scaling step is illustrated in FIG. 2 as the transition from the qtr-scale 4LC circuit 215 to regions with a shrunken 4LC circuit 216. This step scales the inductors areally and connects them to a subset of the reversible logic circuit of equal area. This scaling is replicated to fill the original area of qtr-scale 4LC circuit 215. Since the reversible logic circuit is presumed to have equal capacitance per unit area, this step reduces capacitance per region by the replication factor:A / Rtype = (Zh / Zqtrjype)2'(1 +ItyPel, (15)

[0176] where NRtypeis, the number of regions needed to shift the resonant frequency to fR, for each inductor type, and note that if NRtypeis not an integer the value should be rounded up.

[0177] The step just described has some unusual properties that deserve an intuitive description. Imagine the schematic diagram of an adiabatic circuit drawn on a piece of paper. The parameter NRtypeeffectively uses scissors to cut the paper into NRtypepieces of equal size, using cuts do not necessarily follow any boundary in the original schematic. Then, the schematic on each piece of paper is implemented with a separate shrunken 4LC circuit, whose inductance scaled according to a power law with potentially irrational exponent (such as Σm= 0.4681). While the neighboring pieces of the original schematic end up powered by different power supplies, all the power supplies provide the same voltage.

[0178] Based on the above parameters and equations:Attorney Docket No. DEBEN-1003PCTPATENT APPLICATION• NRk(= 1,527) (kinetic inductor)• NRm(= 40) (meander inductor)• NRs(= 100) (spiral inductor),• with N = 4 meanders or turns

[0179] These equations show how to scale a successful test chip into a utilitarian reversible logic system. From the design of a successful test chip, the designer updates the CMOS parameters (with C subscripts) to correspond to a “utilitarian” CMOS system and applies correction factors, yielding reversible logic parameters (with R subscripts). The equations above specify the number of regions and their parameters, allowing design of the required inductor.

[0180] Generally, the quality factor Qnductor is needed to proceed. However, superconducting inductors have zero wire resistance, so their Q-factor will be high enough not to affect the design process, and the design may proceed. A superconducting embodiment is described next, followed by an analysis of resistance for normal metal inductors.

[0181] In an embodiment, aspects include further specifying that the energy-recycling power supply includes at least one superconducting inductor. Superconducting inductors — including those made from niobium nitride (NbN) and yttrium barium copper oxide (YBCO) — exhibit zero resistive loss and high kinetic inductance, enabling high-frequency, low-loss sine wave generation. This is critical for maintaining a high Q-factor and achieving 90-99% energy recycling efficiency and thus forms the difference between operation at high loss (15KQ plot 700) which fails due to inadequate power 703 and 5KQ plot 710 where the generated clocks 710 do not fail. The use of superconductors is supported by existing cryogenic fabrication processes used in quantum computing and for YBCO inductors with measured with a Q-factor of 1172 and can be suitable for an immediately actionable reversible logic system. This embodiment enables significant performance gains over normal metal inductors, such as copper, and is essential for achieving the 10x energy efficiency improvement of the “10x principle” (Qsystem > 10) to create a utilitarian reversible logic system.Attorney Docket No. DEBEN-1003PCTPATENT APPLICATION

[0182] Non-superconducting meanders and spirals

[0183] The next step is to add equations for the resistance of normal metal inductors; this disclosure defines:

[0184] h = min(10 pm, w), where h is the thickness of an integrated circuit metal layer and w is the width of a wire. For this disclosure, thin wires may not be taller than they are wide, and top-level metal may not exceed 10 pm in thickness.

[0185] The expression for h requires comment. To fairly compare CMOS with its reversible redesign, both must use the same semiconductor process. The expression for h is based on a survey of current CMOS processes. If a fair comparison is not needed, the expression can be fine-tuned for a specific CMOS process, or could ask a foundry to create a variant of the CMOS process for reversible logic.

[0186] LRm(= 2.55 nH) (16)

[0187] where LRmis the inductance computed from the meander inductance formula applied to area Aqtr / NRm,CRm= Cqtr / NRm(= 1.99 nF) (17)RRm= (2 N h + 2 h) / (h w) × ρcopper(= 0.189 Ω) (18)

[0188] where F? Rm is the resistance of the meander, calculated from the wire length (2 N h + 2 / 7) divided by the cross sectional area (h w), multiplied by copper resistivity pcoPPer (=1.68x10’8).LRS (= 6.33 nH) (19)

[0189] where LRsis the inductance computed from the spiral inductance formula applied to area Aqtr / NRs.CRs= Cqtr / NRs(= 0.8 nF) (20)Attorney Docket No. DEBEN-1003PCTPATENT APPLICATIONHRRs= ½ √(Aqtr / NRs) / (h w) × ρcopper(= 0.214 Ω) (21)

[0190] where RRsis the resistance of the spiral, derived from half the edge length times four times the number of turns divided by cross-sectional area (h w) multiplied by copper resistivity.

[0191] In summary, based on Q = 1 / R × √(L / C):QRm(= 5.98) (meanders) (22)QRS (= 13.15) (spirals) (23)

[0192] These values reveal limitations of prior art. At 5.98, QRmis below the minimum required by the 10× principle, but QRsis above the limit by 32%. In this case, integrated spiral inductors rely on magnetic fields extending out-of-plane in both directions by approximately the diameter of the coil (equivalent to the edge length of the region), reducing Q. This can be mitigated by inserting a shield or ground plane between the reversible logic and the chipcutting off half the field would halve the inductance, placing spiral inductors below the limit. There are other losses and overheads as well.

[0193] Although the Q factors indicate limited potential for the exemplary use case, a 4LC configuration — or four tanks — with normal metal inductors may advance the state of the art in low-energy-density applications. For instance, implantable medical devices and wearable electronics operating on harvested energy.

[0194] Superconducting but non-kinetic meanders and spirals

[0195] Meanders and spirals fabricated from superconducting wire have zero resistance, but superconductivity breaks down when current reaches the critical current lc. For this disclosure Imax= Icw, where Imaxis the maximum current in the wire, w is the width of the wire, and Icis defined for a wire trace of a specific height.

[0196] Representative performance of a spiral YBCO inductor in an ion trap quantumAttorney Docket No. DEBEN-1003PCTPATENT APPLICATIONcomputer could be a maximum current of 0.64 A through a 300 pm-wide wire, corresponding to Ic,traphub= 2,133.33 A / m. Based on the above parameters and equations, the wire operates at 75% utilization (meander) and 48% utilization (spiral). These hig h- Tcinductors would have electrical parameters of Qtraphub= 1,172, considerably greater than QRm(= 5.98) and QRs(= 13.15) presented earlier and providing substantial headroom for a reversible logic system including a power supply 210 and adiabatic logic chip 220 with energy efficiency improvements over CMOS.

[0197] In an embodiment, aspects include further specifying that the energy-recycling power supply includes at least one high-Tc superconducting inductor — such as YBCO, rare-earth barium copper oxide (REBCO), or any superconductor with a Tc above 77 K (liquid nitrogen) that can be reliably formed into inductors. High-Tc superconductors enable simpler and more energy-efficient cooling apparatus, making the system more accessible and cost-effective for broader applications.

[0198] FIG. 8 shows a YBCO reversible logic chip 800, inductor layer 801, inductor reference area A 802, equivalent capacitor 803, reversible logic semiconductor chip 804, ground plane 805, and path 806.

[0199] As shown in FIG. 8, a YBCO reversible logic chip 800 can include YBCO-based inductor layer 801 and a ground plane 805 on opposite sides of a sapphire substrate 804. This structure exposes one side of a superconducting inductor to empty space, thus providing a region for the storage of magnetic energy. However, the logic circuitry is shielded from the inductor by the superconducting ground plane 805. As an independent alternative, high-Tc HKI material also has kinetic inductance, allowing this embodiment to function with layered kinetic inductors 801. This embodiment is especially relevant for intermediate-term deployment where cryogenic CMOS circuits can be incrementally converted to reversible logic.

[0200] In an embodiment, aspects include further specifying that a tested and characterized high- Tcinductor design (or the actual parts, if available), is used as the inductors in a complete reversible logic system. Four copies of the inductor would form the energy-recycling power supply 210, either as a 4LC circuit or as four synchronized tanks. AAttorney Docket No. DEBEN-1003PCTPATENT APPLICATIONmatching adiabatic logic chip 220 could be based on small-scale four-phase reversible logic circuits potentially scaled up.

[0201] Furthermore, high- Tcsuperconducting integrated circuits can be used to produce additional superconducting inductor designs with varied power levels and operating frequencies. This could generally enable utilitarian reversible logic systems at high-Tctemperatures.

[0202] In an embodiment, aspects include further specifying use of the YBCO reversible logic chip 800 of FIG. 8 as a rigid structure in position 222 for high-7“csuperconducting meanders and spirals. In the figure, the YBCO chip is slightly smaller than the semiconductor chip, allowing assembly by inserting the YBCO chip along the path 806. In an embodiment, sapphire wafers can be coated with YBCO on both sides (e.g. inductor layer 801 and ground plane 805) and one or both sides can be patterned. The sapphire substrate 804 is positioned to fill the space between the inductor layer 801 and ground plane 805. To reduce magnetic coupling to the circuit, the bottom side (from the perspective of FIG. 8) is a large ground plane 805, and the top side is patterned with YBCO inductors 801. The conductive interposer structures 803 bond to metal pads on the adiabatic logic chip 132 and extend over the top of the YBCO chip, where they can be soldered (using a bespoke soldering method for YBCO) 802. A non-conductive interposer body (not shown) can rigidly hold the structures while inserting the YBCO chip along the path 806 for soldering to YBCO 802. The illustration shows two power-clock phases, but the full perimeter of the chip is available for additional conductive interposer structures 803. The structure of YBCO reversible logic chip 800 in FIG.8 can be modified to support a multi-layer stack of several YBCO chips of progressively smaller size.

[0203] Kinetic inductors and energy content

[0204] The process above includes the non-intuitive step of raising a variable to the 2 / (1+Σtype) power, but the equivalent process for kinetic inductors is simple. A kinetic inductor must have enough energy capacity EKto hold the energy in the capacitance of the reversible logic ER:Attorney Docket No. DEBEN-1003PCTPATENT APPLICATIONEK ≥ ER (24)

[0205] subject to corrections discussed below, where:EK =1 / 2L□ / c2, (= 26.6 pJ / m2) (25)(subject to corrections)ER =1 / 2CR R2, (= 1.6 mJ / m2) (26)(subject to corrections)

[0206] Unlike a normal-metal meander, the kinetic energy is within the wire, so the wire needs to be surrounded by just enough insulating material to prevent shorts to adjacent structures. This enables layering, with the following expression computing the minimum number of layers: / Vk = ER / EK (= 60.2) (27)(subject to corrections)

[0207] Kinetic inductance originates from charge-carrier momentum and can exceed the magnetic or geometric inductance by an order of magnitude or more. Moreover, a kinetic inductor does not require empty space for magnetic-field energy. These properties enable the fabrication of superconducting inductors with lower loss and higher inductance, stemming from both the HKI material and multiple layers.

[0208] It is easy to show that the energy capacity of a one square meter kinetic inductor is1 / 2L□ / c2. Further thought reveals that the energy capacity of HKI material in any shape will be1 / 2LD / C2per unit area— subject to the constraint that the current in every location is the same.

[0209] Corrections. The simple equation EK > ER above must be corrected to allow for manufacturing variance of / c and to recognize that sinusoidal signals express voltage and current as Vrmsand Irms.

[0210] Fig. 10 shows the fraction of the meander shape is filled with HKI material, and thisAttorney Docket No. DEBEN-1003PCTPATENT APPLICATIONfraction is a correction. Consider removing one of the meanders, but avoiding a gap by making the wire wider. Overall, this will make the inductor’s wire shorter and thicker, lowering the inductance. Since removing a meander minimally affects the fraction of the shape filled with HKI material, the energy capacity will be about the same regardless of the inductance.

[0211] Materials. Niobium-class superconductors operate near 4 K; high-Tc superconductors exhibit similar behavior up to about 93 K (YBCO). Embodiments may include high-Tc superconductors with high kinetic inductance. As described herein, niobium and NbN represent low-Tcmaterials, while YBCO represents high-Tc materials

[0212] Embodiments may include superinductors - inductors that exceed the vacuum limit imposed by magnetic fields in free space. Because kinetic inductors rely on charge-carrier momentum rather than magnetic fields, such limitations are irrelevant, thereby opening a path to kinetic superinductors. HKI inductors have reported values that exceed the vacuum limit.

[0213] Consequently, the kinetic inductors described herein can be low- or high-Tc and can function as superinductors.

[0214] Layering. Two forms of layering are covered below. Integrated circuits can have multiple wiring layers, but each wiring layer must be lithographically patterned. The cost and probability of defects make more than about a dozen such layers impractical. This disclosure presents use cases with a few layers.

[0215] Commercial 3D flash-memory chips contain over 200 layers and sometimes up to 1,000 layers or more. While having many layers, this type of processing requires one lithography step for all the layers. Embodiments disclosed herein include a method of creating layered kinetic inductors using common lithography and applying it to energyrecycling power supplies.

[0216] Availability. Take an exemplary case of one HKI layer in niobium-based integrated circuits, including niobium nitride (NbN), and associated design rules and performance parameters. Consider fabrication of two layers. Representative parameters are:Attorney Docket No. DEBEN-1003PCTPATENT APPLICATION

[0217] / c(= 2.5 mA / pm = 2,500 A / m) (28)(critical current), / max (= IcW = 2 mA)(maximum current on a minimum-width wire) (29)

[0218] The numerical computations above yielded NR = 60.2 layers (with no corrections applied), indicating that the use case in the narrative requires multi-layer kinetic inductors.

[0219] To maintain continuity, this disclosure diverts to a cryo-CMOS use case that can be achieved with one or two HKI layers. The second section below returns to the original use case with the disclosure of 3D kinetic inductors.

[0220] Cryo-CMOS conversion

[0221] Consider a case where a few HKI layers are fabricated. The table below shows that one or two layers are sufficient to perform CMOS conversion on cryo-CMOS quantumcomputer controllers. This results in a reversible redesign that meets the threshold for utilitarian reversible logic. The ~4 K cryo-CMOS controllers’ interface with qubits operating at millikelvin temperatures, where low power is critical. Qubits are also noise sensitive, so sinusoidal power-clocks may offer an advantage because of their smooth power waveforms 513 compared with CMOS’s abrupt 0-to-1 transitions 502 and the power flow of the ramped waveforms 523. Using the equations above but overriding parameters as shown below, the required number of HKI layers decreases:TABLE 2CMOS conversion of a representative qubit controller to reversible logicfR = 100 MHz fR = 100 MHz Operating frequency (qubits only)VR = 0.4 V VR = 0.497 V VR based on VC = 1 VPc = 13 W Pc = 17 W Pc based on original 100 WL□ = 11 pH / □, L□ = 11 pH / □, Inductance per square, was L□ = 8.5 pH / □ w = 28.8 μm w = 34.4 μm Wire width (same spacer), was 0.8 μm1 layer 2 layers Energy shortfall / number of HKI inductorlayersAttorney Docket No. DEBEN-1003PCTPATENT APPLICATION

[0222] Thus, a cryo-CMOS controller can be converted to four-phase reversible logic, based on the concepts above, subject to the following considerations:• The conversion applies only to the CMOS logic, not the analog circuits.• The conversion applies only to the operating speed when interfacing to qubits (100 MHz). Testing of the cryo-CMOS chips may use speeds 1 GHz or more, but these higher speeds are not necessary to support utilitarian use.

[0223] In an embodiment, aspects include further specifying that the energy-recycling power supply includes at least one kinetic inductor. Kinetic inductors do not require empty space for magnetic-field storage, allowing dense, compact designs that scale efficiently with area. The inductance per unit area (.□) is size independent, so the energy density of the system remains constant as chip size increases. This property enables scalable design — higher power density applications simply require additional layers of kinetic inductor material. The embodiment is enabled by current foundries offering HKI layers in niobium-based processes and is directly linked to the scalability roadmap described in the scalability section.

[0224] The embodiment has alternatives depending on how it is applied. The embodiment applies to heterogeneous integration of the energy-recycling power supply 210 and adiabatic logic chip 220 provided that the HKI material can be fabricated directly onto a semiconductor chip — for which many current low- Tcoptions exist. A second embodiment can include the manufacture of kinetic inductors separately and integrating them with additional rigid conductive structures in position 222 or structures such as YBCO reversible logic chip 800 of FIG. 8. The use of kinetic inductors supports, but does not require, disclosure of multilayer HKI below and the claim that scaling up the number of HKI layers is compatible with Moore’s Law, since increasing chip density can be met by adding more layers without performance degradation.

[0225] In an embodiment, aspects include further specifying that the reversible redesign results from converting a cryo-CMOS quantum computer controller. This could apply to the cryo-CMOS chips, and it could also apply to new designs with similar functions.Attorney Docket No. DEBEN-1003PCTPATENT APPLICATION

[0226] Ultra-steep slope. Aspects include a cryo-CMOS process with transistor parameters rebalanced for quantum-computer use down to temperatures around1 / 2 K. Ultrasteep slope permits operation with dd in the tens of millivolts, achieving a substantial power reduction. Furthermore, as illustrated in FIG. 5, reversible logic does not have CMOS switching noise. Thus, applying CMOS conversion to a CMOS chip using ultra-steep slope transistors offers both lower power and lower noise.

[0227] In an embodiment, aspects include that the reversible redesign uses an “ultrasteep” slope CMOS process. Kinetic inductance remains stable at temperatures down to1 / 2 K where the large Vdd reduction would substantially reduce the required number of HKI layers — or enable a substantially more complex circuit. A utilitarian tradeoff would be to increase the complexity of the use case until a single kinetic-inductor layer is fully utilized. Without reversible logic, CMOS (including ultra-steep CMOS) generates multi-GHz switching noise that interferes with sensitive signals (including qubits and sensed data). The embodiment is general but could also be combined with several specific use cases: (a) For quantum computer control the system-level advantage is that more qubits could be supported, and the qubits would have local control. Local control offers greater precision because it operates on the same temperature stage and improves the fidelity of qubit operations, (b) For sensor arrays with integrated readout, the lower operating temperature would allow in situ operation with sensor elements for progressively longer-wavelength images.

[0228] Aspects of the disclosed embodiments can provide more energy-efficient control electronics, allowing more qubits in a quantum computer, advancing quantum computing and satisfying the utilitarian use case standard.

[0229] High-Tc superconductors such as YBCO exhibit kinetic inductance and are preferred for many applications because of their higher operating temperatures. These superconductors can be integrated into 3D chips, chip stacking, interposers, etc., which may be considered integrated circuits.

[0230] Layered HKIAttorney Docket No. DEBEN-1003PCTPATENT APPLICATION

[0231] FIG. 9A illustrates a method of fabricating layered kinetic inductors that multiplies energy capacity. FIG. 9A includes illustration of even HKI layer 901, insulating layer 902, odd HKI layer 903, stair step stack 910, stack 920, insulator 921, angle 922, directional etch 930, top down etch 931, approximately vertical angle 932, directional deposition 940, metal 941, oblique angle 942, and vertical turn point 944.

[0232] Kinetic inductors do not rely on magnetic fields for inductance but cannot function in large magnetic fields. If multiple independent kinetic inductor layers are stacked, they may all experience current flowing in the same direction, creating a large magnetic field that causes the superconductors to become normal conductors. A solution is to stack layers where adjacent layers carry currents of equal magnitude but opposite direction.

[0233] To visualize the solution, imagine a vertical stack of 100 copies of the element illustrated in FIG. 10 separated by insulating layers. FIG. 10 shows contacted kinetic inductor shape 1010, core section 1011, minimum-radius turn 1012, inductor contact area 1013 and inductor contact area 1014, midpoint contact area 1015 and midpoint contact area 1016, and alternative shorting area 1017.

[0234] Suppose the odd-numbered layers connect to contact areas 1013 and 1015, while the even-numbered layers connect to contact areas 1016 and 1014. Considering only kinetic inductance, this arrangement produces two inductors, each with 50 layers and 1 / 50ththe inductance of FIG. 10 (taken as a single-layer inductor). Connecting these in series by shorting midpoint contact areas 1015 and 1016 yields a single inductor with 1 / 25ththe inductance of FIG. 10. Because the inductors are in series, their currents are equal, and the currents travel in opposite directions.

[0235] The layered inductor comprises 50 wires in parallel, increasing / max by 50x, but L drops to 1 / 25th. Because the maximum energy in an inductor is Emax=1 / 2LImax2, the stored energy increases by 100x.

[0236] In an embodiment, aspects include specifying that the energy-recycling power supply includes a two-layer kinetic inductor comprising two layers of HKI material: even layerAttorney Docket No. DEBEN-1003PCTPATENT APPLICATION901, odd layer 903 separated by an insulating layer 902 and formed into two identical, vertically stacked contacted kinetic inductor shapes 1010. For this embodiment, the layers at one end, midpoint contact areas 1015 and 1016 are shorted together and the two layers at the other end, inductor contact areas 1013 and 1014 are used as the contacts of the inductor. By stacking alternating layers in a current-canceling configuration, the magnetic fields cancel, avoiding a reduction in critical current / c due to a large internally generated magnetic field. The embodiment provides a clear path for future scaling of reversible logic systems with increased energy density per unit area.

[0237] The disclosed process is based on an etched stair-step structure with four layers per etch step. FIG. 9A includes multiple illustrations of a four-sublayer stair-step where the top layer in each stair-step even HKI layer 901 and the third layer odd HKI layer 903 comprise identical HKI material of the same thickness, distinguished by their position in the stair-step and graphic fill pattern. The other two insulating layers 902 have a nearly white fill pattern and consist of insulator of the same thickness. To reduce clutter from lead lines, these elements are represented by fill patterns in the same configuration without lead lines.

[0238] If the HKI layers are numbered from 1 at the bottom, the method of connecting all even layers together and all odd layers together is illustrated in Fig. 9B. The right column of odd / even stairstep etch method 900 of Fig. 9A shows an alternate implementation. Aspects can include etching the stair-step at an oblique angle, making the HKI layer endpoints vertical and better matching layer sizes. Details in geometry and implementation may prevent perfectly vertical endpoints, but an intermediate angle may be used to ensure better matching of HKI layer sizes. The odd / even stairstep etch method proceeds as follows:• Step 950: Deposit N / 2 repetitions of the four-layer stack even HKI layer 901, insulating layer 902, odd HKI layer 903, insulating layer 902;• Step 951: Using a mask, remove the top two layers even HKI layer 901, insulating layer 902 from areas designated for connecting to odd layers 1013, 1015. Since each pair has equal thickness, after removal, the region contains N / 2 -1 / 2 repetitions of the four-layer stack — but with the even / odd designations reversed — even HKI layer 901 (now odd), insulating layer 902, odd HKI layer 903 (now even), insulating layer 902.Attorney Docket No. DEBEN-1003PCTPATENT APPLICATIONRemove the mask;• Step 952: Apply stair-step etching for N / 2 - 1 stair-steps to create the stair-step stack 910;• Step 953: As shown by stack 920, deposit insulator 921 on the stair-step at angle 922 to cover both vertical and horizontal surfaces;• Step 954: Apply a directional etch at an approximately vertical angle 932 to expose the edge of the top layer of each stair-step, even HKI layer 901;• Step 955: Deposit metal 941 on the stair-step at an oblique angle 942 to cover the exposed edges of the top layer of each stair-step, even HKI layer 901. The metal shorts together alternating layers (odd or even as determined in step 951) and is available for connection to other circuit parts through its top surface;• Step 956: Using a mask, perform a high-aspect-ratio vertical etch to create a contacted kinetic inductor shape 1010, including the bifurcated ends. The bifurcations terminate on the metal 941 connecting to alternate layers. The odd and even HKI layers 941 at one end are shorted together 1015, 1016, and the odd and even HKI layers 941 at the other end become the terminals of the inductor 1013, 1014;• Step 957: Alternatively, short odd and even layers together by performing a high- aspect-ratio vertical etch and depositing metal on the exposed surface 1017.

[0239] The 3D process and contact area 1013-1016 of FIG. 10, can be designed to support the required current. The HKI material in the core section 1011 must operate near its / c, which will be lower than that of a non-HKI superconducting metal layer. However, the current in the metal 941 will be N / 2 times greater than in each layer, potentially causing current crowding at the vertical turn point 944. To alleviate both issues, the width of the HKI inductor’s leads is increased at inductor contact area 1013, inductor contact area 1014, midpoint contact area 1015, and midpoint contact area 1016.

[0240] In an embodiment, aspects include an N-layer multilayer kinetic inductor, where N is three or more, with electrical contacts A and B. It comprises N layers of HKI material even HKI layer 901, and odd HKI layer 903 interleaved with N-1 insulating layers 902. All layers are patterned into a contacted kinetic inductor shape 1010 with terminals identified as firstAttorney Docket No. DEBEN-1003PCTPATENT APPLICATIONand second. All layers are shorted together at the first terminal midpoint contact area 1015 and 1016; the even-numbered layers are shorted together at the second terminal to form contact A at inductor contact area 1014, and the odd-numbered layers are shorted together at the second terminal to form contact B at inductor contact area 1013. Alternatively, the shorting of all layers could use a single vertical etch followed by a deposition on the exposed surface at alternative shorting area 1017. By stacking alternating layers in a current-canceling configuration, the inductor maintains superconductivity across all layers while increasing total stored energy and inductance. Multi-layer chip fabrication has been patented for flash memories, but the required method of fabricating odd / even connections with one lithographic step is unknown, nor is there a prior art reference suggesting that multi-layer kinetic inductors represent a step toward practical utilitarian reversible logic systems. The design enables system power to increase linearly with N, allowing performance growth in direct proportion to Moore’s Law.

[0241] Subject to the assumption of asymptotic scaling, HKI inductors have the same energy density per unit area regardless of inductance. Thus, changing the Pc of a CMOS conversion affects only the number of HKI layers.

[0242] Chip Power Grids

[0243] The previous section discussed dividing an integrated circuit into regions, each with an identical 4LC circuit, yet combining such circuits can be beneficial. Fig. 11 illustrates a system of four touching 4LC circuits 1100, and system of four merged 4LC circuits 1110, in a chip power grid, described earlier as region 216. Clock phases are assigned so that touching circles 1101 share the same phase.

[0244] If all the four touching 4LC circuits 1100 are initialized identically, they will produce identical waveforms 400 indefinitely. By symmetry, merging nodes with equal voltages into a single electrical node does not alter circuit behavior.

[0245] The interior of the chip power grid contains pairs of 4LC circuits connected by two inductors in parallel. The diagram merges such pairs of inductors of value L into a single inductor of value L / 2, as shown as four merged 4LC circuits 1110, leaving edge inductorsAttorney Docket No. DEBEN-1003PCTPATENT APPLICATION1111 still labeled with value L. In FIG. 11 merged vertical inductors are moved into the adjacent 4LC circuit with clockwise numbering and similarly for horizontal inductors with counterclockwise numbering.

[0246] The result is a chip power grid containing repetitions of four merged 4LC circuits 1110 with a checkerboard pattern of two subcircuits, corresponding to black and white squares. One subcircuit has two vertical inductors with clockwise phase numbering; the other has horizontal inductors with counterclockwise phase numbering. Each subcircuit can be a variant of the inductor layer 810. The overall pattern represents four regions, each like YBCO reversible logic chip 800.

[0247] However, the chip power grid concept does not require identical rectangular regions, equal areas, or equal capacitances. The concept applies to any set of regions and any capacitance per region, provided sufficient space and wiring layers exist to form a 4LC circuit at the specified frequency across all regions.

[0248] A design could include high- and low-power-density areas, such as processors and memories. The chip power grid concept could allow inductors supplying power to processors to extend into the area above memory.

[0249] A regular chip power grid such as the four touching 4LC circuits 1100, or the four merged 4LC circuits 1110 gains layout efficiency through merged contact points and inductors. A chip power grid with uneven loading might benefit more from arrays that are not aligned, despite requiring wires to maintain the same connection pattern.

[0250] The overall chip power grid concept is to create an independent 4LC circuit for each region, based on the region’s circuit capacitance and the inductance required to resonate at a specified frequency. For a more efficient layout, the power-clock connections can be merged with the same voltage and inductors can be merged between the same voltage nodes. Then place-and-route inductor material above the regions. Finally, add drive circuits and iteratively refine placement by simulating the network with expected loads and component variability.Attorney Docket No. DEBEN-1003PCTPATENT APPLICATION

[0251] Reusable Layout Geometry (IP)

[0252] This disclosure envisions reusable reversible logic IP, which expands upon the energy-recycling power supply 131 and adiabatic logic chip 132, and aspects of FIG. 15. Note that the standalone term “IP” is broadly used refer to either integrated circuit layout geometry or legal rights (patents). This disclosure accommodates this ambiguity by never using “IP” in isolation but always in conjunction with modifiers that differentiate the term from legal rights (patents). “IP” as used herein refers to integrated circuit layout geometry, such as the geometric patterns that form a wiring layer or positions of transistor gates. This layout geometry — often called “artwork” — is eligible for copyright protection, hence use of the term “IP” and sale of this IP is a sector of the semiconductor industry. Based on the previous, this disclosure anticipates an ecosystem where designers specialize by function — such as “logic IP designer,” “power IP designer,” and so forth — collectively producing a toolbox or library of design pieces called IP blocks that can be later assembled into a larger system by a system designer with assurance that it is correct by construction.

[0253] Consider a reversible logic adder as an example. A circuit IP designer would create layout geometry for a reversible adder circuit within a layout region corresponding to boundary of adder IP block 1520. This yields a logic IP block that expects to receive drive waveforms, which are defined as power-clocks local to the IP block. A power IP designer would create an inductor layout for an energy recycling power supply in an identical layout region, which would be called a power IP block, or specifically, 10-meander IP block 1500. However, a second logic IP block, a subtractor circuit, would be subtractor IP block 1530, and would function with the same 10-meander IP block in region 1500. A second power IP block in the identical layout region would be called 8-meander IP block 1510 would work with both arithmetic IP blocks 1520 and 1530 but at a different operating frequency or power level.

[0254] Reusable reversible logic IP requires the development of IP conventions. For instance, hard CMOS IP blocks function only for specific process parameters (such as line width), while hard reversible logic IP blocks may function only at a specific frequency. Reversible logic IP conventions should define values and tolerances for frequency, phase, loading, crosstalk, capacitive load, port layout, combining rules, rotations, etc. TheAttorney Docket No. DEBEN-1003PCTPATENT APPLICATIONconventions would apply to both logic and power IP blocks 1500, 1510, 1520, 1530.

[0255] Fig. 15 further explains IP-based design for reversible logic. FIG. 15 shows 10 meander IP block 1500, port 1501, 8 meander IP block 1510, adder IP block 1520, and subtractor IP block 1530.

[0256] The layout geometry of reversible logic IP could include power-clock ports 1501 at standard positions, which could be circles. The conventions could require that reversible logic circuits provide a path between each power-clock port and GND of a specific capacitance value C.

[0257] A power IP designer can create energy-recycling power supplies principally but not exclusively in inductor layers, with two alternatives illustrated in FIG. 15 as HKI 10-meander IP block 1500, and HKI 8-meander IP block 1510. Each inductor layer generates reversible power-clocks on the power-clock ports — subject to the circuit IP designer providing the required capacitance (C) to GND. However, the power IP designers can create different layouts for different operating frequencies. For example, the 10-meander IP block 1500 includes ten meanders; the second 8-meander IP block 1510 includes eight. Different meander counts yield different inductances, and thus different power-clock frequencies.

[0258] The 10-meander IP block 1500 shows wires as thin lines, which would lead to inductors with a lower energy density than thick wires in 8-meander IP block 1510. A circuit with low computational density, such as memory, would require an inductor layer with thinner wires than a circuit with high computation density, such as an arithmetic circuit.

[0259] Circuit IP designers can create circuits that consistently place a specific capacitive load on power-clock ports at designated locations. They are free to create layouts for different functions, such as adder IP block 1520 or a subtractor IP block 1530. A circuit with a less complex function can initially place a smaller load on the power-clock port, requiring a trimming capacitance (Ctrim) to GND to comply with the convention.

[0260] Embodiments disclosed above facilitate construction of a library of interchangeable reversible logic IP blocks, including logic and power types. A system designer can assembleAttorney Docket No. DEBEN-1003PCTPATENT APPLICATIONlogic IP blocks to perform a desired function and then add power IP blocks. The toolbox can include power IP blocks for different operation speeds, such as 200, 500, and 1,000 MHz. If the logic IP blocks included lower-power memory functions and higher-power logic functions, there could be two sets of power IP blocks, one set for each power level. If assembled in accordance with conventions, the resulting system would be correct by construction.

[0261] Embodiments anticipate that a reversible logic subsystem can coexist with CMOS, analog circuits, or even Josephson junction logic circuits. A system designer could subdivide the chip into IP regions and apply different design processes in each IP region. Additionally, a multi-mode IP designer could create IP that includes reversible and other design styles, such as IP that converts a CMOS data stream to a reversible logic data stream. Specifically, logic IP blocks could include reversible logic circuits connected to the power-clock ports while also containing CMOS connected to the power distribution layers in the original CMOS process.

[0262] The IP assembly rules can be extended to attributes unique to reversible logic, such as rotation (physical and logical). For example, the chip power grid of four merged 4LC circuits 1110 delivers clock phases in different physical configurations (rotations and mirrors) based on the IP block’s position in the grid. Four-phase logic design generally requires configuring circuits with logically renumbered (rotated) clock phases (i.e., a circuit may need power-clocks ordered as (φ₁-φ₂-φ₃-φ₀)). The convention shown in FIG. 16 allows hard logic IP blocks to operate correctly in any of the four rotated and mirrored positions as provided in FIG. 11, as well as enabling the clock phases to be logically rotated by physical 90-degree rotations of the layout geometry.

[0263] FIG. 16 illustrates a reversible logic IP block 1600, including double lines 1601, port 1602, metal traces 1603, square logic IP block 1610, P₀ 1611, and P₁1612.

[0264] FIG. 16 first shows the junction between four IP blocks; the double lines 1601 represent a block boundary. The logic IP block conventions have four power-clock ports 1602 in each corner. The convention requires each IP block to run metal traces 1603 to its boundary, where they abut a corresponding trace in the neighboring IP block, which follows the same convention and thus has the other end of the wire. The power IP block would driveAttorney Docket No. DEBEN-1003PCTPATENT APPLICATIONjust one of the power-clock ports P₀–P₃ from a different layer such as comprising four touching 4LC circuits 1100 or four merged 4LC circuits 1110.

[0265] A square logic IP block 1610 can have the power-clock ports on its outer corners as shown. Ports are defined in each corner for each clock phase, but only port is driven; therefore the IP block must run a wire to each port P₀ 1611. This creates the required power connections for the illustrated circuit.

[0266] However, the effect of rotating the layout geometry clockwise by 90 degrees should be considered. The illustrated structure connected to P₀ 1611 rotates to have the geometry of element P₁ 1612, which connects to P₁ at four places. Generally φᵢ maps to φ(i+1) mod 4, providing clock phase rotation as desired.

[0267] Reversible logic derives its energy efficiency in part from the tight coupling between the logic and the energy-recycling power supply. Embodiment make use of processes to extend IP concepts to support these additional constraints.

[0268] In an embodiment, aspects include energy-recycling IP comprising:(a) an IP block on the surface of an integrated circuit, such as IP blocks 1500, 1510, 1520, and 1530;(b) power-clock port 1501 positions in the IP region;(c) one or more logic IP blocks 1520, 1530 comprising layout geometry for one or more logic circuits within the IP region and connecting to the power-clock port positions; (d) one or more power IP blocks 1500, 1510 comprising layout geometry for an energyrecycling power supply 210 within the IP region and connecting to the power-clock port positions, wherein every combination of one logic IP block and one power IP block performs the repeating cycle of: transferring energy Efrom the energy-recycling power supply to the logic circuits, powering their logic functions, and transferring energy E back to the energy-recycling power supply 210.

[0269] In an embodiment, aspects include refinements where:Attorney Docket No. DEBEN-1003PCTPATENT APPLICATIONa) the number of logic IP blocks plus the number of power IP blocks is three or more, forcing either multiple logic IP blocks such as 1500, 1520, 1530 or multiple power IP blocks such as 1500, 1520, 1530 and providing a compositional choice;b) the combination of all logic IP blocks and power IP blocks forms a library of layout geometry that can be combined to perform logic functions, where the combination is correct by construction.

[0270] In an embodiment, aspects include refinements, wherein:a) each logic IP block / has an associated capacitance Cr,b) each power IP block / has an associated inductance Lf,c) there exists a frequency equation fR = F(Lj× Ci), where fa is the clock rate;d) a set of at least two target clock rates, such as 200, 500, and 1,000 MHz, is provided; e) every logic IP block can function at every frequency by selecting the appropriate power IP block, thereby creating a set of logic IP blocks that can function at any frequency in the specified set. The claim implies the algebraic process of taking each Ci and reversing the equation to obtain Lj. Thus, Lj must be included in the set of power IP blocks provided.

[0271] In an embodiment, each 90-degree rotation of the logic IP block layout geometry remaps each power-clock 0 / to ( / +i)mod4, so that a single optimized logic block may be used in any clock phase.

[0272] In an embodiment, aspects further include wherein:a) the IP region is within a chip power grid (Fig. 11, Fig. 13) that has a checkerboard structure, with the IP region designated as black or white depending on its position; b) each power IP block is available in two forms corresponding to black and white squares on the checkerboard;c) the power IP block has the form corresponding to the black or white designation. This embodiment supports reversible logic IP when using a chip power grid.

[0273] In an embodiment, additional aspects comprise one or more other IP blocks whoseAttorney Docket No. DEBEN-1003PCTPATENT APPLICATIONlayout geometry is based on non-reversible technology, including CMOS, non-CMOS logic circuits (e.g., nMOS), analog electronics, non-transistor electronics (e.g., Josephson junctions), or semiconductor electronics augmented with unconventional components (e.g., memristors), or so forth, thereby permitting reversible logic to be applied to a subset of a system.

[0274] Four-to-Eiqht Phase Converter Circuit and Generalizations

[0275] The four-phase power supply disclosed is sufficient for the 2LAL logic family, which is in turn sufficient for universal logic and general computing. However, eight-phase logic families are better suited for certain applications. Reversible logic circuits based on retractile cascade clocks allow realization of complex logic functions with fewer transistors. Embodiments include reversible converter synthesis, a process that synthesizes circuits capable of converting four-phase power-clocks into any waveform eligible for energy recycling, using the four-to-eight phase converter circuit as an example. Waveforms eligible for energy recycling include power-clocks, data signals, and bus-driving signals (including tristate drive). Electrical noise and power-clocks whose frequency is faster than the four-phase power supply are examples of waveforms not eligible for energy recycling.

[0276] The circuit includes a tick selector and a connection array. The tick selector may be implemented as a 2LAL circuit or a conventional CMOS circuit.

[0277] FIG. 12 illustrates tick selector waveforms 1200, φ̂A0 1201, combiner circuit 1210, output waveform 1211, output wire 1212, code word 515453559 1213, connection array 1214, and alphabet of waveforms / / rectangular selection alphabet; sine waves with negative offset 1220.

[0278] FIG. 13 illustrates tick-selector circuit 1300, Four-phase power clocks 1301, 2LAL phase 1302, replicated phases 1303, wrap around notation 1304, and dual-rail tick-selection waveforms 1305.

[0279] If the tick selector is a 2LAL circuit, it generates tick selector waveforms 1200 shown in FIG. 12, using two 2LAL register stages labeled A and B, connected in a cycle as indicatedAttorney Docket No. DEBEN-1003PCTPATENT APPLICATIONby the wrap-around notation 1304 illustrated in Fig. 13 and initialized to states 1 and 0. The circuit perpetually transitions between states (1, 0) and (0, 1). Fig. 13 illustrates eight dualrail tick-selection waveforms 1305 and shows how the circuit can be extended to 4 / V pairs of waveforms by replicating 2LAL phase 1302 as replicated phase 1303, where N is a positive integer. The circuit has been simulated with the results in FIG. 7 and associated description.

[0280] A single 1 -bit in 2LAL encoding comprises three ticks: a transition from 0 to 1, a sustained state of 1, and a transition from 1 to 0. Since each 2LAL register stage operates over four ticks, the combined two-stage cycle yields an output period of eight ticks. These eight output wires are dual-rail tick-selection waveforms 1305. The first tick-selector waveform 1200 in Fig. 12 is denoted as φ̂A0 1201 and corresponds to AO of dual-rail tickselection waveforms 1305 and the remaining ones φ̂A1 through φ̂B3 are also contained in the dual-rail tick-selection waveforms 1305.

[0281] The alphabet of waveforms 1220 comprise waveforms for V = GND, V = R, and the four four-phase power-clocks, which may be rectangular AC power-clock waveforms 100, sinusoidal power-clocks 110, or any other shape suitable for energy recycling.

[0282] The connection array 1214 comprises single transistors or transmission gates that bidirectionally connect waveforms from the alphabet of waveforms 1220 to the output wire 1212. The combiner circuit 1210 illustrates an output waveform 1211; however, a designer can synthesize other waveforms by selecting different sources.

[0283] Circuits resulting from reversible converter synthesis carry parts of their input waveform shape to their output wire 1212. The alphabet of waveforms 1220 illustrates both ramped and sinusoidal power-clocks.

[0284] Fig. 13 provides additional detail for implementing a 2LAL tick-selector circuit 1300. Four-phase clocks 1301 drive a 2LAL phase 1302. Each left-to-right replicated phase 1303 receives the clock phases in the correct (rotated) order for its position. Four such stages form a 2LAL register; thus, all eight stages form the two 2LAL registers A and B. The registers form a cycle as indicated by the wrap-around notation 1304. The 2LAL logic family is dual rail, meaning each data pulse φ⁺ within the set of dual-rail tick-selection waveforms 1305 fromAttorney Docket No. DEBEN-1003PCTPATENT APPLICATION GND to R (a positive-going pulse, indicated by an upward-pointing diacritical mark) pairs with a data pulse 0“ within the set of dual-rail tick-selection waveforms 1305 from R to GND (the downward-pointing shape indicating a negative-going pulse). Thus, the circuit produces dual-rail tick-selection waveforms: positive-going pulses suitable for driving n-channel FETs in transmission gates, and negative-going pulses suitable for p-channel FETs.

[0285] Embodiments include the reversible converter synthesis process for variants of the connection array 1214 capable of generating any waveform eligible for energy recycling. A waveform is defined by a code word comprising a sequence of symbols, one symbol per tick. The following symbol mapping is illustrative; any consistent mapping may be used.TABLE 3Waveform source SymbolConnect waveform to GND 9Connect 0o to waveform 0Connect 01 to waveform 1Connect 02 to waveform 2Connect 03 to waveform 3Connect waveform to VR 4No connection (or tri-state) 5

[0286] An eight-tick waveform is described by a code word with eight symbols corresponding to the eight ticks numbered 0-7 in reading order. The figure shows the code word 515453559 1213, which generates the output waveform 1211.

[0287] In an embodiment, aspects comprise reversible converter synthesis, comprising the process illustrated in Fig. 12B. The method proceeds as follows:• Step 1230: Providing an A / -symbol code word, numbering the symbols from 0— / -1 in reading order, where each symbol is selected from the set comprising GND,, “no connection,” and the four-phase energy-recycling power-clocks φ₀ to φ₃ 100, 110; the code word specifies the desired waveform; and an output wire 1212;• Step 2 1231: Outputting a tick-selector circuit 1300 with repetition factor N• Step 3 1232: Repeating steps 1233 through 1235 for each symbol / of the code word,Attorney Docket No. DEBEN-1003PCTPATENT APPLICATIONindexed from symbol 0 to symbol A / -1;• Step 4 1233: Unless symbol / specifies “no connection,” output a transmission gate between the source specified by symbol / and the output wire, where the transmission gate connects to both rails of tick selection waveform / ;• Step 5 1234: If symbol / specifies R, delete the n-channel FET from the transmission gate just added, if any;• Step 6 1235: If symbol / specifies GND, delete the n-channel FET from the transmission gate just added, if any;• Step 7 1236: The output now comprises a circuit design ready for detailed electrical design and fabrication.

[0288] Considering words as components of a language, a code word that satisfies the grammar and semantics below is considered eligible for energy recycling:• Words are treated as cyclic sequences of symbols, so the last symbol is adjacent to the first.• Any symbol may be repeated, causing the source signal to remain connected for longer durations.• Two distinct symbols must be separated by at least one “no connection” symbol, and the ending voltage of the first symbol must match the beginning voltage of the second. This requirement accounts for the transition period of transmission gates and transistors — approximately halfway into adjacent ticks.• A bus drive waveform in the tri-state (non-driving) state can be represented by a sequence of “no connection” symbols.• Because of half-tick turn on / off times, most reversible logic signals can be driven only on even or odd ticks. However, the most consistent drive for non-reversible logic — such as driving an LED — involves driving on every tick.

[0289] The discussion above applies to 4 / V-tick waveforms, where / Vis a positive integer. The process can be extended to any N> 4: the concept is to append two or four copies of the waveform into a single waveform whose length is twice or four times the original. One or both copies will be a multiple of four; therefore, synthesize the shorter of these waveforms.Attorney Docket No. DEBEN-1003PCTPATENT APPLICATIONNote that appending waveforms described by a code word involves appending the waveforms and then converting the waveform back to symbols, which may adjust the powerclock phases.

[0290] In an embodiment, aspects include generalized reversible converter synthesis, comprising the process illustrated in FIG. 12C. The method proceeds as follows:• Step 1240: Providing an / V-symbol code word, where each symbol is selected from the set comprising GND, R, “no connection,” and the four-phase energy-recycling power-clocks φ₀ to φ₃ 100, 110; the code word specifies the desired waveform; and an output wire 1212;• Step 1241: Append two copies of the waveform represented by the code word into a single waveform whose length is twice the original and designate its code word W2;• Step 1242: Append four copies of the waveform represented by the code word into a single waveform whose length is four times the original and designate its code word W4;• Step 1243: If / Vis a multiple of four, perform reversible converter synthesis on the code word, otherwise if N is even, perform reversible converter synthesis on W2, otherwise perform the reversible converter synthesis on W4.

[0291] In an embodiment, aspects include multiple circuits created by either reversible converter synthesis and / or generalized reversible converter synthesis, wherein the code word used in the process obeys the grammar and semantics defined in the referenced embodiments, and wherein the resulting structures are capable of generating a waveform suitable for driving reversible logic in a system with four or more phases.

[0292] Embodiments disclosed herein can include a reversible logic system that integrates an adiabatic logic chip with an energy-recycling power supply, enabling scalable, efficient, and low-power computation through a novel power-clock architecture.

[0293] In an embodiment, a method of converting a CMOS design into a functionallyAttorney Docket No. DEBEN-1003PCTPATENT APPLICATIONequivalent reversible redesign, comprises:a) receiving CMOS parameters for power (Pc), clock rate (fc), and supply voltage (Vc); b) receiving an architectural description of the CMOS chip 204, 206, 207, 208;c) receiving a floorplan of the CMOS chip 200;d) receiving a gate-level or register-transfer-level description of the CMOS logic; e) converting the gate-level or register-transfer-level (RTL) description from CMOS gates 205 to a partially reversible gate-level description 225 using known reversible logic mappings (e.g., AND-OR-NOT to Toffoli gates, CNOT gates, and retractile cascades); f) receiving reversible logic parameters for supply voltage (VR) and clock rate (fR); g) receiving correction factors (δleak, δdark, δsize, and δqtr) to account for leakage, dark silicon, gate count, and the four phases of the clocks;h) using correction factors to estimate the CMOS capacitance (CR) and the area of the reversible redesign (AR);i) computing the required number of layers (Nk) or Q factor (QRtype) for the energyrecycling power supply based on the scaling equations in the specification;j) selecting the most suitable option (e.g., kinetic, meander, or spiral based on Nkand QRtype), or deciding no option is suitable;k) generating layout geometry for the reversible gates and the energy-recycling power supply.

[0294] In an embodiment, a problem-solving system with higher energy efficiency based on CMOS conversion is disclosed, wherein the CMOS design is part of a problem-solving system further comprises:a) performing the process in FIG. 2B;b) simulating the layout geometry to assess the effect of load and process variations under realistic loads;c) iteratively refining the design based on simulation results;d) fabricating the layout geometry to create a physical implementation of the reversible redesign called a reversible chip;e) integrating the reversible chip into the problem-solving system to achieve reduced power consumption.Attorney Docket No. DEBEN-1003PCTPATENT APPLICATION

[0295] Reversible Logic Systems

[0296] Reversible logic systems were described as problem-solving resources for people, but they can also be used by other computers via electronic connections such as a network interface 202, including local area networks, the internet, wireless communications, and software linkages on the same computer. They can replace CMOS in use cases beyond problem solving — such as real-time control, data collection, or other CMOS use cases.

[0297] The phrase “CMOS conversion” is used because CMOS is the preeminent technology of the era, but reversible logic can be developed for other implementations of digital logic, including other semiconductor materials, Josephson junctions, and neural networks. CMOS conversion implicitly applies to new designs, where the designer translates design requirements into reversible logic without CMOS as an intermediate step.

[0298] Reversible logic systems are described as obtaining energy from a power source 201, which could be DC or AC, and extends to a battery, harvested energy, or another source that powers CMOS. Power in any of these forms enters conventional electronics 1401, which generates two or more drive waveforms 1409, Vp (power) 1404, and GND 1408.

[0299] Reversible logic does not need to be the only circuit type in a system. CMOS 1402 can be used for power-up, reset operations, and other computational functions that are not strictly implemented with logic gates. Examples of non-logic functions include an analog timer to detect when system voltage is stable after power up or to detect a cyber security attack where an adversary probes the circuit with electrical noise or elementary particle beams. The other functions may connect to Vp= Vdd1404, GND 1408, and may utilize the drive waveforms 1409 as clocks or signaling sources.

[0300] More generally, reversible logic systems can co-exist with other electronic technologies such as chip 203, storage device 204, CMOS 1402, such as CMOS, analog electronics, transistors in non-CMOS transistor logic circuits (e.g., nMOS), non-transistor electronics (e.g., Josephson junctions), and semiconductor electronics augmented with unconventional components (e.g., memristors). Reversible logic systems could function as interface circuitry for quantum computers, enabling them to coexist with qubits.Attorney Docket No. DEBEN-1003PCTPATENT APPLICATION

[0301] Reversible logic systems may coexist with CMOS or other technologies at a functional level. For instance, a CMOS chip containing a processor and an accelerator could have CMOS conversion applied to its accelerator, preserving the CMOS implementation of remaining functions. Likewise, a quantum computer could have CMOS conversion applied to its control electronics.

[0302] A reversible logic system may include multiple energy-recycling power supplies operating at different frequencies.

[0303] A single energy-recycling power supply may support multiple reversible logic families simultaneously, where power-clocks can be generated as illustrated in FIG. 12 and FIG. 13 which extended to more than four ticks.

[0304] The reversible redesign 1407 shares the GND connection 1408. An energy recycling circuit 1403, illustrated as a 4LC, includes inductors Lo-3 and capacitances Co-3. The 01 power-clock connects to the reversible logic and its wire capacitance becomes the Ci capacitance 1406; the Co 1405, C2, and C3 are shown schematically. Symbols 0o-3, equivalent to P0-3, represent the four power-clocks.

[0305] This disclosure has been deliberately written without differentiating between integers and real numbers. For example, the number of HKI layers must be an integer. If an expression in the disclosure concludes that 2½ layers are required, this could implicitly mean three layers with one only half used — or three layers where 1 / 6thof each layer is empty.

[0306] Aspects of the embodiments can be understood to include a system-level design approach for reversible logic that matches CMOS performance at lower energy dissipation. Aspects include an energy-recycling power supply that can be combined with an adiabatic logic chip created with known methods without undue experimentation, yielding a utilitarian reversible logic system. Thus, this system can enable full system prototyping for commercial deployment, and potentially a scale up path based on N-layer kinetic inductors.

[0307] Aspects can further include conversion of quantum computer control circuits using one or two layers of HKI material, and a reversible logic system powered by existing YBCOAttorney Docket No. DEBEN-1003PCTPATENT APPLICATIONinductors or new designs from the same source.

[0308] Certain notation in the provisional patents is outlined in the table below for consistency:TABLE 3Term in Term in this Term in Term in thisprovisionals disclosure provisionals disclosure1 / 4 5qtr NL NL0.8 (Jleak PCMOS Pc2 Sdark LR Z-RkA Ac Vdd VcAL Aqtr 4lc 4LCC Cqtr. draining out drainingCR CRk phase-selection tick selectorCs Cc top-off rechargef / R inductor array chip power grid / CMOS fc

[0309] It will be appreciated that variations of the above-disclosed and other features and functions, or alternatives thereof, may be desirably combined into many other different systems or applications.

[0310] In an embodiment, a reversible logic system comprises a physically rigid structure, an adiabatic logic chip configured on the physically rigid structure, and an energy-recycling power supply configured on the physically rigid structure, the energy-recycling power supply being electrically connected to the reversible logic chip via power-clocks. In an embodiment, the energy-recycling power supply powers the adiabatic logic chip. In an embodiment, the energy-recycling power supply generates power-clocks comprising at least four clock signals, wherein each of the at least four clock signals are divided into four or more ticks. In an embodiment, the power-clocks have sinusoidal waveforms. In an embodiment, the adiabatic logic chip and the energy-recycling power supply are co-fabricated on a single substrate. In an embodiment, the rigid structure comprises vias interconnecting metal layers. In an embodiment, the adiabatic logic chip and the energy-recycling power supply are physically separated and physically and electrically connected. In an embodiment, the adiabatic logicAttorney Docket No. DEBEN-1003PCTPATENT APPLICATIONchip and the energy-recycling power supply are connected by one or more of: die stacking, hybrid bonding, chiplets, through-silicon vias, microbumps, package-on-package, interposers, co-fired ceramic structures, and / or physical structures for filling a space. In an embodiment, the energy-recycling power supply comprises inductors that resonate with a circuit capacitance of the adiabatic logic chip, forming an LC network that generates sinusoidal power-clocks. In an embodiment, the LC network comprises a 4LC circuit that simultaneously produces four sine-wave power-clocks with 90-degree phase shifts between the four sine-wave power-clocks. In an embodiment, the energy-recycling power supply comprises at least one superconducting inductor. In an embodiment, the energy-recycling power supply comprises at least one high-Tc superconducting inductor. In an embodiment, the energy-recycling power supply comprises at least one kinetic inductor. In an embodiment, the kinetic inductor comprises two layers of HKI material separated by an insulator and formed into an inductor shape, a short between the two layers of HKI material at one end of the inductor shape, and a first contact of the kinetic inductor at the other end of the inductor shape associated with one of the two HKI layers, and a second contact of the kinetic inductor at the other end of the inductor shapes associated with another of the two HKI layers.

[0311] In an embodiment, / V-layer multilayer kinetic inductor comprises a first electrical contact A and a second electrical contact B, comprising: a plurality of layers of HKI material interleaved with a plurality of insulating layers, the plurality of layers patterned into an inductor shape with a first terminal and a second terminal, a short between the plurality of layers HKI material at the first terminal, a short between a first set of alternating layers at the second terminal forming a contact A, and a short between a second set of alternating layers at the second terminal forming contact B.

[0312] In an embodiment, an energy-recycling IP block comprises a region on a surface of an integrated circuit, a power-clock port positioned in the region, at least one logic IP block comprising layout geometry for at least one logic circuit within the region and connecting to the power-clock port positioned in the region, at least one power IP block comprising layout geometry for an energy-recycling power supply within the region, connecting to the powerclock port positioned in the region. In an embodiment, every combination of one logic IP block and one power IP block, perform a repeating cycle comprising: transferring energy in the oneAttorney Docket No. DEBEN-1003PCTPATENT APPLICATIONpower IP block to the one logic circuit, powering logic functions, and transferring energy back to the one power IP block. In an embodiment, the number of the at least one logic blocks plus the number of the at least one power IP blocks is three or more. In an embodiment, a combination of all the at least one logic blocks and the at least one power blocks forms a library of layout geometry that can combined to perform logic functions. In an embodiment, each 90-degree rotation of a logic block layout geometry causes each power-clock to be remapped to 4>(i+1) mod 4, wherein a single optimized logic block can be used in any clock phase. In an embodiment, the region is within a chip power grid that has a structure of a checkerboard, with the region being designated as black and white depending on its position, wherein each of the at least one power block is available in two forms corresponding to black and white squares on the checkerboard, and each of the at least one power blocks is of a form corresponding to a black and white designation. In an embodiment, the energy-recycling system further comprises at least one other block where a layout geometry is based on non-reversible technology comprising at least one of: CMOS, non-CMOS logic circuits, analog electronics, non-transistor electronics, Josephson junctions, or semiconductor electronics.

[0313] In an embodiment, a method of creating a four phase-to-specified N-tick waveform converter circuit, comprises providing an A / -symbol code word, where symbols are chosen from a set comprising GND, VR, a four four-phase energy-recycling power-clocks, and “no connection,” where the A / -symbol code word specifies a desired waveform, and an output wire, outputting a tick generator circuit with a repetition factor N, outputting a transmission gate from a source specified by symbol i to the output wire, where the transmission gate connects to both rails of tick selection waveform / , unless symbol / specifies “no connection”, deleting an n-channel FET from the transmission gate if a transmission gate was added and symbol / specifies VR, deleting the n-channel FET from the transmission gate if a transmission gate was added and symbol / specifies GND, wherein an output comprises a circuit design.

[0314] In an embodiment, a method of converting a CMOS design into a functionally equivalent reversible redesign, comprises receiving CMOS parameters for power (Pc), clock rate (fc), and supply voltage (Vc), receiving an architectural description of a CMOS chip, receiving a floorplan of the CMOS chip, receiving a gate-level or register-transfer-level description of a CMOS logic, converting the gate-level or register-transfer-level descriptionAttorney Docket No. DEBEN-1003PCTPATENT APPLICATIONfrom CMOS gates to a partially reversible gate-level description, receiving reversible logic parameters for supply voltage (Vf) and clock rate (fa), receiving correction factors to account for leakage, dark silicon, gate count, and four phases of the clocks, using the correction factors to estimate a CMOS capacitance (CR) and an area of a reversible redesign (AR), identifying a required number of layers (Nk) or Q factor (QRtype) for an energy-recycling power supply, selecting a most suitable option, and generating a layout geometry for reversible gates and the energy-recycling power supply. In an embodiment, the CMOS design is part of a problem-solving system. In an embodiment, the method of converting a CMOS design into a functionally equivalent reversible redesign further comprises simulating the layout geometry to assess an effect of load and process variations under realistic operating conditions, iteratively refining a design based on simulation results, fabricating the layout geometry to create a reversible chip comprising a physical implementation of the reversible redesign, and integrating the reversible chip into the problem-solving system.

[0315] Various presently unforeseen or unanticipated alternatives, modifications, variations or improvements therein may be subsequently made by those skilled in the art which are also intended to be encompassed by the following claims.

Claims

Attorney Docket No. DEBEN-1003PCTPATENT APPLICATION CLAIMSWhat is claimed is:

1. A reversible logic system comprising:a physically rigid structure;an adiabatic logic chip configured on the physically rigid structure; andan energy-recycling power supply configured on the physically rigid structure, the energy-recycling power supply being electrically connected to the adiabatic logic chip via power-clocks.

2. The reversible logic system of claim 1 wherein the energy-recycling power supply powers the adiabatic logic chip.

3. The reversible logic system of claim 1 wherein the energy-recycling power supply generates power-clocks comprising at least four clock signals, wherein each of the at least four clock signals are divided into four or more ticks.

4. The reversible logic system of claim 1 wherein the power-clocks have sinusoidal waveforms.

5. The reversible logic system of claim 1 wherein the adiabatic logic chip and the energyrecycling power supply are co-fabricated on a single substrate.

6. The reversible logic system of claim 5 wherein the rigid structure comprises vias interconnecting metal layers.

7. The reversible logic system of claim 1 wherein the adiabatic logic chip and the energyrecycling power supply are physically separated and physically and electrically connected.

8. The reversible logic system of claim 7 wherein the adiabatic logic chip and the energy-Attorney Docket No. DEBEN-1003PCTPATENT APPLICATIONrecycling power supply are connected by one or more of:die stacking;hybrid bonding;chiplets;through-silicon vias;microbumps;package-on-package;interposers;co-fired ceramic structures; and / orphysical structures for filling a space.

9. The reversible logic system of claim 1, wherein the energy-recycling power supply comprises inductors that resonate with a circuit capacitance of the adiabatic logic chip, forming an LC network that generates sinusoidal power-clocks.

10. The reversible logic system of claim 9, wherein the LC network comprises a 4LC circuit that simultaneously produces four sine-wave power-clocks with 90-degree phase shifts between the four sine-wave power-clocks.

11. The reversible logic system of claim 1 wherein the energy-recycling power supply comprises at least one superconducting inductor.

12. The reversible logic system of claim 1, wherein the energy-recycling power supply comprises at least one high-Tc superconducting inductor.

13. The reversible logic system of claim 1 wherein the energy-recycling power supply comprises at least one kinetic inductor.

14. The reversible logic system of claim 13 wherein the kinetic inductor comprises:two layers of HKI material separated by an insulator and formed into an inductor shape;Attorney Docket No. DEBEN-1003PCTPATENT APPLICATIONa short between the two layers of HKI material at one end of the inductor shape; and a first contact of the kinetic inductor at an other end of the inductor shape associated with one of the two layers of HKI; anda second contact of the kinetic inductor at the other end of the inductor shapes associated with another of the two layers of HKI.

15. An energy-recycling IP block comprising:a region on a surface of an integrated circuit;a power-clock port positioned in the region;at least one logic IP block comprising layout geometry for at least one logic circuit within the region and connecting to the power-clock port positioned in the region;at least one power IP block comprising layout geometry for an energy-recycling power supply within the region, connecting to the power-clock port positioned in the region.

16. The energy-recycling system of claim 15 wherein every combination of one logic IP block and one power IP block, perform a repeating cycle comprising:transferring energy in the one power IP block to the one logic circuit;powering logic functions; andtransferring energy back to the one power IP block.

17. The energy-recycling system of claim 15, wherein each 90-degree rotation of a logic block layout geometry causes each power-clock i to be remapped to φ(i+1) mod 4, wherein a single optimized logic block can be used in any clock phase.

18. The energy-recycling system of claim 15, wherein the region is within a chip power grid that has a structure of a checkerboard, with the region being designated as black and white depending on its position, wherein each of the at least one power block is available in two forms corresponding to black and white squares on the checkerboard, and each of the at least one power blocks is of a form corresponding to a black and white designation.

19. A method of creating a four phase-to-specified / V-tick waveform converter circuit,Attorney Docket No. DEBEN-1003PCTPATENT APPLICATIONcomprising:providing an / V-symbol code word, where symbols are chosen from a set comprising GND, R, a four four-phase energy-recycling power-clocks, and “no connection,” where the / V-symbol code word specifies a desired waveform, and an output wire;outputting a tick generator circuit with a repetition factor N;outputting a transmission gate from a source specified by symbol / to the output wire, where the transmission gate connects to both rails of tick selection waveform / , unless symbol / specifies “no connection”;deleting an n-channel FET from the transmission gate if a transmission gate was added and symbol / specifies \ / R;deleting the n-channel FET from the transmission gate if a transmission gate was added and symbol / specifies GND, wherein an output comprises a circuit design.

20. A method of converting a CMOS design into a functionally equivalent reversible redesign, comprising:receiving CMOS parameters for power (Pc), clock rate (fc), and supply voltage (Vc); receiving an architectural description of a CMOS chip;receiving a floorplan of the CMOS chip;receiving a gate-level or register-transfer-level description of a CMOS logic; converting the gate-level or register-transfer-level description from CMOS gates to a partially reversible gate-level description;receiving reversible logic parameters for supply voltage (VR) and clock rate (fR); receiving correction factors to account for leakage, dark silicon, gate count, and four phases of the clocks;using the correction factors to estimate a CMOS capacitance (CR) and an area of a reversible redesign (AR);identifying a required number of layers ( / k) or Q factor (QRtype) for an energy-recycling power supply;selecting a most suitable option; andgenerating a layout geometry for reversible gates and the energy-recycling power supply.

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