Microelectromechanical system comprising a coating, and method for manufacturing the same

Abstract

There is provided a microelectromechanical system (MEMS) comprising two surfaces, wherein at least a portion of one of the surfaces has a coating comprising an etch resistant layer. Also described is an optical element for semiconductor manufacturing processes comprising such a system, as well as an exposure apparatus for semiconductor manufacturing processes comprising such a system or optical element. Further describes is a the use of such system, optical element or exposure apparatus, as well as a method of coating a silicon-based surface of a MEMS device with a metal silicate layer, and a method of manufacturing a MEMS device.

Description

MICROELECTROMECHANICAL SYSTEM COMPRISING A COATING, AND METHOD FOR MANUFACTURING THE SAMECROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority of EP application 25155293.1 which was filed on 31 January 2025, and which is incorporated herein in its entirety by reference.FIELD

[0002] The present invention relates to a microelectromechanical system (MEMS) comprising a surface that is coated. An optical element and an exposure apparatus comprising the microelectromechanical system are also described, along with a method of manufacturing a microelectromechanical system and the use of a microelectromechanical system in a semiconductor manufacturing method. The present invention has particular, but not exclusive, application to exposure apparatuses and methods for semiconductor manufacturing, such as lithographic apparatuses and methods, metrology apparatuses and methods, inspection apparatuses and methods, such as mask inspection apparatuses and methods, for example actinic mask inspection apparatuses and methods, all of which are or relate to exposure apparatuses or methods for semiconductor manufacturing processes.BACKGROUND

[0003] Light generated by means of a radiation source can be used by exposure apparatuses for semiconductor manufacturing processes. Examples of such exposure apparatuses are a lithographic apparatus, a metrology, or an inspection apparatus, such as a mask inspection apparatus or an actinic mask inspection apparatus.

[0004] A lithographic apparatus is a machine constructed to apply a desired pattern onto a substrate. A lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). A lithographic apparatus may for example project a pattern from a patterning device (e.g. a mask) onto a layer of radiation-sensitive material (resist) provided on a substrate.

[0005] The wavelength of radiation used by a lithographic apparatus to project a pattern onto a substrate determines the minimum size of features which can be formed on that substrate. A lithographic apparatus which uses EUV radiation, being electromagnetic radiation having a wavelength within the range 4-20 nm, may be used to form smaller features on a substrate than a conventional lithographic apparatus (which may for example use electromagnetic radiation with a wavelength of 193 nm).

[0006] Microelectromechanical systems (MEMS) are used to provide precise control of optical elements, such as mirrors. MEMS may be, for example, piezoelectric or capacitive. MEMS devices are sensitive to the environment in which they are located and may be impaired or damaged within the environment within an operating exposure apparatus for semiconductor manufacturing processes, suchas a lithographic apparatus, such as an EUV lithographic apparatus. This is due to the presence of radiation as well as hydrogen plasma in addition to the way in which MEMS devices function using a potential difference.

[0007] Accordingly, there is a requirement to provide a modified or improved microelectromechanical system that is suitable for operation in an exposure apparatus for semiconductor manufacturing processes, such as a lithographic apparatus that utilises EUV radiation in the presence of an ambient partial pressure of hydrogen.

[0008] The present invention has been devised in an attempt to address at least some of the problems identified above.SUMMARY OF THE INVENTION

[0009] According to a first aspect of the present disclosure, there is provided a microelectromechanical system (MEMS) comprising two surfaces, wherein at least a portion of one of the surfaces has a coating comprising an etch resistant layer.

[0010] The surfaces may be interdigitated. The surfaces may be planar. It will be appreciated that in a MEM system, the two surfaces are arranged facing one another such that an applied potential difference can be used to control the distance between the opposing surfaces.

[0011] It will be appreciated in the context of the invention that an “etch resistant layer” is a layer that does not show substantial etching, preferably no etching, in the presence of a hydrogen plasma. For example, an etch resistant layer at a temperature of 550°C may have an etch rate in hydrogen plasma of less than 1 nm h ’. The etch resistant layer may exhibit no change in surface roughness, thickness, mass density, crystal phase, and / or composition in nominal use. It has been found that providing resistance to etching is key to minimising long-term damage to the MEMS when operating the MEMS in an EUV lithographic apparatus. Etching of a layer will reduce the performance of the MEMS by changing the distances between the surfaces, thereby affecting the fine control of the component (e.g. mirror).

[0012] It has been found that available microelectromechanical systems are not suitable for operation in an environment which includes EUV radiation and hydrogen plasma. While EUV scanners operate in a high vacuum base pressure, there is a high flux of hydrogen present in the source vessel, which entails a flux of hydrogen entering the scanner in the intermediate focus (IF). The H flux creates a reducing environment that attenuates oxidation of mirror coatings. As a result of a flux of EUV photons, with some out-of-band contributions of other wavelengths (deep ultraviolet (DUV), vacuum UV (VUV) and infrared (IR)), the EUV photons interact with the H2molecules and create a low-ion energy plasma. Scanner surfaces are therefore exposed to low-pressure low-ion energy H plasma, as well as energetic EUV photons if they are in direct contact with the EUV beam. Existing MEMS devices are not exposed to such conditions and therefore are not provided with a coating since it is unnecessary and indeed it is undesirable in such cases to add to manufacturing complexity by providing such a coating when it is not needed.

[0013] Microelectromechanical systems typically comprise two interdigitated “comb-shaped” surfaces separated by a gap. In other examples, microelectromechanical systems may comprise two planar surfaces. Such microelectromechanical systems may be referred to as plate capacitive actuators or piezo-actuators. A potential difference is applied between the two surfaces which causes a controllable change in the distance between the two surfaces. This allows for precise alignment of an optical element. These interdigitated or planar surfaces are typically constructed from silicon and would etch very quickly when exposed to the low-ion energy H plasma environment of an EUV apparatus, especially for surfaces comprising the protruding digits due to the increased surface area. The etching of the silicon would affect the distance between the surfaces, particularly interdigitated surfaces, affecting the precise control afforded by the MEMS and drastically reducing the lifetime of the MEMS device.

[0014] The coating may further comprise a diffusion barrier layer. In such embodiments, the etch resistant layer will be a capping layer. A “capping layer” as used herein is intended to mean the layer which comes into contact with the hydrogen plasma in use, i.e. the outer layer of the coating.

[0015] It will be appreciated in the context of the invention that a “diffusion barrier layer” is a layer that does not show substantial permeation of hydrogen through the layer. For example, a diffusion barrier layer may comprise a hydrogen permeability of less than 7E-15 mol s1m1Pa1 / 2. The resistance to hydrogen permeation will mitigate the amount of hydrogen that reaches and reacts with the pristine (uncoated) surface, thereby therefore reduce damage to the underlying material, such as silicon.

[0016] This multilayer construction allows for a coating that is capable of withstanding etching in hydrogen plasma, and stopping diffusion of the hydrogen to the underlying surfaces, without necessarily requiring a single material that is capable of fulfilling both functions. This widens the number of suitable materials. It can also allow for a thinner overall coating, through the use of two thin layers optimised for each function. Providing a thin coating is particularly relevant given the small and finely tuned distances between interdigitated surfaces within a MEMS. The multilayer construction can also allow for design of a system that can withstand the voltages associated with the operation of MEMS, while still providing the beneficial properties described above.

[0017] The coating may further comprise an interlayer between the etch resistant capping layer and the diffusion barrier layer. Advantageously, an interlayer may mitigate stress-induced failures that can occur when applying the coatings to the interdigitated surfaces. In particular, the inventors have found that there is often large differences in the physical properties, for example the thermal expansion coefficient (CTE) and Young’s modulus (YM), of the etch resistant layer and the diffusion barrier layer, which can result in mechanical tensile pre-tension related issues and cause delamination of the two layers, particularly when exposed to the harsh conditions within a EUV lithographic apparatus.

[0018] The interlayer may comprise a thermal expansion coefficient that is between the thermal expansion coefficient of the etch resistant layer and the thermal expansion coefficient of the diffusion barrier layer.

[0019] The interlayer may comprise a Young’s modulus that is between the Young’s modulus of the etch resistant layer and the Young’s modulus of the diffusion barrier layer.

[0020] It will be appreciated that the interlayer is typically a different material to either the etch resistant layer and to the diffusion barrier layer. However, in some embodiments it may be hybrid material that has a composition formed from mixing the chemical compositions of the etch resistant layer and the diffusion barrier layer.

[0021] The etch resistant layer may comprise a metal oxide, a metal silicate, hexagonal boron nitride, or combinations thereof.

[0022] The metal oxide may be selected from Y2O3, AI2O3, HfCh. ZrC>2, RuCh. C1O2. E Ch, TiCF, NlvO or non-stoichiometric variants thereof.

[0023] The metal silicate may be selected from Y2SiOs, Al₂SiO₅, ZrSiOr. HFSiOr. RuSiOr, CrSiOr. or non-stoichiometric variants thereof.

[0024] In some preferred embodiments, the etch resistant layer comprises Y2O3, AI2O3, Al₂SiO₅, Y2SiC>5, or non-stoichiometric variants thereof. For example, the etch resistant layer may comprise Y2O3, AI2O3, or non-stoichiometric variants thereof.

[0025] The metal oxide and / or metal silicate may be polycrystalline, nanocrystalline or amorphous. The hexagonal boron nitride may be polycrystalline or nanocrystalline.

[0026] For example, the etch resistant layer may comprise nanocrystalline AI2O3, polycrystalline Y2O3, amorphous Y2SiOs, or amorphous AFSiOi.

[0027] Alternatively or additionally, the etch resistant layer may comprise amorphous ZrSiO-i. polycrystalline ZrC>2, polycrystalline Hf'CF, or amorphous HfSiOr.

[0028] The diffusion barrier layer may comprise a silicon nitride (SiNx), such as amorphous Si iNr; a silicon oxide, such as amorphous Si Ch; a Hafnium oxide, such as HfCh. or hexagonal boron nitride.

[0029] In some preferred embodiments, the diffusion barrier layer comprises SiiNr. or a non-stoichiometric variant thereof.

[0030] The interlayer may comprise a metal silicate or a metal oxide.

[0031] The metal silicate of the interlayer may be selected from Y2SiOs, AFSiOi. ZrSiOr. HfSiOr. RuSiCh. C SiO-i. or non-stoichiometric variants thereof. The dielectric breakdown voltage (Vb,i) of each i-th layer in the multilayer stack, must have a minimal value of Vb.i> Vo / (Ki- dm), lest dielectric breakdown occurs in two possible operating conditions of the MEMS device, explained shortly. Here Vo is the actuation voltage (that is the voltage drop that would reside over the actuation combs in absence of any coating), Ki is the i-th layer dielectric constant and dmis the combined thickness of the multilayers over which the voltage drop resides. For the first condition, here referred to as normal force actuation condition, the summation number m runs from m = 1 to 7 for the 7 dielectric layers (including the air gap) over which the voltage drop resides. For the second condition, here referred to as neutralized-plasma condition (explained further shortly), the summation number runs from 5 to 7 and the voltage drop resides over the coating on the actuation comb only.

[0032] The metal oxide of the interlayer may be a silicon oxide, such as SiCT. or a hafnium oxide, such as HfOi. Preferably, the metal oxide is HfCh.

[0033] In some preferred embodiments, the interlayer comprises Al₂SiO₅, SiCh, HfCh, or non-stoichiometric variants thereof.

[0034] In advantageous embodiments of the disclosure, at least one layer of the coating, optionally the diffusion barrier layer, has a dielectric breakdown voltage of at least 500 V pm1. The dielectric breakdown voltage of the layer may be at least 700 V m1, such as at least 800 V pm1. In preferred embodiments, the dielectric breakdown voltage of at least one layer (e.g. diffusion barrier layer) may be at least 1000 V pm1.

[0035] The dielectric breakdown voltage is an intrinsic property of a material that describes it resistance to a potential difference being applied across the material. It may be measured with currentvoltage (I-V) measurements.

[0036] A layer with a high dielectric breakdown voltage is advantageous because it can allow for thin layers to be used will mitigating damage to the coating that can arise from the voltage applied to the coating during operation, and during switching off of the MEMS system. In particular, after the plasma density vanishes and the actuation plate is grounded, a condition here referred to as plasmaneutralization condition, a higher voltage drop V’i spans over the i-th layer in the coating on the actuator plate. This could cause significant damage to the coating if none of the layers are capable of tolerating the voltage.

[0037] Accordingly, all of the layers on the actuation plate (for the opposite plate this condition does not hold unless that plate is used for actuation with positive bias), must adhere to the requirement that Vtoi > Vi‘ with V’i = —71 / (1—, wherein the tolerable voltage of the layer is defined by the dielectricSm=5 dmbreakdown voltage (in Vpm ') multiplied by the layer thickness (in pm). The summation runs from m = 5 to 7, which entails the voltage drop V’i spans only the 5th, 6thand 7thdielectric layers, see Fig. 5, so only the coating on the active actuator plate. It is thus from an electrical perspective possible to have a different multi-layer coating on the bottom than on the top plate electrode, but this is practically not possible as both bottom- and top-coatings are applied in a single ALD process.

[0038] Each of the individual layers of the coating may have a thickness of from 5 to 500 nm, such as from 10 to 400 nm provided that the condition of

[0036] is fulfilled.

[0039] In multilayer coatings, it is envisaged that one of the layers may be thicker than the other layers. This layer would typically be the layer capable of holding the majority of the voltage during operation and / or switch off. The thicker layer may be the diffusion barrier layer. The thickness of the diffusion barrier layer be of from 2 to 20 times the thickness of the etch resistant layer.

[0040] The diffusion barrier layer may have a thickness of from 20 to 500 nm. For example, diffusion barrier layer may have a thickness of from 40 to 400 nm.

[0041] The etch resistant layer may have a thickness of from 5 to 50 nm. For example, the etch resistant layer may have a thickness of from 10 to 30 nm.

[0042] The interlayer may have a thickness of from 5 to 50 nm. For example, the interlayer may have a thickness of from 10 to 30 nm.

[0043] The total thickness of a multilayer coating (i.e. a coating with at least an etch resistant layer and a diffusion layer) may be less than 500 nm. As explained above, providing a thinner coating can be advantageous to reduce the overall impact of the coating on the air gap in-between the two interdigitated surfaces and therefore reduce the impact on the precise control provided under applied voltages.

[0044] In one particular embodiment, the coating may consist of a single layer of hexagonal boron nitride. Advantageously hexagonal boron nitride has been found to provide good etch resistance and good barrier functions. In such embodiments, the thickness of the layer may be 1 μm or more, such as 1 to 2 pm. Using this thickness of hexagonal boron nitride provides a high tolerable voltage, allowing it to mitigate damage to the coating during unexpected shutoff of the device.

[0045] In multilayer coatings, it is beneficial if the inner layer (i.e. the layer that is applied to the interdigitated surface) has a thermal coefficient similar to the thermal coefficient of the interdigitated surface. As explained above, the surface is typically silicon, which has a thermal expansion coefficient of 2.6- 106°C'1. As a result, the inner layer of the coating, preferably the diffusion barrier layer, may have a thermal expansion coefficient of 4 • 106°C1or less, such as between 1.5 and 3.5 • 106°C'1.

[0046] In one particular embodiment, the coating comprises:an etch resistant capping layer comprising Y2O3 or AI2O3 with a thickness of 5 to 50 nm; and a diffusion barrier layer comprising Si iNr with a thickness of 20 to 500 nm.

[0047] This coating may further comprise a interlayer between the etch resistant capping layer and the diffusion barrier layer, the interlayer comprising a metal silicate, or a metal oxide different to metal oxide of the etch resistant capping layer, the interlayer comprising a thickness of 5 to 50 nm.

[0048] It will be appreciated in embodiments of the first aspect of the invention that the entire surface of one of the interdigitated surfaces may comprise the coating. Similarly, the entire surface of both interdigitated surfaces may comprise the coating.

[0049] The coating may be uniform over the entire surface(s), which may be interdigitated or planar. By interdigitated, it will be understood that such surfaces comprise a plurality of upstanding protrusions which are configured to interdigitate with corresponding protrusions from another, opposing surface. A conformal coating is advantageous as it ensure that all of the surface is protected from the hydrogen plasma environment of the EUV lithographic apparatus and ensure that the is no variation in the thickness of the gap between the i surfaces due to uneven coating at different points. This can provide more reliable operation of the MEMS.

[0050] According to a second aspect of the present disclosure, there is provided an optical element for semiconductor manufacturing processes comprising the microelectromechanical system (MEMS) of the first aspect of the present disclosure.

[0051] According to a third aspect of the present disclosure, there is provided an exposure apparatus for semiconductor manufacturing processes, such as a lithographic apparatus, comprising the microelectromechanical system (MEMS) of the first aspect of the present disclosure, or the optical element of the second aspect of the present disclosure.

[0052] According to a fourth aspect of the present disclosure, there is provided the use of any of the first to third aspects of the present disclosure in a semiconductor manufacturing method.

[0053] According to a fifth aspect of the present disclosure, there is provided a method of coating a silicon-based surface of a microelectromechanical system (MEMS) device with a metal silicate layer, the method comprising the steps of:depositing a layer of a metal or a metal oxide directly to the silicon-based surface by atomic layer deposition; andannealing the metal or metal oxide layer at a temperature of 600°C or greater in the presence of oxygen.

[0054] According to a sixth aspect of the present disclosure, there is provided a method of coating a surface of a microelectromechanical system (MEMS) with a metal silicate layer, the method comprising the steps of:providing a layer of silicon oxide, such as Si Ch. on the surface by depositing the silicon oxide on the surface by atomic layer deposition, or by annealing a silicon-based surface in oxygen; anda) depositing a metal oxide layer on the silicon oxide layer by atomic layer deposition and annealing at a temperature of 600°C or greater; orb) depositing a metal layer on the silicon oxide layer by atomic layer deposition and annealing at a temperature of 600°C or greater in the presence of oxygen.

[0055] In the fifth and sixth aspects of the present invention, the metal oxide may be selected from RuC, Y2O3, AI2O3, HfC, Z1O2.

[0056] In the fifth and sixth aspects of the present invention, the metal may be Ruthenium, Yttrium, Aluminium, Hafnium, or Zirconium.

[0057] In the fifth and sixth aspects of the present invention, the annealing may be at a temperature of 700 °C or greater, optionally 800 °C or greater. For example, the annealing may be at 900 °C or greater.

[0058] According to a seventh aspect of the present disclosure, there is provided a method of manufacturing a microelectromechanical system (MEMS) according to the first aspect of the invention, the method comprising:applying an etch resistant layer over at least a portion of one of the surfaces of the microelectromechanical system by atomic layer deposition.

[0059] The method may further comprise applying a diffusion barrier layer to the surface by atomic layer deposition prior to applying the etch resistant (capping) layer over the diffusion barrier layer.

[0060] The method may further comprise applying an interlayer over the diffusion barrier layer prior to applying the etch resistant (capping) layer over the interlayer.

[0061] For the avoidance of doubt, the etch resistant layer, diffusion barrier layer and / or interlayer may be the layers as defined in relation to the first aspect of the invention.

[0062] In embodiments, where the etch resistant layer, diffusion barrier layer, and / or the interlayer comprise a metal silicate, said layer may be applied via the method according the fifth or sixth aspects of the invention.

[0063] According to an eighth aspect of the present disclosure, there is provided a coating for a microelectromechanical system (MEMS) system, the coating comprising:an etch resistant capping layer comprising Y2O3 or AI2O3 with a thickness of 5 to 50 nm; a interlayer under the etch resistant capping layer, the interlayer having a thickness of 5 to 50 nm,a diffusion barrier layer under the interlayer, the diffusion barrier layer comprising Si₃N₄ with a thickness of 20 to 500 nm;wherein the interlayer comprises a metal silicate, or a metal oxide and has a thermal expansion coefficient that is in-between the thermal expansion coefficient of the etch resistant capping layer and the thermal expansion coefficient of the diffusion barrier layer.

[0064] The diffusion barrier thickness may be a minimum of 25 nm in thickness. The diffusion barrier thickness may be around 25 to 50 nm, for example around 40 nm.

[0065] It will be appreciated that features described in respect of one aspect may be combined with any features described in respect of another aspect and all such combinations are expressly considered and disclosed herein.BRIEF DESCRIPTION OF THE DRAWINGS

[0066] Embodiments of the invention will now be described, by way of example only, with reference to the accompanying schematic drawing in which corresponding reference symbols indicate corresponding parts, and in which:

[0067] Figure 1 depicts a lithographic apparatus according to an embodiment of the invention;

[0068] Figure 2 is a schematic showing the architecture of a microelectromechanical system;

[0069] Figure 3 is a schematic showing the coating of two interdigitated surfaces of a microelectromechanical system;

[0070] Figure 4 is a schematic depiction of a multilayer coating applied to a surface within a microelectromechanical system;

[0071] Figure 5 (left) is a schematic showing the potential applied between two surfaces that are each coated with a multilayer coating in the normal force actuation condition; Figure 5 (right) is a schematic showing the potential drop falls over only the coating on the active actuator surface after the plasma turns off and that plate is grounded. This condition is called the plasma-neutralization condition;

[0072] Figures 6 to 8 depicts examples of methods of manufacturing according to the present disclosure.

[0073] The features and advantages of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings, in which like reference characters identify corresponding elements throughout. In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements.DETAILED DESCRIPTION

[0074] Figure 1 shows an exposure apparatus for semiconductor manufacturing processes, specifically a lithographic system according to one aspect of the present disclosure. The lithographic system comprises a radiation source SO and a lithographic apparatus LA. The radiation source SO is configured to generate an extreme ultraviolet (EUV) radiation beam B. The lithographic apparatus LA comprises an illumination system IL, a support structure MT configured to support a patterning device MA (e.g. a mask), a projection system PS and a substrate table WT configured to support a substrate W. The illumination system IL is configured to condition the radiation beam B before it is incident upon the patterning device MA. The projection system is configured to project the radiation beam B (now patterned by the mask MA) onto the substrate W. The substrate W may include previously formed patterns. Where this is the case, the lithographic apparatus aligns the patterned radiation beam B with a pattern previously formed on the substrate W.

[0075] The radiation source SO, illumination system IL, and projection system PS may all be constructed and arranged such that they can be isolated from the external environment. A gas at a pressure below atmospheric pressure (e.g. hydrogen) may be provided in the radiation source SO. A vacuum may be provided in illumination system IL and / or the projection system PS. A small amount of gas (e.g. hydrogen) at a pressure well below atmospheric pressure may be provided in the illumination system IL and / or the projection system PS.

[0076] The radiation source SO shown in Figure 1 is of a type which may be referred to as a laser produced plasma (LPP) source. A laser, which may for example be a CO2 laser, is arranged to deposit energy via a laser beam into a fuel, such as tin (Sn) which is provided from a fuel emitter. Although tin is referred to in the following description, any suitable fuel may be used. The fuel may for example be in liquid form, and may for example be a metal or alloy. The fuel emitter may comprise a nozzle configured to direct tin, e.g. in the form of droplets, along a trajectory towards a plasma formation region. The laser beam is incident upon the tin at the plasma formation region. The deposition of laser energy into the tin creates a plasma at the plasma formation region. Radiation, including EUV radiation, is emitted from the plasma during de-excitation and recombination of ions of the plasma.

[0077] The EUV radiation is collected and focused by a near normal incidence radiation collector (sometimes referred to more generally as a normal incidence radiation collector). The collector may have a multilayer structure which is arranged to reflect EUV radiation (e.g. EUV radiation having a desired wavelength such as 13.5 nm). The collector may have an elliptical configuration, having twoellipse focal points. A first focal point may be at the plasma formation region, and a second focal point may be at an intermediate focus, as discussed below.

[0078] The laser may be separated from the radiation source SO. Where this is the case, the laser beam may be passed from the laser to the radiation source SO with the aid of a beam delivery system (not shown) comprising, for example, suitable directing mirrors and / or a beam expander, and / or other optics. The laser and the radiation source SO may together be considered to be a radiation system.

[0079] Radiation that is reflected by the collector forms a radiation beam B. The radiation beam B is focused at a point to form an image of the plasma formation region, which acts as a virtual radiation source for the illumination system IL. The point at which the radiation beam B is focused may be referred to as the intermediate focus. The radiation source SO is arranged such that the intermediate focus is located at or near to an opening in an enclosing structure of the radiation source.

[0080] The radiation beam B passes from the radiation source SO into the illumination system IL, which is configured to condition the radiation beam. The illumination system IL may include a facetted field mirror device 16 and a facetted pupil mirror device 11. The faceted field mirror device 16 and faceted pupil mirror device 11 together provide the radiation beam B with a desired cross-sectional shape and a desired angular distribution. The radiation beam B passes from the illumination system IL and is incident upon the patterning device MA held by the support structure MT. The patterning device MA reflects and patterns the radiation beam B. The illumination system IL may include other mirrors or devices in addition to or instead of the faceted field mirror device 16 and faceted pupil mirror device 11.

[0081] Following reflection from the patterning device MA the patterned radiation beam B enters the projection system PS. The projection system comprises a plurality of mirrors 13, 14 which are configured to project the radiation beam B onto a substrate W held by the substrate table WT. The projection system PS may apply a reduction factor to the radiation beam, forming an image with features that are smaller than corresponding features on the patterning device MA. A reduction factor of 4 may for example be applied. Although the projection system PS has two mirrors 13, 14 in Figure 1, the projection system may include any number of mirrors (e.g. six mirrors).

[0082] The radiation sources SO shown in Figure 1 may include components which are not illustrated. For example, a spectral filter may be provided in the radiation source. The spectral filter may be substantially transmissive for EUV radiation but substantially blocking for other wavelengths of radiation such as infrared radiation.

[0083] The exposure apparatus may include a MEMS device according to the present disclosure.

[0084] Figure 2 depicts the basic architecture of a microelectromechanical system 1. The MEMS includes a mirror plate 2, a fixing plate 3, an isolator 4, an upper combs 5, and a lower combs 6 interdigitated with the upper combs 5. The upper and lower combs can also be referred to as plates. A leaf spring (not shown) may be located between the upper 5 and lower combs 6. During operation, a potential difference is applied to the upper 5 and lower combs 6, for example, a voltage of + 40V onthe upper combs a voltage of - 100V on the lower combs. The interaction between the plates at different voltages causes the distance between the upper and lower combs to change relative the starting geometry (e.g. for the gap between the plates to decrease). By tuning the voltage (and knowing the strength of the resisting leaf spring), the distance between the combs can be precisely controlled allowing for accurate adjustment of the mirror plate. The mirror plate can then be used to direct EUV radiation within the lithographic apparatus.

[0085] In conventional microelectromechanical systems, the interdigitated plates (combs) are made of silicon and the gap between the interdigitated surfaces is in the order of 2 to 5 pm. The potential difference between the plates can be up to 300 V.

[0086] Whilst microelectromechanical systems are known, they have not previously been considered for use within an EUV lithographic apparatus. A primary issue that prevents their use is that the interdigitated silicon surfaces will be susceptible to etching from the hydrogen plasma that is generated in the EUV lithographic apparatus. Similarly, since the present disclosure is also applicable to MEMS devices comprising planar surfaces which are not interdigitated in the assembled form, the planar surfaces can also be damaged by hydrogen plasma that is generated in the lithographic apparatus, or indeed other exposure apparatus for manufacture of semiconductor devices which generates hydrogen plasma.

[0087] The present disclosure attempts to address this issue by providing a coating that protects the surfaces and allow the microelectromechanical system to be used under the harsh conditions within an EUV lithographic apparatus.

[0088] Figure 3 depicts a schematic of a coating applied to a portion of the interdigitated surfaces. A coating 17 is applied to the upper combs 15 and a coating 18 is applied to lower combs 16.

[0089] The coating comprises at least an etch resistant layer but is preferably a multilayer coating comprising both an etch resistant layer, a diffusion barrier layer and an interlayer between the diffusion barrier layer and the etch resistant layer.

[0090] Figure 4 provides a schematic of a multilayer layer coating applied to one of the interdigitated surfaces (combs). There is a diffusion barrier layer 23 positioned on the silicon surface 24 of the pristine combs, an interlayer 22 positioned on the diffusion barrier layer and an etch resistant layer 21 positioned on the interlayer. The etch resistant layer acts as a capping layer preventing direct etching of the layers underneath from the hydrogen plasma during operation.

[0091] An example of the structure of the microelectromechanical system with a multilayer coating is shown in Table 1 below, in the condition of normal force actuation operation (i.e. that no plasma with neutralizing mobile charge carriers has been applied between the plates of the device). The normal force actuation operation condition is depicted in Figure 5 (left). This example uses Si₃N₄ as the diffusion barrier material, HfO₂ as the interlayer and Al₂O₃ as the etch resistant layer. As can be seen, the layers are relatively thin compared to the gap between the coated surfaces (air gap). In the example below, the coatings reduce the air gap from about 3 pm to 2.84 pm. HfCh has mechanical properties (e.g. thermalexpansion) falling between Si₃N₄ and Al₂O₃ and therefore works well as the interlayer. Further, theTop plate Bottom platediffusion barrier layer has a thermal expansion coefficient that is similar to the silicon substrate that the coating is applied to (CTEsi = 2.6).VoltageCTE Dielectric Layer Breakdown Tolerable ALD overFunction dielectric / io-6constant thickness voltage Voltage Material layer°c-1Kj / - dj / m Vb / V.μm-1Vtol / V Vi / VVoltagedroplayer & Si3N4 1 ~3 7.5 4E-08 0.53 1160 46 DiffusionbarrierCTE &YMHfO2 2 ~6 26 2E-08 0.08 550 11 matchlayerPlasmaetch stop A12O3 3 7.7 8.5 2E-08 0.24 700 14 layerGap Air 4 1 2.84E-06 284 3000000 8520000 Plasmaetch stop A12O3 5 7.7 8.5 2E-08 0.24 700 14 layerCTE &YMHfO2 6 ~6 26 2E-08 0.08 550 11 matchlayerVoltagedroplayer & Si3N4 7 ~3 7.5 4E-08 0.53 1160 46 DiffusionbarrierKeq =Total 3.00E-06 285.71.050Consistency check: Veq = VO / Keq = 300 / 1.05 = 285.7 V correctTop plateTable 1 - Example coating of two interdigitated surfaces in a microelectromechanical system under normal force actuation operation conditions (i.e. in the absence of any plasma with neutralizing mobile charge carriers). Keq, Veqare the effective or equivalent dielectric constant and voltage, respectively. A multilayer coating comprising layers of different dielectric constants may be electrically represented by a single-layer coating with equivalent dielectric constant (and equivalent thickness).As Table 1 reveals in the normal force actuation condition the tolerable voltage of the i-th layer in the tri-layer stack (Vtoi,i = Vbj-di), which is the product of the breakdown voltage (Vb,i) and the layer thickness (di), exceeds the voltage (Vi) that resides over the layer, with Vi = di·V₀ / (Ki·∑dm), this holds for all layers in the tri-layer stack and there is no apparent risk for dielectric breakdown of any of the layers.

[0092] The same example MEMS structure with a multilayer coating is shown in Table 2 below, in the condition that the actuation voltage has been applied, then a plasma has been created between the plates and negative charges from the plasma have migrated to the coating on the coated positive actuation plate, then the voltage has been turned off and then the coated positive actuation plate has been grounded, in that specific sequence. We refer to this situation as plasma-neutralized condition, it is sketched in Figure 5 (right). For this same example with again Si₃N₄ as the diffusion barrier material, HfO₂ as the interlayer and Al₂O₃ as the etch resistant layer, it can be understood that any voltage now resides over the actuation comb that was positive but is now grounded. It is evident that there is no longer an air gap present that accommodates the large voltage drop. Table 2 shows how the voltage values change after the plasma-neutralized condition has been realized.VoltageCTE Dielectric Layer Breakdown Tolerable ALD overFunction dielectric / io-6constant thickness voltage Voltage Material layer°c-1K / - dj / m Vh / V.pm1Vtol / V Vi / VVoltagedroplayer & Si3N4 1 ~3 7.5 4E-08 20 1160 46 DiffusionbarrierCTE &HfO2 2 ~6 26 2E-08 2.9 550 11 YMmatchlayerPlasmaetch stop A12O3 3 7.7 8.5 2E-08 8.8 700 14 layerKeq =Total 8E-08 31.79.46Consistency check: Veq = VO / Keq = 300 / 9.46 = 31.7 V correctTable 2 - Example coating of two interdigitated surfaces in a microelectromechanical system after plasma-neutralization has occurred (i.e. the actuation voltage is applied, a plasma is created between the plates and negative charges from the plasma have migrated to the coating on the coated positive actuation plate, then the voltage has been turned off and then the coated positive actuation plate has been grounded, in that specific sequence).The actuation voltage of Vo = 300 V now initially (before electric shielding occurs) resides over the coating of the actuation comb that was positively charged but after the plasma was turned on and off, was actively grounded. The 300 V initially resides over the coating thickness of 80 nm, the tri-layer coating has in the example an effective dielectric constant of Keq= 9.46, so the 300 V is rapidly reduced by that factor (due to shielding of the electric fields of the bound charges in the coating) to Veq= Vo / Keq= 31.7 V. That voltage divides over the three layers in the stack and for each layer the value is below the tolerable value and there is no risk of ESD.

[0093] The layers can be applied by atomic layer deposition. The metal silicate layers (e.g. Al₂SiO₅), can be applied via the multi-step atomic deposition and annealing method described in more detail below.

[0094] Table 1 shows the voltage division over the various layers during normal force actuation operation, along with the tolerable voltage Vtolof each layer. The voltage drop Viover each sublayer is determined by the dielectric strength Ki, the thickness of the layer di and by the gap distance di according to the equations below, which also show the derivation of the equivalent voltage, dielectric constant and capacitance. Here, Ceq, Veq, Keqare equivalent capacitance, voltage drop and dielectric constant, respectively. Q and o are charge and -density on actuator plate, resp. A is plate surface area, Ei and 8i are electric field in and dielectric permittivity of the i-th layer, resp. Vo is the applied actuation force, which would be over the gap between the plates in absence of any coating. The summation numbers i, n and m run from 1 to 7 (number of dielectric layers plus air gap).Equivalent multi-layer coating capacitance Ceq, Q _ ^-*4 21 On £n_ 2k0Jin Kneq” S^ " S£Eidi "S. £d. “ S£d£n7;^ ” S££ n7J^ KjVoltage drop V, over i-th layer in multi-layer coatingV1= E1d1= (σ / ε1)d1= (σ / (K1ε₀))d1= (d1 / K1)(σ / ε₀) = (d1 / K1)(V₀ / d₀) = (d1V₀) / (K1∑mdm) ⇒ Vi= (diV₀) / (Ki∑mdm)Equivalent multi-layer coating dielectric constant Keq∑iVi= (V₀ / ∑mdm)∑i(di / Ki) = (V₀ / (∑mdm∏nKn))∑idi∏j,j≠iKj; Veq= V₀ / Keq; Veq= ∑iVi; Keq= (∑mdm∏nKn) / (∑idi∏j,j≠iKj)Veq= S£Vi > Equivalent multi-layer coating voltage drop VeqVQvexi =2uL“eq _ do. IlaA.. \Si di

[0095] As can be seen, during normal force actuation operation, i.e. application of the actuation voltage of Vo, the presence of the two multi-layer coatings and the air gap result in reduction of Vo to Veqdue to the capacitances of the layers. During normal force actuation operation the majority of voltage is held over the air gap as its dimension (thickness di) exceeds that of the individual coating thicknesses by factor lOOx. As a result the coatings experience only a limited voltage drop of Vi. Hereby it is key that the voltage drop is smaller than the tolerable voltage drop Vtoi(Vi < Vtoi, with Vtoi= Vbj-di), otherwise dielectric breakdown occurs.

[0096] However, in the event that the normal force actuation operation changes to the plasmaneutralization condition, then the same formulism applies (it is practical to provide ‘ to the quantities, e.g. Vi Vi’), but the summation numbers i, n and m run from 5 to 7 only. So the voltage only spans the thickness of the multi-layer coating on the actuation plate that was positively charged but was grounded after the plasma turned off. Numerically this entails that in the plasma-neutralization condition Keqis much larger, and Veqis much smaller. Now the condition Vi < Vb,i-di) is much more gating as the value of Vi has increased drastically. The combination of coating thicknesses, dielectric constants and breakdown voltage are crucial to avoid dielectric breakdown of one or more of the layers, which terminates the protective function of the coating.

[0097] As specified above, the thin coatings can be provided on the interdigitated (comb-shaped) surfaces or planar surfaces using atomic layer deposition. For multilayer coatings, the coating can bebuilt up layer-by-layer using atomic layer deposition. Atomic layer deposition has advantageous been found to provide conformal coating of the complicated interdigitated surfaces within the MEMS.

[0098] However, metal silicate layers (for example YiSiCU Al₂SiO₅, ZrSiOr. HfSiOr. and RuSiOr), cannot be applied directly via atomic layer deposition. A number of multi-step methods for applying these coatings to a MEMS device have therefore been developed. Examples of these methods are provided below (examples 3 to 5).

[0099] Example 3 (shown in Figure 6) comprises applying a metal oxide (RuO₂, Y₂O₃, Al₂O₃, HfO₂ or ZrO₂) layer 52 directly onto a silicon substrate 51 by atomic layer deposition. The layer is then annealed at elevated temperature of 600-900°C for 2-8 hours in the presence of an O2 flow. During the anneal step, silicon atoms are consumed from the surface of the pristine silicon substrate 51 and combined with the metal oxide layer to form a single layer of metal silicate 53.

[0100] Example 4 (shown in Figure 7) comprises an initial step of providing a silicon oxide (SiO₂) layer 62 on a silicon substrate 61, or on another layer of the coating. This can either be obtained through atomic layer deposition of SiO₂, or by annealing a silicon surface in an oxygen or water partial pressure. A metal (Ru, Y, Al, Hf or Zr) layer 63 is then applied onto a silicon oxide by atomic layer deposition. The layers are then annealed at 600-900°C for 2-8 hours in the presence of an O2 or H2O flow and combine to form a single layer of metal silicate 64.

[0101] Example 5 (shown in Figure 8) has the same initial step as example 4 but instead of applying a metal layer to the silicon oxide, it comprises applying a metal oxide (RuO₂, Y₂O₃, Al₂O₃, HfO₂ or ZrO₂) layer 73 onto the silicon oxide layer 72 by atomic layer deposition. In example 5, the silicon oxide layer is on a silicon substrate 71, but in other examples, the silicon oxide can be positioned on another layer of the coating. The silicon oxide and metal oxide layers are then annealed at 600-900°C for 2-8 hours to form a single layer of metal silicate 74. Unlike examples 3 and 4, this anneal step does not require the presence of an O2 or H2O flow due to the higher oxygen content provided by the metal oxide and silicon oxide layers.

[0102] While specific embodiments of the invention have been described above, it will be appreciated that the invention may be practiced otherwise than as described. The descriptions above are intended to be illustrative, not limiting. Thus it will be apparent to one skilled in the art that modifications may be made to the invention as described without departing from the scope of the claims and clauses set out below.1. A microelectromechanical system (MEMS) comprising two surfaces, wherein at least a portion of one of the surfaces has a coating comprising an etch resistant layer.2. The microelectromechanical system of clause 1 wherein the coating further comprises a diffusion barrier layer, and wherein the etch resistant layer is a capping layer.3. The microelectromechanical system of clause 2 wherein the coating further comprises an interlayer between the etch resistant capping layer and the diffusion barrier layer.4. The microelectromechanical system of clause 3, wherein the interlayer comprises a thermal expansion coefficient that is between the thermal expansion coefficient of the etch resistant layer and the thermal expansion coefficient of the diffusion barrier layer.5. The microelectromechanical system of clauses 3 or 4, wherein the interlayer comprises a Young’s modulus that is between the Young’s modulus of the etch resistant layer and the Young’s modulus of the diffusion barrier layer.6. The microelectromechanical system of any preceding clause, wherein the etch resistant layer comprises a metal oxide, a metal silicate, hexagonal boron nitride, or combinations thereof.7. The microelectromechanical system of clause 6, wherein the metal oxide is selected from Y₂O₃, Al₂O₃, HfO₂, ZrO₂, RuO2, CrO₂, Er₂O₃, TiO₂, Nb₂O₅, or non-stoichiometric variants thereof.8. The microelectromechanical system of clauses 6, wherein the metal silicate is selected from Y₂SiO₅, Al₂SiO₅, ZrSiO₄, HFSiO₄, RuSiO₄, CrSiO₄, or non-stoichiometric variants thereof.9. The microelectromechanical system of clause 7 or 8, wherein the etch resistant layer comprises Y₂O₃, Al₂O₃, Al₂SiO₅, Y₂SiO₅, or non-stoichiometric variants thereof; preferably wherein the etch resistant layer comprises Y2O3, AI2O3, or non-stoichiometric variants thereof.10. The microelectromechanical system of clauses 2 to 9, wherein the diffusion barrier layer comprises a silicon nitride (SiNx), such as amorphous Si₃N₄; a silicon oxide, such as amorphous SiO₂; a Hafnium oxide, such as HfO₂, or hexagonal boron nitride; preferably wherein the diffusion barrier layer comprises Si₃N₄, or a non-stoichiometric variant thereof.11. The microelectromechanical system of clause any preceding clause, wherein the interlayer comprises a metal silicate or a metal oxide.12. The microelectromechanical system of clause 11 wherein the silicate is selected from Y₂SiO₅, Al₂SiO₅, ZrSiO₄, HfSiO₄, RuSiO₄, CrSiO₄, or non-stoichiometric variants thereof, preferably wherein the silicate is Al₂SiO₅; and / or wherein the metal oxide is a silicon oxide, such as SiC>2, or a hafnium oxide, such as HfCh.13. The microelectromechanical system of clauses 2 to 12, wherein one of the layers, optionally the diffusion barrier layer, has a dielectric breakdown voltage of at least 500 V m1, such as at least 1000 V pm1.14. The microelectromechanical system of clauses 2 to 13, wherein one of the layers, optionally the diffusion barrier layer, has a tolerable voltage of at least Vtoi> Vi‘ with Vt= —71 / (1—, whereinKl Sm=5 the tolerable voltage of the layer is defined by the dielectric breakdown voltage (in Vpm1) multiplied by the layer thickness (in pm), optionally wherein m = 5 to 7, such that the voltage drop V’i spans only the 5th, 6thand 7thdielectric layers, so only the coating on the active actuator plate.15. The microelectromechanical system of clauses 2 to 11, wherein the diffusion barrier layer has a thickness of from about 20 to about 500 nm, optionally a thickness of about 40 nm to about 400 nm.16. The microelectromechanical system of any preceding clause, wherein the etch resistant layer has a thickness of 5 to 50 nm, preferably 10 to 30 nm.17. The microelectromechanical system of clauses 3 to 16, wherein the interlayer has a thickness of 5 to 50 nm, preferably 10 to 30 nm.18. The microelectromechanical system of clauses 2 to 17, wherein the total thickness of the coating is less than 500 nm.19. The microelectromechanical system of clause 1, wherein the coating consists of a single layer of hexagonal boron nitride, preferably wherein the thickness of the layer is 1 μm or more.20. The microelectromechanical system of clauses 2 to 18, wherein the coating comprises:an etch resistant capping layer comprising Y2O3 or AI2O3 with a thickness of 5 to 50 nm; and a diffusion barrier layer comprising Si₃N₄ with a thickness of 20 to 500 nm;optionally wherein the coating further comprises a interlayer between the etch resistant capping layer and the diffusion barrier layer, the interlayer comprising a metal silicate, or a metal oxide different to metal oxide of the etch resistant capping layer, the interlayer comprising a thickness of 5 to 50 nm.21. The microelectromechanical system of any preceding clause, wherein the entire surface of one of the surfaces comprises the coating, optionally wherein the entire surface of both surfaces comprise the coating.22. The microelectromechanical system of clause 21, wherein the coating is uniform over the entire surface.23. The microelectromechanical system of any preceding clause, wherein the surface(s) comprise silicon.24. The microelectromechanical system of any preceding clauses, wherein the surfaces are interdigitated or planar.25. An optical element for semiconductor manufacturing processes comprising the microelectromechanical system (MEMS) of any one of clauses 1 to 24.26. An exposure apparatus for semiconductor manufacturing processes, such as a lithographic apparatus, comprising the microelectromechanical system (MEMS) of any one of clauses 1 to 24, or the optical element of clause 25.27. The use of a microelectromechanical system (MEMS,) optical element or exposure apparatus according to any one of clauses 1 to 26 in a semiconductor manufacturing method.28. Method of coating a silicon-based surface of a microelectromechanical system (MEMS) device with a metal silicate layer, the method comprising the steps of:depositing a layer of a metal or a metal oxide directly to the silicon-based surface by atomic layer deposition; andannealing the metal or metal oxide layer at a temperature of 600°C or greater in the presence of oxygen.29. Method of coating a surface of a microelectromechanical system (MEMS) with a metal silicate layer, the method comprising the steps of:providing a layer of silicon oxide, such as Si Ch. on the surface by depositing the silicon oxide on the surface by atomic layer deposition, or by annealing a silicon-based surface in oxygen; and a) depositing a metal oxide layer on the silicon oxide layer by atomic layer deposition and annealing at a temperature of 600°C or greater; orb) depositing a metal layer on the silicon oxide layer by atomic layer deposition and annealing at a temperature of 600°C or greater in the presence of oxygen.30. The method of clauses 28 or 29 wherein the metal oxide is selected from RuO₂, Y₂O₃, Al₂O₃, HfO₂, ZrO₂, or the metal is Ruthenium, Yittrium, Aluminium, Hafnium or Zirconium.31. The method of clauses 28 to 30 wherein the annealing is at a temperature of 700 °C or greater, optionally 800 °C or greater, such as 900 °C or greater.32. A method of manufacturing a microelectromechanical system (MEMS) of any one of clauses 1 to 24, the method comprising:applying an etch resistant layer over at least a portion of one of the interdigitated surfaces of the microelectromechanical system by atomic layer deposition.33. The method of clause 32 further comprising:applying a diffusion barrier layer to the surface by atomic layer deposition prior to applying the etch resistant (capping) layer over the diffusion barrier layer.34. The method of clause 33, further comprising:applying an interlayer over the diffusion barrier layer prior to applying the etch resistant (capping) layer over the interlayer.35. The method according to clause 32 to 34, wherein the etch resistant layer, diffusion barrier layer, and / or the interlayer comprise a metal silicate and are applied via the method of clauses 28 to 31.36. A coating for a microelectromechanical system (MEMS) system, the coating comprising: an etch resistant capping layer comprising Y2O3 or AI2O3 with a thickness of 5 to 50 nm; a interlayer under the etch resistant capping layer, the interlayer having a thickness of 5 to 50 nm,a diffusion barrier layer under the interlayer, the diffusion barrier layer comprising Si₃N₄ with a thickness of 20 to 500 nm;wherein the interlayer comprises a metal silicate, or a metal oxide and has a thermal expansion coefficient that is in-between the thermal expansion coefficient of the etch resistant capping layer and the thermal expansion coefficient of the diffusion barrier layer.

Claims

CLAIMS1. A microelectromechanical system (MEMS) comprising two surfaces, wherein at least a portion of one of the surfaces has a coating comprising an etch resistant layer.

2. The microelectromechanical system of claim 1 wherein the coating further comprises a diffusion barrier layer, and wherein the etch resistant layer is a capping layer.

3. The microelectromechanical system of claim 2 wherein the coating further comprises an interlayer between the etch resistant capping layer and the diffusion barrier layer.

4. The microelectromechanical system of claim 3, wherein the interlayer comprises a thermal expansion coefficient that is between the thermal expansion coefficient of the etch resistant layer and the thermal expansion coefficient of the diffusion barrier layer.

5. The microelectromechanical system of claims 3 or 4, wherein the interlayer comprises a Young’s modulus that is between the Young’s modulus of the etch resistant layer and the Young’s modulus of the diffusion barrier layer.

6. The microelectromechanical system of any preceding claim, wherein the etch resistant layer comprises a metal oxide, a metal silicate, hexagonal boron nitride, or combinations thereof.

7. The microelectromechanical system of claim 6, wherein the metal oxide is selected from Y₂O₃, Al₂O₃, HfO₂, ZrO₂, RuO2, CrO₂, Er₂O₃, TiO₂, Nb₂O₅, or non-stoichiometric variants thereof.

8. The microelectromechanical system of claims 6, wherein the metal silicate is selected from Y₂SiO₅, Al₂SiO₅, ZrSiO₄, HFSiO₄, RuSiO₄, CrSiO₄, or non-stoichiometric variants thereof.

9. The microelectromechanical system of claim 7 or 8, wherein the etch resistant layer comprises Y₂O₃, Al₂O₃, Al₂SiO₅, Y₂SiO₅, or non-stoichiometric variants thereof; preferably wherein the etch resistant layer comprises Y2O3, AI2O3, or non-stoichiometric variants thereof.

10. The microelectromechanical system of claims 2 to 9, wherein the diffusion barrier layer comprises a silicon nitride (SiNx), such as amorphous Si₃N₄; a silicon oxide, such as amorphous SiO₂; a Hafnium oxide, such as HfO₂, or hexagonal boron nitride; preferably wherein the diffusion barrier layer comprises Si₃N₄, or a non-stoichiometric variant thereof.

11. The microelectromechanical system of claim any preceding claim, wherein the interlayer comprises a metal silicate or a metal oxide.

12. The microelectromechanical system of claim 11; wherein the silicate is selected from Y2SiO5, A12SiO5, ZrSiO4, HfSiO4, RuSiO4, CrSiO4, or non-stoichiometric variants thereof, preferably wherein the silicate is A12SiO5; and / or wherein the metal oxide is a silicon oxide, such as SiO2, or a hafnium oxide, such as HfO2.

13. The microelectromechanical system of claims 2 to 12, wherein one of the layers, optionally the diffusion barrier layer, has a dielectric breakdown voltage of at least 500 V μm-1, such as at least 1000 V μm-1.

14. The microelectromechanical system of claim 1, wherein the coating consists of a single layer of hexagonal boron nitride, preferably wherein the thickness of the layer is 1 μm or more.

15. The microelectromechanical system of claims 2 to 14, wherein the coating comprises:an etch resistant capping layer comprising Y2O3 or A12O3 with a thickness of 5 to 50 nm; and a diffusion barrier layer comprising Si3N4 with a thickness of 20 to 500 nm;optionally wherein the coating further comprises a interlayer between the etch resistant capping layer and the diffusion barrier layer, the interlayer comprising a metal silicate, or a metal oxide different to metal oxide of the etch resistant capping layer, the interlayer comprising a thickness of 5 to 50 nm.

16. The microelectromechanical system of any preceding claims, wherein the surfaces are interdigitated or planar.

17. An optical element for semiconductor manufacturing processes comprising the microelectromechanical system (MEMS) of any one of claims 1 to 16.

18. An exposure tool, such as a lithographic apparatus, comprising the microelectromechanical system (MEMS) of any one of claims 1 to 16, or the optical element of claim 17.

19. Method of coating a silicon-based surface of a microelectromechanical system (MEMS) device with a metal silicate layer, the method comprising the steps of:depositing a layer of a metal or a metal oxide directly to the silicon-based surface by atomic layer deposition; andannealing the metal or metal oxide layer at a temperature of 600°C or greater in the presence of oxygen.

20. Method of coating a surface of a microelectromechanical system (MEMS) with a metal silicate layer, the method comprising the steps of:providing a layer of silicon oxide, such as SiO2, on the surface by depositing the silicon oxide on the surface by atomic layer deposition, or by annealing a silicon-based surface in oxygen; and a) depositing a metal oxide layer on the silicon oxide layer by atomic layer deposition and annealing at a temperature of 600°C or greater; orb) depositing a metal layer on the silicon oxide layer by atomic layer deposition and annealing at a temperature of 600°C or greater in the presence of oxygen.

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