Dicing configuration
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- KYOCERA TECH OY
- Filing Date
- 2026-01-28
- Publication Date
- 2026-08-06
Smart Images
Figure FI2026050036_06082026_PF_FP_ABST
Abstract
Description
[0001] DICING CONFIGURATION
[0002] TECHNICAL FIELD
[0003] The present disclosure generally relates to the field of semiconductors and semiconductor manufacturing. The disclosure relates particularly, though not exclusively, to dicing of semiconductor devices.
[0004] BACKGROUND
[0005] This section illustrates useful background information without admission of any technique described herein representative of the state of the art.
[0006] Semiconductors are typically manufactured on substrates, such as on silicon wafers. One substrate may comprise hundreds, thousands or even tens of thousands of semiconductor devices.
[0007] Typically, each semiconductor device must be separated from the substrate to individual chips or dies at the final stages of the backend manufacturing. If a semiconductor device is damaged and scrapped at said dicing stage for any reason, all the preceding process steps and possibly months’ worth of efforts in the manufacturing are in vain. Loss of yield in dicing may occur due to various reasons, such as due to cracking of the chip.
[0008] SUMMARY
[0009] The appended claims define the scope of protection. Any examples and technical descriptions of apparatuses, products and / or methods in the description and / or drawings not covered by the claims are presented not as embodiments of the invention but as background art or examples useful for understanding the invention.It is an object of certain embodiments of the present disclosure to provide a scheme to solve at least one of the problems related to the prior art, or at least to provide an alternative to existing technology. Accordingly, certain disclosed embodiments provide for an ingenious method solving at least one of the problems related to the prior art.
[0010] According to a first example aspect of the present disclosure there is provided a method, comprising the steps of:
[0011] - providing a substrate, wherein the substrate comprises a handle layer, a device layer, and an insulator layer in between the handle layer and the device layer, wherein the substrate comprises a device;
[0012] - etching a groove (a trench) into the substrate reaching the insulator layer; and - dicing the substrate into dies by using the groove to prevent cracking of the substrate.
[0013] In certain embodiments, the substrate comprises a handle layer, a device layer, and an insulator layer in between the handle layer and the device layer. In certain embodiments, the device is located in the device layer.
[0014] In certain embodiments, the substrate comprises dicing streets on the opposite side of the substrate than the grooves. As used herein, the dicing street refers to the narrow lines (narrow areas) on the substrate where the substrate is diced (cut, sawed) to separate individual dies. As used herein, the dicing streets mark the location of the dicing (e.g. for the dicing apparatus or a dicing process). A dicing line is a synonym for a dicing street and can be used interchangeably. In certain embodiments, the dicing streets are oriented in a different direction with from silicon crystal orientation of the handle layer.
[0015] In certain embodiments, the groove etched into the substrate reaches the insulator layer (the buried insulator layer, the buried oxide, BOX, layer). In certain embodiments, the groove reaches through all the layers on top of the insulator layer (all the way to the insulator layer). In certain embodiments, the groove reaches through all the layers on top of the insulator layer, such as the piezoelectric layer and the top electrode layer.
[0016] In certain embodiments, the method comprises etching a groove into the device layer. In certain embodiments, the method comprises etching a groove into the device layer reaching the insulator layer. In certain embodiments, the dicing street(s) is (are) provided on the handle layer side of the substrate.In certain embodiments, the method comprises etching a groove into the device layer reaching the insulator layer (wherein the groove reaches the insulator layer). In certain alternative embodiments, the method comprises etching a groove into the handle layer reaching the insulator layer.
[0017] In certain embodiments, the method comprises providing a substrate, wherein the substrate comprises a handle layer, a device layer, and an insulator layer in between the handle layer and the device layer, wherein the substrate comprises a device; wherein the method comprises the steps of, in this order:
[0018] - etching a groove into the substrate reaching the insulator layer; and
[0019] - dicing the substrate into dies by using the groove, to prevent cracking of the substrate.
[0020] In certain embodiments, the method comprises providing a substrate, wherein the substrate comprises a handle layer, a device layer, and an insulator layer in between the handle layer and the device layer, wherein the substrate comprises a device; wherein the method comprises the steps of, in this order:
[0021] - etching a groove into the device layer of the substrate reaching the insulator layer;
[0022] and
[0023] - dicing the substrate into dies by using the groove, on the opposite side as the groove, to prevent cracking of the substrate.
[0024] In certain embodiments, the method comprises etching the groove via dry etching. In certain embodiments, the method comprises etching the groove via dry etching, such as deep reactive ion etching, DRIE. In certain embodiments, the method comprises etching the groove via deep reactive ion etching, DRIE.
[0025] In certain embodiments, the groove has a rectangular cross-section (in side view). In certain embodiments, the groove has a U-shaped, or V-shaped cross-section (in side view).
[0026] In certain example embodiments, the groove has a width of 3-7 microns (pm). In certain example embodiments, the groove has a width of (approximately) 5 microns.
[0027] In certain embodiments, the groove is configured to expose the layer beneath the device layer. In certain embodiments, the groove is configured to expose the insulator layer beneath the device layer.
[0028] In certain embodiments, as used herein, “dicing” refers to a specific process step that uses a special processing equipment. In certain embodiments, dicing is performed with aprocessing equipment. In certain embodiments, dicing is performed with a dicing equipment (apparatus, device). In certain embodiments, the method comprises dicing via a dicing saw (an equipment having a saw meant to dice the substrates). In certain embodiments, the method comprises dicing via a diamond saw. In certain embodiments, the method comprises dicing via laser dicing. In certain embodiments, as used herein, dicing and etching are defined as different process steps.
[0029] In certain embodiments, the method comprises dicing the substrate into dies at the dicing street(s). In certain embodiments, the dicing street marks the location of the dicing. In certain embodiments, the corresponding groove and dicing street are located on the opposite sides of the substrate. In certain embodiments, the corresponding groove and dicing street are located on the opposite sides of the substrate atop (on top of) one another (in a matching vertical location with one another, but on opposite sides).
[0030] In certain embodiments, the method comprises dicing the substrate into dies on the opposite side as the groove to prevent cracking (of the substrate). In certain embodiments, the method comprises dicing the substrate into dies on the opposite side as the groove is etched to prevent cracking (of the substrate). In certain alternative embodiments, the method comprises dicing the substrate into dies on both sides of the substrate.
[0031] In certain embodiments, the method comprises dicing the substrate into dies via (using) stealth dicing. In this embodiment, the dicing street is a stealth dicing street (dicing line). In certain embodiments, the method comprises dicing the substrate via laser dicing.
[0032] In certain embodiments, the method comprises dicing the substrate into dies by using the groove and the dicing street on the opposite sides of the substrate to prevent cracking of the substrate. In certain embodiments, the method comprises dicing the substrate into dies by using the groove and the dicing street on the opposite sides of the substrate to prevent cracking of the die.
[0033] In certain embodiments, the die is fabricated on a substrate. In certain embodiments, the substrate is a wafer. In certain embodiments, the substrate is a silicon wafer. In certain embodiments, the substrate is a silicon-on-insulator, SOI, wafer. In certain embodiments, the substrate is a cavity silicon-on-insulator, CSOI, wafer. In certain embodiments, the substrate is a silicon-on-insulator, SOI, substrate, or a cavity silicon-on-insulator, CSOI, substrate In certain embodiments, the In certain embodiments, the die is fabricated on a 50 micron thickness substrate.In certain embodiments, the substrate comprises a handle layer, an insulator layer, and a device layer. In certain embodiments, the substrate comprises an insulator layer in between the handle layer and the device layer. In certain embodiments, the substrate comprises a handle layer, an insulator layer, a device layer, and a cavity. In certain embodiments, the substrate comprises an insulator layer and a cavity in between the handle layer and the device layer.
[0034] In certain embodiments, the handle layer comprises silicon. In certain embodiments, the device layer comprises silicon. In certain embodiments, the device layer comprises silicon, preferably doped silicon, such as ultra-heavily doped, UHD, silicon. In certain preferred embodiments, the silicon is of single-crystal silicon. In certain embodiments, more than 50% of the mass of the resonator comprise material portions of single-crystalline silicon.
[0035] In certain embodiments, the device layer has a different silicon crystal orientation compared to the handle layer. In certain embodiments, the device layer has a <100> crystal direction of silicon, or deviates at most 25 degrees from that direction. In certain embodiments, the device layer has a
[0100] crystal direction of silicon, or deviates at most 25 degrees from that direction. In certain embodiments, the device layer has a
[0110] crystal direction of silicon, or deviates at most 25 degrees from that direction. In certain embodiments, the device layer has a
[0111] crystal direction of silicon, or deviates at most 25 degrees from that direction. In certain embodiments, the handle layer has a silicon crystal orientation different from the device layer silicon crystal orientation. In certain embodiments, the handle layer has a <100> crystal direction of silicon, or deviates at most 25 degrees from that direction. In certain embodiments, the handle layer has a
[0100] crystal direction of silicon, or deviates at most 25 degrees from that direction. In certain embodiments, the handle layer has a
[0110] crystal direction of silicon, or deviates at most 25 degrees from that direction. In certain embodiments, the handle layer has a
[0111] crystal direction of silicon, or deviates at most 25 degrees from that direction.
[0036] In certain embodiments, the insulator layer comprises dielectric material. In certain embodiments, the insulator layer comprises (is of) silicon dioxide, SiC>2. In certain embodiments, the insulator layer is a buried oxide layer (BOX).
[0037] In certain embodiments, the device layer comprises a piezoelectric layer. In certain embodiments, the device layer comprises a piezoelectric layer on the silicon layer (silicon body) of the device layer. In certain embodiments, the piezoelectric layer (material) is of aluminum nitride, AIN.In certain embodiments, the device layer of the die comprises a material stack, the material stack comprising the silicon layer (the bottom electrode), the piezoelectric layer on top of the silicon layer, and a top electrode on top of the piezoelectric layer. In certain embodiments, the device layer of the die comprises a piezoelectric device.
[0038] In certain embodiments, the top electrode is implemented by a layer of metal. In certain embodiments, the top electrode comprises (is of) metal, preferably gold (Au). In certain embodiments, the top electrode is of gold, preferably doped gold. In certain embodiments, the top electrode is of gold alloy. In certain embodiments, the top electrode (layer) is implemented by a layer of doped silicon. In certain embodiments, the silicon layer is of single-crystal silicon. In certain embodiments, the top electrode (layer) is implemented by a layer of doped polysilicon.
[0039] In certain embodiments, the device layer of the die comprises a piezoelectric layer, wherein the top electrode is on the piezoelectric layer, and a bottom electrode on the opposite side of the piezoelectric layer than the top electrode. In certain embodiments, the bottom electrode comprises silicon, preferably doped silicon, such as ultra-heavily doped, UHD, silicon. In certain preferred embodiments, the silicon is of single-crystal silicon. In certain embodiments, the bottom electrode (layer) is implemented by an UHD silicon layer.
[0040] In certain embodiments, the doping level of the silicon is above 1019cm-3. In certain embodiments, the doping level of the silicon is above 102° cm-3. In certain embodiments, the doped silicon is of N-type or P-type doping.
[0041] In certain embodiments, the die comprises at least one device. In certain embodiments, the die comprises a plurality of devices (such as two devices).
[0042] In certain embodiments, the device is a resonator. In certain embodiments, the device is a microelectromechanical systems, MEMS, resonator. In certain embodiments, the device is (part of) a semiconductor device. In certain embodiments, the device is configured to operate in a megahertz frequency area. In certain embodiments, the device is configured to operate at 32 MHz frequency.
[0043] In certain embodiments, the device comprises at least one resonating element. In certain embodiments, the device comprises a plurality of resonating elements. In certain embodiments, the resonating element comprises a plurality of resonating beam elements. In certain embodiments, each beam element is a sub-element of the device.In certain embodiments, the resonating element comprises a plurality of beam elements having a length and a width. In certain embodiments, the plurality of beam elements are positioned adjacent to each other. In certain embodiments, adjacent beam elements are mechanically connected to each other by connection elements.
[0044] In certain embodiments, the device is a stacked beam resonator. In certain embodiments, the stacked beam resonator comprises a plurality of beam elements positioned side-by-side in a plane. In certain embodiments, the plurality of beam elements are positions adjacent to each other in a width direction thereof. In certain embodiments, the plurality of beam elements are positioned adjacent to each other in a width direction of the device. In certain embodiments, the beam elements are separated by trenches. In certain embodiments, the beam elements are connected to each other by connection elements.
[0045] In certain embodiments, the resonating element of the device comprises a plurality of beam elements, such as seven, nine, or eleven beam elements. In certain embodiments, said adjacent beam elements are mechanically connected to each other by connection elements. In certain embodiments, the beam elements of the device are arranged in a rectangular array configuration.
[0046] In certain embodiments, the resonating element is in a shape of a rectangle. In certain embodiments, the resonating element is in a shape of an elongated rectangle (beamshaped). In certain embodiments, the resonating element has an aspect ratio (ratio of length to width, when observed from above) different from 1.
[0047] In certain embodiments, the resonating element of the device has a length-to-width aspect ratio of less than 1. In certain embodiments, the device is attached (supported, anchored, suspended) to a support structure. In certain embodiments, the device is attached to a support structure from the outermost beam elements of the device. In certain embodiments, the device comprises at least one anchor configured to connect the device to, and suspend the device from surrounding layers. In certain embodiments the at least one anchor comprises portions of the piezoelectric layer, the top electrode and the bottom electrode. In certain embodiments, each beam element is in ashape of a (rectangular) beam. In certain embodiments, each beam element has an aspect ratio (ratio of length to width, when observed from above) different from 1. In certain embodiments, each beam element has a length-to-width aspect ratio of more than 1.In certain embodiments, the resonating beam element(s) are longitudinally aligned within 25 degrees of a <100> crystal direction of silicon (of the bottom electrode). Within at least some embodiments the resonating beam element(s) are longitudinally aligned with a <100> crystal direction of the silicon (of the bottom electrode) such that a longitudinal axis of each resonating beam is within 25 degrees of the <100> crystal direction of the silicon (of the bottom electrode). In certain embodiments, the resonating beam element(s) are longitudinally aligned within 25 degrees of a <100> crystal direction of silicon (of the bottom electrode). Within at least some embodiments the resonating beam element(s) are longitudinally aligned with a <100> crystal direction of the silicon (of the bottom electrode) such that a longitudinal axis of each resonating beam is within 25 degrees of the <100 crystal direction of the silicon (of the bottom electrode).
[0048] In certain embodiments, the resonating beam element(s) are longitudinally aligned within 45 degrees, or 50 degrees of a <100> crystal direction of silicon (of the bottom electrode). Within at least some embodiments the resonating beam element(s) are longitudinally aligned with a <100> crystal direction of the silicon (of the bottom electrode) such that a longitudinal axis of each resonating beam is within 45 degrees, or 50 degrees of the <100> crystal direction of the silicon (of the bottom electrode).
[0049] In certain embodiments, the resonating beam element(s) are longitudinally aligned within 25 degrees of a
[0100] crystal direction of silicon (of the bottom electrode). Within at least some embodiments the resonating beam element(s) are longitudinally aligned with a
[0100] crystal direction of the silicon (of the bottom electrode) such that a longitudinal axis of each resonating beam is within 25 degrees of the
[0100] crystal direction of the silicon (of the bottom electrode).
[0050] In certain embodiments, the resonating beam element(s) are longitudinally aligned within 25 degrees of a
[0110] crystal direction of silicon (of the bottom electrode). Within at least some embodiments the resonating beam element(s) are longitudinally aligned with a
[0110] crystal direction of the silicon (of the bottom electrode) such that a longitudinal axis of each resonating beam is within 25 degrees of the
[0110] crystal direction of the silicon (of the bottom electrode).
[0051] In certain embodiments, the resonating beam element(s) are longitudinally aligned within 25 degrees of a
[0111] crystal direction of silicon (of the bottom electrode). Within at least some embodiments the resonating beam element(s) are longitudinally aligned with a
[0111] crystal direction of the silicon (of the bottom electrode) such that a longitudinal axis of eachresonating beam is within 25 degrees of the
[0111] crystal direction of the silicon (of the bottom electrode).
[0052] In certain embodiments, the device is configured to resonate (operate, oscillate, vibrate) in an in-plane resonance mode. In certain embodiments, the device is configured to resonate in an in-plane length-extensional, LE, resonance mode. In certain embodiments, the length extensional resonance mode is configured to resonate parallel to the length direction of the device. In certain embodiments, the length extensional resonance mode is configured to resonate perpendicular to the width direction of the device.
[0053] In certain embodiments, the device is configured to resonate in a square-extensional, SE, resonance mode. In certain embodiments, the device is configured to resonate in a widthextensional, WE, resonance mode.
[0054] In certain embodiments, the device is configured to resonate in a collective resonance mode. In certain embodiments, each resonating element of the device is configured to resonate in the (same) collective resonance mode. In certain embodiments, the device is configured to resonate in a desired (main) resonance mode. In certain embodiments, each beam element of the resonator is configured to resonate in the (same) desired resonance mode.
[0055] According to a second example aspect of the present disclosure there is provided an apparatus, comprising a die having a groove surface and a dicing surface on the faces (sides, vertical sides, vertical faces) of the die. In certain embodiments, the groove is visible after dicing (and on the final product / die).
[0056] In certain embodiments, the groove is an etched groove. In certain embodiments, the groove surface is formed during etching of the groove. In certain embodiments, the groove is etched into the substrate (into the device layer) prior to dicing. In certain embodiments, the groove provides a smooth surface (due to the etching). In certain embodiments, the dicing surface is formed during dicing. In certain embodiments, the dicing surface is rough in comparison to the groove.
[0057] According to a third example aspect of the present disclosure there is provided an apparatus, comprising a die obtained according to the first aspect or any of its embodiments. In certain embodiments, the apparatus comprises at least one die of the first aspect or any of its embodiments. In certain embodiments, the apparatus comprises a plurality of dies of the first aspect or any of its embodiments (such as two dies, or three dies).In accordance with certain embodiments, embodiments of the second aspect are provided, the embodiments comprising subject matter of any single embodiment presented in connection with the first aspect, or the embodiments comprising subject matter of any of the embodiments presented in connection with the first aspect combined with subject matter presented in any other embodiment or embodiments.
[0058] Different non-binding example aspects and embodiments have been illustrated in the foregoing. The embodiments in the foregoing are used merely to explain selected aspects or steps that may be utilized in different implementations. Some embodiments may be presented only with reference to certain example aspects. It should be appreciated that corresponding embodiments may apply to other example aspects as well. In particular, the embodiments described in the context of the first aspect are applicable to each further aspect. Any appropriate combinations of the embodiments may be formed.
[0059] BRIEF DESCRIPTION OF THE FIGURES
[0060] Some example embodiments will be described with reference to the accompanying figures, in which:
[0061] Fig. 1a schematically shows a semiconductor substrate comprising dies according to an example embodiment;
[0062] Fig. 1b schematically shows four dies each comprising a device according to an example embodiment;
[0063] Fig. 1c schematically shows a die comprising groove according to an example embodiment;
[0064] Fig. 2a schematically shows a die and location of dicing according to an example embodiment;
[0065] Fig. 2b schematically shows a die and damages caused by the dicing process according to an example embodiment;
[0066] Fig. 3 schematically shows a die having a material stack according to an example embodiment; and
[0067] Fig. 4 schematically shows an example device according to an example embodiment.DETAILED DESCRIPTION
[0068] In the following description, like reference signs denote like elements or steps.
[0069] The axes x, y and z are denoted to each Figure to illustrate the direction of observing. The axes are interrelated, meaning that each of the notations x, y or z are to be understood as the same x, y or z direction in all the Figures.
[0070] Fig. 1a schematically shows a semiconductor substrate 10 comprising dies 100 according to an example embodiment. Fig. 1a provides a top view (bird view, up to down) of the substrate 10. As used herein, the term die means the part that is diced from a ready fabricated silicon wafer in the dicing operation. In dicing, the dies are separated from each other using a special equipment. As used herein, the term chip means a single package, i.e. one physical entity that comprises resonating structure(s). In the context of instant disclosure, the term die forms a synonym to the term chip. Another synonym to the terms chip and die is the term component.
[0071] In certain embodiments, the substrate 10 is a silicon wafer, such as a silicon-on-insulator, SOI, substrate, or a cavity silicon-on-insulator, CSOI, substrate. In certain embodiments, the substrate 10 is a thin substrate, such as a 50 micron thickness substrate.
[0072] In certain embodiments, the substrate 10 comprises a plurality of dies 100. In certain embodiments, the dies are separated from the substrate at the final stages of semiconductor manufacturing. In certain embodiments, dies are separated from the substrate (and from one another) via dicing. In certain embodiments, the dicing is performed via (predefined) dicing streets. The dicing streets are located in Fig. 1A at the same location as denoted by numeral 101, but on the opposite side of the substrate. In certain embodiments, the grooves and the dicing streets are at locations where the dies are separated from one another, such as is illustrated in Fig. 1A.
[0073] In certain embodiments, the substrate 10 comprises grooves 101 (not to be confused with dicing streets - the dicing streets are marked with numeral 220). As used herein, the term groove (or grooves) is used to refer to an etched groove (trench, trenches) on the substrate. In certain embodiments, the groove is an etched groove (trench). In certain embodiments, the groove is not limited to a particular shape. In certain embodiments, the groove is in a shape of a rectangle (when observing the cross-section), or a line (when observing fromabove). In certain embodiments, the groove has a II- or V-shaped cross-section (when observing from side).
[0074] In certain embodiments, the grooves 101 are etched on the substrate. In certain embodiments, the grooves 101 are etched on the substrate on the opposite side as the (predefined) dicing streets 220 are. Dicing streets 220 are shown in Fig. 1c.
[0075] In certain embodiments, the grooves 101 are made on the substrate via lithographic patterning followed by etching. After lithographic patterning, relevant layer(s) are removed in successive etching process steps. In certain embodiments, the width / size / diameter of the grooves 101 in a mask prior to etching controls the depth of the etching. In certain embodiments, the groove 101 is patterned via dry etching, such as deep reactive ion etching, DRIE, or via laser dicing.
[0076] Accordingly, herein is provided a method, comprising the steps of providing a substrate 10, wherein the substrate comprises a device 110, etching a groove 101 into the substrate 10; and dicing the substrate 10 into dies 100 by using the groove 101 to prevent cracking.
[0077] As used herein, the term cracking is used to refer to uncontrollable, undesired phenomenon of the substrate breaking (partially or completely). In certain embodiments, the instant method enables preventing cracking of the substrate 10 (die 100, device layer 203) upon dicing. In certain embodiments, the instant method enables preventing damaging the device 110 upon dicing.
[0078] Fig. 1b schematically shows four dies 100 each comprising a device 110 according to an example embodiment. Fig. 1b provides a top view of the four dies 100. The arrow from Fig.
[0079] 1a to Fig. 1b is used to demonstrate an example location of the particular die 100 in both Figures. In certain embodiments, the grooves 101 are configured to encircle a die (and to encircle a device).
[0080] In certain embodiments, each die 100 comprises at least one device 110. In certain embodiments, the device 110 is a microelectromechanical systems, MEMS, resonator. In certain embodiments, the device is configured to operate in a megahertz frequency area, such as at 32 MHz frequency.
[0081] Fig. 1c schematically shows a die 100 comprising groove 101 according to an example embodiment. Fig. 1c provides a cross-sectional view (side view, left to right or right to left)of the die 100. The arrow from Fig. 1b to Fig. 1c is used to demonstrate a location of the groove 101 in both Figures. In certain embodiments, the numeral 110 denotes the location of the device 110 in the cross-section of the die 100.
[0082] In certain embodiments, the substrate comprises a handle layer 201, a device layer 203, and an insulator layer 202 in between the handle layer 201 and the device layer 203, as shown in the example embodiment of Fig. 1c. In certain embodiments, the substrate comprises also a cavity (not shown) in between the handle layer 201 and the device layer 203.
[0083] In certain embodiments, the handle layer 201 comprises silicon. In certain embodiments, the device layer 203 comprises silicon, preferably doped silicon, such as ultra-heavily doped, UHD, silicon. In certain preferred embodiments, the silicon is of single-crystal silicon. In certain embodiments, the doping level of the silicon is above 1019cm-3, preferably above 102° cm-3. In certain embodiments, the insulator layer 202 comprises dielectric material, such as silicon dioxide, SiC>2. In certain embodiments, the insulator layer 202 is a buried oxide layer (BOX).
[0084] In certain embodiments, the groove 101 etched into the substrate reaches the insulator layer 202. In certain embodiments, the method comprises etching a groove 101 into the device layer 203 reaching the insulator layer 202, as shown in Fig. 1c. In certain embodiments, the groove 101 is configured to expose the layer beneath the device layer 203. In certain embodiments, the groove 101 is configured to expose the insulator layer 202 beneath the device layer 203.
[0085] In certain embodiments, the side of the device layer 203 is referred to as the top side of the die 100. In certain embodiments, the side of the handle layer 201 is denoted as the bottom side of the die 100. In certain embodiments, the groove 101 is etched on the top side of the die 100. In certain embodiments, the method comprises etching a groove 101 into the device layer 203 reaching the insulator layer 202. In this embodiment, the dicing street 220 is provided onto the handle layer 201.
[0086] As shown in Fig. 1c, in certain embodiments, the dicing streets 220 are on the opposite side of the substrate 10 as the grooves 101. As used herein, the dicing street(s) 220 refers to the narrow lines on the substrate where the substrate is diced to separate dies 100, suchthat the dicing streets 220 mark the location of the dicing. In certain embodiments, the dicing of the substrate into dies is performed at the dicing street(s) 220.
[0087] As shown in Fig. 1c, in certain embodiments, the corresponding groove 101 and dicing street 202 are located on the opposite sides of the substrate, in a matching vertical location with one another.
[0088] In certain alternative embodiments, the groove 101 is etched on the bottom side (handle layer 201) of the die 100 (not shown). In this alternative embodiment, the dicing street 220 is provided onto the device layer 203.
[0089] In certain embodiments, the groove 101 has a width W of 3-7 microns, such as a width W of approximately 5 microns. In certain embodiments, the groove 101 has a depth D of 10-30 microns, preferably a depth D of 10-20 microns, such as a depth D of approximately 15 microns.
[0090] Fig. 2a schematically shows a die and locations of dicing according to an example embodiment. In certain embodiments, the substrate is diced into dies 100 on the opposite side as the groove 101 to prevent cracking of the substrate. In certain embodiments, the dicing is performed on the handle layer 201 side, when the grooves 101 are etched into the device layer 203. Arrows 220 (location of the dicing streets) denote the location of where dicing is performed according to certain embodiments.
[0091] In certain embodiments, the dicing streets 220 located on the opposite side of the die 100 in comparison to the grooves 101. In the Fig. 2, the dicing streets are located at the arrows 220. In certain embodiments, the dicing streets are used to focus (direct) the dicing to a correct location.
[0092] In certain embodiments, the dicing is stealth dicing. In certain embodiments, the dicing is done via a laser beam (that are focused to the dicing streets 220). In accordance with certain embodiments, the depth of the stealth dicing depends on the parameters used (by way of example, how many passes of laser beam needed). In accordance with certain embodiments, the dicing laser exposed onto the (backside of) substrate generates a damage layer therein. In accordance with certain embodiments, the individual dies 100 are thereafter separated from one another via tape expansion (“tear” process). In certain embodiments, the damage (damage area, damage layer, damage propagation) is visible on the final die 100.The dicing process aims to dice the substrate into smaller units, and according to the present disclosure, to individual dies 100.
[0093] In certain embodiments, tape expansion is used to separate individual dies 100. In certain embodiments, the tape expansion comprises providing a temporary dicing tape, such as a PET film, onto the substrate prior the stealth dicing process. In certain embodiments, in stealth dicing, the laser is provided onto the substrate on the opposite side of the temporary tape. In certain embodiments, the individual dies 100 are separated from one another by stretching the tape. In certain embodiments, the substrate breaks into individual dies 100 in the area of the groove 101 and the dicing street area 220 having the damage layer. In other words, this means pulling the substrate having the tape in horizontal direction, thereby separating the diced individual dies 100. In certain embodiments, the individual dies 100 are configured to stay attached to the tape, even though they are now separated from one another. This is convenient for instance for shipping purposes.
[0094] In certain preferred embodiments, the substrate is a silicon wafer having a crystal orientation. Typically, silicon breaks cleanly (no cracking) if the crystal orientation of the silicon wafer is aligned with the desired dicing direction. However, if the crystal direction varies, is arbitrary or misaligned with the desired dicing direction, the silicon wafer typically cracks uncontrollably into several unwanted directions. In certain embodiments, the device layer has a different silicon crystal orientation compared to the handle layer. In certain embodiments, the cracking can be caused by layers of other materials, such as piezoelectric material layer, on top of the substrate.
[0095] In certain embodiments, the utilization of the etched groove 101 is configured to minimize cracking of the substrate regardless of the crystal orientation of the substrate. This is due to improved separation of dies 100 provided by the groove 101. Since the groove 101 is located on the opposite side as the dicing is performed, the dicing does not have to be performed all the way through (risking more cracking and / or damaging the semiconductor device 110). Once the dicing is close enough or reaches the grooves 101 at the location of the insulator layer 202, the substrate can be separated into individual dies 100 without cracks or unwanted damage to the device 110. Hence, the grooves 101 enable reducing or preventing the loss of dies, especially if the handle layer and the device layer are of different crystal orientation (the crystalline orientation varies therebetween) or there are additional material layers, such as piezoelectric layer, on top, in accordance with certain embodiments.Fig. 2b schematically shows a die and damages caused by the dicing process according to an example embodiment. In certain embodiments, the groove 101 is visible on the finished product (die 100). In certain embodiments, the groove 101 surface is shown as S101 in Fig.
[0096] 2b. In certain embodiments, the groove 101 is an etched groove, provided into the device layer 203 prior to dicing.
[0097] In certain embodiments, the dicing surface S220 is formed during dicing, in certain embodiments, the dicing surface S220 is formed during stealth dicing.
[0098] In certain embodiments, the groove surface S101 and the dicing surface S220 are distinguishable from one another. In certain embodiments, the dicing surface S22ois rough in comparison to the groove surface S101 ■ In certain embodiments, the groove 101 provides a smooth surface S101 due to the etching.
[0099] In certain embodiments, the groove surface Sno is located at the face of the die 100. In certain embodiments, the dicing surface S220 is located at the face of the die 100.
[0100] As used herein, the face of the die 100 is used to refer to the edge of the die 100 after dicing it into individual unit. By way of an example, in Fig. 2b, one face of the die 100 is located at the place marked for Sno and S220 in combination. In certain embodiments, the die 100 has a rectangular shape (area, when observed from above). In certain embodiments, the rectangular die 100 has four vertical faces. In certain embodiments, the faces of the die 100 run along the vertical direction (when observed from the side). In certain embodiments, the faces of the die 100 run along the z-direction (according to the axes used in the present disclosure). As used herein, the bottom surface of the die or the top surface of the die are not to be referred to as faces of the die.
[0101] In certain embodiments, the groove surface S101 and the dicing surface S220 are visible in all (vertical) faces of the die 100 (regardless of the shape of the die 100).
[0102] By detecting the groove surface S101 and dicing surface S220 on a die, one can easily determine, if the particular die has been manufactured using the method according to the first aspect of any of its embodiments.
[0103] Accordingly, herein is provided an apparatus, comprising a die 100 having a groove surface S101 and a dicing surface S22o on the faces of the die 100. Herein is further provided an apparatus, comprising a die 100 obtained according to the method of first aspect or any of its embodiments.Fig. 3 schematically shows a die 100 having a material stack according to an example embodiment. Fig. 3 schematically shows an example cross section (sectional view, side view) of a die 100 having the resonator 110.
[0104] In certain embodiments, the die 100 is fabricated on a substrate 350, such as a silicon-on-insulator (SOI) substrate (wafer) or a cavity silicon-on-insulator (CSOI) substrate. The reference numerals 301 and 302 denote bottom electrode and top electrode contacts for the device 110, respectively.
[0105] In certain embodiments, the device layer 203 comprises a piezoelectric layer L2. In certain embodiments, the device layer 203 comprises a piezoelectric layer L2 on the silicon layer (silicon body) L4 of the device layer. In certain embodiments, the piezoelectric layer (material) is of aluminum nitride, AIN.
[0106] In certain embodiments, the device layer 203 of the die 100 comprises a material stack, the material stack comprising at least the silicon layer L4, the piezoelectric layer L2 on top of the silicon layer, and a top electrode L1 on top of the piezoelectric layer.
[0107] In the example embodiment shown in Fig. 3, the top electrode is implemented in layer L1. In certain embodiments, the top electrode L1 is implemented by a layer of metal, preferably gold (Au). In this example embodiment, layer L2 is a piezoelectric layer for piezoelectric actuation of the device residing in the area of denoted by 110. An opening in L2 is denoted by 320. In this example embodiments, layer L3 denotes a layer for the bottom electrode. In this example embodiment, layer L4 is a silicon layer for the die.
[0108] In certain embodiments, the die 100 comprises an insulator layer 202, such as a buried oxide layer (SiO2) of the SOI wafer, in certain embodiments, the insulator layer 202 is beneath the device layer 203. In certain embodiments, the die 100 comprises a silicon handle layer 201. lin certain embodiments, the handle layer 201 is beneath the insulator layer 202. In certain embodiments, the handle layer 201 comprises a cavity C1. In certain embodiments, the insulator layer 202 follows the cavity C1 shape as shown in Fig. 3.
[0109] In certain embodiments, when a doped silicon layer is used as L4, it is possible to leave out the separate L3 bottom electrode. In such embodiments, the conductive doped silicon layer L4 acts as the bottom electrode for the device 110. In certain embodiments, the silicon layer L4 comprises degenerately doped silicon. In certain embodiments, more than 50 % of the silicon layer L4 mass consists of degenerately doped silicon. In certain embodiments, thesilicon layer L4 is doped to an average impurity concentration of at least 2*1019cm-3, such as at least 102° cm-3. In certain embodiments, the doped silicon is of N-type or P-type doping. In certain embodiments, the bottom electrode comprises ultra-heavily doped, UHD, silicon. In certain embodiments, the silicon layer L4 of the device layer 203 comprises single crystalline silicon. In certain embodiments, the silicon layer L4 consists essentially of single crystalline silicon. In certain embodiments, the silicon layer L4 comprises degenerately doped single crystalline silicon.
[0110] In certain preferred embodiments, the device layer 203 of the die 100 comprises a material stack, the material stack comprising the silicon layer L4, the piezoelectric layer L2 on top of the silicon layer L4, and a top electrode L1 on top of the piezoelectric layer L1. In certain embodiments, the die 100 comprises a piezoelectric resonator. In certain embodiments, the piezoelectric layer L2 comprises aluminum nitride.
[0111] In certain embodiments, the groove 101 continue (reach) through the top electrode layer L1 , the piezoelectric layer L2, the bottom electrode layer L3 and the silicon layer L4 of the device layer 203 to expose the insulator layer 202 beneath these layers.
[0112] Fig. 4 schematically shows a top view (from above, from up to down) of an example device 110 according to an example embodiment. In certain embodiments, the device 110 comprises at least one resonating element 400. In certain embodiments, the resonating element 400 comprises a plurality of resonating elements 401.
[0113] The resonating element 400 according to embodiment shown in Fig. 4 comprises a plurality of resonating beam elements 401 having a length L and a width W. In the embodiment shown in Fig. 4, the resonating element 400 comprises seven resonating beam elements 401 (the number of elements 401 may vary depending on the embodiment). In certain embodiments, the resonating beam elements 401 are longer L than they are wide W.
[0114] According to the example embodiment shown in Fig. 4, the plurality of resonating beam elements 401 are positioned adjacent to each other. In certain embodiments, the plurality of resonating beam elements 4101 form a ladder-like configuration (stacked beam resonator). In certain embodiments, the plurality of resonating beam elements 401 are positioned adjacent to each other in a width direction W thereof. The adjacent resonating beam elements 401 are mechanically connected to each other by connection elements 402. In certain embodiments, the resonating element 400 is formed of the plurality of resonatingbeam elements 401 and a plurality of connection elements 402. In certain embodiments, the adjacent resonating beam elements 401 are separated by trenches 404. In certain embodiments, the trenches 404 have a length TL (trench length). In certain embodiments, the length L of the beam element 401 comprises at least the length of the trench TL and the length of at least one connection element 402.
[0115] In certain preferred embodiments, the device 110 comprises a stacked beam resonator comprising a plurality of resonating beam elements 401 positioned side-by-side in a plane, separated by trenches 404 and connected by connection elements 402. In at least some stacked beam resonators, the resonating beam elements 401 are positioned in the same plane. In certain stacked beam resonators, no two resonating beam elements 401 are positioned atop each other.
[0116] In certain embodiments, the resonating beam elements 401 are arranged in a rectangular array configuration. In certain embodiments, resonating element 400 has a length L (which is equal to the length of the beam element 401). In certain embodiments, the resonating element 400 has a width RW (resonating element width).
[0117] In certain embodiments, the resonating element 400 is attached to a support structure (not shown). In certain embodiments, the resonating element 400 is attached to the support structure from the outermost resonating beam elements 401 by anchoring point(s) 403. In certain embodiments, the resonating element 400 comprises electrical terminal(s) at anchoring points 403.
[0118] In certain embodiments, the resonating element 400 is of an elongated shape (having the length L smaller than their width RW). In certain embodiments, the resonating element 400 is in the shape of a rectangle. In certain embodiments, the resonating element 400 has an aspect ratio (ratio of length L to width RW, when observed from above) of less than 1.
[0119] In certain embodiments, the resonating beam elements 401 are of an elongated shape (having their length L larger than their width W). In certain embodiments, each resonating beam element 401 is in the shape of a rectangular beam (beam-shaped). In certain embodiments, each resonating beam element 101 has a length-to-width, L-to-W, aspect ratio of more than 1. In certain example embodiments, each resonating beam element 401 has a length-to-width, L-to-W, aspect ratio of more than 2, such as 5, 8, or 10.In certain embodiments, the resonating beam element(s) 401 are longitudinally aligned within 25 degrees of a <100> crystal direction of silicon (of the bottom electrode). Within at least some embodiments the resonating beam element(s) 401 are longitudinally aligned with a <100> crystal direction of the silicon (of the bottom electrode) such that a longitudinal axis of each resonating beam 401 is within 25 degrees of the <100> crystal direction of the silicon (of the bottom electrode).
[0120] In certain embodiments, the resonating element 400 of the device 110 is configured to resonate (operate, oscillate, vibrate) in an in-plane length-extensional, LE, resonance mode. In certain embodiments, resonating element 400 the device 110 is configured to resonate in a collective resonance mode, wherein each resonating beam element 401 is configured to resonate in the (same) collective resonance mode.
[0121] Without limiting the scope and the interpretation of the patent claims, certain technical effects of one or more of the example embodiments disclosed herein are listed in the following. A technical effect is providing a dicing process with improved yield. A technical effect is avoiding yield loss, for instance due to dies or chips cracking due to dicing. A further technical effect according to certain embodiments is to increase the previously low yield of stealth dicing process to up to 100% yield. Hence, a technical effect is providing high-yield dicing due to reduced cracking for semiconductor substrates having varying / arbitrary crystal orientation, such as varying silicon crystal orientation. A further technical effect is providing high-yield dicing for substrates having additional material layers (in addition to substrate material) in the dicing areas, such as piezoelectric material layers. Additional material layers may also contribute to the cracking while dicing. A further technical effect is enabling high-yield dicing for any type of substrate material, and any material stack provided onto the substrate.
[0122] A further technical effect is minimizing particle generation during dicing process, due to reduction in cracking (cracking typically causes particle generation on the substrate).
[0123] A further technical effect is providing a simple and fast process for manufacturing the groove for dicing the substrate to a semiconductor die. It is possible to etch the groove simultaneously as the device release etching.
[0124] In conventional process flows, without the presence of the grooves, dicing should be performed on both sides of the substrate to enable sufficient separation of the dies.However, this is often not possible due to the high doping levels of the device layer. Hence, a further technical effect is enabling efficient and functional dicing by providing the grooves in situations where it has not been possible before. Also, a further technical effect is omitting the need to provide a dicing process, such as stealth dicing process, on both sides of the substrate.
[0125] A further technical effect is providing simultaneous stress relief for the semiconductor device as the groove is manufactured. Wafer level bonding in the wafer level packaging (WLP) process may induce stresses that change the resonator resonance frequency. The stress relief (i.e. an etched trench to the buried oxide) alleviates the stresses of the device layer by creating a discontinuity to the stress / strain field in the device layer. Therefore, the stress is only mediated via the bulk.
[0126] Various embodiments have been presented. It should be appreciated that in this document, words comprise, include, and contain are each used as open-ended expressions with no intended exclusivity.
[0127] The foregoing description has provided by way of non-limiting examples of particular implementations and embodiments a full and informative description of the best mode presently contemplated by the inventors for carrying out the invention. It is however clear to a person skilled in the art that the invention is not restricted to details of the embodiments presented in the foregoing, but that it can be implemented in other embodiments using equivalent means or in different combinations of embodiments without deviating from the characteristics of the invention.
[0128] Furthermore, some of the features of the afore-disclosed example embodiments may be used to advantage without the corresponding use of other features. As such, the foregoing description shall be considered as merely illustrative of the principles of the present invention, and not in limitation thereof. Hence, the scope of the invention is only restricted by the appended patent claims.
Claims
CLAIMS1. A method, comprising the steps of:providing a substrate (10), wherein the substrate (10) comprises a handle layer (201), a device layer (203), and an insulator layer (202) in between the handle layer (201) and the device layer (203), wherein the substrate (10) comprises a device (110); etching a groove (101) into the substrate (10) reaching the insulator layer (202); and dicing the substrate (10) into dies (100) by using the groove (101) to prevent cracking of the substrate (10).
2. The method of claim 1, comprising dicing the substrate (10) into dies (100) on the opposite side as the groove (101) to prevent cracking.
3. The method of claim 1 or 2, comprising etching a groove (101) into the device layer (203) reaching the insulator layer (202).
4. The method of any preceding claim, wherein the substrate (10) comprises dicing streets (220) on the opposite side of the substrate (10) than the grooves (101).
5. The method of claim 4, wherein the dicing streets (220) are provided on the handle layer (201) side of the substrate (10).
6. The method of any preceding claim, comprising dicing the substrate (10) into dies (100) via stealth dicing.
7. The method of any preceding claim, comprising etching the groove (101) via dry etching, such as deep reactive ion etching, DRIE.
8. The method of any preceding claim, wherein the substrate (10) is a silicon-on-insulator, SOI, substrate, or a cavity silicon-on-insulator, CSOI, substrate.
9. The method of any preceding claim, wherein the device (110) is a microelectromechanical systems, MEMS, resonator.
10. The method of any preceding claim, wherein the device layer (203) has a different silicon crystal orientation compared to the handle layer (201).
11. The method of claim 3, wherein the dicing streets (220) are oriented in a different direction with from silicon crystal orientation of the handle layer (201).
12. An apparatus, comprising a die (100) having a groove surface (S101) and a dicing surface (S220) on the faces of the die (100).
13. An apparatus, comprising a die (100) obtained according to the method of any one of claims 1-11.