Semiconductor device and methods of fabrication

Abstract

A semiconductor device and methods of fabrication of a semiconductor device. The semiconductor device comprises a memory cell and a logic gate. The memory cell comprises a floating gate and a readout channel. The logic gate comprises a first channel, a second channel, and a logic charge reservoir disposed between the first channel and the second channel and arranged to provide charge carriers to the first channel or the second channel dependent on an input voltage applied to the logic gate. The readout channel of the memory cell and the first channel of the logic gate are formed from a common layer of semiconductor material.

Description

SEMICONDUCTOR DEVICE AND METHODS OF FABRICATIONTECHNICAL FIELD

[0001] The present disclosure relates to semiconductor devices and methods of fabrication of semiconductor devices. In particular, the present disclosure relates to semiconductor devices and methods of fabrication of semiconductor devices which include at least one memory cell and at least one logic gate.BACKGROUND

[0002] Semiconductor devices are integral to modern electronics, forming the backbone of numerous technologies that power everyday life. They are used in everything from smartphones and computers to medical equipment and automotive systems, highlighting their vast applicability. These devices function as essential building blocks that manage and process information, making them crucial for the development and operation of advanced electronic systems. Developments in semiconductors continue to drive the miniaturization and efficiency of electronic components, enabling the proliferation of more compact and powerful digital devices.

[0003] Digital electronics, which is the core building block of modern computing, is primarily realised through a combination of digital logic, such as a central processing unit (CPU) and memory for storing digital information. Both digital logic and memory are typically realised using semiconductor devices. Digital logic and memory and often considered to be separate aspects. For example, the von Neumann architecture includes a separate processing unit and memory unit.

[0004] Electronic memory devices, serve the critical function of data storage across a myriad of applications. A memory device may comprise a plurality of memory cells, where each memory cell is operable to store one or more bits of information. Memory cells are typically arranged in an array and connected to word and bit lines which form rows and columns of the array. Program and erase operations are used to modify the information stored by the memory cells. Read operations are used to read the information stored in the memory cells.

[0005] Memory devices may be implemented in many different ways such as random-access memory (RAM), read only memory (ROM), non-volatile memory and dynamic randomaccess memory (DRAM). At least some memory devices include memory cells in which information is stored in a floating gate. For example, flash memory (NOR flash and NAND flash) typically includes a plurality of memory cells each including a floating gate.

[0006] Charge carriers may be moved into or out of a floating gate during program and erase operations so as to selectively set an occupancy state of the floating gate, the occupancy state corresponding to the information which is stored in the floating gate. Other than when executing program and erase operations, the floating gate is electrically isolated so as to retain storage of information even in the absence of power (non-volatile memory). The occupancy state of a floating gate is typically read during a read operation by applying a voltage to a control gate located in proximity to the floating gate. A read voltage applied to the control gate generates an electric field which alters the conductivity of a semiconductor readout channel. The floating gate is typically positioned between the control gate and the readout channel such that changes in conductivity of the readout channel depend on the occupancy state of the floating gate as well as the voltage applied to the control gate. A current flowing through the readout channel during a read operation (when a voltage is applied to the control gate) may be measured in order to determine the occupancy state of the floating gate and thus the information stored in the memory cell.

[0007] Recently a new form of memory cell has been proposed which, like flash memory, utilises a floating gate to store information but, instead of a single barrier layer, utilises a plurality of layers arranged to provide a resonant tunneling barrier to selectively isolate the floating gate. The resonant tunneling barrier can be switched between insulating and conductive states with application of a low voltage, relative to some other floating gate devices with a single barrier layer (e.g., known flash memory devices), in order to move charge carriers into and out of the floating gate. In particular, the resonant tunneling barrier may include one or more quantum wells and can be switched to a conductive state by aligning resonantly to energies of the one or more quantum wells to enable resonant tunneling of charge carriers through the resonant tunneling barrier. Such a memory device may provide improved speed, reliability and efficiency when compared to traditional flash memory.

[0008] Digital logic is typically realised using semiconductor devices which incorporate logic gates. Logic gates are devices that act as building blocks for digital circuits, and perform basic logical functions that are fundamental to those digital circuits. Digital computing is largely based on CMOS (complementary metal oxide semiconductor) logic gates, which are made up of pairs of devices (transistors, or switches) that show complementary behaviour in use. That is, in use, when one of the pair is on, the other of the pair is off, and vice versa. In CMOS logic gates, this is achieved by one of the pair being an n-type semiconductor (nMOS), and the other of the pair being a p-type semiconductor (pMOS).

[0009] Recently a new form of logic gate has been proposed which utilises two semiconductor channels situated either side of a charge reservoir. The location of mobilecharge carriers in the logic gate can be controlled by applying an input voltage to the logic gate. A first input voltage may serve to cause charge carriers to move from the charge reservoir into a first of the semiconductor channels such that the first channel is conductive. A second input voltage may serve to cause charge carriers to move from the charge reservoir into a second of the semiconductor channels such that the second channel is conductive. By applying a drive voltage to one end of one or both of the channels, an output voltage can be obtained at the other end of the channels which is dependent on the input voltage (and the channel which is conductive).

[0010] It is in this context the present disclosure has been devised.SUMMARY

[0011] As was explained above, the function of digital logic and memory devices are often considered as separate and are often realised using separate devices. While digital logic and memory devices are typically viewed as distinct entities, it is often desirable to integrate both memory and digital logic. For instance, CPUs often incorporate memory elements, such as registers and cache, while memory chips include logic for addressing memory sectors during programming, erasing, or reading, often overseen by an on-chip memory controller. This integration is a core feature, making embedded memory a vital class of memory used from small components to larger systems like graphics processing units (GPUs) in artificial intelligence, which possess substantial integrated memory.

[0012] It has been realised that memory cells and logic gates can be formed from layers of semiconductor material having similar material properties and structural characteristics. It has further been realised that at least one logic gate and at least one memory cell may be formed in such a way that they can be combined in a single semiconductor device (e.g., on the same substrate and / or forming part of a common integrated circuit). Semiconductor devices and methods of fabrication of semiconductor devices are disclosed herein in which at least one memory cell and at least one logic gate form part of the same semiconductor device and share part of at least one common layer of semiconductor material. That is, part of the at least one common layer of semiconductor material may form a component part of at least one logic gate and another part of the at least one common layer of semiconductor material may form a component part of at least one memory cell.

[0013] According to a first aspect of the present disclosure there is provided a semiconductor device comprising a plurality of layers of materials. The semiconductor device comprises a memory cell and a logic gate. The memory cell comprises: a floating gate for storing charge carriers so as to provide a plurality of occupancy states of the floating gate; a readout channelarranged such that when a read voltage is applied to the memory cell, the electrical resistance of the readout channel depends on the occupancy state of the floating gate. The logic gate comprises a first channel comprising a first current flow path; a second channel comprising a second current flow path; and a logic charge reservoir disposed between the first channel and the second channel and arranged to provide charge carriers to the first channel or the second channel dependent on an input voltage applied to the logic gate. The readout channel of the memory cell and the first channel of the logic gate are formed from a common layer of semiconductor material.

[0014] The semiconductor device may comprise a plurality of memory cells as described herein. For example, the semiconductor device may comprise a plurality of memory cells, wherein each memory cell comprises a floating gate for storing charge carriers so as to provide a plurality of occupancy states of the floating gate; a readout channel arranged such that when a read voltage is applied to the memory cell, the electrical resistance of the readout channel depends on the occupancy state of the floating gate. The semiconductor device may comprise a plurality of logic gates as described herein. For example, the semiconductor device may comprise a plurality of logic gates, each comprising a first channel comprising a first current flow path; a second channel comprising a second current flow path; and a logic charge reservoir disposed between the first channel and the second channel and arranged to provide charge carriers to the first channel or the second channel dependent on an input voltage applied to the logic gate. A plurality of memory cells and / or a plurality of logic cells may share at least one material layer with at least one other memory cell and / or logic gate.

[0015] The use of one or more common material layers in the memory cell and the logic gate may allow for flexibility as to the arrangement of one or more memory cells and one or more logic gates in the same semiconductor device (e.g., on the same substrate and / or chip). For example, the plurality of layers of material may be formed across the semiconductor device to form a single material layer structure. The same material layer structure may then be modified (e.g., material layers selectively removed) at selected locations in order to form one or more memory cells and / or logic gates at desired locations in the same semiconductor device.

[0016] The semiconductor device may be formed by forming the plurality of layers of material on a common substrate. For example, the plurality of layers of material may be deposited and / or grown on a substrate. Portions of one or more of the layers of material may be removed to isolate parts of the memory cell and the logic gate from each other to allow for independent operation of the logic gate and the memory cell. For example, one or more ofthe plurality of layers of material may be selectively etched so as to form the memory cell and the logic gate.

[0017] One or more semiconductor materials described herein may be doped.

[0018] The readout channel of the memory cell and the first channel of the logic gate may be electrically isolated from each other. For example, whilst the readout channel of the memory cell and the first channel of the logic gate may be formed from a common layer of semiconductor material, a portion of the common layer of semiconductor material between the readout channel and the first channel of the logic gate may be removed (e.g., through etching) such that the layer of semiconductor material does not continuously extend between the readout channel of the memory cell and the first channel of the logic gate.

[0019] The readout channel of the memory cell and the first channel of the logic gate may comprise the same semiconductor. The readout channel of the memory cell and the first channel of the logic gate may comprise the same base semiconductor. The readout channel of the memory cell and the first channel of the logic gate may comprise the same semiconductor compound. The readout channel of the memory cell and the first channel of the logic gate may comprise the same semiconductor material. The readout channel of the memory cell and the first channel of the logic gate may comprise substantially the same thickness of the semiconductor material. The readout channel of the memory cell and the first channel of the logic gate may be arranged at substantially the same position within the layers of material forming the semiconductor device. For example, the readout channel and the first channel may be arranged at substantially the same vertical position with respect to a common substrate on which both the memory cell and the logic gate are formed.

[0020] Using a common layer of semiconductor material for both the first channel of the logic gate and the readout channel of the memory cell allows a single layer of semiconductor material to be deposited or grown in the device and used to form both the logic gate and readout channel. This allows for integration of both the logic gate and the memory cell on the same substrate. This may further allow for the integration of a plurality of logic gates and memory cells on the same substrate and forming an integrated circuit.

[0021] One or more additional components of the logic gate and memory cell may be formed of one or more common layers of material.

[0022] The readout channel of the memory cell and the first channel of the logic gate may comprise a semiconductor compound such as a III-V semiconductor compound. The readout channel of the memory cell and the first channel of the logic gate may comprise indium arsenide (InAs), indium gallium arsenide (InGaAs) or any other semiconducting material(including semiconductor compounds) such as van der Waals materials. The readout channel of the memory cell and the first channel of the logic gate may comprise a quantum well. The readout channel of the memory cell and the first channel of the logic gate may have discrete energy levels corresponding to confined internal states in which mobile charge carriers can pass.

[0023] The logic charge reservoir may comprise a semiconductor compound such as a III-V semiconductor compound. The logic charge reservoir may comprise gallium antimonide (GaSb), indium gallium antimonide (InGaSb) or any other semiconductor material (including semiconductor compounds) such as van der Waals materials. The logic charge reservoir may comprise a quantum well. The logic charge reservoir may have discrete energy levels corresponding to confined internal states in which mobile charge carriers can pass.

[0024] The second channel may comprise the same material as the first channel or may comprise a different material. The second channel may have a similar layer thickness as the first channel. In at least some examples, the layer thickness of the second channel may be different to the layer thickness of the first channel. The second channel may comprise a semiconductor compound such as a III-V semiconductor compound. The second channel may comprise indium arsenide (InAs), indium gallium arsenide (InGaAs) or any other semiconducting material (including semiconductor compounds) such as van der Waals materials. The second channel may comprise a quantum well. The second channel may have discrete energy levels corresponding to confined internal states in which mobile charge carriers can pass.

[0025] The floating gate may be suitable for storing charge carriers so as to provide a plurality of discrete occupancy states. Alternatively, the floating gate may be suitable for storing charge carriers so as to provide a continuum of occupancy states. A plurality of occupancy states may, for example, allow analogue information to be stored by the memory cell. A plurality of occupancy states may allow multiple binary bits to be stored by the memory cell, for example, two bits, three bits, four bits or a larger number of bits. Both a continuum of occupancy states and a plurality of discrete occupancy states are examples of a plurality of occupancy states.

[0026] The floating gate may comprise a semiconductor compound such as a III-V semiconductor compound. The floating gate may comprise indium arsenide (InAs), indium gallium arsenide (InGaAs), or any other semiconductor material (including semiconductor compounds) such as van der Waals materials.

[0027] The memory cell and the logic gate may further comprise electrical contacts formed with one or more of the layers of material in the semiconductor device. The electrical contacts may be arranged for allowing application of voltages across and / or to the memory cell and logic gate and for making measurement of electrical current flowing through sections of the memory cell and / or logic gate and / or a voltage at sections of the memory cell and / or logic gate. Electrical contacts may comprise an electrically conductive material (e.g., a conductive metal) disposed on sections of the memory cell and / or logic gate.

[0028] The memory cell may comprise electrical contacts in the form of a memory control gate and a memory back gate contact for applying a voltage across the memory cell. For example, a memory control gate and a memory back gate contact may be arranged for applying a read voltage across the memory cell or applying any other form of voltage for the purposes of programming the memory cell, erasing or reading the memory cell or for any other purpose for operation of the memory cell. The memory cell may comprise a first electric contact and a second electric contact (e.g., source and drain contacts) contacting the readout channel and between which the readout channel extends. The first electric contact and the second electric contact may allow for measurement of a current flowing through the readout channel when a read voltage is applied across the memory cell. The current flowing through the readout channel when a read voltage is applied across the memory cell is indicative of the occupancy state of the floating gate and therefore of the information stored in the memory cell. The first electric contact and the second electric contact may also allow for programming the memory cell, erasing the memory cell or for any other purpose for operation of the memory cell.

[0029] The logic gate may comprise electrical contacts in the form of a logic control gate and a logic back gate contact for applying an input voltage to the logic gate. Alternatively, only a logic control gate may be included and used to apply voltages with respect to ground. Different input voltages applied to the logic gate may result in different configurations of charge carriers in the logic gate. For example, in the absence of an applied voltage to the logic gate (between the logic back gate contact and the logic control gate), charge carriers may reside in the logic charge reservoir and both the first channel and the second channel may have relatively high resistances. When a first input voltage is applied to the logic gate (between the logic back gate contact and the logic control gate) charge carriers may move from the logic charge reservoir into one of the first channel or the second channel. One of the first channel or the second channel may therefore have a relatively high resistance and the other of the first channel or the second channel may be conductive. When a second input voltage (which may be of opposite polarity to the first input voltage) is applied to the logicgate (between the logic back gate contact and the logic control gate) charge carriers may move from the logic charge reservoir into the other of the first channel or the second channel. The channel of the first channel or the second channel having a relatively high resistance and the channel of the first channel or the second channel being conductive may therefore be reversed when compared to the application of the first input voltage.

[0030] The logic gate may comprise a first drive contact and a first output contact both in contact with the first channel and between which the first channel extends. The logic gate may comprise a second drive contact and a second output contact in contact with the second channel and between which the second channel extends. The first drive contact and the second drive contact may be used to apply different voltages to the first channel and the second channel. For example, a first drive voltage may be applied to the first drive contact and a second drive voltage may be applied to the second drive contact. In some examples, one of the first drive voltage or second drive voltage may be a ground voltage. For example, one of the first drive contact and the second drive contact may be connected to ground. In other examples, the first drive voltage and the second drive voltage may be non-zero (not grounded). The first drive voltage or the second drive voltage may be of a positive polarity with respect to ground or the first drive voltage or the second drive voltage may be of a negative polarity with respect to ground. The first drive voltage and the second drive voltage may have opposite polarities. The first drive voltage or the second drive voltage may be substantially the same as the first or second input voltages. For example, the first drive voltage may be substantially the same as the second input voltage and the second drive voltage may be substantially the same as first input voltage. The first output contact and the second output contact may be used to measure a voltage at the first output contact and second output contact. In some examples, the first output contact and the second output contact may be electrically connected to each other. A voltage at the common connection of the first output contact and second output contact (e.g., a potential difference with respect to ground) depends on which of the first channel and the second channel are conductive, which is dependent on the input voltage applied to the logic gate. For example, if the first channel is conductive and the second channel has a relatively high electrical resistance then the voltage at the common connection of the first output contact and second output contact may be substantially the voltage at the first drive contact. If the second channel is conductive and the first channel has a relatively high electrical resistance then the voltage at the common connection of the first output contact and the second output contact may be substantially the voltage at the second drive contact.

[0031] One or more of the plurality of layers of material forming the semiconductor device may be formed through epitaxy (epitaxial growth) such as molecular beam epitaxy, liquid phase epitaxy, metal-organic chemical vapor deposition or metal-organic vapor phase epitaxy.

[0032] The memory cell may further comprise a memory charge reservoir arranged to provide charge carriers to the readout channel, dependent on the occupancy state of the floating gate and a read voltage applied to the memory cell. The memory charge reservoir of the memory cell and the logic charge reservoir of the logic gate may be formed from a common layer of semiconductor material.

[0033] The memory charge reservoir and the logic charge reservoir may be electrically isolated from each other. For example, whilst the memory charge reservoir and the logic charge reservoir may be formed from a common layer of semiconductor material, a portion of the common layer of semiconductor material between the memory charge reservoir and the logic charge reservoir may be removed (e.g., through etching) such that the layer of semiconductor material does not continuously extend between the memory charge reservoir and the logic charge reservoir.

[0034] The memory charge reservoir and the logic charge reservoir may comprise the same semiconductor material. The memory charge reservoir and the logic charge reservoir may comprise substantially the same thickness of the semiconductor material. The memory charge reservoir and the logic charge reservoir may be arranged at substantially the same position within the layers of material forming the semiconductor device. For example, the memory charge reservoir and the logic charge reservoir may be arranged at substantially the same vertical position with respect to a common substrate on which both the memory cell and the logic gate are formed.

[0035] Using a common layer of semiconductor material for both the memory charge reservoir and the logic charge reservoir allows a single layer of semiconductor material to be deposited or grown in the device and used to form both the memory charge reservoir and the logic charge reservoir. This may be advantageous for integration of both the logic gate and the memory cell on the same substrate.

[0036] The memory charge reservoir may comprise a semiconductor compound such as a III-V semiconductor compound. The memory charge reservoir may comprise gallium antimonide (GaSb), indium gallium antimonide (InGaSb) or any other semiconductor material (including semiconductor compounds) such as van der Waals materials. In some examples, the memory charge reservoir may comprise a quantum well. The memory charge reservoirmay have discrete energy levels corresponding to confined internal states in which mobile charge carriers can pass.

[0037] The memory cell may comprise a memory back gate for applying a voltage across the memory cell. The logic gate may comprise a logic back gate for applying an input voltage to the logic gate. The memory back gate of the memory cell and the logic back gate of the logic gate may be formed from a common layer of semiconductor material.

[0038] The memory back gate and / or the logic back gate may be disposed between the memory cell and the logic gate and a substrate on which the memory cell and the logic gate are disposed. The memory back gate may be disposed between the substrate and the readout channel (one or more additional layers, such as a memory charge barrier and memory charge reservoir, may be arranged between the memory back gate and the readout channel). The logic back gate may be disposed between the substrate and the second channel (one or more additional layers, such as a logic charge barrier may be arranged between the logic back gate and the second channel).

[0039] The memory back gate and the logic back gate may be formed of different parts of a continuous layer of semiconductor material. For example, the memory back gate and the logic back gate may not be electrically isolated from each other.

[0040] A portion of layers disposed on (above) the memory back gate and the logic back gate may be removed (e.g., etched) to expose a portion of the layer of semiconductor material forming the memory back gate and the logic back gate on which a back gate contact is formed. The back gate contact may allow for application of a voltage across the memory cell and / or to the logic gate.

[0041] The memory back gate and the logic back gate may comprise the same semiconductor material. The memory back gate and the logic back gate may comprise substantially the same thickness of the semiconductor material. The memory back gate and the logic back gate may be arranged at substantially the same position within the layers of material forming the semiconductor device. For example, the memory back gate and the logic back gate may be arranged at substantially the same vertical position with respect to a common substrate on which both the memory cell and the logic gate are formed.

[0042] The memory back gate and the logic back gate may comprise a semiconductor compound such as a III-V semiconductor compound. The memory back gate and the logic back gate may comprise indium arsenide (InAs), indium gallium arsenide (InGaAs) or any other semiconductor material (including semiconductor compounds) such as van der Waals materials.

[0043] The semiconductor layer forming the memory back gate in one or more memory cells and the logic back gate in one or more logic cells may be continuous in order to form a common back gate for at least one memory cell and at least one logic gate. The semiconductor layer forming the common back gate may only be continuous for a subset of memory cells and / or logic gates in the semiconductor device such that a subset of memory cells and / or logic gates share a common back gate. The back gate may thereby form a common ground for a plurality of memory cells and / or logic gates in the semiconductor device. Different subsets of memory cells and / or logic gates in the semiconductor device may share substantially the same ground potential, for example by means of an alternative conductive connection, or they may be at a different ground potential.

[0044] The memory cell may comprise a memory charge barrier arranged to provide a charge barrier between the memory back gate and the readout channel. The logic gate may comprise a logic charge barrier arranged to provide a charge barrier between the logic back gate and the second channel of the logic gate. The memory charge barrier and the logic charge barrier may be formed of a common layer of material.

[0045] The memory charge barrier may provide a charge barrier between the memory back gate and the readout channel. The logic charge barrier may provide a charge barrier between the logic back gate and the second channel.

[0046] The common layer of material forming the memory charge barrier and the logic charge barrier may comprise a layer of material configured to substantially prevent transfer of charge carriers across the logic charge barrier and the memory charge barrier under normal operating conditions of the semiconductor device. The common layer of material may comprise a layer of semiconductor material. For example, the layer of semiconductor material may comprise a semiconductor material providing a potential barrier sufficient to substantially prevent transfer of charge carriers across the charge barrier under normal operating conditions of the semiconductor device. The common layer of material forming the memory charge barrier and the logic charge barrier may comprise a semiconductor compound such as a III-V semiconductor compound. The common layer of material forming the memory charge barrier and the logic charge barrier may comprise aluminium antimonide (AlSb). The common layer of material forming the memory charge barrier and the logic charge barrier may comprise any suitable semiconductor material (including semiconductor compounds) such as a van der Waals material.

[0047] Alternatively, the common layer of material may comprise an electrical insulator and / or a dielectric material. The common layer of material (e.g., insulator or dielectric)forming the memory charge barrier and the logic charge barrier may comprise an oxide of a metal, such as aluminium (Al) or hafnium (Hf). The common layer may comprise an oxide of a semiconductor material, such as an oxide of silicon (Si) or the oxide of a III-V semiconductor compound. For example, the common layer of material forming the memory charge barrier and the logic charge barrier may comprise an oxide of indium arsenide (InAs), aluminium indium arsenide (AllnSb), gallium antimonide (GaSb), or aluminium gallium antimonide (AlGaSb).

[0048] The memory charge barrier and the logic charge barrier may comprise the same material. The memory charge barrier and the logic charge barrier may comprise substantially the same thickness of the material. The memory charge barrier and the logic charge barrier may be arranged at substantially the same position within the layers of material forming the semiconductor device. For example, the memory charge barrier and the logic charge barrier may be arranged at substantially the same vertical position with respect to a common substrate on which both the memory cell and the logic gate are formed.

[0049] The memory charge barrier and the logic charge barrier may be isolated from each other. For example, whilst the memory charge barrier and the logic charge barrier may be formed from a common layer of material, a portion of the common layer of material between the memory charge barrier and the logic charge barrier may be removed (e.g., through etching) such that the layer of material does not continuously extend between the memory charge barrier and the logic charge barrier. In other examples, the memory charge barrier and the logic charge barrier may be formed of a continuous layer of common material and may not be isolated from each other.

[0050] The memory cell may further comprise a layer formed of a common layer of semiconductor material with the second channel of the logic gate.

[0051] The layer formed of a common layer of semiconductor material with the second channel of the logic gate may form a second memory channel (where the readout channel is a first memory channel). The second memory channel may have little or no functional role in the operation of the memory cell. For example, the memory cell may be configured such that when a read voltage is applied across the memory cell, charge carriers move into the readout channel (dependent on the occupancy state of the floating gate) and the resistance of the second memory channel remains relatively high. Normal operation of the memory cell may only include application of a voltage across the memory cell which would result in the second memory channel becoming conductive during an erase operation of the memory cell.During such an erase operation, the presence of charge carriers in the second memory channel may have little or no impact on the erase operation.

[0052] The second memory channel may be included in the memory cell in order to allow the memory cell and the logic gate to be formed of a plurality of common layers of material. For example, the semiconductor material forming the second channel of the logic gate and the second memory channel may be formed as one of a plurality of materials on the same substrate. The inclusion of the second memory channel in the memory cell allows for common layers of material formed above the second memory channel to form functional layers of the memory cell and the logic gate without requiring modification of the material layer structure of the semiconductor device.

[0053] The second channel of the logic gate and the second memory channel may be electrically isolated from each other. For example, whilst the second channel of the logic gate and the second memory channel may be formed from a common layer of semiconductor material, a portion of the common layer of second channel of the logic gate and the second memory channel may be removed (e.g., through etching) such that the layer of semiconductor material does not continuously extend between the second channel of the logic gate and the second memory channel.

[0054] The second channel of the logic gate and the second memory channel may comprise the same semiconductor material. The second channel of the logic gate and the second memory channel may comprise substantially the same thickness of the semiconductor material. The second channel of the logic gate and the second memory channel may be arranged at substantially the same position within the layers of material forming the semiconductor device. For example, the second channel of the logic gate and the second memory channel may be arranged at substantially the same vertical position with respect to a common substrate on which both the memory cell and the logic gate are formed.

[0055] The second channel of the logic gate and the second memory channel may comprise a semiconductor compound such as a III-V semiconductor compound. The second channel of the logic gate and the second memory channel may comprise indium arsenide (InAs), indium gallium arsenide (InGaAs) or any other semiconductor material (including semiconductor compounds) such as van der Waals materials. The second channel of the logic gate and / or the second memory channel may comprise a quantum well. The second channel of the logic gate and / or the second memory channel may have discrete energy levels corresponding to confined internal states in which mobile charge carriers can pass.

[0056] The memory cell may further comprise a selective conduction barrier arranged between the floating gate and the readout channel and to allow for selective conduction of charge carriers into and out of the floating gate so as to change the occupancy state of the floating gate.

[0057] The selective conduction barrier may comprise one or more layers of semiconductor materials (e.g., semiconductor compounds such as III-V semiconductor compounds or van der Waals materials). In the absence of an applied electric field (e.g., a voltage applied across the memory cell) the selective conduction barrier may be configured to provide an insulating layer between the floating gate and the readout channel so as to electrically isolate the floating gate from the readout channel. The selective conduction barrier may be operable to allow for selective conduction of charge carriers into and out of the floating gate to change the occupancy state of the floating gate during program and erase operations. That is, the selective conduction barrier may be configured such that its conductivity can be switched on and off by the application of a voltage (e.g., to a control gate).

[0058] In some examples, the selective conduction barrier may comprise a resonant tunneling barrier. The resonant tunneling barrier may comprise a plurality of layers of semiconductor materials (e.g., III-V semiconductor compounds) arranged to form one or more quantum wells. The one or more quantum wells may be configured such that in the absence of an applied electric field, the resonant tunneling barrier electrically isolates the floating gate from the readout channel. The resonant tunneling barrier may be configured such that when a suitable voltage is applied across the resonant tunneling barrier resonant tunneling of charge carriers through the resonant tunneling barrier may occur. This allows for the selective movement of charge carriers into and out of the floating gate in order to change the occupancy state of the floating gate during program and erase operations.

[0059] In at least some examples, the selective conduction barrier may comprise a triple resonant tunneling barrier. The triple resonant tunneling barrier may comprise three tunneling barriers with two quantum wells formed between the tunneling barriers. The tunneling barriers may be substantially similar to each other or may be different to each other. The tunneling barriers may comprise the same material or may comprise different materials. The three tunneling barriers may have substantially the same layer thickness or have different layer thicknesses. For example, in some implementations a first and third barrier of three tunneling barriers may be substantially the same but different from a middle barrier (disposed between the first and third barriers) of the three tunneling barriers. The quantum wells formed between the tunneling barriers may be substantially similar or may be different. The quantum wells formed between the tunnelling barriers may comprise the same material or maycomprise different material. The quantum wells formed between the tunneling barriers may have substantially the same layer thickness or may have different layer thicknesses. Different thicknesses of quantum wells formed between the tunneling barriers may have substantially different confined energy levels such that in the absence of any voltage applied across the resonant tunneling barrier the confined energy levels of the quantum wells formed between the tunneling barriers are not aligned and are substantially de-coupled, quantum-mechanically, from each other. The quantum wells formed between the tunneling barriers may comprise the same material or may comprise different materials. Quantum wells formed between tunneling barriers comprising different materials may have substantially different confined energy levels such that in the absence of any voltage applied across the resonant tunneling barrier, the confined energy levels of the quantum wells formed between the tunneling barriers are not aligned and are substantially de-coupled, quantum-mechanically, from each other.

[0060] The resonant tunneling barriers may comprise alternating layers of two or more semiconductor materials (e.g., semiconductor compounds such as III-V semiconductor compounds or van der Waals materials). In at least some examples, the resonant tunneling barriers may comprise alternating layers of aluminium antimonide (AlSb) and indium arsenide (InAs).

[0061] In other examples, other arrangements may be used in order to move charge carriers into and out of the floating gate, such as any arrangement used in known flash memory cells.

[0062] The memory cell may further comprise a memory control gate and a memory insulating barrier arranged between the floating gate and the memory control gate, wherein the memory control gate is arranged for applying a voltage across the memory cell.

[0063] The memory control gate may be arranged for applying one or more of a read voltage for performing a memory read operation, a program voltage for performing a memory program operation and / or an erase voltage for performing a memory erase operation across the memory cell.

[0064] The memory control gate may comprise an electrical contact in the form of an electrical conductor (such as a conductive metal). The memory insulating barrier is configured to provide an electrically insulating barrier between the memory control gate and the floating gate and thus substantially prevent movement of charge carriers between the control gate and the floating gate . The memory insulating barrier may comprise a dielectric such as aluminium oxide (AI2O3) or hafnium oxide (HfO2).

[0065] The logic gate may further comprise a logic control gate and a logic insulating barrier arranged between the first channel and the logic control gate, wherein the logic control gate is arranged for applying an input voltage to the logic gate.

[0066] The logic control gate may comprise an electrical contact in the form of an electrical conductor (such as a conductive metal). The logic insulating barrier is configured to provide an electrically insulating barrier between the logic control gate and the first channel and thus substantially prevent movement of charge carriers between the control gate and the first channel . The logic insulating barrier may comprise a dielectric such as aluminium oxide (AI2O3) or hafnium oxide (HfO2).

[0067] The memory insulating barrier and the logic insulating barrier may be formed of a common layer of material.

[0068] In some examples, the logic gate may further comprise material layers corresponding to a gate stack of the memory cell. For example, the logic gate may comprise a selective conduction barrier disposed on the first channel, and / or a floating gate disposed on the selective conduction barrier. The selective conduction barrier and floating gate layers may play no functional role in the logic gate but may be included in the logic gate in order to allow the memory cell and the logic gate to be formed of the same layers of material.

[0069] For example, a plurality of layers of material may be formed on a substrate to form a material layer structure from which both the memory cell and the logic gate may be formed. Portions of one or more material layers may be selectively removed (e.g., etched) in order to form the memory cell and the logic gate. The material layer structure may include layers which form, for example, the floating gate of the memory cell and a selective conduction barrier between the readout channel and the floating gate of the memory cell.

[0070] In some examples, layers which form the floating gate of the memory cell and a selective conduction barrier between the readout channel and the floating gate of the memory cell may be retained in the logic gate. A common insulating barrier may then be disposed on both the memory cell and the logic gate. The logic gate may be operated in such a manner that a selective conduction barrier included in a logic gate remains non-conductive. For example, the logic gate may be operated in such a manner that insufficient voltage is applied across it to allow resonant tunneling and the passage of charge carriers across the selective conduction barrier in the logic gate.

[0071] In other examples, at least some material layers used in the memory cell may be removed from portions of the material layer structure used to form the logic gate. For example, layers which form the floating gate of the memory cell and a selective conductionbarrier between the readout channel and the floating gate of the memory cell may be removed (e.g., etched) at a position at which the logic gate is formed. In such examples, the logic insulating barrier may, for example, be disposed on the first channel of the logic gate.

[0072] According to a second aspect of the present disclosure there is provided a method of fabrication of a semiconductor device. The method comprises: forming a plurality of layers of material; forming a memory cell comprising at least some of the layers of the plurality of layers of material; and forming a logic gate comprising at least some of the plurality of layers of material. The memory cell comprises: a floating gate for storing charge carriers so as to provide a plurality of occupancy states of the floating gate; and a readout channel arranged such that when a read voltage is applied to the memory cell, the electrical resistance of the readout channel depends on the occupancy state of the floating gate. The logic gate comprises: a first channel comprising a first current flow path; a second channel comprising a second current flow path; and a logic charge reservoir disposed between the first channel and the second channel and arranged to provide charge carriers to the first channel or the second channel dependent on an input voltage applied to the logic gate. The readout channel of the memory cell and the first channel of the logic gate are formed from the same layer of the plurality of layers of material.

[0073] The plurality of layers of material may comprise a plurality of layers of semiconductor material. For example, one or more of the layers may comprise semiconductor compounds such as III-V semiconductor compounds. In some examples, one or more of the layers may comprise van der Waals materials.

[0074] One or more of the plurality of layers of material may be formed through epitaxy (epitaxial growth) such as molecular beam epitaxy, liquid phase epitaxy, metal-organic chemical vapor deposition or metal-organic vapor phase epitaxy.

[0075] Forming the memory cell and the logic gate may comprise removing portions of at least some of the plurality of layers of material so as to isolate portions of material layers which form the memory cell and logic gate. For example, the plurality of layers of material may be selectively etched so as to remove portions of one or more material layers. Removing portions of one or more material layers may comprise entire material layers at selected horizontal positions in the plurality of layers of material.

[0076] Forming the plurality of layers of material may comprises forming: a back gate layer; a charge barrier layer; a second channel layer; a charge reservoir layer; and a first channel layer.

[0077] The back gate layer may be disposed on a substrate. The charge barrier layer may be disposed on the back gate layer. The bottom channel layer may be disposed on the charge barrier layer. The charge reservoir layer may be disposed on the bottom channel layer. The first channel layer may be formed on the charge reservoir. The layers may comprise semiconductor materials. The layers may comprise semiconductor compounds such as III-V semiconductor compounds. In some examples, one or more of the layers may comprise van der Waals materials.

[0078] The back gate layer may comprise indium arsenide (InAs). The charge barrier layer may comprise aluminium antimonide (AlSb). The second channel layer may comprise indium gallium arsenide (InGaAs). The charge reservoir layer may comprise gallium antimonide (GaSb). The first channel layer may comprise indium arsenide (InGaAs).

[0079] Forming the plurality of layers of material may further comprise forming: a selective conduction barrier; and a floating gate layer.

[0080] The selective conduction barrier may be disposed on the first channel layer. The floating gate layer may be disposed on the selective conduction barrier.

[0081] The selective conduction barrier may comprise a plurality of layers of semiconductor materials (e.g., semiconductor compounds such as III-V semiconductor compounds or van der Waals materials). The selective conduction barrier may comprise layers of semiconductor material arranged to form at least one resonant tunneling barrier. The resonant tunneling barrier may comprise a plurality of layers of semiconductor materials (e.g., III-V semiconductor compounds or van der Waals materials) arranged to form one or more quantum wells. In at least some examples, the selective conduction barrier may comprise a triple resonant tunneling barrier comprising three tunneling barriers with two quantum wells formed between the tunneling barriers. In at least some examples, the resonant tunneling barrier may comprise alternating layers of aluminium antimonide (AlSb) and indium arsenide (InAs).

[0082] The floating gate layer may comprise a layer of semiconductor materials (e.g., a semiconductor compound such as III-V semiconductor compound or a van der Waals material). The floating gate layer may comprise indium arsenide (InAs).

[0083] The floating gate of the memory cell may be formed from the floating gate layer.

[0084] Forming the memory cell and forming the logic gate may comprise: removing portions of the first channel layer, the charge reservoir layer, and the second channel layer to isolate portions of the first channel layer, the charge reservoir layer, and the second channel layer from each other.

[0085] Removing portions of the material layers may comprise etching.

[0086] The method may further comprise removing portions of the charge barrier layer to isolate portions of the charge barrier layer from each other. Alternatively, a memory charge barrier and a logic charge barrier may be formed from different portions of a continuous charge barrier layer such that the memory charge barrier and the logic charge barrier are not isolated from each other.

[0087] The method may further comprise removing portions of a selective conduction barrier and / or a floating gate layer. In some examples, the method may comprise removing portions of the selective conduction barrier and / or the floating gate layer to isolate portions of the selective conduction barrier and / or the floating gate layer. In some examples, the method may comprise removing the selective conduction barrier and / or the floating gate layer in portions of the semiconductor device which are to form the logic gate. In other examples, the selective conduction barrier and / or the floating gate layer may be retained in portions of the semiconductor device which are to form the logic gate.

[0088] Different portions of the first channel layer, the charge reservoir layer, the second channel layer and the charge barrier layer which are isolated from each other may form parts of the memory cell and the logic gate respectively. Isolated portions of a selective conduction barrier and / or a floating gate layer may form part of the memory cell. In some examples, isolated portions of a selective conduction barrier and / or a floating gate layer may form part of the logic gate.

[0089] The method may comprise removing portions of the charge barrier layer. For example, portions of the charge barrier layer may be removed to expose a portion of the back gate layer for forming a back gate contact on a portion of the back gate layer.

[0090] The readout channel of the memory cell and the first channel of the logic gate may be formed from the first channel layer.

[0091] The logic charge reservoir may be formed from the charge reservoir layer.

[0092] The memory cell may comprise a memory charge reservoir formed from the charge reservoir layer.

[0093] The second channel of the logic gate may be formed from the second channel layer.

[0094] According to a third aspect of the present disclosure there is provided a semiconductor device comprising a plurality of layers of materials, the semiconductor device comprising: a memory cell comprising a plurality of memory component layers configured so as to be operable to perform memory storage, program and erase operations; and a logic gate comprising a plurality of logic component layers configured so as to be operable to performa logic operation. At least one memory component layer and at least one logic component layer are formed from a common layer of semiconductor material.

[0095] The logic gate and the memory cell share at least one common material layer, which forms part of both the memory cell and the logic gate. That is, a first portion of a common material layer may form a memory component layer of the memory cell and a second portion of the common material layer may form a logic component layer of the logic gate. The plurality of layers of materials, the memory cell comprising a plurality of memory component layers and / or the logic gate comprising a plurality of logic component layers may include any of the features, materials, components and / or properties described herein, for example, with reference to the first and / or second aspect.

[0096] According to a fourth aspect of the present disclosure there is provided a semiconductor device comprising a plurality of layers of materials, the semiconductor device comprising: a memory cell and a logic gate. The memory cell comprising: a floating gate for storing charge carriers so as to provide a plurality of occupancy states of the floating gate; a readout channel arranged such that when a read voltage is applied to the memory cell, the electrical resistance of the readout channel depends on the occupancy state of the floating gate; a memory charge reservoir arranged to provide charge carriers to the readout channel, dependent on the occupancy state of the floating gate and a read voltage applied to the memory cell; and a memory back gate for applying a voltage across the memory cell. The logic gate comprises: a first channel comprising a first current flow path; a second channel comprising a second current flow path; a logic charge reservoir disposed between the first channel and the second channel and arranged to provide charge carriers to the first channel or the second channel dependent on an input voltage applied to the logic gate; and a logic back gate for applying an input voltage to the logic gate. At least one of the readout channel, the memory charge reservoir and the memory back gate are formed from a common layer of semiconductor material as at least one of the first channel, the second channel, the logic charge reservoir and the logic back gate.

[0097] For example, the readout channel and the first channel may be formed from a common layer of semiconductor material. The memory charge reservoir and the logic charge reservoir may be formed from a common layer of semiconductor material. The memory back gate and the logic back gate may be formed from a common layer of semiconductor material. The memory cell may further comprise a second memory channel. The second memory channel and the second channel of the logic gate may be formed from a common layer of semiconductor material. The memory cell and / or the logic gate may include any of thefeatures, materials, components and / or properties described herein, for example, with reference to the first and / or the second aspect.

[0098] According to a fifth aspect of the present disclosure there is provided a method of fabrication of a semiconductor device, the method comprising: forming a plurality of layers of material; forming a memory cell comprising at least some of the layers of the plurality of layers of material, wherein the memory cell comprises a plurality of memory component layers configured so as to be operable to perform memory storage, program and erase operations; and forming a logic gate comprising at least some of the layers of the plurality of layers of material, wherein the logic gate comprises a plurality of logic component layers configured so as to be operable to perform a logic operation. At least one memory component layer and at least one logic component layer are formed from a common layer of semiconductor material.

[0099] The plurality of layers of materials, the memory cell comprising a plurality of memory component layers and / or the logic gate comprising a plurality of logic component layers may include any of the features, materials, components and / or properties described herein, for example, with reference to the first and / or second aspect.

[0100] According to sixth aspect of the present disclosure there is provided a method of fabrication of a semiconductor device, the method comprising: forming a plurality of layers of material; forming a memory cell comprising at least some of the layers of the plurality of layers of material, and forming a logic gate comprising at least some of the layers of the plurality of layers of material. The memory cell comprises: a floating gate for storing charge carriers so as to provide a plurality of occupancy states of the floating gate; a readout channel arranged such that when a read voltage is applied to the memory cell, the electrical resistance of the readout channel depends on the occupancy state of the floating gate; a memory charge reservoir arranged to provide charge carriers to the readout channel, dependent on the occupancy state of the floating gate and a read voltage applied to the memory cell; and a memory back gate for applying a voltage across the memory cell. The logic gate comprises: a first channel comprising a first current flow path; a second channel comprising a second current flow path; a logic charge reservoir disposed between the first channel and the second channel and arranged to provide charge carriers to the first channel or the second channel dependent on an input voltage applied to the logic gate; and a logic back gate for applying an input voltage to the logic gate. The at least one of the readout channel, the memory charge reservoir and the memory back gate are formed from a common layer of semiconductor material as at least one of the first channel, the second channel, the logic charge reservoir and the logic back gate.

[0101] The memory cell and / or the logic gate may include any of the features, materials, components and / or properties described herein, for example, with reference to the first and / or the second aspect.

[0102] It will be appreciated from the foregoing disclosure and the following detailed description of the examples that certain features and implementations described as being optional in relation to any given aspect of the disclosure set out above should be understood by the reader as being disclosed also in combination with the other aspects of the present disclosure, where applicable. Similarly, it will be appreciated that any attendant advantages described in relation to any given aspect of the disclosure set out above should be understood by the reader as being disclosed as advantages of the other aspects of the present disclosure, where applicable. That is, the description of optional features and advantages in relation to a specific aspect of the disclosure above is not limiting, and it should be understood that the disclosures of these optional features and advantages are intended to relate to all aspects of the disclosure in combination, where such combination is applicable.BRIEF DESCRIPTION OF THE DRAWINGS

[0103] Certain examples of the present disclosure will now be described, with reference to the accompanying drawings, in which:- FIG. 1 is a schematic illustration of an example semiconductor device including a memory cell and a logic gate;- FIG. 2 is a schematic illustration of a further example of a semiconductor device including a memory cell and a logic gate;- FIG. 3 is a schematic illustration of an example of a selective conduction barrier;- FIG. 4 is a schematic illustration of a top-down view of a first channel and a second channel included in an example logic gate;- FIG. 5A is a schematic illustration of charge carriers in an example logic gate in the absence of an applied input voltage;- FIG. 5B is a schematic illustration of charge carriers in an example logic gate in the presence of a first applied input voltage;- FIG. 5C is a schematic illustration of charge carriers in an example logic gate in the presence of a second applied input voltage;FIG. 6 is a flowchart of an example method of fabrication of a semiconductor device;FIG. 7 is a schematic illustration of a material layer structure comprising a plurality of layers of semiconductor material;FIG. 8 is a graph illustrating energy levels in a material layer structure as a function of position in the structure;FIG. 9 is a graph illustrating an integrated electron density in a readout channel of memory cell as function of a voltage applied the memory cell;FIG. 10 is three graphs of energy levels in a logic gate as a function of position in the logic gate; andFIG. 11 is a graph of integrated electron density in a first channel and a second channel of a logic gate as a function of an applied input voltage.DETAILED DESCRIPTION

[0104] Hereinafter, examples of the disclosure are described with reference to the accompanying drawings. However, it should be appreciated that the disclosure is not limited to the described examples, and all changes and / or equivalents or replacements thereto also belong to the scope of the disclosure. The same or similar reference denotations may be used to refer to the same or similar elements throughout the specification and the drawings.

[0105] As used herein, the terms “have,” “may have,” “include,” or “may include” a feature (e.g., a number, function, operation, or a component such as a part) indicate the existence of the feature and do not exclude the existence of other features. Throughout the description and claims of this specification, the words “comprise” and “contain” and variations of them mean “including but not limited to”, and they are not intended to (and do not) exclude other components, integers or steps. Throughout the description and claims of this specification, the singular encompasses the plural unless the context otherwise requires. In particular, where the indefinite article is used, the specification is to be understood as contemplating plurality as well as singularity, unless the context requires otherwise.

[0106] As used herein, the terms “A or B,” “at least one of A and / or B,” or “one or more of A and / or B” may include all possible combinations of A and B. For example, “A or B,” “at least one of A and B,” “at least one of A or B” may indicate all of (1) including at least one A, (2) including at least one B, or (3) including at least one A and at least one B.

[0107] As used herein, the terms “first” and “second” may modify various components regardless of importance and do not limit the components. These terms are only used to distinguish one component from another. For example, reference to a first component and a second component may indicate different components from each other regardless of the order or importance of the components.

[0108] It will be understood that when an element (e.g., a first element) is referred to as being (physically, operatively or communicatively) “coupled with / to,” or “connected with / to” another element (e.g., a second element), it can be coupled or connected with / to the other element directly or via a third element. In contrast, it will be understood that when an element (e.g., a first element) is referred to as being “directly coupled with / to” or “directly connected with / to” another element (e.g., a second element), no other element (e.g., a third element) intervenes between the element and the other element.

[0109] The terms as used herein are provided merely to describe some embodiments thereof, but not to limit the scope of other embodiments of the disclosure. It is to be understood that the singular forms “a,” “'an,” and “the” include plural references unless the context clearly dictates otherwise. All terms including technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments of the disclosure belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0110] As was explained above, semiconductor devices are contemplated herein in which at least one memory cell and at least one logic gate are included in the same semiconductor device. For example, semiconductor devices are contemplated herein in which at least one common layer of semiconductor material that forms part of both a memory device and a logic gate. Several examples of such devices will be described below, for example, with reference to FIG. 1 and FIG. 2. Whilst devices are illustrated as including a single memory cell and a single logic gate, it will be appreciated that the ideas and devices described herein extend to semiconductor devices which include a plurality of memory cells and / or a plurality of logic gates.[OHl] FIG. l is a schematic illustration of a semiconductor device 202. The semiconductor device 202 comprises a memory cell 204 and a logic gate 206. The memory cell 204 and the logic gate 206 comprise a plurality of common material layers. That is, the semiconductor device 202 includes a plurality of layers of materials which form part of both the memory cell204 and the logic gate 206. As will be described in further detail below, this allows the memory cell 204 and the logic gate 206 to be formed on a common substrate 208. The memory cell 204 and the logic gate 206 may be formed on the same chip. The memory cell 204 and the logic gate 206 may form part of an integrated circuit.

[0112] The semiconductor device 202 may be fabricated by forming (e.g., growing) a plurality of layers of materials on the substrate 208. The plurality of layers of materials may comprise semiconductor materials. For example, the plurality of layers of materials may comprise semiconductor compounds such as III-V semiconductor compounds or van der Waals materials.

[0113] Portions of the layers of materials may then be modified (e.g., selectively removed) in order to form the memory cell 204 and the logic gate 206 from parts of the layers of materials. One or more further materials (e.g., a dielectric and / or electric contacts) may be further added to the semiconductor device 202 in order to form the memory cell 204 and / or the logic gate 206.

[0114] The memory cell 204 is operable to store at least one bit of information. The memory cell 204 is further operable to be subjected to program and erase operations in order to set a state of the memory cell 204 and the at least one bit of information which is stored by the memory cell 204. The memory cell 204 is further operable to be subjected to a read operation in order to read a state of the memory cell 204 and the at least one bit of information which is stored by the memory cell 204.

[0115] The logic gate 206 is operable to perform a Boolean function. In particular, the logic gate 206 is operable to produce an output voltage which is dependent on an input voltage applied to the logic gate 206.

[0116] In the example of FIG. 1, the memory cell 204 comprises a back gate 210, a memory charge barrier 214, a second memory channel 216, a memory charge reservoir 218, a readout channel 220, a selective conduction barrier 222, a floating gate 224, a memory insulating barrier 226, a memory control gate 228, a source contact 230, a drain contact 232 and a back gate contact 212. As shown in FIG. 1 the memory charge barrier 214 is arranged on the back gate 210. The second memory channel 216 is arranged on the memory charge barrier 214. The memory charge reservoir 218 is arranged on the readout channel 220. The selective conduction barrier 222 is arranged on the readout channel 220. The floating gate 224 is arranged on the selective conduction barrier 222. The memory insulating barrier 226 is arranged on the floating gate 224. The memory control gate 228 is arranged on the memory insulating barrier 226.

[0117] The floating gate 224 is operable to store charge carriers so as to take on a plurality of occupancy states. For example, the floating gate 224 may take on a first occupancy state in which charge carriers are stored in the floating gate 224 and a second occupancy state in which substantially no charge carriers are stored in the floating gate 224. In this way the floating gate 224 can function as an information storage. For example, the floating gate 224 may serve to store a bit of information, where the value of the bit of information depends on the occupancy state of the floating gate 224. In an illustrative example, the memory cell 204 may be considered to store a state “0” when charge carriers are stored in the floating gate 224 (the first occupancy state) and to store a state “1” when substantially no charge carriers are stored in the floating gate 224 (the second occupancy state).

[0118] In some examples, the floating gate 224 may take on more than two occupancy states. A floating gate 224 which can take on more than two occupancy states may be used to store a plurality of bits of information in a single memory cell 204. For example, a floating gate 224 which can take on four occupancy states may be used to store two bits of information. A floating gate 224 which can take on eight occupancy states may be used to store three bits of information, a floating gate which can take on sixteen occupancy states may be used to store four bits of information and so on. In some examples, the floating gate 224 may take on a continuum of occupancy states. Such a floating gate 224 may be used to store a representation of analogue information. Such a memory cell may have utility in analogue in-memory computing, for example, to perform a multiply and accumulate (MAC) operation.

[0119] The state of the memory cell 204 may be changed through program and erase operations which will be described in further detail below. In the absence of any applied electric fields (e.g., when not executing program or erase operations), the floating gate 224 may be electrically isolated such that its occupancy state remains substantially constant and thus the floating gate 224 serves to store the respective information.

[0120] The source contact 230 and the drain contact 232 are arranged on the readout channel 220. The readout channel 220 extends between the source contact 230 and the drain contact 232. The readout channel 220 may comprise a semiconductor material (such as a semiconductor compound). The readout channel 220 may comprise a III-V semiconductor compound such as indium gallium arsenide (InGaAs). The source contact 230 and the drain contact 232 may comprise any suitable electric conductor such as a metal.

[0121] The floating gate 224 is arranged between the memory control gate 228 and the readout channel 220. The memory control gate 228 may comprise any suitable electric conductor such as a metal. The state of the memory cell 204 may be measured (read out) byapplying a voltage to the memory control gate 228 and measuring any electrical current flowing between the source contact 230 and the drain contact 232 (and through the readout channel 220). The voltage applied to the memory control gate during a read operation may be a zero, a positive voltage or a negative voltage. The electrical resistance of the readout channel 220 (and correspondingly its conductance) is dependent on the occupancy state of the floating gate 224 and any voltage applied to the memory control gate 228. During a read process a voltage may additionally be applied between the source contact 230 and the drain contact 232 to drive a read current through the readout channel 220 when the readout channel 220 is in a conductive state.

[0122] As also shown in FIG. 1, the memory cell 204 further comprises the back gate 210. The back gate 210 is in electrical contact with the back gate contact 212. The back gate contact 212 may comprise any suitable electric conductor such as a metal. The back gate 210 may comprise a semiconductor material such as a semiconductor compound (e.g., a III-V semiconductor compound or van der Waals material). The back gate 210 may be used to apply a voltage across the memory cell 204 and thus across the readout channel 220, for example by applying a voltage between the back gate contact 212 and the memory control gate 228.

[0123] The memory charge barrier 214 is arranged between the back gate 210 and the second memory channel 216. The memory charge barrier 214 is configured to substantially prevent the transfer of mobile charge carriers across the memory charge barrier 214 during normal operation of the memory cell 204. For example, the memory charge barrier 214 may substantially prevent the transfer of mobile charge carriers between the back gate 210 and at least one of the second memory channel 216, the memory charge reservoir 218 and the readout channel 220. The memory charge barrier 214 may comprise a semiconductor compound such as a III-V semiconductor compound. The memory charge barrier 214 may comprise aluminium antimonide (AlSb). More generally, the memory charge barrier 214 may comprise any suitable semiconductor material (including semiconductor compounds) such as a van der Waals material. Alternatively, the memory charge barrier 214 may comprise an electrical insulator and / or a dielectric material, including any oxides of semiconductor materials.

[0124] The second memory channel 216 may play little or no functional role in the memory cell 204 and its presence in the memory cell 204 will be described in further detail below with reference to the logic gate 206. The second memory channel 216 may be referred to as a second memory channel 216 where the readout channel 220 forms a first channel of the memory cell 204. The second memory channel 216 may comprise a semiconductor compound such as a III-V semiconductor compound. The second memory channel 216 may compriseindium arsenide (InAs), indium gallium arsenide (InGaAs) or any other semiconductor material (including semiconductor compounds) such as van der Waals materials. In at least some examples, the second memory channel 216 may comprise a quantum well.

[0125] The memory insulating barrier 226 is arranged between the floating gate 224 and the memory control gate 228. The selective conduction barrier 222 is arranged between the floating gate 224 and the readout channel 220. In some examples, the selective conduction barrier 222 may comprise one or more resonant tunneling barriers. For example, the selective conduction barrier 222 may comprise alternating layers of different semiconductor materials (e.g., III-V semiconductor compounds or van der Waals materials) having offsets between their conduction band and arranged to form one or more quantum wells. In some examples, the selective conduction barrier 222 may comprise alternating layers of indium arsenide (InAs) and aluminium antimonide (Al Sb).

[0126] An example arrangement of the selective conduction barrier 222 is shown in more detail in FIG. 3 which is a schematic illustration of an example of a selective conduction barrier 222. The selective conduction barrier 222 comprises alternating layers of a first semiconductor 302 and a second semiconductor 304. In at least some examples, the first semiconductor 302 may comprise AlSb. The second semiconductor 304 may comprise InAs. The layers of first semiconductor 302 and second semiconductor 304 may be arranged to form a plurality of quantum wells. The quantum wells may be arranged to form a plurality of resonant tunneling barriers. In the example, shown in FIG. 3, the first semiconductor 302 and the second semiconductor 304 are arranged to form a triple resonant tunneling barrier comprising three resonant tunneling barriers. However, in other examples a different number of resonant tunneling barriers may be used.

[0127] The quantum wells may be configured to enable resonant tunneling of charge carriers which have energies which are substantially equal to a respective resonant energy for each quantum well. The resonant energy levels may, as a result of quantum confinement effects in the quantum wells, lie at an energy that is several times (e.g., two times, three times, five times, ten times or twenty times to name a few examples) a thermal energy associated with the temperature of the memory cell 204. The one or more quantum wells which form the selective conduction barrier 222 may be configured such that in the absence of an applied electric field, the resonant energies of the quantum wells do not align with each other (e.g., there may be substantial differences between the resonant energies of different quantum wells). Accordingly, in the absence of an applied electric field, there is no charge carrier energy that can tunnel through the one or more quantum wells and as such charge carriers are not able to tunnel through the selective conduction barrier 222. In the absence of an appliedelectric field, the floating gate 224 is therefore electrically isolated from the readout channel 220 by the selective conduction barrier 222.

[0128] The selective conduction barrier 222 may be further configured such that when a predetermined electric field is applied to the selective conduction barrier 222, one or more of the resonant energies of the quantum wells in the selective conduction barrier 222 substantially align with an energy level of a triangular quantum well created in the floating gate 224 or the readout channel 220 by application of the electric field. Consequently, charge carriers at the aligned resonant energies can tunnel through the selective conduction barrier 222 through a process of resonant tunneling. This process therefore allows charge carriers to be moved into and out of the floating gate 224 so as to change the occupancy state of the floating gate 224 during program and erase operations.

[0129] The floating gate 224 may comprise a semiconductor material, such as a III-V semiconductor compound or van der Waals material. The floating gate 224 may comprise InAs. The floating gate 224 may be arranged to form an electrically isolated quantum well defined between the selective conduction barrier 222 and the memory insulating barrier 226. Alternatively, the floating gate 224 may not form a quantum well. The floating gate 224 may be suitable for storing a finite number of charges carriers in quantised energy levels.

[0130] The memory insulating barrier 226 is configured to electrically isolate the floating gate 224 from the memory control gate 228 (i.e., to provide electrical insulation between the memory control gate 228 and the floating gate 224). The memory insulating barrier 226 may comprise a semiconductor material such as AlSb configured to provide a large potential barrier between the floating gate 224 and the memory control gate 228 or may comprise a dielectric such as silicon dioxide (SiCh), hafnium oxide (HfCh) or aluminium oxide (AI2O3).

[0131] The memory cell 204 may be subjected to one or more of a program operation, an erase operation and a read operation. In an example program operation, the drain contact 232 may be shorted to the back gate 210 (e.g., using the back gate contact 212) and a program voltage applied between the memory control gate 228 and the source contact 230. Alternatively, a program voltage may be applied between the memory control gate 228 and both the drain contact 232 and the source contact 230. The program voltage is configured to align resonant energies of quantum wells in the selective conduction barrier 222 such that charge carriers can tunnel through the selective conduction barrier 222. The program voltage may be a suitable voltage such that the resulting electric field drives charge carriers to pass into the floating gate 224.

[0132] In an example erase operation, the drain contact 232 may be shorted to the back gate 210 (e.g., using the back gate contact 212) and an erase voltage applied between the memory control gate 228 and the source contact 230. Alternatively, an erase voltage may be applied between the memory control gate 228 and both the drain contact 232 and the source contact 230. The erase voltage is again configured to align resonant energies of quantum wells in the selective conduction barrier 222 such that charge carriers can tunnel through the selective conduction barrier 222. The erase voltage may be a suitable voltage such that the resulting electric field drives charge carriers to pass out of the floating gate 224. The program voltage and erase voltage have different polarities and may have substantially equal magnitudes.

[0133] The example arrangement of the floating gate 224 and selective conduction barrier 222 which has been described above with reference to FIG. 1 and which utilises a one or more resonant tunneling barriers comprising one or more quantum wells is provided merely as an illustrative example. Further detail regarding memory cells including functionality similar to that described with reference to FIG. 1 are provided in published US patent applications with publication numbers US 2022 / 0230686 Al and US 2017 / 0352767 Al which are incorporated by reference herein in their entirety. In other examples, other forms of selective conduction barrier 222 may be used and other methods of moving charge carriers into and out of the floating gate 224 in program and erase operations may be used. For example, arrangements such as those used in known flash memory devices may be used.

[0134] In order to read the state of the memory cell 204, a read voltage may be applied to the memory cell 204. For example, a read voltage may be applied to the memory control gate 228 and any current flowing between the source contact 230 and the drain contact 232 (through the readout channel 220) measured. Applying a read voltage to the memory cell 204 may comprise applying the read voltage between the memory control gate 228 and the back gate 210 (e.g., using the back gate contact 212). Alternatively, applying a read voltage to the memory cell 204 may comprise applying the read voltage between the memory control gate 228 and the source contact 230 (or drain contact 232). When applying the read voltage between the memory control gate 228 and the source contact 230 (or drain contact 232), the back gate 210 may be connected to the source contact 230 (or drain contact 232). In at least some examples, the read voltage may be applied to the memory cell 204 by applying the read voltage between the memory control gate 228 and the back gate 210 in order to reduce a voltage which is induced across the selective conduction barrier 222.

[0135] Additionally, during a read operation, a voltage may be applied between the source contact 230 and the drain contact 232 so as to drive a current through the readout channel 220 when the readout channel 220 is conductive.

[0136] The memory cell 204 may be configured such that the electrical resistance (and correspondingly the conductance) of the readout channel 220 is dependent on a read voltage applied to the memory cell 204. For example, the readout channel 220 may transition between a non-conductive state and conductive state (or vice versa) when a read voltage which is greater than a threshold voltage is applied to the memory cell 204 (e.g., to the memory control gate 228). For example, the memory cell 204 may be configured such that in the absence of an applied electric field (e.g., in the absence of an applied read voltage exceeding a threshold voltage) charge carriers reside in the memory charge reservoir 218 and substantially no free charge carriers are available in the readout channel 220 and the readout channel 220 is non-conductive. When a read voltage which is greater than a threshold voltage is applied to the memory cell 204, the read voltage may cause charge carriers to move from the memory charge reservoir 218 into the readout channel 220. Consequently, free charge carriers may be available in the readout channel 220 and the readout channel 220 is conductive.

[0137] The memory cell 204 is arranged such that the threshold voltage, at which the readout channel 220 transitions between being non-conductive and conductive (or vice-versa), depends on the occupancy state of the floating gate 224. For example, in the absence of charge carriers stored in the floating gate 224 (the second occupancy state or state “1” described above), the readout channel 220 may transition between being non-conductive and conductive (or vice-versa) when a read voltage which is greater than a first threshold voltage is applied to the memory cell 204 (e.g., to the memory control gate 228). When charge carriers are stored in the floating gate 224 (the first occupancy state or state “0” described above), the charge carriers may serve to screen some of the electric field which results from an applied read voltage so as to increase the threshold voltage at which the readout channel 220 transitions between being non-conductive and conductive. That is, when charge carriers are stored in the floating gate 224 (the first occupancy state or state “0” described above), the readout channel 220 transitions between being non-conductive and conductive when a read voltage which is greater than a second threshold voltage is applied to the memory cell 204 (e.g., to the memory control gate 228). The first threshold voltage and the second threshold voltage may be different from each other. For example, the second threshold voltage may be greater than the first threshold voltage.

[0138] The difference between the first threshold voltage and the second threshold voltage may be utilised to read the state of the memory cell 204. For example, a read voltage which is between the first threshold voltage and the second threshold voltage may be applied to the memory cell 204 (e.g., to the memory control gate 228). In the absence of charge carriers stored in the floating gate 224 (the second occupancy state or state “1”), the applied readvoltage may exceed the threshold voltage for transitioning the readout channel 220 between a non-conductive state and a conductive state. In the presence of charge carriers stored in the floating gate 224 (the first occupancy state or state “0”) the applied read voltage may not exceed the threshold voltage for transitioning the readout channel 220 between a non-conductive state and a conductive state. Any current flowing through the readout channel 220 (between the source contact 230 and drain contact 232) may be measured whilst the read voltage is applied and may be used to determine the occupancy state of the floating gate 224.

[0139] In some examples, the memory cell 204 may be configured such that in the absence of an applied electric field (e.g., by way of a voltage applied to the memory cell 204) the readout channel 220 is not electrically conductive, such that substantially no current flows between the source contact 230 and the drain contact 232. Such a memory cell 204 may be referred to as a normally-off or enhancement mode memory cell 204. In a normally-off memory cell 204, the readout channel 220 may become electrically conductive, such that current flows between the source contact 230 contact and the drain contact 232, when a voltage is applied to the memory cell 204 (e.g., by applying a voltage between the memory control gate 228 and the back gate 210) which is greater than a threshold voltage.

[0140] As explained above, the threshold voltage may be dependent on the occupancy state of the floating gate 224. For example, for a normally-off memory cell 204, in the absence of charge carriers stored in the floating gate 224 (the second occupancy state or state “1” described above), the readout channel 220 may transition from being non-conductive to conductive when a read voltage which is greater than a first threshold voltage is applied to the memory cell 204. When charge carriers are stored in the floating gate 224 (the first occupancy state or state “0” described above), the readout channel 220 may transition from being non-conductive to conductive when a voltage which is greater than a second threshold voltage is applied to the memory cell 204.

[0141] When a read voltage (which is between the first threshold voltage and the second threshold voltage) is applied, in the absence of charge carriers stored in the floating gate 224 (the second occupancy state or state “1”), the applied read voltage may exceed the threshold voltage for transitioning the readout channel 220 to a conductive state. The readout channel 220 may therefore become conductive and a current may flow between the source contact 230 and the drain contact 232. Measurement of a current between the source contact 230 and the drain contact 232 during a readout operation may therefore indicate that the floating gate 224 is in the second occupancy state (state “1”). In the presence of charge carriers stored in the floating gate 224 (the first occupancy state or state “0”), the read voltage applied during a readout operation may not exceed the threshold voltage for transitioning the readout channel220 to a conductive state, the readout channel 220 may remain as non-conductive and substantially no current may flow between the source contact 230 and the drain contact 232. An absence of current flowing between the source contact 230 and the drain contact 232 during a readout operation may therefore indicate that the floating gate 224 is in the first occupancy state (state “0”).

[0142] A normally-off or enhancement mode memory cell 204 may have several advantages when compared to a normally-on or depletion mode memory cell. For example, a normally-off memory cell 204 may allow for independent addressing of each memory cell 204 in an array of memory cells 204 connected to common connection line (e.g., word line and / or bit line).

[0143] A normally-off or enhancement mode memory cell 204 may be realised by suitable choice of material layers. For example, the readout channel 220 and the memory charge reservoir 218 may be configured such that in the absence of an applied electric field, a lowest energy state in which charge carriers can reside in the memory charge reservoir 218 is lower than a lowest energy state in which charge carriers can reside in the readout channel 220. Consequently, in the absence of an applied electric field, mobile charge carriers may substantially reside in the memory charge reservoir 218 and the readout channel 220 may remain non-conductive. The readout channel 220 and the memory charge reservoir 218 may be configured such that the interface between the readout channel 220 and the memory charge reservoir 218 is a heterojunction. Conduction and / or valence band offsets at a heterojunction interface between the readout channel 220 and the memory charge reservoir 218 may be configured such that in the absence of an applied electric field, a lowest energy state in which charge carriers can reside in the memory charge reservoir 218 is lower than a lowest energy state in which charge carriers can reside in the readout channel 220.

[0144] In at least some examples, the readout channel 220 may comprise a quantum well having discrete energy levels corresponding to confined internal states in which mobile charge carriers can reside. In such examples, a lowest confined energy level of the quantum well of the readout channel 220 (in the absence of an applied electric field) may be at a higher energy than a lowest energy state in which charge carriers can reside in the memory charge reservoir 218. For example, in the absence of an applied electric field, the lowest confined energy level of the quantum well of the readout channel 220 may be at a higher energy than the valence band of the memory charge reservoir 218.

[0145] In some examples, the interface between the readout channel 220 and the memory charge reservoir 218 may be a type-III heterojunction. At a type-III heterojunction betweentwo materials, there is overlap between the valence band of a first of the materials and the conduction band of the second of the materials. For example, the material used to form the readout channel 220 may have a conduction band which is at a lower energy than a valence band of the memory charge reservoir 218. A type-III heterojunction may allow for a passage of charge carriers between the valence band of the first of the materials (e.g., the memory charge reservoir 218) and the conduction band of the second of the materials (e.g., the readout channel 220) such that the second of the materials (e.g., the readout channel 220) is conductive even in the absence of an applied electric field. In order to negate the passage of charge carriers from the memory charge reservoir 218 to the readout channel 220 (in the absence of an applied electric field) so as to realise a normally-off device, the readout channel 220 may comprise a quantum well having discrete energy levels corresponding to confined internal states in which mobile charge carriers can reside. The quantum well of the readout channel 220 may be configured such that a lowest confined energy level of the quantum well (in the absence of an applied electric field) is higher than the valence band of the memory charge reservoir 218. In such an implementation, in the absence of an applied electric field mobile charge carriers may remain in the memory charge reservoir 218 and the readout channel 220 may be substantially non-conductive, so as to realise a normally-off memory cell 204.

[0146] The use of a readout channel 220 comprising a quantum well as described above, may allow the use of materials which normally form a type-III heterojunction at their interface, to form a normally-off memory cell 204. For example, the readout channel 220 may comprise In As and the memory charge reservoir 218 may comprise GaSb. In As and GaSb form a type-III heterojunction, but the use of a readout channel 220 comprising a quantum well allows forming a normally-off device. InAs and GaSb are both 6.1 A semiconductor materials having lattice constants of approximately 6.1 angstroms and can therefore be substantially lattice matched. Additionally or alternatively, to the use of a readout channel 220 comprising a quantum well, a normally-off memory cell 204 may be realised using III-V semiconductor compounds by using III-V alloys to modify the valence and conduction bands of materials according. In at least some examples, the readout channel 220 may comprise InGaAs which may allow for modification of the valence and conduction bands of the readout channel 220 and the memory charge reservoir 218 so as to realise a normally-off memory cell 204.

[0147] As described above, a read operation may include the application of a read voltage which is between a first threshold voltage and a second threshold voltage, where the first and second threshold voltage correspond to two different occupancy states of the floating gate 224. More generally, the memory cell 204 is configured such that the electrical resistance ofthe readout channel 220 is dependent on a read voltage applied to the memory cell 204 (e.g., to the memory control gate 228 and the occupancy state of the floating gate 224. This may be utilised in any suitable manner in a read operation to apply a pre-determined read voltage to the memory control gate 228 and measure a current between the source contact 230 and the drain contact 232. The current measured between the source contact 230 and the drain contact 232 then depends on the occupancy state of the floating gate 224 and may be used to determine the occupancy state. In some examples, the floating gate 224 may take on more than two different occupancy states and the different occupancy states may be distinguished from each other by virtue of the magnitude of any measured current flowing between the source contact 230 and the drain contact 232. In this way the memory cell 204 may be capable of storing more than one bit of information. In some examples, the floating gate 224 may take on a continuum of occupancy states. In some examples, the floating gate 224 may be capable of storing analogue information.

[0148] As is shown in FIG. 1, at least one of the components of the memory cell 204 and at least one of the components of the logic gate 206 may be formed from a common layer of material. In at least some examples, a plurality of the components of the memory cell 204 may be formed from the same (common) layer of material as a respective component of the logic gate 206. For example, a first component of the memory cell 204 and a first component of the logic gate 206 may be formed from a common layer and a second component of the memory cell 204 and a second component of the logic gate 206 may be formed from a common layer of material.

[0149] Components which are formed from a common layer of material may be formed from a layer of material which is formed in a single layer process. For example, a common layer of material may be grown and / or deposited in a layer fabrication process and the components may be formed from different portions of the common layer of material. Components which are formed from a common layer of material may be formed from the same layer of a material layer structure comprising a plurality of layers of materials. For example, a material layer structure comprising a plurality of layers of material may be formed (e.g., grown and / or deposited) and the subsequently modified to form the memory cell 204 and the logic gate 206 where at least one of the plurality of layers of material forms a component of both the memory cell 204 and the logic gate 206.

[0150] Components which are formed from a common layer of material may comprise substantially the same material (e.g., semiconductor material). Whilst components are formed from a common layer of material, different portions of the common layer may be subjected to selective treatments such as selective doping (e.g, by ion-bombardment) and / or selectiveoxidation. In such examples, the components may still be considered to be formed from a common layer of material even if one or more portions of the common layer of material undergo some subsequent modification. Components which are formed from a common layer of material may comprise the same base semiconductor and / or semiconductor compound. Different portions of the same base semiconductor and / or semiconductor compound may be subjected to selective treatments (e.g., doping). Components which are formed from a common layer of material may comprise substantially the same thickness (i.e., layer thickness) of the material. Components which are formed from a common layer of material may be arranged at substantially the same position within the layers of material forming the semiconductor device 202. For example, components which are formed from a common layer of material may be arranged at substantially the same vertical position with respect to a common substrate 208 on which both the memory cell 204 and the logic gate 206 are formed.

[0151] In the example of FIG. 1, the logic gate 206 comprises the back gate 210, a logic charge barrier 234, a second channel 236, a logic charge reservoir 238, a first channel 240, a logic insulating barrier 242, a logic control gate 244, a first drive contact 256, a first output contact 254, a second drive contact 250, a second output contact 252 and the back gate contact 212. As shown in FIG. 1 the logic charge barrier 234 is arranged on the back gate 210. The second channel 236 is arranged on the logic charge barrier 234. The logic charge reservoir 238 is arranged on the second channel 236. The first channel 240 is arranged on the logic charge reservoir 238. The logic insulating barrier 242 is arranged at least partially on the first channel 240.

[0152] In the example shown in FIG. 1 the back gate 210 and the back gate contact 212 are shared between the memory cell 204 and the logic gate 206. That is, a common back gate 210 and back gate contact 212 are used for operation of both the memory cell 204 and the logic gate 206. In other examples, a separate memory back gate and logic back gate may be provided in the memory cell 204 and the logic gate 206 respectively. Similarly, a separate memory back gate contact and logic gate contact may be provided in the memory cell 204 and the logic gate 206 respectively. The material properties and arrangement of the back gate 210 and back gate contact 212 were described above with reference to the memory cell 204 and will not be described in detail again with reference to the logic gate 206.

[0153] The readout channel 220 of the memory cell 204 and the first channel 240 of the logic gate 206 may be formed of a common layer of material. The memory charge reservoir 218 and the logic charge reservoir 238 may formed of a common layer of material. The second memory channel 216 and the second channel 236 may formed of a common layer of material. The memory charge barrier 214 and the logic charge barrier 234 may be formed of a commonlayer of material. As was explained above, in the example shown in FIG. 1 the back gate 210 is common to both the memory cell 204 and the logic gate 206 and is thus also formed of a common layer of material.

[0154] Components of the logic gate 206 which are formed from a common layer of material as a component of the memory cell 204 may share one or more of the properties of corresponding component of the memory cell 204 which was described above. For example, components of the logic gate 206 which are formed from a common layer of material as a component of the memory cell 204 may comprise the same base semiconductor. Components of the logic gate 206 which are formed from a common layer of material as a component of the memory cell 204 may comprise the same semiconductor, the same semiconductor and / or the same material as the corresponding component of the memory cell 204 which was described above.

[0155] As will be described in further detail below, the first channel 240, the second channel 236 and the logic charge reservoir 238 may be configured such that in the absence of an applied electric field to the logic gate 206, charge carriers reside in the logic charge reservoir 238, whilst both the first channel 240 and the second channel 236 have a high electrical resistance (i.e., are substantially non-conducting). The first channel 240, the second channel 236 and the logic charge reservoir 238 may for example, be configured such that, in the absence of an applied electric field, a lowest energy state in which mobile charge carriers may reside in the logic charge reservoir 238 is lower than a lowest energy state in which mobile charge carriers may reside in either the first channel 240 or the second channel 236. The first channel 240 and the second channel 236 are however capable of accepting mobile charge carriers and thus are capable of becoming electrically conductive.

[0156] The first channel 240, the second channel 236 and the logic charge reservoir 238 may each comprise a semiconductor material. The first channel 240, the second channel 236 and / or the logic charge reservoir 238 may each comprise a semiconductor compound such as a III-V semiconductor compound. The first channel 240 and / or the second channel 236 may comprise InAs, InGaAs or any other semiconductor material (including semiconductor compounds) such as van der Waals materials. The logic charge reservoir 238 may comprise GaSb. The first channel 240 may comprise the same material as the readout channel 220. The logic charge reservoir 238 may comprise the same material as the memory charge reservoir 218. The second channel 236 may comprise the same material as the second memory channel 216.

[0157] During operation of the logic gate 206, an input voltage may be applied to the logic gate 206. For example, an input voltage may be applied to the logic control gate 244. The logic control gate 244 comprises an electric contact and may comprise any suitable conductive material such as a conductive metal. In at least some examples, an input voltage may be applied to the logic gate 206 by applying an input voltage between the logic control gate 244 and the back gate 210 (e.g., using the back gate contact 212).

[0158] The logic charge barrier 234 is arranged between the back gate 210 and the second channel 236. The logic charge barrier 234 is configured to substantially prevent the transfer of mobile charge carriers across the logic charge barrier 234 during normal operation of the logic gate 206. For example, the logic charge barrier 234 may substantially prevent the transfer of mobile charge carriers between the back gate 210 and at least one of the first channel 240 or the second channel 236. The logic charge barrier 234 may share any of the properties of the memory charge barrier 214 described above. The logic charge barrier 234 may comprise a semiconductor compound such as a III-V semiconductor compound. The logic charge barrier 234 may comprise aluminium antimonide (AlSb). More generally, the logic charge barrier 234 may comprise any suitable semiconductor material (including semiconductor compounds) such as a van der Waals material. Alternatively, the logic charge barrier 234 may comprise an electrical insulator and / or a dielectric material, which may include any oxides of semiconductor materials.

[0159] The logic insulating barrier 242 is arranged between the first channel 240 and the logic control gate 244. The logic control gate 244 may comprise any suitable electric conductor such as a metal. The logic insulating barrier 242 is configured to electrically isolate the first channel 240 from the logic control gate 244 (i.e., to provide electrical insulation between the logic control gate 244 and the first channel 240). The logic insulating barrier 242 may comprise a semiconductor material such as AlSb configured to provide a large potential barrier between the first channel 240 and the logic control gate 244 or may comprise a dielectric such as SiCh or AI2O3. As shown in the arrangement of FIG. 1, the logic insulating barrier 242 may further extend around side walls of the first channel 240 and / or the logic charge reservoir 238 and may be at least partially disposed on the second channel 236.

[0160] The first drive contact 256, the second drive contact 250, the first output contact 254 and the second output contact 252 each comprise electrical contacts and may comprise any suitable electrically conductive material such as a conductive metal. The first drive contact 256 and the first output contact 254 are electrically connected to the first channel 240 which extends between the first drive contact 256 and the first output contact 254. The second drivecontact 250 and the second output contact 252 are electrically connected to the second channel 236 which extends between the second drive contact 250 and the second output contact 252.

[0161] In at least some examples, the first channel 240 and the second channel 236 may extend approximately perpendicular to each other to form a cross shape. Such an example is shown in FIG. 4 which is a schematic illustration of a top-down view of a first channel 240 and second channel 236 included in an example logic gate 206. As can be seen in FIG. 4 the first channel 240 and the second channel 236 may extend in different directions (e.g., in perpendicular directions) such that a portion of the first channel 240 and the second channel 236 overlap with each other and portions of the second channel 236 do not overlap with the first channel 240. This may allow for portions of the second channel 236 to be exposed below the first channel 240, which may allow for formation of the second drive contact 250 and the second output contact 252 on the second channel 236. Additionally, or alternatively, the first channel 240 and the second channel 236 may have different dimensions in at least one direction (for example, as shown in FIG. 1) which may allow for exposed portions of the second channel 236 to which electric contact may be made.

[0162] The first drive contact 256 and the second drive contact 250 are arranged to allow for the application of different drive voltages to the first channel 240 and the second channel 236. For example, during operation a first drive voltage may be applied to the first drive contact 256 and a second drive contact may be applied to the second drive contact 250. At least one of the first drive voltage and the second drive voltage may comprise a ground voltage. For example, one of the first drive contact 256 and the second drive contact 250 may be connected to ground. The other of the first drive voltage and the second drive voltage may comprise a non-zero voltage (e.g., relative to ground). Alternatively, neither of the first drive voltage or the second drive voltage may comprise a ground voltage. For example, the first drive voltage and the second drive voltage may comprise non-zero voltages of opposite polarity. In some examples, the first drive voltage may be substantially the same as the first input voltage and / or the second drive voltage may be substantially the same as the second input voltage.

[0163] As will be explained in further detail below, a voltage (e.g., relative to ground) at the first output contact 254 and the second output contact 252 depends on conductivity states of the first channel 240 and the second channel 236 (and on the drive voltage at the first drive contact 256 or second drive contact 250 which is connected to a conductive channel). Whilst not shown in FIG. 1, the first output contact 254 and the second output contact 252 may be electrically connected together to form a common output of the logic gate 206.

[0164] As was explained above, the first channel 240, the second channel 236 and the logic charge reservoir 238 may be arranged such that in the absence of an applied electric field, mobile charge carriers substantially reside in the logic charge reservoir 238 and the electrical resistance of the first channel 240 and the second channel 236 is relatively high. This is illustrated in FIG. 5A, which is a schematic illustration of the first channel 240, the logic charge reservoir 238, the second channel 236 and the location of mobile charge carriers 502 in the absence of an applied electric field. The absence of an applied electric field corresponds with no input voltage (0V) applied to logic gate 206.

[0165] A configuration in which mobile charge carriers 502 substantially reside in the logic charge reservoir 238 under no applied electric field may be achieved through any suitable configuration of the material layers forming the logic charge reservoir 238 and the first and second channels 236, 240. For example, the materials may be chosen such that the interfaces between the logic charge reservoir 238 and the first channel 240 and between the logic charge reservoir 238 and the second channel 236 comprise heterojunctions. The offsets between conduction and valence bands at the heterojunctions may be such that (in the absence of an applied electric field) a conduction band minimum energy of the logic charge reservoir 238 is lower than a conduction band minimum energy of the first channel 240 and a conduction band minimum energy of the second channel 236. In at least some examples, one or more of the logic charge reservoir 238, the first channel 240 and the second channel 236 may comprise a quantum well. One or more quantum wells may be configured such that (in the absence of an applied electric field) a lowest confined energy state in the logic charge reservoir 238 is lower than a lowest confined energy state in the first channel 240 or in the second channel 236.

[0166] The location of mobile charge carriers 502 and the conductivity of the first channel 240 and the second channel 236 may be changed by application of an input voltage to the logic gate 206 (e.g., to the logic control gate 244). When a first input voltage is applied to the logic gate 206 (e.g., between the back gate 210 and the logic control gate 244) charge carriers 502 may move from the logic charge reservoir 238 into one of the first channel or the second channel. FIG. 5B is a schematic illustration of the same arrangement of components as shown in FIG. 5A with a first input voltage (+V) applied to the logic gate 206. In the example, shown in FIG. 5B a positive first input voltage is applied to the logic gate 206 (e.g., to the logic control gate 244) and the charge carriers 502 comprise electrons such that the charge carriers 502 move into the first channel 240. The first channel 240 therefore becomes electrically conductive under application of the first input voltage. Substantially no chargecarriers move into the second channel 236 under the application of the first input voltage and thus the electrical resistance of the second channel 236 remains high.

[0167] When a second input voltage is applied to the logic gate 206 (e.g., to the logic control gate 244) charge carriers 502 may move into the second channel 236. The second input voltage may have an opposite polarity to the first input voltage. FIG. 5C is a schematic illustration of the same arrangement of components as shown in FIG. 5A and FIG. 5B with a second input voltage (-V) applied to the logic gate 206. In the example, shown in FIG. 5C a negative second input voltage is applied to the logic gate 206 (e.g., to the logic control gate 244) and the charge carriers 502 comprise electrons such that the charge carriers 502 move into the second channel 236. The second channel 236 therefore becomes electrically conductive under application of the second input voltage. Substantially no charge carriers move into the first channel 240 under the application of the second input voltage and thus the electrical resistance of the first channel 240 remains high.

[0168] In the example described with reference to FIG. 5B and FIG. 5C, the charge carriers 502 comprise electrons such that a positive input voltage causes the charge carriers 502 to move into the first channel 240 and a negative input voltage causes the charge carriers 502 to move into the second channel 236. In other examples the charge carriers 502 may comprise holes and the application of a positive input voltage may cause the charge carriers 502 to move into the second channel 236 and a negative input voltage may cause the charge carriers 502 to move into the first channel 240.

[0169] In general, under the application of a first input voltage to the logic gate 206, one of the first channel 240 or the second channel 236 may become conductive, whilst the electrical resistance of the other of the first channel 240 and the second channel 236 remains high. When a second input voltage is applied to the logic gate 206 (which may be of opposite polarity to the first input voltage), the channel (of the first channel 240 and the second channel 236) which was conductive under application of the first input voltage may have a relatively high resistance and the channel which had a high resistance under application of the second input voltage may become conductive. Under all input voltages only one of the first channel 240 and the second channel 236 may therefore be conductive and the other of the first channel 240 and the second channel 236 may have a relatively high resistance.

[0170] The above described properties of the first channel 240, second channel 236 and logic charge reservoir 238 may allow these components to be operated as a logic gate 206 having an output which is dependent on the input voltage applied to the logic gate 206. The output of the logic gate 206 is provided by the first output contact 254 and the second output contact252. In at least some examples, the first output contact 254 and the second output contact 252 may be electrically connected to each other to form a common logic gate 206 output (not shown in the Figures).

[0171] A voltage at the logic gate 206 output will depend on an input voltage applied to the logic gate 206 and first and second drive voltages applied to the first drive contact 256 and second drive contact 250 respectively. For example, when a first input voltage is applied to the logic gate 206 which causes the first channel 240 to be conductive and the second channel 236 to have a high resistance, then the first drive voltage which is applied to the first drive contact 256 will appear at the logic gate 206 output (by virtue of the conductance of the first channel 240). When a second input voltage is applied to the logic gate 206 which causes the second channel 236 to be conductive and the first channel 240 to have a high resistance, then the second drive voltage which is applied to the second drive contact 250 will appear at the logic gate 206 output (by virtue of the conductance of the second channel 236). As was explained above, in at least some examples, one of the first drive voltage and the second drive voltage may comprise a ground voltage. For example, the second drive contact 250 may be connected to ground. In such examples, a voltage at the logic gate 206 output may be a ground voltage when the channel with a ground drive voltage is conductive. In other examples, neither of the first drive voltage and second drive voltage are ground voltages. In such examples, the voltage at the logic gate 206 output may not be a ground voltage when one of the first channel 240 and the second channel 236 are conductive.

[0172] The logic gate 206 described above with reference to FIG. 1 is operable to perform a Boolean function to produce an output which is dependent on an input voltage applied to the logic gate 206. Further detail regarding logic gates having similar functionality and / or properties to that described with reference to FIG. 1 is provided in published PCT patent application with publication number W02024003523 Al which is incorporated by reference herein in their entirety.

[0173] As described above with reference to FIG. 1, the memory cell 204 and the logic gate 206 share a plurality of common layers of material. That is, a plurality of common layers of material form part of both the memory cell 204 and the logic gate 206. This allows the memory cell 204 and the logic gate 206 to be formed on the same substrate 208 and, for example, integrated into a common integrated circuit.

[0174] In order to allow for forming both the memory cell 204 and the logic gate 206 on the same substrate 208, in some examples, one or more components in one or both of the memory cell 204 and the logic gate 206 may be included but may not perform a functional role. In theexample of FIG. 1, one component of the semiconductor device 202 which may not perform a functional role in the memory cell 204 or the logic gate 206 is the second memory channel 216 of the memory cell 204. However, the second memory channel 216 of the memory cell 204 may still be included in the memory cell 204 so that both the memory cell 204 and the logic gate 206 can be formed from the same multi-layer material structure. That is, since a layer of material corresponding to the second channel 236 of the logic gate 206 is included in order to provide the functionality of second channel 236, a corresponding layer is included in the memory cell 204 (the second memory channel 216) so that a common multi-layer material layer structure can be used for both the memory cell 204 and the logic gate 206.

[0175] The memory cell 204 may be configured such that when a read voltage is applied across the memory cell 204, charge carriers are driven towards the readout channel 220 and may move into the readout channel 220 (dependent on the occupancy state of the floating gate). The resistance of the second memory channel 216 may remain relatively high during application of a read voltage and thus the second memory channel 216 does not affect a read operation of the memory cell 204. Normal operation of the memory cell 204 may only include application of a voltage across the memory cell 204 which would result in the second memory channel 216 becoming conductive during an erase operation of the memory cell 204. During such an erase operation, the presence of charge carriers in the second memory channel 216 may have little or no impact on the erase operation.

[0176] In the example shown in FIG. 1, logic gate 206 does not include material layers corresponding to the selective conduction barrier 222 or the floating gate 224. As will be described in further detail below, in some examples, a multi-layer material structure may be formed which includes material layers corresponding to the selective conduction barrier 222 and the floating gate 224. The selective conduction barrier 222 and the floating gate 224 layers may then be selectively removed from the portion of the structure which is to form the logic gate 206 such that the logic gate 206 does not include these layers as shown in FIG. 1. The logic insulating barrier 242, the memory insulating barrier 226 and / or one or more of the electric contacts may then subsequently be formed on the semiconductor device 202 to form the device 202 shown in FIG. 1.

[0177] In other examples, material layers corresponding to the selective conduction barrier 222 and / or the floating gate 224 may be retained in a logic gate 206. FIG. 2 is a schematic illustration of an example semiconductor device 258 in which the logic gate 206 includes a logic selective conduction barrier 246 and a logic insulating barrier 242 corresponding to material layers of the memory cell 204. The semiconductor device 258 shown in FIG. 2 includes many of the same components as the semiconductor device 202 shown in FIG. 1.Components of the semiconductor device 258 of FIG. 2 which correspond with components of the semiconductor device 202 of FIG. 1 are labelled with corresponding reference numerals. Any of the properties of these components described above with reference to FIG.1 may also apply to the corresponding components of the semiconductor device 258 of FIG.2 and no further detailed description of these components is provided with reference to FIG.2.

[0178] The semiconductor device 258 of FIG. 2 differs from the semiconductor device 202 of FIG. 1 by virtue of the logic selective conduction barrier 246 and logic floating gate 248 included in the logic gate 206 of the semiconductor device 258 of FIG. 2. The logic selective conduction barrier 246 is formed from a plurality of common layers of material with the selective conduction barrier 222 which forms part of the memory cell 204. For example, the logic selective conduction barrier 246 may include the same layers of material as the selective conduction barrier 222 described above with reference to FIG. 1 and FIG. 3. The logic insulating barrier 242 is formed from a common layer of material with the floating gate 224. For example, any of the material properties of the floating gate 224 described above may also apply to the logic floating gate 248.

[0179] In the example, of FIG. 2 the logic insulating barrier 242 is arranged on the logic floating gate 248 and the logic control gate 244 is arranged on the logic insulating barrier 242. The logic insulating barrier 242 may have any of the material and / or functional properties of the logic insulating barrier 242 described above with reference to FIG. 1, but with the logic insulating barrier 242 disposed on the logic floating gate 248 rather than on the first channel 240 as in FIG. 1. The inclusion of the logic selective conduction barrier 246 and logic floating gate 248 means that the removal of the material layers which form the selective conduction barrier 222 and the floating gate 224 of the memory cell 204 from the logic gate 206 is not necessary.

[0180] As was described above with reference to the selective conduction barrier 222 of FIG. 1 and FIG. 3, the selective conduction barrier 222 may only become conductive when a specific voltage is applied across the selective conduction barrier 222 which aligns resonant energies of quantum wells in the selective conduction barrier 222. During normal operation of the logic gate 206 the logic selective conduction barrier 246 may remain non-conductive. For example, the logic gate 206 may be operated in such a manner that insufficient voltage is applied across it to allow resonant tunneling and the passage of charge carriers across the logic selective conduction barrier 246. For example, an input voltage applied to the logic gate 206 may not correspond to a voltage which serves to align resonant energies of quantum wells in the logic selective conduction barrier 246. The logic selective conduction barrier 246and / or the logic floating gate 248 may therefore play little or no functional role in operation of the logic gate 206.

[0181] Whilst the example shown in FIG. 2 includes the logic insulating barrier 242, in other examples, which include a logic selective conduction barrier 246, the logic insulating barrier 242 may not be needed. For example, the logic control gate 244 may be disposed directly on the logic floating gate 248. In such examples, if no input voltage is applied to the logic gate 206 which serves to align resonant energies of quantum wells in the logic selective conduction barrier 246, then the selective conduction barrier 222 may provide sufficient isolation between the logic control gate 244 and the first channel 240.

[0182] FIG. 6 is a flow chart of a method 600 of fabrication of a semiconductor device. The method 600 may be used to fabricate a semiconductor device including any of the features of the semiconductor device 202 and / or semiconductor device 258 described above.

[0183] At step 602, a plurality of layers of material are formed. The plurality of layers of material may comprise semiconductor materials. For example, the plurality of layers of material may comprise one or more semiconductor compounds such as III-V semiconductor compounds or any other semiconductor material such as van der Waals materials. The plurality of layers of material may be formed by any suitable method such as material growth and / or deposition. In at least some examples, forming the plurality of layers of material may comprise epitaxy (epitaxial growth) such as molecular beam epitaxy, liquid phase epitaxy, metal-organic chemical vapor deposition or metal-organic vapor phase epitaxy. The plurality of layers of materials may be formed on a substrate 208. The plurality of layers of materials may, for example, be formed across a substantially full extent of a substrate 208.

[0184] FIG. 7 is a schematic illustration of an example material layer structure 702 formed according to step 602 of the method 600 of FIG. 6. The material layer structure 702 comprises a plurality of layers of material formed on a substrate 208.

[0185] In the example shown in FIG. 7 the material layer structure 702 comprises a back gate layer 704, a charge barrier layer 706, a second channel layer 708, a charge reservoir layer 710, a first channel layer 712, a selective conduction barrier 714 and a floating gate layer 720. The selective conduction barrier 714 may comprise alternating layers of a first semiconductor 716a, 716b, 716c and a second semiconductor 718a, 718b. The back gate layer 704 is arranged on the substrate 208. The charge barrier layer 706 is arranged on the back gate layer 704. The second channel layer 708 is arranged on the charge barrier layer 706. The charge reservoir layer 710 is arranged on the second channel layer 708. The first channel layer 712 is arranged on the charge reservoir layer 710. The selective conduction barrier 714 is arranged on thefirst channel layer 712. The floating gate layer 720 is arranged on the selective conduction barrier 714.

[0186] Purely by way of illustrative example, specific properties of the material layers in a functioning example are provided in the Table 1 below. The layer to which each row of Table 1 relates is named in the first column of the table and using the same reference numerals as in FIG. 7. The first semiconductor layers with reference numerals 716a, 716b, and 716c and the second semiconductor layers with reference numerals 718a and 718b together form the selective conduction barrier 714. The material used to form each layer is provided in the second column of table 1. The thickness of each layer (e.g., layer thickness in the vertical direction in FIG. 7) is provided in nanometres (nm) in the third column of Table 1. The fourth column of Table 1 lists any doping of each layer including a doping type and concentration in centimetres cubed (cm3). Rows in which the doping column is empty correspond with layers which are undoped.Table 1

[0187] It will be appreciated that in other examples modifications may be made to the materials, thicknesses and / or doping of one or more of the layers. Additionally or alternatively, in some examples, one or more of the layers listed in Table 1 may not be included in a material layer structure 702 and / or one or more additional layers may be included in a material layer structure 702.

[0188] In at least some examples, the relative composition of one or more of the material layers may be controlled and may, for example, differ between two layers which are formed of the same general material, such as a semiconductor alloy. For example, material layers which comprise InGaAs may comprise different ratio amounts of indium and gallium. In a merely illustrative example, the first channel 240 may comprise a first alloy composition of InGaAs such as In0.sGa0.2As. The second channel 236 may comprise a second alloycomposition of InGaAs such as Ino.seGao.uAs. Alloy compositions may be chosen in order to provide desired functionality for use in a memory cell 204 and / or a logic gate 206. For example, alloy compositions may be chosen in order to bring about desired mismatches between valence and conductance bands at heterojunction interfaces between materials and / or to bring about desired lowest energy states in which mobile charge carriers can reside in different material layers. Additionally or alternatively alloy compositions may be chosen in order to manage strain in the material layer structure 702 as a result of lattice mismatch between the different materials in the different layers of the material layer structure 702.

[0189] At step 604 of FIG. 6 a memory cell 204 is formed comprising at least some of the layers of the plurality of layers of material which form the material layer structure 702. At step 606 of FIG. 6 a logic gate 206 is formed comprising at least some of the layers of the plurality of layers of material which form the material layer structure 702. In practice, step 604 and step 606 may be performed in parallel and / or as part of the same process. Forming the memory cell 204 and the logic gate 206 may comprise removing portions of one or more of the layers of material in the material layer structure 702. For example, portions of one or more of the layers of material may be removed to leave only portions of those layers of material which form part of a logic gate 206 and / or a memory cell 204.

[0190] It can be seen, for example, that the semiconductor device 202 of FIG. 1 and / or the semiconductor device 258 of FIG. 2 could be formed from the material layer structure 702 of FIG. 7 by removing portions of the charge barrier layer 706, the second channel layer 708, the charge reservoir layer 710, the first channel layer 712, the selective conduction barrier 714 and the floating gate layer 720.

[0191] The memory charge barrier 214 and the logic charge barrier 234 may then comprise remaining portions of the charge barrier layer 706. For example, removing at least one portion of the charge barrier layer 706 may serve to isolate the memory charge barrier 214 from the logic charge barrier 234 and to define a lateral position and extent of the memory charge barrier 214 and the logic charge barrier 234.

[0192] The second memory channel 216 and the second channel 236 may comprise remaining portions of the second channel layer 708. For example, removing at least one portion of the second channel layer 708 may serve to isolate the second memory channel 216 from the second channel 236 and to define a lateral position and extent of the second memory channel 216 and the second channel 236.

[0193] The memory charge reservoir 218 and the logic charge reservoir 238 may comprise remaining portions of the charge reservoir layer 710. For example, removing at least oneportion of the charge reservoir layer 710 may serve to isolate the memory charge reservoir 218 from the logic charge reservoir 238 and to define a lateral position and extent of the memory charge reservoir 218 and the logic charge reservoir 238.

[0194] The readout channel 220 and the first channel 240 may comprise remaining portions of the first channel layer 712. For example, removing at least one portion of the first channel layer 712 may serve to isolate the readout channel 220 from the first channel 240 and to define a lateral position and extent of the readout channel 220 and the first channel 240.

[0195] The selective conduction barrier 222 (and in the example of FIG. 2 the logic selective conduction barrier 246) may comprise remaining portion(s) of the selective conduction barrier 714. For example, removing at least one portion of the selective conduction barrier 714 may serve to isolate the selective conduction barrier 222 of the memory cell 204 and to define a lateral position and extent of the selective conduction barrier 222. In the example, of FIG. 1, the selective conduction barrier 714 is removed from the logic gate 206. In the example of FIG. 2 at least one portion of the selective conduction barrier 714 is removed to isolate the selective conduction barrier 222 of the memory cell 204 and the logic selective conduction barrier 246 and to define a lateral position and extent of the selective conduction barrier 222 and the logic selective conduction barrier 246.

[0196] The floating gate 224 (and in the example of FIG. 2 the logic floating gate 248) may comprise remaining portion(s) of the floating gate layer 716. For example, removing at least one portion of the floating gate layer 716 may serve to isolate the floating gate 224 of the memory cell 204 and to define a lateral position and extent of the floating gate 224. In the example, of FIG. 1, the floating gate layer 716 is removed from the logic gate 206. In the example, of FIG. 2 at least one portion of the floating gate layer 716 is removed to isolate the floating gate 224 of the memory cell 204 and the logic floating gate 248 and to define a lateral position and extent of the floating gate 224 and the logic floating gate 248.

[0197] Removing portions of one or more material layers may comprise etching portions of the one or more material layers. For example, selective etching may be performed in order to only remove selected portions of one or more material layers and to retain portions which form part of a memory cell 204 and / or a logic gate 206. Selective removal (e.g., selective etching) may be performed as part of a lithography process (e.g., photolithography). An example lithography process, which may be used to define portions of material to be removed (and thus also the position and extent of remaining portions which form a memory cell 204 and / or a logic gate 206), may include deposition of a resist on to the material layer structure 702. A patterned beam of radiation (e.g., of photons or electrons) may then be projected ontothe resist using a lithography apparatus. The patterned radiation beam may induce a chemical reaction in portions of the resist which are exposed to radiation. The resist may then be developed, for example, using a solvent to remove either exposed or unexposed portions of the resist (depending on the type of resist which is used) to leave a patterned mask. One or more materials which form the material layer structure 702 may then be subjected to a selective etching process (e.g., chemical etching or dry etching using ions or a plasma) in which portions which are exposed through the patterned mask are etched away. Forming the memory cell 204 and the logic gate 206 may comprise performing a plurality of lithography and selective etching processes (e.g., using a plurality of different patterned masks) to selectively remove different portions of different material layers.

[0198] The method may further comprise forming one or more additional materials on the semiconductor device. For example, after portions of the material layer structure 702 are removed to define the lateral positions and extents of the semiconductor components which form the memory cell 204 and the logic gate 206, additional material may be formed on one or more of the remaining portions of material layers. For example, material forming one or more insulating barriers (e.g., a dielectric) may be formed at appropriate positions to form, for example, the memory insulating barrier 226 and / or the logic insulating barrier 242. Additionally or alternatively, one or more electric contacts (e.g., the back gate contact 212, the source contact 230, the drain contact 232, the memory control gate 228, the first drive contact 256, the first output contact 254, the second drive contact 250, the second output contact 252 and / or the logic control gate 244) may be formed at appropriate locations to form electric contacts of the semiconductor device. One or more additional or alternative steps may also be performed as part of the method 600. For example, one or more passivation layers (such as a silicon nitride (SiaN4)) may be added to the semiconductor device.

[0199] In at least some examples, a semiconductor device as contemplated herein may comprise a plurality of memory cells 204 and / or a plurality of logic gates 206. For example, the same material layer structure 702 may be used to form a plurality of memory cells 204 and / or a plurality of logic gates 206. Portions of one or more of the layers of material may be removed (for example, using any of the processes described above) to isolate and to define the lateral position and extent of components of one or more memory cells 204 and / or logic gates 206. Forming at least one memory cell 204 and at least one logic gate 206 from a common material layer structure 702 may allow for flexibility as to the positions of the at least one memory cell 204 and at least one logic gate 206 in the same semiconductor device (for example, on the same substrate and / or forming part of the same integrated circuit). A plurality of layers of material may be formed across a semiconductor device to form a singlematerial layer structure 702. The same material layer structure 702 may then be modified (e.g., material layers selectively removed) at selected locations in order to form one or more memory cells 204 and / or logic gates 206 at desired locations in the same semiconductor device.

[0200] In order to illustrate the utility of a semiconductor device as described herein, several properties of an example semiconductor device will be described with reference to FIG. 8 -FIG. 11. The properties illustrated in FIG. 8 - FIG. 11 correspond to the room temperature behaviour of a semiconductor device of the type shown in FIG. 1 and having the material and layer properties described above with reference to Table 1.

[0201] FIG. 8 is a graph showing a room temperature energy level diagram of a material layer structure 702 as described herein and detailed above with reference to Table 1. Energy levels are shown on the vertical axis as a function of position in the material layer structure 702 (with the top being at 0 nm and the bottom being at 250 nm). The position of the different layers of the material layer structure 702 are labelled on the graph using the same reference numerals as used in FIG. 7. Additionally, an insulation barrier layer is included and labelled 226 in FIG. 8. The labelled lines shown in FIG. 8 represent the lowest energy state of a conduction band 818 of the different layers, the highest energy state of a valence band 822 of the different layers, a Fermi level 824 of the different layers and a quantum well energy 820. The quantum well energy 820 corresponds to a lowest confined energy state in a quantum forming the first channel layer 712. Each of the energy levels correspond to respective energies in the absence of an electric field. As can be seen in FIG. 7, the quantum well energy 820 in the first channel 240 is higher than the Fermi level 824 thus ensuring that substantially no mobile charge carriers are available in the first channel layer 712 in the absence of an applied voltage. As was explained above, this may realise normally-off memory cell 204.

[0202] FIG. 9 is a graph showing an integrated electron density in the readout channel 220 of the memory cell 204 as a function of a voltage applied to the memory control gate 228 at room temperature. The integrated electron density of the readout channel 220 is plotted on the vertical axis as a function of the voltage applied to the memory control gate 228 on the horizontal axis. The integrated electron density is plotted for a first occupancy state "0" 902 in which charge carriers are stored in the floating gate 224 and a second occupancy state "1" 904 in which substantially no charge carriers are stored in the floating gate 224. As can be seen in FIG. 9 there is a clear separation between the integrated electron density in the readout channel 220 for the two different occupancy states. For example, at a reference read voltage of 0.4 V the ratio of the integrated electron density between the two occupancy states isapproximately 25. This allows the occupancy states to be clearly distinguished from each by virtue of a difference in current in the readout channel 220 when a read voltage is applied.

[0203] FIG. 10 includes three graphs of energy levels as a function of position in a logic gate 206 of the type shown in FIG. 1 at room temperature. The logic gate 206 is formed from a material layer structure 702 as described herein and detailed above with reference to Table 1 with the selective conduction barrier 714 and the floating gate layer 716 removed. Energy levels are shown on the vertical axis as a function of position in the logic gate 206 (with the bottom being at 0 nm and the top being at 250 nm). The energy levels are shown in the context of the use of a logic gate 206 and for different applied input voltages. The approximate positions of the first channel 240, the logic charge reservoir 238 and the second channel 236 are indicated in FIG. 10 using the same reference numerals as those used in FIG. 1. The lefthand panel 1002 in FIG. 10 represents a first input voltage of +2V. The middle panel 1004 in FIG. 10 represents no applied input voltage (0 V). The right-hand panel 1006 in FIG. 10 represents a second input voltage of -2V. The energy levels plotted in FIG. 10 include a first channel quantum well energy 1008, a second channel quantum well energy 1010, a lowest energy state of the conduction band 1012, a highest energy state of the valence band 822, and an electron Fermi level 1016. The first channel quantum well energy 1008 represents a lowest confined energy level in a quantum well forming the first channel 240. The second channel quantum well energy 1010 represents a lowest confined energy level in a quantum well forming the second channel 236.

[0204] As can be seen in FIG. 10 in the absence of an applied input voltage (as shown in the middle panel 1004) the electron Fermi level 1016 is below both the first channel quantum well energy 1008 and the second channel quantum well energy 1010. As a result, mobile charge carriers (electrons) are absent from the first channel 240 and the second channel 236 as was described above with reference to FIG. 5A, and thus the first channel 240 and the second channel 236 are substantially non-conductive. When a first input voltage is applied (as shown in the left-hand panel 1002) the first channel quantum well energy 1008 is below the electron Fermi level 1016. However, the second channel quantum well energy 1010 remains above the electron Fermi level 1016. As a result, mobile charge carriers (electrons) move into the first channel 240 which becomes conductive as was described above with reference to FIG. 5B. The second channel 236 however remains unoccupied of mobile charge carriers (electrons) and thus remains substantially non-conductive.

[0205] When a second input voltage is applied (as shown in the right-hand panel 1006) the second channel quantum well energy 1010 is below the electron Fermi level 1016. However, the first channel quantum well energy 1008 remains above the electron Fermi level 1016. Asa result, mobile charge carriers (electrons) move into the second channel 236 which becomes conductive as was described above with reference to FIG. 5C. The first channel 240 however remains unoccupied of mobile charge carriers (electrons) and thus remains substantially non-conductive.

[0206] FIG. 11 is a graph of integrated electron density in both the first channel 240 and the second channel 236 of the logic gate 206 as a function of an applied input voltage (CG bias in FIG. 11) at room temperature. The line labelled 1102 represents the integrated electron density of the first channel 240 and the line labelled 1104 represents the integrated electron density of the second channel 236. As can be seen in FIG. 11 the integrated electron density of the first channel 240 and the second channel 236 cross at an input voltage of approximately 0 V and exhibit approximately symmetrical behaviour around 0 V. The value of the integrated electron density (1102, 1104) at 0 V is sufficiently low that it can be expected that both the first channel 240 and the second channel 236 are substantially non-conductive. At positive input voltages the integrated electron density in the first channel 1102 increases, such that the first channel 240 becomes conductive at positive input voltages. Conversely, at negative input voltages the integrated electron density in the second channel 1104 increases and the second channel 236 becomes conductive at negative input voltages.

[0207] As demonstrated by the results shown in FIG. 8 - FIG. Il a memory cell 204 and logic gate 206 according to examples disclosed herein exhibit behaviour necessary for their functionality as a memory cell 204 and logic gate 206 respectively. It will be appreciated that various modifications may be made to the specific examples disclosed herein whilst retaining the functionality of the memory cell 204 and logic gate 206.

[0208] Features, integers, characteristics or groups described in conjunction with a particular aspect, embodiment or example of the invention are to be understood to be applicable to any other aspect, embodiment or example described herein unless incompatible therewith. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and / or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and / or steps are mutually exclusive. The invention is not restricted to the details of any foregoing embodiments. The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed. In particular, any dependent claims may be combined with any of the independent claims and any of the other dependent claims.

[0209] Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features. The invention is not restricted to the details of any foregoing embodiments. The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed. The claims should not be construed to cover merely the foregoing embodiments, but also any embodiments which fall within the scope of the claims.

Claims

CLAIMS1. A semiconductor device comprising a plurality of layers of materials, the semiconductor device comprising:a memory cell comprising:a floating gate for storing charge carriers so as to provide a plurality of occupancy states of the floating gate;a readout channel arranged such that when a read voltage is applied to the memory cell, the electrical resistance of the readout channel depends on the occupancy state of the floating gate; anda logic gate comprising:a first channel comprising a first current flow path;a second channel comprising a second current flow path; anda logic charge reservoir disposed between the first channel and the second channel and arranged to provide charge carriers to the first channel or the second channel dependent on an input voltage applied to the logic gate,wherein the readout channel of the memory cell and the first channel of the logic gate are formed from a common layer of semiconductor material.

2. The semiconductor device of claim 1, wherein the memory cell further comprises a memory charge reservoir arranged to provide charge carriers to the readout channel, dependent on the occupancy state of the floating gate and a read voltage applied to the memory cell, wherein the memory charge reservoir of the memory cell and the logic charge reservoir of the logic gate are formed from a common layer of semiconductor material.

3. The semiconductor device of claim 1 or 2, wherein the memory cell comprises a memory back gate for applying a voltage across the memory cell,wherein the logic gate comprises a logic back gate for applying an input voltage to the logic gate, andwherein the memory back gate of the memory cell and the logic back gate of the logic gate are formed from a common layer of semiconductor material.

4. The semiconductor device of claim 3, wherein the memory cell comprises a memory charge barrier arranged to provide a charge barrier between the memory back gate and the readout channel, andwherein the logic gate comprises a logic charge barrier arranged to provide a charge barrier between the logic back gate and the second channel of the logic gate, andwherein the memory charge barrier and the logic charge barrier are formed of a common layer of material.

5. The semiconductor device of any one of claims 1 to 4, wherein the memory cell further comprises a layer formed of a common layer of semiconductor material with the second channel of the logic gate.

6. The semiconductor device of any one of claims 1 to 5, wherein the memory cell further comprises a selective conduction barrier arranged between the floating gate and the readout channel and to allow for selective conduction of charge carriers into and out of the floating gate so as to change the occupancy state of the floating gate.

7. The semiconductor device of any one of claims 1 to 6, wherein the memory cell further comprises a memory control gate and a memory insulating barrier arranged between the floating gate and the memory control gate, wherein the memory control gate is arranged for applying a voltage across the memory cell.

8. The semiconductor device of any one of claims 1 to 7, wherein the logic gate further comprises a logic control gate and a logic insulating barrier arranged between the first channel and the logic control gate, wherein the logic control gate is arranged for applying an input voltage to the logic gate.

9. The semiconductor device of claim 8, as dependent on claim 7, wherein the memory insulating barrier and the logic insulating barrier are formed of a common layer of material.

10. A method of fabrication of a semiconductor device, the method comprising:forming a plurality of layers of material;forming a memory cell comprising at least some of the layers of the plurality of layers of material, wherein the memory cell comprises:a floating gate for storing charge carriers so as to provide a plurality of occupancy states of the floating gate; anda readout channel arranged such that when a read voltage is applied to the memory cell, the electrical resistance of the readout channel depends on the occupancy state of the floating gate; andforming a logic gate comprising at least some of the plurality of layers of material, wherein the logic gate comprises:a first channel comprising a first current flow path;a second channel comprising a second current flow path; anda logic charge reservoir disposed between the first channel and the second channel and arranged to provide charge carriers to the first channel or the second channel dependent on an input voltage applied to the logic gate,wherein the readout channel of the memory cell and the first channel of the logic gate are formed from the same layer of the plurality of layers of material.

11. The method of claim 10, wherein forming the plurality of layers of material comprises forming:a back gate layer;a charge barrier layer;a second channel layer;a charge reservoir layer; anda first channel layer.

12. The method of claim 11, wherein forming the plurality of layers of material further comprises forming:a selective conduction barrier; anda floating gate layer.

13. The method of claim 12, wherein the floating gate of the memory cell is formed from the floating gate layer.

14. The method of any one of claims 11 to 13, wherein forming the memory cell and forming the logic gate comprises:removing portions of the first channel layer, the charge reservoir layer, and the second channel layer to isolate portions of the first channel layer, the charge reservoir layer, and the second channel layer from each other.

15. The method of any one of claims 11 to 14, wherein the readout channel of the memory cell and the first channel of the logic gate are formed from the first channel layer.

16. The method of any one of claims 11 to 15, wherein the logic charge reservoir is formed from the charge reservoir layer.

17. The method of claim 16, wherein the memory cell comprises a memory charge reservoir formed from the charge reservoir layer.

18. The method of any one of claims 11 to 16, wherein the second channel of the logic gate is formed from the second channel layer.

19. A semiconductor device comprising a plurality of layers of materials, the semiconductor device comprising:a memory cell comprising a plurality of memory component layers configured so as to be operable to perform memory storage, program and erase operations; anda logic gate comprising a plurality of logic component layers configured so as to be operable to perform a logic operation;wherein at least one memory component layer and at least one logic component layer are formed from a common layer of semiconductor material.

20. A semiconductor device comprising a plurality of layers of materials, the semiconductor device comprising:a memory cell comprising:a floating gate for storing charge carriers so as to provide a plurality of occupancy states of the floating gate;a readout channel arranged such that when a read voltage is applied to the memory cell, the electrical resistance of the readout channel depends on the occupancy state of the floating gate;a memory charge reservoir arranged to provide charge carriers to the readout channel, dependent on the occupancy state of the floating gate and a read voltage applied to the memory cell; anda memory back gate for applying a voltage across the memory cell; and a logic gate comprising:a first channel comprising a first current flow path;a second channel comprising a second current flow path;a logic charge reservoir disposed between the first channel and the second channel and arranged to provide charge carriers to the first channel or the second channel dependent on an input voltage applied to the logic gate; anda logic back gate for applying an input voltage to the logic gate, wherein at least one of the readout channel, the memory charge reservoir and the memory back gate are formed from a common layer of semiconductor material as at least one of the first channel, the second channel, the logic charge reservoir and the logic back gate.

21. A method of fabrication of a semiconductor device, the method comprising:forming a plurality of layers of material;forming a memory cell comprising at least some of the layers of the plurality of layers of material, wherein the memory cell comprises a plurality of memory component layers configured so as to be operable to perform memory storage, program and erase operations; andforming a logic gate comprising at least some of the layers of the plurality of layers of material, wherein the logic gate comprises a plurality of logic component layers configured so as to be operable to perform a logic operation,wherein at least one memory component layer and at least one logic component layer are formed from a common layer of semiconductor material.

22. A method of fabrication of a semiconductor device, the method comprising:forming a plurality of layers of material;forming a memory cell comprising at least some of the layers of the plurality of layers of material, wherein the memory cell comprises:a floating gate for storing charge carriers so as to provide a plurality of occupancy states of the floating gate;a readout channel arranged such that when a read voltage is applied to the memory cell, the electrical resistance of the readout channel depends on the occupancy state of the floating gate;a memory charge reservoir arranged to provide charge carriers to the readout channel, dependent on the occupancy state of the floating gate and a read voltage applied to the memory cell; anda memory back gate for applying a voltage across the memory cell; and forming a logic gate comprising at least some of the layers of the plurality of layers of material, wherein the logic gate comprises:a first channel comprising a first current flow path;a second channel comprising a second current flow path;a logic charge reservoir disposed between the first channel and the second channel and arranged to provide charge carriers to the first channel or the second channel dependent on an input voltage applied to the logic gate; anda logic back gate for applying an input voltage to the logic gate, wherein at least one of the readout channel, the memory charge reservoir and the memory back gate are formed from a common layer of semiconductor material as at least one of the first channel, the second channel, the logic charge reservoir and the logic back gate.

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