System and method for pseudo-random number generation

Abstract

Provided are computer-implemented methods, systems, and computer-readable program products for pseudo-random number generation. The method includes providing a neuron comprising a synaptic weight and a current state; receiving, at an integrator block, an initial spike signal; determining, at the integrator block, a state change of the neuron based on the synaptic weight of the neuron and the initial spike signal; determining, at a neuron block, an updated state of the neuron based on the current state of the neuron and the state change of the neuron; if the updated state of the neuron exceeds a predetermined threshold: generating, at the neuron block, a subsequent spike signal; determining, at a function block, a pseudo-random function value based on the subsequent spike signal; and determining, at an output, an output bit based on pseudo-random function value.

Description

SYSTEM AND METHOD FOR PSEUDO-RANDOM NUMBER GENERATIONCROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to US provisional patent application no.63 / 750,608 filed 01 / 28 / 2025 and US provisional patent application no. 63 / 867,976 filed 08 / 21 / 2025, the entire contents of which are hereby incorporated by reference.TECHNICAL FIELD

[0002] The invention relates to the generation of pseudo-random numbers, and in particular, to the generation of pseudo-random numbers using spiking neural networks.BACKGROUND

[0003] A pseudorandom number generator (PRNG), also known as a deterministic random bit generator (DRBG), is a system for generating a sequence of numbers whose properties approximate the properties of sequences of random numbers. The PRNG-generated sequence is not truly random, because it is completely determined by an initial value, called the PRNG's seed (which may include truly random values). Although sequences that are closer to truly random can be generated using hardware random number generators, pseudorandom number generators are important in practice for their speed in number generation and their reproducibility.

[0004] PRNGs power much of modern computing. PRNGs are central in applications such as simulations (e.g. for the Monte Carlo method), electronic games (e.g. for procedural generation), cryptography (e.g. as streaming ciphers for secure communications), and as inputs for generative artificial intelligence. Cryptographic applications require the output not to be predictable from earlier outputs, and moreelaborate algorithms, which do not inherit the linearity of simpler PRNGs, are needed. Most PRNGs operate as a recurrence relation, where an initial state (the seed) is used along with iteratively applied nonlinear operations that produce random looking but deterministic streams of bits.

[0005] Good statistical properties are a central requirement for the output of a PRNG. In general, careful analysis is required to have any confidence that a PRNG generates numbers that are sufficiently close to random to suit the intended use.

[0006] High quality pseudo-random number generation comes with a price. To produce pseudo-random numbers that are statistically indistinguishable from true random numbers, sometimes computational expensive nonlinear operations are required. This makes ultra-low and passively powered random number generation difficult, even with custom made hardware.

[0007] Conventional PRNGs exhibit several technical problems when they cannot provide high quality pseudo-random numbers. These include shorter-than-expected periods for some seed states (such seed states may be called "weak" in this context), lack of uniformity of distribution for large quantities of generated numbers; correlation of successive values; poor dimensional distribution of the output sequence; distances between where certain values occur are distributed differently from those in a random sequence distribution.

[0008] Defects exhibited by flawed PRNGs range from unnoticeable (and unknown) to very obvious. An example was the RANDU random number algorithm used for decades on mainframe computers. It was seriously flawed, but its inadequacy went undetected for a very long time.

[0009] In many fields, research work prior to the 21 st century that relied on random selection or on Monte Carlo simulations, or in other ways relied on PRNGs, were muchless reliable as a result of using poor-quality PRNGs. Even today, caution is sometimes required, as illustrated by the following warning in the International Encyclopedia of Statistical Science (2010).The list of widely used generators that should be discarded is much longer [than the list of good generators]. Do not trust blindly the software vendors. Check the default RNG of your favorite software and be ready to replace it if needed. This last recommendation has been made over and over again over the past 40 years. Perhaps amazingly, it remains as relevant today as it was 40 years ago.

[0010] Unfortunately, the exact quality that can make for good pseudo-random number generation, a complex nonlinearity, is often resource (power) intensive to implement even in application specific dedicated hardware modules.

[0011] There is a need therefore for improved systems and methods of pseudorandom number generation.SUMMARY

[0012] The present embodiments are directed to a neural network architecture, for example, a spiking neural network model of integrate-and-fire neurons. As described in Examples 1 and 2, the neural network architecture may be implemented in ultra-low power FPGAs that may consume less than 5 milliwatts during operation. This FPGA implementation may be configured to operate in this hyperchaotic state, with randomly generated weights.

[0013] When implemented in hardware, the present embodiments provide ultralower power neuromorphic pseudo random number generators (NPRNGs) produce high-quality random numbers as demonstrated by standard random number generation packages (NIST SP-800-22 that correspond to truly random processes with highstatistical similarity. Further, the network structure of the NPRNG leads to a search space (for the parameters that define the NPRNG) that scales like O(2N), which produces resistance to duplication of hardware-based NPRNGs. These embodiments show that the highly unpredictable, excitatory / inhibitory balanced state displayed by neural networks is useful for random-number generation, which may have applications in both computer science, and as a mechanistic explanation for how the brain can generate stochastic dynamics for performing computations.

[0014] The spiking neural network model may be inspired from the human brain. The human brain can generate random dynamics efficiently by occupying a highdimensional and highly unpredictable state based on the balance between excitatory and inhibitory connections. In models of this balanced state, the networks of neurons may display hyperchaos. The brain produces unpredictability far more efficiently than existing computing hardware. Experimentally, it is known that certain brain states are intrinsically high-dimensional and chaotic. This is supported by multiple lines of evidence.

[0015] First, the balance between excitation and inhibition in cortical brain networks is well modeled by a hyperchaotic so-called "balanced state". This asynchronous dynamical state is easy to produce with randomly generated synaptic weights in both recurrent artificial neural networks, and recurrent spiking neural networks. Further, for large networks, the state is asymptotically provable to lead to the neurons behaving as if they were driven by noise. Finally, the entire brain operates on as little as 20 watts, which includes the totality of brain metabolic activities supporting vital neural circuit life functions, and not just computation.

[0016] The embodiments herein provide a spiking neural network model that may be implemented in an FPGA in order to provide a PRNG that can operate using low power and with improved random distribution of random numbers.

[0017] In a first aspect there is provided a computer-implemented method for pseudo-random number generation, comprising: providing, in a memory, a neuron comprising a synaptic weight and a current state; receiving, at an integrator block in communication with the memory, an initial spike signal; determining, at the integrator block, a state change of the neuron based on the synaptic weight of the neuron and the initial spike signal; determining, at a neuron block in communication with the integrator block, an updated state of the neuron based on the current state of the neuron and the state change of the neuron; if the updated state of the neuron exceeds a predetermined threshold: generating, at the neuron block, a subsequent spike signal; determining, at a function block in communication with the neuron block, a pseudorandom function value based on the subsequent spike signal; and determining, at an output block in communication with the function block, an output bit based on pseudorandom function value.

[0018] In one or more embodiments, the determining, at the output block, the output bit may comprise: determining the output bit by converting the pseudo-random function value using a Look-Up Table (LUT) and an index of the neuron corresponding to the subsequent spike signal.

[0019] In one or more embodiments, the method may further comprise: determining, at a synaptic filter block in communication with the integrator block, hi[n + 1] value for the neuron; and determining, at the synaptic filter block, an r n + 1] value for the neuron based on the Zi n + 1] value for the neuron; and wherein the determining, at the neuron block, the updated state of the neuron may be further based on the ri[n + 1] value for the neuron.

[0020] In one or more embodiments, the determining, at the neuron block, the updated state of the neuron may further be based on a bias value.

[0021] In one or more embodiments, the method may further comprise: storing the subsequent spike signal in a Serial-ln-Parallel-Out (SIPO) register.

[0022] In one or more embodiments, the method may further comprise: generating, at a control unit, one or more control signals to operate the integrator block, the neuron block, the function block and the output block.

[0023] In one or more embodiments, the memory may further comprise: an input weight of the neuron; and wherein the method further comprises: determining, at a seed multiplication block in communication with the memory and the neuron block, an initialization value of the neuron based on a seed value and the input weight of the neuron; determining, at the neuron block, an initial state of the neuron by using the initialization value of the neuron as the bias value.

[0024] In one or more embodiments, the method may include: receiving a streaming input signal; and wherein the method may further comprise: determining, at a seed multiplication block in communication with the memory and the neuron block, an initialization value of the neuron based on a the streaming input signal; determining, at the neuron block, an initial state of the neuron by using the initialization value of the neuron as the bias value.

[0025] In one or more embodiments, the streaming input signal may comprise a 1 D time series signal.

[0026] In one or more embodiments, the determining, at the integrator block, the state change of the neuron may further comprise: determining, at a Multi-Layer Temporal (MLT) block of the accumulator block, a converted synaptic weight of the neuron; and determining, at the accumulator block, the state change of the neuron based on the converted synaptic weight of the neuron, and the initial spike signal.

[0027] In one or more embodiments, the memory may further comprise: a Spiking Neural Network (SNN) model comprising the neuron.

[0028] In one or more embodiments, the SNN model may comprise a Leaky-Integrate-and-Fire (LIF) model.

[0029] In one or more embodiments, at least one selected from the group of the control unit, the integrator block, the neuron block, the function block and the output block may be implemented in a Field-Programmable Gate Array (FPGA).

[0030] In a second aspect, there is provided a system for pseudo-random number generation, the system comprising a memory and a processor, the processor configured to provide the method of the embodiments described herein.

[0031] In one or more embodiments, the system may further comprise an encryption application receiving the output bit.

[0032] In one or more embodiments, the system may further comprise a generative artificial intelligence application receiving the output bit.

[0033] In one or more embodiments, the system may further comprise a Monte-Carlo simulation application receiving the output bit.

[0034] In a third aspect, there is provided a computer-readable program product for a processor, the computer-readable program product comprising instructions for the processor that when executed perform the methods described herein.BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Having thus generally described the nature of the invention, reference will now be made to the accompanying drawings, showing by way of illustration example embodiments thereof and in which:

[0036] FIG.1 A — 1 J provides analysis of quantizing balanced spiking neural network models for pseudo-random number generation. FIG. 1A shows a schematic of a spiking neural network with random, but balanced connectivity. Neuron / has both excitatory (+-j=) and inhibitory synaptic (~^=) connections to all other neurons in the network. Allneurons, / = 1,2,... N form excitatory and inhibitory synaptic connections randomly. This connectivity profile may produce an asynchronous, irregular spiking state for well chosen g. FIG. 1B shows the voltage traces (grey / light) and postsynaptic filters (dark) for 5 neurons in a simulated balanced network connected as in FIG. 1 A for 1 second of simulation time. The neurons spike irregularly. FIG. 1C shows a spike raster plot for 1 second of simulation for all N = 256 neurons. FIG 1D shows the inter-spike-interval (ISI) histogram measured for all neurons in a 100 second simulation of a network with N = 256 neurons (from FIGs. 1B - 1C). The ISI distribution has two notable features: no density at 0, and an exponentially decaying tail for larger inter-spike-intervals. The lack of density at 0 is caused by the finite time required for a neuron to generate a spike by integrating a current (the relative refractory period). The distribution of the coefficient of variation (CV) for each of the N = 256 is shown as an inset. A CV of 1 indicates spiking behavior similar to that of a Poisson process. FIG. 1E shows the irregular dynamics exhibited by balanced are chaotic: if a single spike fails to produce a postsynaptic filter (i.e. the spike was “deleted"), the constellation of spikes produced differs. The non-deleted voltage trace is shown in grey, while a spike deletion is performed at 500 ms, for a single neuron. FIG. 1F shows the irregular dynamics exhibited by balanced are also sensitive to single weight flips. For a pair of parameter-matched, parallel simulations, a single weight (W12) was flipped in sign (excitatory to inhibitory). This also leads to a change in the constellation of spikes fired after the weight flip. FIG.1G shows that in a quantized spiking neural network, all of the network parameters are powers of 2 (binary) to allow for a simplified implementation of all network operations in hardware. FIG. 1H shows a 1 -second simulation of a quantized, balanced neuralnetwork, with the voltage traces plotted. The neurons still display irregular spiking, as in FIG. 1 B. A sample of 5 neurons was plotted for a network of A / = 256. FIG. 11 shows a 1 -second raster plot of a quantized, balanced neural network, for all N = 256 neurons. FIG. 1J shows the ISI distribution, and CV distribution for all of the spikes in a quantized, balanced neural network. The network of spiking neurons in FIG. 1A-F may be integrated with a forward Euler integration scheme with a time step of A = 0.05 ms. The parameters can be found in Table 4. The network was simulated with a total period of 100 seconds with random initial conditions where the voltage was uniformly distributed in the interval [vreset, 30] mV. The row sum of the weight matrix was precisely balanced (to 0) with the procedure described in FIG. 4. The interspikeintervals were estimated asISIjk = tjk- tjk-1(Equation 28)

[0037] The ISI distribution was computed with a histogram with a bin size of 0.001 seconds. The coefficient of variation for a neuron was defined as:& ISI ■CVj = — (Equation 29)Where1njJk=2Is the mean ISI for neuron j and°isij = (Equation 30)

[0038] is the standard deviation of the I Si’s for neuron j.

[0039] In the spike failure / deletion experiment (FIG. 1 E), the network was first simulated with an initial seed without deletion. Then a single spike was prevented from eliciting a post-synaptic response by manually deleting the increment in the synaptic filter that would otherwise occur. In the weight-flip experiment, the initially positive W21 was set to W21 after t = 2 seconds for the remainder of the simulation.

[0040] For the quantized network (FIG. 1G-J), the network was simulated identically to FIG. 1, only with dimensionless quantized parameters (Table 4). The integration time-step was also quantized with dt = 2-10. The network was initialized with the identical uniform distribution in vi(t) as in the non-quantized case, and with all other variables as ( / 77(f), (f)) at 0.

[0041] FIGs. 2A - 2I show the use of Balanced Spiking Neural Networks to Generate Random Bit Strings. FIG 2A shows a conventional pseudorandom number generator (PRNG) that uses an input seed s and a recursive / iterative operation, f(x) to generate a bit string. The system operates as a discrete time dynamical system, where the seed acts as the initial state to produce a deterministic, but random appearing stream of bits. FIG. 2B shows a Neuromorphic pseudorandom number generator (NPRNG) which operates differently from a conventional PRNG. Due to hardware limitations, the neural network requires an input signal to initialize the system onto a chaotic trajectory and generate spikes / spike times pseudorandomly. This avoids having to provide an initial state v / (f), (t) for each neuron as an input to the NPRNG. The NPRNG produces a spike raster plot, which is then transformed into a bit stream with some mapping function, T(s) that takes the spike raster plot and transforms it into a bit stream, bo,bi... bn. FIG. 2C shows the NIST-SP800-22 package of statistical tests used to test the null hypothesis that the bit string is generated from a series of independent Bernoulli random variables with bk = 1 with probability p = 1 / 2, and 0 otherwise. The NIST-SP800-22 package consists of 15 tests that test for various aspects of non-randomness in a stream of bits (see below for a detailed discussion).FIG. 2D shows the input signals provided to the NPRNG initialize the system onto different hyperchaotic trajectories, including a 5 Hz sinusoid (top) that is used as the input signal for a quantized network of A / = 256 neurons. The signal is shut off after 1 second (bottom). A randomly generated sequence of square wave pulses is used as a second input signal for the same network as in FIG. 2A. The two differing inputs produce different spike raster plots. FIG. 2E shows a naive transform, b = T(s) for converting the spike raster plot into a bit stream. For a network of N = 2k neurons in base k, each spike index is represented in k-bit binary. The bit string is constructed by using the individual index representation in k-bits sequentially as the spikes are fired (Top). NIST testing reveals this as a poor way of generating pseudo-random bits, largely due to the fact that individual neurons have a refractory period of firing. FIG. 2F shows a dynamic look-up table that produces high-quality pseudorandom bit streams. The Lookup table may consist of a sequence of N randomly generated bits, L( / ) that is hard-coded into the NPRNG. A counter, yndynamically shifts the look-up table based on the indices of the neurons to spike so-far, yn= mod yn-^+Sn, N) where snis the index of the nth spike. For the nth spike, the bit reported is the ynth bit in the lookup table. FIG. 2G shows the coefficient of variation of the inter-spike-interval distribution, as a function of the coupling gq(x-axis) and the decay time, Td (y-axis) of the synapses. The region in the top-corner correspond to the “rate-chaos" regime for the SNN. FIG. 2H shows the average number of NIST tests passed as a function of the coupling gq(x-axis) and the decay time, Td (y-axis) of the synapses. The smaller the mean-CV, the better the performance of the network in generating pseudorandom bit streams (e.g. FIG. 8). FIG. 2I shows a comparison of quantized and non-quantized SNN bitstreams to bitstreams generated by other PRNGs. NIST testing was performed on the quadratic congruential generator, modular exponentiation, a linear congruential generator, Blum-Blum-Shaub, and the Mersenne Twister. The NPRNG, either quantized or nonquantized performed comparably to the latter 3 PRNGs. The networks in FIG. 2D were simulated with identical parameters as the quantized network in FIG. 1. The networkwas simulated for a total of T = 3 time units (dimensionless). The sinusoidal input provided to initialize the network wasc(t) = sin(107rt) (Equation 31)

[0042] for t <= 1. The input c(t) is set to 0 for t > 1. The randomly generated step function consisted of random positive or negative deflection for t = 0.05 time units, followed by 0 deflection at time for 0.05 time units, periodically. These deflections persisted for t < 1 and were shut off after.

[0043] The networks in FIG. 2E-H contained identical parameters as in FIG 2D, however the synchronization signals used to initialize a network were randomly generated with LFSR. Each network was simulated until 115 million spikes were fired, with the last 100 million spikes used in the NIST testing.

[0044] FIGs. 3A - 3D show NPRNGs implemented in hardware with Ultralow Power Field Programmable Gate Arrays (FPGAs). FIG. 3A shows an architecture of the NPRNG. The main microarchitecture (left) comprises a data path and a control unit. The data path unit includes a memory, multiply-accumulate (MAC) block, synaptic and neuron dynamics, function block F[n], and LUT. Synaptic and neuron dynamics are implemented using pipeline designs. Two, five, and five pipeline stages are used for h[n], r[n], and v[n], respectively. Each block includes a computational block and a RAM. The synapse and neuron blocks perform the computations and the results are stored in the RAM for the next time step. FIG. 3B shows the 1 cm x 1 cm FPGA board including two switching regulators and one diode. The FPGA receives a seed via the UART protocol on pin rx and outputs random bits on pin data at the rising edge of clock signal when signal ready is asserted. FIG. 3C current and power consumption for simulations and tests is shown. Higher power usage on the fabricated board is due to extra components and regulator inefficiencies. FIG. 3D illustrates a Monte-Carlo estimate ofTT using the hardware-based NPRNG. A sequence of 2.2 million random numbers coming from the uniform distribution on [0, 1] was generated using the NPRNG. These created 1.1 million ordered pairs, uniformly distributed on [0, 1] (the unit square). The proportion of points that lie below the red line in the inset relative to the total number of points is approximately TT / 4. The final Monte-Carlo estimate of IT using the NPRNG was 3.1413.

[0045] FIG. 4A - 4C shows the behavior of the SNN with binarized weights for varying connection strengths. FIG. 4A shows the voltage traces for 5 neurons samples from four networks with increasing g for a 3 second period. Note that all 4 networks have the same weight matrix, only scaled by the different g value (omegaij = ±-j=)-As g is increased, the neurons fire bursts of varying size / duration. Each network contains N = 256 neurons. FIG. 4B shows the distribution of inter-spike-intervals for the 4 simulated networks from FIG. 4A. For lower values of g, the distributions resemble a Poisson process with a refractory period. Note that the log-ISI count is used on the y-axis. FIG. 4C shows the distribution of the coefficient of variation for the networks in FIGs. 4A - 4B. The mean and standard deviation of the CVs are shown in the title. For more strongly coupled networks g = 0.15, g = 0.2, the mean CV is greater than 1, indicating the burstiness of the neurons in these coupling regimes. The parameters for the neurons and network are identical as in FIG. 1 (non-quantized network with binary weights), with a total simulation time of 100 seconds. The networks were initialized identically to FIG. 1. The ISI distribution / Coefficient of Variation were identically computed as in FIG. 1. The log of the histogram count was plotted for clarity in FIGs.4-5.

[0046] FIG. 5A - 5C shows the behavior of a quantized SNN with binarized weights for varying connection strengths. FIG. 5A shows the voltage traces for 5 neurons from four networks with increasing quantized connection strength gq= 2~nfor a 3 secondperiod. Note that all 4 networks have the same weight matrix, only scaled by the different gq value omegatj = ±-j=)- As gqis increased, the neurons fire bursts ofvarying size / duration. Each network contains N = 256 neurons. All operations in the network are quantized. FIG. 5B shows the distribution of inter-spike-intervals for the 4 simulated networks from FIG. 5A. For lower values of gq, the distributions resemble a Poisson process with a refractory period. Note that the log-ISI count is used on the y-axis. FIG. 5C shows the distribution of the coefficient of variation for the networks in FIG. 5A - 5B. The mean and standard deviation of the CVs are shown in the title. For more strongly coupled networks gq= 0.15, gq= 0.2, the mean CV is greater than 1, indicating the burstiness of the neurons in these coupling regimes. The simulations in FIGs. 5A - 5C are identical to FIG. 4, only with the quantized network parameters of FIG. 1.

[0047] FIGs. 6A - 6B shows synchronizing NPRNGs with input currents. FIG. 6A shows the voltage traces for 5 neurons of the same balanced and quantized network of N = 256 neurons. Voltages for each neuron are initialized at different values for both simulations (grey, black). An input current is applied each neuron, multiplied by an input weight (see below). The input current is non-zero for a short duration of time (250 ms) The input current causes a transient synchronization of the neurons in the network. Eventually, the neuron’s desynchronizes. FIG. 6B is identical to FIG. 6A, only the input current is applied for a longer duration of time (750 ms). The neurons maintain synchrony, despite the hyperchaotic dynamics, in perpetuity. The networks were quantized and simulated for a total of 5 time units, with identical parameters as in FIG.1. The input signal to these networks was on in the interval [0.5, 0.75] (FIG. 6A) or [0.5, 1.25] (FIG. 6B). The synchronization signal was defined asc(t) = 40 (cos (1 Ont)) Equation (32)

[0048] FIGs. 7A - 7B show correlation structure in a Balanced-Quantized Network. FIG. 7A shows the sign of the weights between 5 neurons in a network of A / = 256 neurons with balanced connectivity, and quantized operations. FIG. 7B shows the autocorrelation (diagonal) and cross-correlations (off-diagonal) between neurons in a balanced, quantized network simulated for T = 1000 seconds. The cross-correlations are weak, and scale-like N-1. The autocorrelation functions have prominent peaks in between a refractory period of non-firing centered at 0. The quantized network had identical parameters to FIG. 1. The network was simulated for 100 time units, at which point the cross-correlation between neurons i and j were computed with the MATLAB crosscorr function with a time lag of 100 time steps, corresponding to approximately 0.1 time units for neurons 1 to 5.

[0049] FIG. 8 shows average CV versus the average number of NIST tests passed. The mean CV is inversely correlated with the quality of random numbers generated (p = -0.8863, p«10-4). The average number of NIST tests passed for the networks simulated in Figure 2G-H was computed and correlated against the average coefficient of variation. The average for each simulation was computed as the average CV over all neurons:Lkv =cvj (Equation 33)

[0050] A least squares model was fit to the average number of NIST tests passed as a function of the average CV with the MATLAB polyfit function. For each parameter set, we varied the connection strengths gq= 2_jfor j = 1, 2,..., 16 and varying synaptic time constants TD = 2-i, for i = 1, 2, 8. Using the same random seed for each configuration, we performed 1000 simulations. The system was simulated until it produced the required number of bits / spikes (108) for NIST testing.

[0051] FIGs. 9A - 9C show poorly generated but still excitatory / inhibitory balanced weights. FIG. 9A shows the weight matrix is generated with 50% excitatory and 50% inhibitory connections. Each row is a circular shift of the previous row, one index to the right. FIG. DB shows the spike raster plot for a simulated quantized network of neurons coupled with the weights in FIG. 9A. The network eventually stabilizes on a fixed periodic sequence of spiking. FIG. 9C shows the index of the bit reported in the lookup table. The bits reported in this case also cycle, but at twice the period of the neurons in the network. The quantized network was simulated with identical parameters as in Figure 1. The weight matrix was precisely balanced, but non-randomly generated with a banding structure along the diagonal. In particular, for neuron 1, the first N / 2 weights were positive while the last N / 2 weights were negative (+g / N ). Each subsequent neuron in the network had identical weights as in neuron 1, but with a circular shift operation applied to shift the row matrix 1 entry to the left. The network was simulated for a total of 0.4 time units.

[0052] FIG. 10 shows a system diagram in accordance with one or more embodiments.

[0053] FIG. 11 shows a device diagram in accordance with one or more embodiments.

[0054] FIG. 12 shows a microarchitecture diagram in accordance with one or more embodiments.

[0055] FIG. 13 shows a method diagram in accordance with one or more embodiments.

[0056] FIG. 14 shows Tables 1-4 in accordance with one or more embodiments.

[0057] FIG. 15A - 15D show NPRNGs implemented in hardware with Ultralow Power Field Programmable Gate Arrays (FPGAs). FIG. 15A shows an exemplary architecture of the NPRNG. The main microarchitecture (left) comprises a data path and a control unit. The data path unit includes a memory, multiply-accumulate (MAC) block, synaptic and neuron dynamics, function block F[n], and LUT. Synaptic and neuron dynamics are implemented using pipeline designs. Two, five, and five pipeline stages are used for h[n], r[n], and v[n], respectively. Each block includes a computational block and a RAM. The synapse and neuron blocks perform the computations and the results are stored in the RAM for the next time step. FIG. 15B shows the 1 cm x 1 cm FPGA board including two switching regulators and one diode. The FPGA receives a seed via the UART protocol on pin rx and outputs random bits on pin data at the rising edge of clock signal when signal ready is asserted. FIG. 15C shows a test setup with the device under test, serial interface, oscilloscope for signal capture, and computer for seed transfer and signal monitoring. Sample ready, data, and elk signals are shown in digital format. FIG. 15D shows current and power consumption from simulations and tests. Higher power usage on the fabricated board is due to extra components and regulator inefficiencies.

[0058] FIG. 16 shows a spike raster of a simulated NPRNG with parameter dependent neurons. Network consists of 256 neurons with a balanced matrix that induces high-dimensional chaotic dynamics. (Bottom) Voltage traces of multiple neurons demonstrating parameter dependence of voltage dynamics and spiking thresholds.

[0059] FIG. 17 shows shared sub-weights between 3 NPRNGs. Any two can crossauthenticate each other with a common shared secret unique only to that pair.

[0060] FIG. 18 shows wherein if a node becomes compromised, you no longer accept its authentication signal. It does not compromise the rest of the nodes ability toauthenticate each other as a compromised node cannot pretend to be any other node. The compromised node can be invalidated by means of a majority vote.

[0061] FIG. 19 shows wherein in a covenant, a server authenticates a union of NPRNGs that may or may not be geofenced and time-locked. This authenticates that multiple NPRNGs are at the same place and time. The server can remotely authenticate a valid covenant (in this case three NPRNGs with weights wi, W2 and ws). If one of the three NPRNGs are missing (middle) or one of the three NPRNGs contains incorrect weights W4, the covenant is not valid. (Bottom)DETAILED DESCRIPTION

[0062] Various embodiments will now be described below to provide an example of the claimed subject matter. No example described below limits any claimed subject matter and any claimed subject matter may cover embodiments such as systems or methods that differ from those described below.

[0063] Furthermore, it will be appreciated that for simplicity and clarity of illustration, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the examples described herein. However, it will be understood by those of ordinary skill in the art that the examples described herein may be practiced without these specific details. In other instances, well-known methods, procedures and components have not been described in detail so as not to obscure the examples described herein. Also, the description is not to be considered as limiting the scope of the examples described herein.

[0064] It should also be noted that, as used herein, the wording “and / or” is intended to represent an inclusive-or. That is, “X and / or Y” is intended to mean X or Y or both,for example. As a further example, “X, Y, and / or Z” is intended to mean X or Y or Z or any combination thereof.

[0065] It should be noted that terms of degree such as "substantially", "about" and "approximately" as used herein mean a reasonable amount of deviation of the modified term such that the end result is not significantly changed. These terms of degree may also be construed as including a deviation of the modified term if this deviation would not negate the meaning of the term it modifies.

[0066] Furthermore, the recitation of numerical ranges by endpoints herein includes all numbers and fractions subsumed within that range (e.g., 1 to 5 includes 1, 1.5, 2, 2.75, 3, 3.90, 4, and 5). It is also to be understood that all numbers and fractions thereof are presumed to be modified by the term "about" which means a variation of up to a certain amount of the number to which reference is being made if the end result is not significantly changed.

[0067] Some elements herein may be identified by a part number, which is composed of a base number followed by an alphabetical or subscript-numerical suffix (e.g., 112a, or 112i). Multiple elements herein may be identified by part numbers that share a base number in common and that differ by their suffixes (e.g., 1121, 1122, and 1123). All elements with a common base number may be referred to collectively or generically using the base number without a suffix (e.g., 112).

[0068] The example systems and methods described herein may be implemented in hardware or software, or a combination of both. In some cases, the examples described herein may be implemented, at least in part, by using one or more computer programs, executing on one or more programmable devices comprising at least one processing element, a data storage element (including volatile and nonvolatile memory and / or storage elements), and at least one communication interface.

[0069] These devices may also have at least one input device (e.g., a keyboard, a mouse, a touchscreen, and the like), and at least one output device (e.g., a display screen, a printer, a wireless radio, and the like) depending on the nature of the device. For example, and without limitation, the programmable devices (referred to below as computing devices) may be a server, network appliance, embedded device, computer expansion module, a personal computer, laptop, personal data assistant, cellular telephone, smart-phone device, tablet computer, a wireless device or any other computing device capable of being configured to carry out the methods described herein.

[0070] In some examples, the communication interface may be a network communication interface. In examples in which elements are combined, the communication interface may be a software communication interface, such as those for inter-process communication (IPC). In still other examples, there may be a combination of communication interfaces implemented as hardware, software, and a combination thereof.

[0071] Program code may be applied to input data to perform the functions described herein and to generate output information. The output information is applied to one or more output devices, in known fashion.

[0072] Each program may be implemented in a high-level procedural, declarative, functional or object-oriented programming and / or scripting language, or both, to communicate with a computer system. However, the programs may be implemented in assembly or machine language, if desired. In any case, the language may be a compiled or interpreted language. Each such computer program may be stored on a storage media or a device (e.g., ROM, magnetic disk, optical disc) readable by a general or special purpose programmable computer, for configuring and operating the computer when the storage media or device is read by the computer to perform theprocedures described herein. Examples of the system may also be considered to be implemented as a non-transitory computer-readable storage medium, configured with a computer program, where the storage medium so configured causes a computer to operate in a specific and predefined manner to perform the functions described herein.

[0073] Furthermore, the example system, processes and methods are capable of being distributed in a computer program product comprising a computer readable medium that bears computer usable instructions for one or more processors. The medium may be provided in various forms, including one or more diskettes, compact disks, tapes, chips, wireline transmissions, satellite transmissions, internet transmission or downloads, magnetic and electronic storage media, digital and analog signals, and the like. The computer useable instructions may also be in various forms, including compiled and non-compiled code.

[0074] Various examples of systems, methods and computer programs products are described herein. Modifications and variations may be made to these examples without departing from the scope of the invention, which is limited only by the appended claims. Also, in the various user interfaces illustrated in the figures, it will be understood that the illustrated user interface text and controls are provided as examples only and are not meant to be limiting. Other suitable user interface elements may be used with alternative implementations of the systems and methods described herein.

[0075] Referring first to FIG. 10, there is shown a system diagram 1000 in accordance with one or more embodiments. The system 1000 is for pseudo-random number generation. The system 1000 includes one or more user devices 1002, a network 1004, a server 1006, and optionally an attached PRNG device.

[0076] The pseudo-random number generation may occur at server 1006, or in an alternate embodiment, by the PRNG device 1008 connected to the server 1006.

[0077] The one or more user devices 1002 may be used by a user such as an administrator, or end-user to access a software application (not shown) running on server 1006 over network 1004. The software application (not shown) may be accessed as a web application over network 1004, or alternatively the user device 1002 may download an application and may communicate with server 1006 using an Application Programming Interface (API).

[0078] In one embodiment, the one or more user devices 1002 may access the web application hosted at server 1006 using a browser for encrypted communications with other users, for exchanging cryptocurrency using a crypto currency exchange located on server 1006, for using generative artificial intelligence running on server 1006, for computation research using Monte-Carlo methods, or other purposes. For example, the end-user at device 1002 may login on to a web interface from server 1006 for sending or receiving email.

[0079] The one or more user devices 1002 may be any two-way communication device with capabilities to communicate with other devices. A user device 1002 may be a desktop computer, mobile device, or laptop computer. A user device 1002 may be a mobile device such as mobile devices running the Google® Android® operating system or Apple® iOS® operating system. A user device 1002 may be the personal device of a user or may be a device provided by an employer.

[0080] The software application running on the one or more user devices 1002 may display one or more user interfaces on a display device of the user device. This may include one or more communication interfaces such as chat or email communications.

[0081] Network 1004 may be any network or network components capable of carrying data including the Internet, Ethernet, fiber optics, satellite, mobile, wireless (e.g. Wi-Fi, WiMAX), SS7 signaling network, fixed line, local area network (LAN), widearea network (WAN), a direct point-to-point connection, mobile data networks (e.g., Universal Mobile Telecommunications System (UMTS), 3GPP Long-Term Evolution Advanced (LTE Advanced), Worldwide Interoperability for Microwave Access (WiMAX), etc.) and others, including any combination of these.

[0082] The server 1006 may be in network communication with the user device 1002 over network 1004. The server 1006 may be configured as a physical server, as a virtual machine, or may be configured as a container. The server 1006, may be provided using Amazon Web Services ® (AWS).

[0083] The server 1006 may host a web application or an Application Programming Interface (API) endpoint that the one or more user devices 1002 may interact with via network 1004.

[0084] In one embodiment, the server 1006 may provide the functionality of the PRNG device 1008 (e.g. as provided in FIGs. 12-13) in a virtual machine or using emulation.

[0085] In an alternate embodiment, the server 1006 may be connected to a hardware device implementing the functionality of the PRNG device 1008 (e.g. as provided in FIGs. 12-13). The PRNG device 1008 may be an FPGA-based device. For example, an FPGA device such as an iCE40UP5K device from Lattice Semiconductor may be used.

[0086] Referring next to FIG. 11, there is shown a device diagram 1100 in accordance with one or more embodiments. The device diagram 1100 corresponds to the server 1000 in FIG. 10.

[0087] The device diagram 1100 includes a communication unit 1104, a display unit 1106, a processor unit 1108, a memory unit 1110, an I / O unit 1112 and a power unit 1116.

[0088] The communication unit 1104 can include wired or wireless connection capabilities. The communication unit 1104 can include a radio that communicates using standards such as IEEE 802.11a, 802.11b, 802.11g, or 802.11 n. The communication unit 1104 can be used by the server 1100 to communicate with other devices or computers.

[0089] Communication unit 1104 may communicate with a network, such as network 1004 (see FIG. 10).

[0090] The display 1106 may be an LED or LCD based display and may be a touch sensitive user input device that supports gestures.

[0091] The processor unit 1108 controls the operation of the server 1100. The processor unit 1108 can be any suitable processor, controller or digital signal processor that can provide sufficient processing power depending on the configuration, purposes and requirements of the server 1100 as is known by those skilled in the art. For example, the processor unit 1108 may be a high-performance general processor. In alternative embodiments, the processor unit 1108 can include more than one processor with each processor being configured to perform different dedicated tasks. The processor unit 1108 may include a standard processor, such as an Intel® processor or an AMD® processor. In one embodiment, processor unit 1108 may comprise one or more Graphic Processing Units (GPUs), such as but not limited to a Compute Unified Device Architecture (CUDA)-compatible GPU with 4 GB of VRAM or higher.

[0092] The memory unit 1110 comprises software code for implementing an operating system 1120, programs 1122, and a virtual machine or emulation machine 1126.

[0093] The memory unit 1110 can include RAM, ROM, one or more hard drives, one or more flash drives or some other suitable data storage elements such as disk drives, etc. The memory unit 1110 is used to store an operating system 1120 and programs 1122 as is commonly known by those skilled in the art.

[0094] The I / O unit 1112 can include at least one of a mouse, a keyboard, a touch screen, a thumbwheel, a track-pad, a track-ball, a card-reader, an audio source, a microphone, voice recognition software and the like again depending on the particular implementation of the server 1100. The I / O unit 1112 may include interconnections such as SATA, USB, PCI, or other serial or parallel interfaces as are known. In some cases, some of these components can be integrated with one another.

[0095] In one embodiment, the I / O unit 1112 is connected to and controls a hardware PRNG device such as 1008 (see e.g. FIGs. 10, 12 -13) that provides pseudorandom numbers to the server 1100.

[0096] The power unit 1116 can be any suitable power source that provides power to the server 1100 such as a power adaptor or a rechargeable battery pack depending on the implementation of the server 1400 as is known by those skilled in the art.

[0097] The memory unit includes an operating system 1120, programs 1122, and a virtual machine or emulation machine 1124.

[0098] The operating system 1120 may provide various basic operational processes for the server 1400. For example, the operating system 1420 may be aserver operating system such as Ubuntu® Linux, Microsoft® Windows Server® operating system, or another operating system.

[0099] The programs 1122 include various user programs. They may include several hosted applications delivering services to users over the network, for example, a web application and an API application, and other applications as known.

[0100] In one or more embodiments, the programs 1422 may provide an application such as a web-based application for secure communication, cryptocurrency, or clientserver based application via an API. The application may provide functionality for a user to communicate securely, perform research using Monte-Carlo methods, or to access, exchange or create cryptocurrency.

[0101] In one embodiment, the programs 1122 include an application that may control and communicate with a hardware-based PRNG (e.g. 1008 in FIG. 10) using I / O unit 1112. For example, the programs may include a cryptographic application for secure communication, a cryptocurrency application, or another application that uses pseudo-random numbers. The connected hardware-based PRNG may provide the method of FIGs. 12 - 13.

[0102] In an alternate embodiment, the virtual machine or emulation machine 1124 provides the method of FIGs. 12 - 13 at the server 1100.

[0103] The virtual machine or emulation machine 1124 comprises a data path unit 1126, a control unit 1128, a pipeline h[n] 1130, a pipeline r[n] 1132, and a pipeline v[n] 1134. The virtual machine or emulation machine 1124 may be a software-based FPGA virtualization or emulation platform that may provide the architecture of FIG. 12 and the method of FIG. 13.

[0104] The data path unit 1126 comprises the data path unit 1202 described in FIG.12 and may operate according to the methods in FIG. 13. The data path unit 1126 may be controlled by clock signals generated by the control unit 1128.

[0105] The control unit 1128 comprises the control unit 1232 described in FIG. 12 and may operate according to the methods in FIG. 13.

[0106] The pipeline h[n] 1130 comprises the pipeline h[n] 1252 described in FIG.12 and may operate according to the methods in FIG. 13.

[0107] The pipeline r[n] 1132 comprises the pipeline r[n] 1262 described in FIG. 12 and may operate according to the methods in FIG. 13.

[0108] The pipeline v[n] 1134 comprises the pipeline v[n] 1282 described in FIG.12 and may operate according to the methods in FIG. 13.

[0109] Referring next to FIG. 12, there is shown a microarchitecture diagram 1200 in accordance with one or more embodiments. As noted above, the microarchitecture 1200 may be provided by hardware PRNG device 1008 (see e.g. FIG. 10) or alternatively may be provided by virtual machine or emulation machine 1124 (see e.g. FIG. 11) at server 1100.

[0110] The microarchitecture 1200 includes a data path unit 1202, a control unit 1232, a pipeline h[n] 1252, a pipeline r[n] 1262, and a pipeline v[n] 1282.

[0111] The data path unit 1202 implements a neural network such as a spiking neural network (SNN). The SNN may comprise a leaky-integrate-and-fire network that may provide a balanced excitatory / inhibitory balanced regime. The leaky-integrate- and-fire network may be operated based on the network equations:τ_m v_i(t) = −v_i + ∑(j=1 to N) w_ij r_j(t) + I (Equation 9)r_j(t) = −r_j / τ_d + h_j (Equation 10)h 'hjt) = r + — St<t,fe5(t - t7k) (Equation 11)

[0112] The state of each neuron may be described as the voltage of that neuron Vj(t). The voltage dynamics may be given by Equation 9 where vj(t) is the voltage of the jth neuron. When the neuron reaches a threshold, Vj(t~) = vth, the neuron may fire a spike and may be reset to v(t+) = vreset. The membrane time constant τ_m may control how much the past history of currents arriving to neuron j is filtered in between spikes. The parameter I may act as a bias current to each neuron and may set the background firing rate of the neurons without any synaptic inputs. Each spike fired by a neuron may be filtered by a double exponential synaptic filter, pipeline r(t) 1262 and pipeline h(t) 1252, implemented by Equations (10)-(11 ). Briefly, this may act to filter the k_th spike fired by the j_th neuron at time t_jk with a synaptic current pulse. This pulse may have a rise time given by trand a decay time given by τ_d.

[0113] The weight matrix w_ij 1204 may couple the j_th neuron to the i_th neuron and may be randomly generated to elicit a hyperchaotic state in both recurrent rate and recurrent spiking neural networks. In particular, the conditions on the moments of wy that may elicit this state areE(ω_ij) = 0 (Equation 12)= v (Equation 13)

[0114] where g is sufficiently large. In spiking neural networks, the hyperchaos displayed may occur in two forms depending on the g parameter: rate chaos or Poisson-like irregular spiking. For larger g, the network may enter into the rate chaosregime, with the specific transition point determinable with dynamic mean-field theories.

[0115] To satisfy the constraints in Equations (12)-(13), while simultaneously allowing for simple implementations in neuromorphic hardware, binary values of the weights in the weight matrix 1204 may be used:ω_ij = ±g / √N (Equation 14)

[0116] Further, each neuron i may receive exactly N / 2 positive weights (+g / √N) and N / 2 negative weights (−g / √N), which implies that Equation (12) holds exactly for each neuron i.

[0117] As noted, the microarchitecture 1200 may be implemented in a hardware device such as an FPGA and may be organized into basic hardware blocks that are implemented in programmable logic. The network Equations, (9), (10), and (11), are the main computation units of the NPRNG and their complexity may have an impact on the space or time complexity of the corresponding hardware blocks.

[0118] Simplifying the multiply-accumulate (MAC) operations 1212, as the fundamental but hardware-costly blocks of neural networks, may lead to efficient implementation of the microarchitecture 1200. In particular, the original Equations (9) to (11 ) may be discretized as follows:v_i[n + 1] = v_i[n] + Δ / τ_m (−v_i[n] + r_i[n] + I_i^B[n]) Equation (17)r_i[n + 1] = r_i[n] − Δ(1 / τ_d r_i[n] + h_i[n]) Equation (18)h_i[n + 1] = h_i[n] + Δ(−1 / τ_r h_i[n] + 1 / (τ_r τ_d) Σ(j=1 to N) w_ij δ[n − n_jk]) Equation (19)F[n + 1] = modulo(i_spk + F[n], N) Equation (20)

[0119] where n and A are the time and duration of the time step.

[0120] Microarchitecture 1200 shows the microarchitecture of the NPRNG comprising a data path unit 1202 and a control unit 1232. The data path unit includes a memory 1205 and the computational blocks including MAC operations 1212, h[n] block 1214, r[n] block 1216, v[n] block 1218, F[n] block 1220 and Lookup Table 1222. The memory 1205 may be used to store synaptic weights (w,) 1206 and input weights (w,) 1208.

[0121] The input weight 1208 of a neuron may be concatenated to the end of its synaptic weights 1206. In the initialization phase, the input weight 1208 of a neuron may be multiplied by the seed s[n] at time step n using the Seed Multiplication block 1210 and the result is applied to the block v[n] 1218 as a bias current. The bias current of neuron / in the time step n may be lB[n] = wzs[n]. The input weights 1208 in the memory may be one bit and are scaled by +A and -A using a multiplexer in Seed Multiplication block 1210. Since the initialization phase is temporary, the second multiplexer of Seed Multiplication block 1210 may be used to remove the seed and apply the constant bias current IB during the operational phase.

[0122] During the initialization phase and the operational phase, the synaptic weights 1206 may be multiplied by the spikes. The synaptic weights 1206 may be organized into a structure N x N 1204, each location comprising one bit. To save memory space, one bit may be used for each weight and the MLT blocks 1224 may convert the binary values (0 and 1) to the signed values (-1 and +1) for weight multiplication. There may be N MLT blocks 1224 in parallel that correspond to N weights per neuron. The truth table 1230 of each MLT block 1224 is shown, where spk[ / ] is the spike of the neuron j at the current time-step. The multipliers 1224 maypass the results to the adder tree 1226 which may be used to calculate the termnjkinEquation 19. An adder tree 1226 may be a parallel computingarchitecture that computes the sum of multiple numbers by recursively adding pairs of numbers until a final sum is obtained.

[0123] An MLT block 1224 may refer to a Multi-Layer Temporal block. This block may be designed to handle temporal data more by capturing and processing the timing information of spikes over multiple layers. This may include temporal processing where a MLT block 1224 may be specialized for processing sequences of spikes, which is important for tasks that involve time-dependent data. The MLT block 1224 may have multiple layers, these blocks may consist of several layers that work together to extract and refine temporal features from the input spike trains. The MLT block 1224 may enhance performance. By leveraging multiple layers, MLT blocks 1224 may improve the network's ability to recognize patterns and make predictions based on the timing of spikes.

[0124] The Multi-Layer Temporal (MLT) blocks 1224 in spiking neural networks (SNNs) may handle and process temporal data. This may occur as follows: first temporal feature extraction may occur. MLT blocks 1224 may be structured to capture the timing information of spikes. The MLT blocks 1224 may perform layered processing. These blocks may consist of multiple layers, each designed to process the spike timing information at different levels of abstraction. Early layers may focus on simple temporal features, while deeper layers may capture more complex temporal dependencies. Finally, the MLT blocks 1224 may provide integration and propagation. Within each layer of the MLT block 1224, neurons may integrate incoming spikes over time. The timing of these spikes may influence the neuron's state, and when a certain threshold is reached, the neuron fires and sends spikes to the next layer. This processmay continue through the layers, allowing the network to build a detailed temporal representation of the input data.

[0125] The blocks h[n] 1214, r[n] 1216, v[n] 1218 and f[n] 1220 may be provided in a pipeline in data unit 1202 as shown. When implemented in hardware, to reduce the hardware area, resource sharing may be used in which each block may be used for calculations of all synapses and neurons. The resource sharing may reduce throughput by the order of N - the number of neurons. To compensate for throughput, the pipeline design may be used to implement the synaptic and neuron’s dynamics.

[0126] The pipeline design of the blocks is shown in further detail. The h[n] block 1214 is provided in further detail at h[n] pipeline block 1252. The r[n] block 1216 is provided in further detail at r[n] pipeline block 1262. The v[n] block 1218 is provided in further detail at v[n] pipeline block 1282. The pipeline architecture may break the combinational circuits down into smaller parts to increase the throughput of the system at the cost of a small increase in total circuit latency and consumption of a few registers. The number of stages in h[n] block 1214 may be two, the number of stages in the r[n] block 1216 and v[n] block 1218 may be taken equally (five).

[0127] As noted, the h[n] block 1214 is provided in further detail at h[n] pipeline block 1252. The pipeline h[n] 1252 may determine hj(t) for a neuron j as provided in Equation 9. Alternatively, the pipeline h[n] 1252 may determine n + 1] as described in discretized Equation 19. This may include, at 1252 for example, receiving the output from the adder 1226 as well as control signals from control unit 1232 including an H-R-add signal, a H_We signal, and a H-W-add signal.

[0128] As noted, the r[n] block 1216 is provided in further detail at r[n] pipeline block 1262. The pipeline r[n] 1262 may determine rj(t) for a neuron j as provided in Equation 10. Alternatively, the pipeline r[n] 1262 may determine r n + l] as described indiscretized Equation 18. This may include, at 1262 for example, receiving the output from the h[n] block 1214 (e.g. pipeline h[n] 1252) as well as control signals from control unit 1232 including the RV_R-add signal, the RV-We signal, and the RV-W-add signal.

[0129] In particular, the r[t] block 1216 and h[t] block 1214 may combine to form a double exponential synaptic filter. This may filter the th spike fired by the jth neuron at time fjk with a synaptic current pulse. This pulse may have a rise time given by trand a decay time given by τ_d.

[0130] As noted, the v[n] block 1218 is provided in further detail at v[n] pipeline block 1282. The pipeline v[n] 1282 may determine vi(t) for a neuron i as provided in Equation 9. Alternatively, the pipeline v[n] 1282 may determine v n + 1] as described in discretized Equation 17. This may include, for example, receiving the output from the r[n] block 1216 (e.g. pipeline r[n] 1262) as well as control signals from control unit 1232 including the RV-R-add signal, the RV-We signal, the RV-W-add signal. The v[n] block 1218 may further receive the bias current signal IiB[n]. The v[n] block 1218 may generate a spike signal. The spike signal may be received by the MLT blocks 1224. The spike signal may also be stored in a serial-in-parallel-out (SIPO) register 1228 so that they may be used in the next time step by MLT blocks 1224.

[0131] The F[n] block 1220 may determine F[n + 1] fora neuron based on Equation (20). The F[n] block 1220 may receive the output of v[n] block 1218 (e.g. pipeline v[n] 1282). Block F[n] 1220, may be implemented by a log2( / \ / )-bit integer adder.

[0132] The LUT block 1222 receives the output of the F[n] block 1220 and may determine pseudo random output bits. This may include the LUT block 1222 using an N x 1 Look-Up Table (LUT).

[0133] The microarchitecture 1200 is driven by a clock signal. At each clock cycle, the calculation in each block is computed and fed into the next block. The values ofh[n] block 1214, r[n] block 1216 and v[n] block 1218 may be stored in the memory 1205 to be used in the next time-step. The spikes in each clock cycle may also be stored in a serial-in-parallel-out (SIPO) register 1228 so that they may be used in the next time step by MLT blocks 1224. The index of the neurons generating spikes may be sent to block F[n] 1220, which may be implemented by a log2(N)-bit integer adder. Finally, the values generated by the F[n] block 1220 may be converted to output bits through a Look-Up Table (LUT) 1222, for example an N ×1 Look-Up Table (LUT).

[0134] The control unit 1232 controls the flow of computations in the data path unit 1202 and the h[n] block 1214, r[n] block 1216 and v[n] block 1218. The control unit 1232 may include one or more modular blocks such as a counter module (CM), comprising a counter and two comparators, e.g. counter module 1 1241, counter module 2 1244, counter module 3 1246, counter module 4 1248, counter module 5 1250. The counter 1240 may be enabled through a pulse with the duration of at least one clock cycle at the ON pin and stays enabled until it receives a pulse at the OFF pin in which it is disabled, and the counter value resets to zero. In this block, the counter may be disabled when the counter value reaches / V— 1. The EN pin may be 1 when the counter is enabled.

[0135] Since the read and write operation of the RAMs in the synaptic and neuron blocks may be performed sequentially, the output of the CM1 block 1242 is used to generate the read address (W-R-add) of the weight memory 1205, and may also used as a reference block to trigger the other CM blocks. The A, B, C and D signals may be related to the number of pipeline stages in the h[n] block 1214 (Hstage), r[n] block 1216 and v[n] block 1218 (RVstage), and adder tree 1226 (Astage), i.e. A = Astage−2, B = Astage+Hstage, C = Astage+Hstage−2, D = Astage+Hstage+RVstage

[0136] Neuromorphic Pseudo-Random Number Generators (NPRNGS) consist of spiking neural networks that may be implemented in the following instantiation:Tmvt = -Vi +I + Wijrjlt) (Equation 34)Trrt(t) = -n(t) (Equation 35)Vpeak ~ * ^i^ik) Preset’ ^i(j-ik) ^i^ik) T 1 (Equation 36)

[0137] where tik denotes the ktn spike fired by the itn neuron.

[0138] Each NPRNG may also use a transform T(s,a) of the spike train to a random bit string, where a is a vector of parameters.

[0139] The weights Wij are generated to induce a high-dimensional chaotic state. One such chaotic state is from the so-called balanced regime= 0, E(wiJ') oc Equation (37)

[0140] In one or more embodiments, heterogenous parameters for each neuron may be provided in NPRNG 1200 (e.g._FIG. 16 shows output from a NPRNG network configured with parameter dependent neurons).

[0141] One improvement on the NPRNGs considered previously is to make each NPRNG parameter dependent at the neuronal level. In particular, if we consider equations (34)-(36), each neuron is parameterized by a vector pt= [m, I,r, vpeak, vreset] which corresponds to the membrane time constant, the background current, and the synaptic time constant, respectively.

[0142] In the instantiation of (34)-(36), pi = p for all i, and the neurons are homogeneous. A straightforward change that would increase the parameter complexity would be to have each neuron have slightly different parameters p = [Tm,i> k>Tr> i> vpeakit, vreseti,. In this way, the hyperchaotic state may continue to exist if each neuron’s parameters are slightly different from any other neuron, and an attackerhas to determine what each parameter value is for each neuron. With k bits per parameter, and nPparameters for N neurons, the complexity space for each NPRNG increases multiplicatively by2Nnk

[0143] While this won’t increase the asymptotic order complexity of O(2N) (since the multiplicative term becomes linear in N in the exponent), this would render it more difficult for an attacker to statistically try to predict the NPRNG weights, as the weights alone are no longer sufficient to determine the output of a NPRNG.

[0144] The parameters for each neuron must be determined at the same time. If we consider the equations (34)-(36) with neuronal heterogeneity, thenτm,iv̇i= −vi+ Ii+ ∑j=1Nwijrj(t) (Equation 38)τr,iṙi(t) = −ri(t) (Equation 39)Vpeak.i ~ * ^i^ik) Preset, i> ^i(j-ik) T 1 (Equation 40)To summarize, NPRNGs can be improved by implementing different or slightly different parameters for each neuron This increases the complexity space of a brute-force search while requiring an attacker to determine both the neuronal parameters and the network parameters simultaneously to reproduce the output of an NPRNG. This can substantially increase the parameter complexity of an NPRNG, and increase the frequency of bit generation by forcing the Neuron’s to fire spikes at a faster rate with altered parameters.

[0145] In one or more embodiments, the neurons may be provided with different nonlinearities and heterogeneities. Referring to equations (34)-(36), the complexity ofthe network may be increased by incorporating neuronal heterogeneity at the functional level:τm,iv̇i= Fi(v, βi) + Ii+ ∑j=1Nwijrj(t) (Equation 41)τr,iṙi(t) = −ri(t) (Equation 42)Vpeak.i ~ * ^i^ik) Preset, i> ^i^Xik) T 1 (Equation 43)

[0146] In networks (41 )-(43), each neuron may determine its own nonlinearityFi(vi, βi)

[0147] parameterized by the vector of parameters pi. Each Fi may be a different nonlinearity specified by the index of neuron i, for example

[0148] or alternatively the nonlinearity Fi need not be explicitly parameterized by the index of neuron i, but can be dependent on i. For example, a subset of neurons in set S maybe of the adaptive exponential integrate and fire typeFi(v) = exp(v) − v, i ∈ S

[0149] while another subset in U maybe of the quadratic-integrate-and-fire typeFi(v, βi) = (v − βi)2, i ∈ U

[0150] This again makes it difficult for an attacker to predict the output of an NPRNG as now, every neuron can be any type of nonlinearity in the network, renderingprediction of the output of the NPRNG more difficult as the weight matrix co is not sufficient.

[0151] For example, if there are a total of q possible discrete nonlinearities to choose from, then the complexity space increases multiplicatively withqN

[0152] By incorporating this improvement to the NRPNG design, an attacker would need to determine, neuron by neuron, which nonlinearity the neuron uses to encode the past history of spiking, in addition to determining the network parameters.

[0153] In a related embodiment, different synaptic filters and heterogeneities may be used for the neurons. Similar to the previous embodiment, except applicable to the synaptic filters:τm,iv̇i= Fi(vi, βi) + Ii+ ∑j=1Nwijrj(t) (Equation 44)τr,iṙi(t) = Gi(−ri(t), κi) (Equation 45)Vpeak.i ~ * ^i^ik) Preset, i> ^i(j-ik) ”1” 1 (Equation 46)

[0154] Here, once again, each synaptic filter has its own nonlinearity Gi(n, Ki) parameterized by Ki. The nonlinearities Gi can be chosen as in the prior embodiment.

[0155] In one or more embodiments, higher dimensional neurons may be used. In this improvement, the neuron’s may be higher than 1 -dimensional integrate-and-fire neurons,.τm,iv̇i= Fi(vi, xi, βi) + Ii+ ∑j=1Nwijrj(t) (Equation 47)ẋi= G(xi, vi, ζi) (Equation 48)τr,iṙi(t) = Hi(ri, κi) (Equation 49)Vpeak.i ~ Preset, i> ^i^ik) T 1 (Equation 50)

[0156] In this instantiation, each isolated neuron may consist of the equationsτm,iv̇i= Fi(vi, xi, βi) + Ii(Equation 51)xẋi= Gi(xi, vi, ζi) (Equation 52)

[0157] where Xi is a vector of k-dynamical variables that impact a single neurons dynamics. This endows a single neuron with a much more complex dynamical repertoire. For example, the Izhikevich neuron can be written in a dimensionless form of the above with xi= wi(t), βi= IiFi(vi, xi, βi) = vi2− wi+ Ii(Equation 53)GGi(vi, xi, ζi) = ai(bivi− wi) (Equation 54)

[0158] where Ki = [ai, bi] is the vector of parameters associated with the dynamics of Wi. This can endow a single neuron with more complex dynamics, such as have subthreshold oscillations, displaying a resonance frequency, or displaying spikefrequency adaptation (a non-stationary firing rate). All of these dynamics can increase the dynamical complexity of a coupled network. This renders it more difficult for an attacker to determine the additional parameters / dimensions associated with a neuron.

[0159] In one or more embodiments, parameters may explicitly depend on time,.τm,i(t)v̇i= Fi(vi, xi, βi(t)) + Ii(t) + ∑j=1Nwij(t)rj(t) (Equation 55)ẋi= G(xi, vi, ζi(t)) (Equation 56)(Equation 57)^peafc.iCO—* Preset, i(0< T(Tifc) T(Tifc) T 1 (Equation 58)

[0160] This time dependence can occur, for example, by having the parameters change according to the previous spike history. In one instantiation, a parameter, p(t) increases or decreases by a discrete amount ePi^ik = Pi(tifc) + (~l)le (Equation 59)

[0161] where i denotes the index of the kth spike. In this instantiation, neuron’s are constantly evolving dynamically according to the previous spike history. This requires an attacker to dynamically determine the parameter history, rather than just the parameters associated with each neuron at one point in time in order to predict the output of an NPRNG.

[0162] In one or more embodiments, every synaptic weight Wij(t) may be plastic and may vary with time. This may occur in a possibly activity dependent way, that may or may not respect the balanced network criteriaE(w0) = 0, OC N-1

[0163] in time. The network equations, with all other improvements / modifications are:τm,i(t)v̇i= Fi(vi, xi, βi(t)) + Ii(t) + ∑j=1Nwij(t)rj(t) (Equation 56)ẋi= G(xi, vi, ζi(t)) (Equation 57)(Equation 58)Vpeak.i (t) Vi(tik) Preset, i(t), r^) =ri(tik) + 1 (Equation 59)

[0164] One example of activity dependent weights is spike-timing-dependent plasticity, where a pair of auxiliary variables, rP(t) and r0(t) implement an STDP-based rule:C^j) = ^(^7) + (Equation 60)Wij(tki) = Wkj(tki) + Arp(ttd (Equation 61)

[0165] In one or more embodiments, a true random number generator (NTRNG) may be provided.

[0166] In the final instantiation, we’ll consider NTRNGs either in completely analog or mixed digital / analog implementation. In one instantiation, we may considerTn.iCOA = Xi, + 7i(t) + w0(t)r7(t) + Ai(t) (Equation 62)xt= G(xi, vi, Ct (t)) (Equation 63)Trj(t)r;(t) = HL(rL, Kj(t)) (Equation 64)Vpeak.i (t) Vi(tik) Preset,;(t)< n(A+fe) = + 1 (Equation 65)

[0167] where Ai(t) is a noisy variable that comes from a true-random number generator (TRNG). The noisy signal Ai(t) may be sparsely applied, and not applied to every neuron, or only applied at the initial time step in a simulation. This would create a partially true random number generator which can be used for the creation of rolling codes / one-time-pads.

[0168] In another instantiation, we can consider a network of analog neurons composed of different circuit elementsC = I - 9L(EL- Vd - g^mlh^V, - ENJ - - Ek) - ^=1g^V - EJs n) (Equation 66)dnt_ noo(Vi') - ntdt Tn(Vi)dht_ h^tVi) - hi dt ^h(Vi)drill Mootyd — Mi dt ^m(Vi)dSi ^ooC^i')sidt Ts(Vj)

[0169] where we have a voltage difference for each neuron Vi, along with a capacitor (C) and circuit elements (e.g. resistors / memristors) that collectively implement a Hodgkin-Huxley network. The conductances go for the coupling variables scale similarly to the weights.

[0170] Referring next to FIG. 13, there is shown a method diagram 1300 in accordance with one or more embodiments. The computer-implemented method is for pseudo-random number generation, for example, neuromorphic pseudo-random number generation.

[0171] At 1302, providing, in a memory, a neuron comprising a synaptic weight and a current state.

[0172] At 1304, receiving, at an integrator block in communication with the memory, an initial spike signal.

[0173] At 1306, determining, at the integrator block, a state change of the neuron based on the synaptic weight of the neuron and the initial spike signal.

[0174] At 1308, determining, at a neuron block in communication with the integrator block, an updated state of the neuron based on the current state of the neuron and the state change of the neuron.

[0175] At 1310, if the updated state of the neuron exceeds a predetermined threshold:

[0176] At 1312, generating, at the neuron block, a subsequent spike signal.

[0177] At 1314, determining, at a function block in communication with the neuron block, a pseudo-random function value based on the subsequent spike signal.

[0178] At 1316, determining, at an output block in communication with the function block, an output bit based on pseudo-random function value.

[0179] Optionally, the determining, at the output block, the output bit may include: determining the output bit by converting the pseudo-random function value using a Look-Up Table (LUT) and an index of the neuron corresponding to the subsequent spike signal.

[0180] Optionally, the method may further comprise: determining, at a synaptic filter block in communication with the integrator block, an h_i[n + 1] value for the neuron; and determining, at the synaptic filter block, an r_i[n + 1] value for the neuron based on the h_i[n + 1] value for the neuron; and wherein the determining, at the neuron block, the updated state of the neuron is further based on the r_i[n + 1] value for the neuron.

[0181] Optionally, the determining, at the neuron block, the updated state of the neuron may be further based on a bias value.

[0182] Optionally, the method may further comprise: storing the subsequent spike signal in a Serial-ln-Parallel-Out (SIPO) register.

[0183] Optionally, the method may further comprise: generating, at a control unit, one or more control signals to operate the integrator block, the neuron block, the function block and the output block.

[0184] Optionally, the memory may further comprise: an input weight of the neuron; and wherein the method may further comprises: determining, at a seed multiplication block in communication with the memory and the neuron block, an initialization value of the neuron based on a seed value and the input weight of the neuron; determining, at the neuron block, an initial state of the neuron by using the initialization value of the neuron as the bias value.

[0185] Optionally, the method may further comprise: receiving a streaming input signal; and wherein the method may further comprise: determining, at a seed multiplication block in communication with the memory and the neuron block, an initialization value of the neuron based on a the streaming input signal; determining, at the neuron block, an initial state of the neuron by using the initialization value of the neuron as the bias value.

[0186] Optionally, the streaming input signal may comprise a 1 D time series signal.

[0187] Optionally, the determining, at the integrator block, the state change of the neuron may further comprise: determining, at a Multi-Layer Temporal (MLT) block of the accumulator block, a converted synaptic weight of the neuron; and determining, atthe accumulator block, the state change of the neuron based on the converted synaptic weight of the neuron, and the initial spike signal.

[0188] Optionally, the memory may further comprise: a Spiking Neural Network (SNN) model comprising the neuron.

[0189] Optionally, the SNN model may comprise a Leaky-Integrate-and-Fire (LIF) model.

[0190] Optionally, at least one selected from the group of the control unit, the integrator block, the neuron block, the function block and the output block may be implemented in a Field-Programmable Gate Array (FPGA).EXAMPLESExample 1: Ultra-Low Power Neuromorphic Pseudo-Random Number Generators Based on Balanced NetworksConventional high quality pseudo-random number generation is expensive. To produce pseudo-random numbers that are statistically indistinguishable from true random numbers, computationally expensive nonlinear operations are required. This makes ultra-low and passively powered random number generation difficult, even with custom made hardware. The brain, however, can generate random dynamics efficiently by occupying a high-dimensional and highly unpredictable state based on the balance between excitatory and inhibitory connections. In models of this balanced state, the networks of neurons display hyperchaos. Here, an investigation was performed whether recent advances in extending this high dimensional, hyperchaotic state to models of spiking neural networks allow for ultra low-power neuromorphic pseudorandom number generation with field-programmable gate arrays (FPGAs).A Spiking Neural Network (SNN) model of integrate-and-fire neurons was successfully constructed that could be readily implemented in ultra-low power FPGAs that can operate on low power, e.g. consume less than 5 milliwatts during operation. This network was readily configured to operate in this hyperchaotic state, with randomly generated weights. In hardware, these ultra-lower power neuromorphic pseudo random number generators (NPRNGs) produce high-quality random numbers as demonstrated by standard random number generation packages (NIST SP-800-22 and NIST Entropy) that are statistically indistinguishable from a truly random process. Further, the network structure of the NPRNG leads to a search space that scales like O(2N), which produces resistance to duplication of hardware-based NPRNGs. This work shows that the highly unpredictable, excitatory / inhibitory balanced state displayed by neural networks is useful for random-number generation.Introduction

[0191] Pseudo-random number generators (PRNGs) power much of modern computing. For example, PRNGs are used to solve advanced computational problems with Monte-Carlo methods, as streaming ciphers for secure communications, or in modern contexts, as inputs for generative artificial intelligence. Most PRNGs operate as a recurrence relation, where an initial state (the seed) is used along with iteratively applied nonlinear operations that produce random-looking but deterministic streams of bits. Unfortunately, the exact quality that makes good pseudo-random number generation, a complex nonlinearity, is often resource (power) intensive to implement even in application specific dedicated hardware modules.

[0192] The brain, however, produces unpredictability far more efficiently than existing computing hardware. Experimentally, it is known that certain brain states are intrinsically high-dimensional and chaotic. This is supported by multiple lines of evidence. First, the balance between excitation and inhibition in cortical brain networksis well modeled by a hyperchaotic so-called "balanced state". This asynchronous dynamical state can be produced with randomly generated synaptic weights in both recurrent artificial neural networks, and recurrent spiking neural networks. Further, for large networks, the state is asymptotically provable to lead to the neurons behaving as if they were driven by noise. Finally, the entire brain operates on as little as 20 watts, which includes the totality of brain metabolic activities supporting vital neural circuit life functions, and not just computation. Collectively, the experimental and theoretical evidence both point to the possibility of efficient random number generation based on neuromorphic computing, where aspects of brain computation, such as the firing of spikes by neurons, are emulated in hardware.

[0193] In this example, brain-based computing principles were analyzed to produce ultra-low power, neuromorphic pseudo-random number generators (NPRNGs). First, it is shown that networks of integrate-and-fire neurons under a balanced connectivity regime produce enough entropy through the hyperchaotic regime to act as good PRNGs. This was validated with empirical analysis with large-scale numerical testing for intermediate sized networks of neurons with the National Institute of Standards and Testing (NIST) SP-800-22 testing package for PRNGs. Briefly, NIST SP-800-22 runs 15 separate statistical tests for randomness where the null hypothesis of each test is a completely random bit string. It was found that not all configurations of balanced spiking networks were suitable as PRNGs, with the connectivity strength or "g" parameter critically determining the optimal parameters for pseudo-random number generation. If the connectivity strength is too high, the neural networks transition to rate-chaos regimes, which leads to poor pseudorandom bit streams, while spike-chaos, and the Poisson like firing statistics of neuron’s produce high quality pseudo-random number bit streams that match or exceed other established PRNGs. With this numerical analysis in hand, NPRNGs were implemented in hardware with ultra-low power field-programmable gate arrays. In hardware, it was found that NPRNGs offered high bandwidth pseudo-random number generation while only using 3.2 milliwatts of power.ResultsThe excitatory / inhibitory balanced state in quantized spiking neural networks

[0194] In order to exploit the energy efficiencies of spiking neural to produce a neuromorphic-pseudo-random-number generator (NPRNG), a key network property is required: a source of entropy.

[0195] In cortical brain networks engaged in tasks, or various states of rest, a state of “balance" between excitatory connections and inhibitory connections. To investigate the ability of SNNs as a generator for pseudo-random numbers, Leaky Integrate and Fire (LIF) neurons were considered:Tmvi(t) = ~vi + S7=iwijrj(t) + 1> 1 = 1,2,... N. (Equation 1)

[0196] where v(t) corresponds to the voltage of the itn neuron. Neuron is said to fire a spike when it reaches a threshold v;(f— ) = vth and is reset at v,(f+) = vreSet. The spikes are filtered by a double-exponential post-synaptic filter ( / j(t)) for each neuron and then multiplied by the weight matrix wto form a network. The LIF model was chosen as it is straightforward to apply in neuromorphic hardware. The background current I drives an isolated neuron, v(t) to fire spikes (Materials and Methods). Depending on the coupling weights, w, the SNN in equation (1) can display complex dynamics. One well studied dynamical regime is the so-called balanced state, where the excitatory weights (wy > 0) are “balanced" by the inhibitory weights (W < 0) by imposing the following conditions on the first two moments:E oc (Equation 2)

[0197] The parameter regime in Equation 2 is possibly one of the most well-studied coupling regimes for recurrent neural networks, as it produces hyperchaotic dynamics where the neurons asymptotically (Nbehave as if they were uncoupled and independently driven by a filtered noise process. More recently, this regime has been validated and analyzed in recurrent SNNs.

[0198] Here, the potential for balanced networks (Equation 1)-(Equation 2) was investigated as a basis for ultra-low power, neuromorphic pseudo-random number generators (NPRNGs), with the caveat that the networks considered may be modified to be implementable in hardware.

[0199] The first such modification considered are discrete weight values:coij = +-j= (Equation 3)

[0200] where g is the overall coupling strength of the connections (FIG. 1A). This modification reduces the storage required for implementation on chip. To investigate if binarizing the weights would impact the balanced state dynamics, a series of simulations were run with a network consisting of N = 256 neurons. It was confirmed that the irregular voltage dynamics (FIG. 1A) irregular spiking and voltage dynamics (FIG. 1B), are still present, and the neurons fire spikes with a distribution of times that is similar to a Poisson process with a refractory period (FIG. 1D), and have a mean coefficient of variation of μcv= 0.99 (N = 256, σcv= 0.25, Materials and Methods), indicating Poisson like-spiking statistics. Further, for larger values of g, an SNN coupled with binarized weights still displays a transition to “rate-chaos" (FIG. 4).

[0201] Further, the Poisson spiking state was confirmed to be chaotic by deleting a single spikes post-synaptic filter (FIG. 1E) which leads to a completely different constellation of spikes, as compared to a non-deleted, parameter and initial state matched simulation. The SNN with binarized weights also displays a sensitivity to theunderlying parameters, like any chaotic system, where the flip of a sign of a single weight W21 leads to a different chaotic trajectory (FIG. 1 F).

[0202] Next, we considered quantizing all of the network parameters for a simplified implementation in hardware. Quantization entails finding parameters that are all of the form p = ±2kwhere k is an integer (FIG. 1 G). This includes the binary coupling strength g. Quantization is critical to efficient neuromorphic implementation of the SNN as it converts all operations required to emulate a spiking neural network in hardware to the movements of bits. The quantized network still displays irregular spiking dynamics (FIGs. 1 H-11), with the neurons displays similar Poisson-like spiking behavior as in the non-quantized network (FIG. 1 J), although with a smaller coefficient of variation (JJCV = 0.68, Ocv = 0.16, N = 256). The quantized network also displays a transition to “rate chaos" as the coupling strength is varied (FIG. 4). To summarize, the key modifications required to implement a balanced network into hardware for neuromorphic randomnumber generation do not impact the overall behaviors of the balanced state.Creating and Testing Random Bit Streams with Balanced SNNs

[0203] With some of the primary hurdles for efficient hardware implementation cleared, the mechanisms for translating the irregular behavior of the SNN into a bit string were considered. The ideal pseudo-random number generator has as its nth, output a bit, bn. A quality pseudo-random number generator will have each bit appear as if its drawn from an unbiased Bernoulli random-variable:with probability |(Equation 4)with probability |

[0204] with bj and bk being statistically independent for any j and k. In practice, these two constraints are difficult to achieve with any pseudo-random number generator.

[0205] A conventional pseudorandom number generator (PRNG) operates by using an initial input, or seed, s = xo and some recursive operation, xn+1= f(xn) to produce pseudorandom sequences of bits (FIG. 2A). For example, the Blum-Blum-Shub (BBS) PRNG uses the nonlinear recurrence relationshipxn+1= mod M (Equation 5)

[0206] where M = p · q is the product of two primes. When converted into bits, xn+1produces a pseudorandom bit string.

[0207] A neuromorphic pseudorandom number generator, NPRNG, has two key differences with a conventional PRNG (FIG. 2B). First, an NPRNG requires an initial state for each voltage, vi(t) and synaptic filter ri(t), rather than an integer seed. This produces challenges in hardware implementation as there are bandwidth limitations that can occur when using ultralow-power chips. However, a 1D time series can also be used as an input signal to initialize an NPRNG onto a chaotic spiking trajectory (FIG.2B) and serve as a seed. The second difference between an NPRNG and a conventional PRNG is that there are multiple possible ways of transforming the spikeraster plot, which is labelled with the n x 2 matrix s, where sn1= jn, the index of the neuron that fired the jthspike, and sn2= tn, the time at which the jth spike is fired.

[0208] With these two key differences in mind, a series of 15 statistical tests developed by the National Institute of Standards and Technology (NIST, NIST-SP-800-22) were used to determine the quality of pseudorandom number bit strings generated by NPRNGs (FIG. 2C). These tests determine if a bit string is indistinguishable from an independent Bernoulli random variable, in various measures (e.g. repetition ofsequences, frequency of bits, etc.). Here, the average of number of tests passed is considered based on 1000 randomly generated bit strings, each with 1,000,000 bits.

[0209] With a metric for PRNG quality defined, the use of input signals, rather than predefined initial states as seeds was investigated. These input signals avoid requiring an NPRNG to store an O(N x 2) initial seed vector and thus lead to more efficient hardware implementations by allowing a streaming input signal to initialize the network onto a chaotic trajectory (FIG. 2D).

[0210] The input signal is applied to each neuron with a binary weight matrixτmvi(t) = −vi+ ∑Nj=1wijrj(t) + I + wiinc(t), i = 1,2,... N. (Equation 6)

[0211] where c(t) is the input signal, and wiin= ±1 is a binary, randomly generated weight for each neuron. With this implementation, only O(N) bits are required for implementation in hardware. Two separate input signals ci(t) and C2(t) can cause a network with the same initial conditions vi(0) = vreset, ri(0) = 0 to produce two different chaotic trajectories, and therefore, bit strings. Further, inputs can also be used to synchronize two NPRNGs that are on initially different chaotic trajectories, provided that c(t) is of sufficiently long duration to wash out the memory (FIG. 6).

[0212] With a mechanism for seeding an NPRNG determined, how to generate bits with the spike raster through some transform, T(s) was investigated. One naive transform would be to take the nth spike index for a network of 2kneurons and convert it into a binary representation with k-bits, and group the resulting nk bits together into a bitstream. This turns out to produce bitstreams that are easily detectable by NIST as be different from the independent Bernoulli random bitstream hypothesis. In particular, this occurs as a neuron in even a balanced network can only fire a spike so fast, leading to a refractory period (FIG. 7). This produces bit streams that appear non-random, asthe bits generated by a neurons index inherit the neuron’s refractory, which does not occur in a truly random bit stream.

[0213] To produce higher quality PRNGs, we considered a transform T(s) that would take into account the refractory period of firing. First, a counter variable ynis computed for the nth spike:yn= mod(yn-1+ sn, N) (Equation 7)

[0214] This variable accumulates and takes into the previous history of spiking by the entire network. Next, a static Lookup table L(i), i = 1,2,… N was generated which corresponds to N randomly generated bits. The nth reported bit is then given bybn= L(yn) (Equation 8)

[0215] The bits in the lookup table are static, and only ever generated once. This solution is simple to implement and a memory efficient transform T(s) with a single randomly generated weight matrix, with 65,536 separate inputs (Materials and Methods), with each input generating a bitstream consisting of 109bits. These 109bits were divided into 1000 individual streams of 106bits each and were tested with NIST (FIG. 2F). Approximately 50% of all initial inputs lead to bitstreams that passed every NIST test, with another 40% passing 14 / 15 NIST tests, and only a small number of bitstreams failing passing 11-13 of 15 tests.

[0216] Next, the impact of the individual weight matrix was considered. Separate weight matrices were generated, and a bitstream of 109bits for each weight was produced (FIG. 2F). The population of weights on average produced slightly poorer quality bit streams than the single randomly generated weights which were considered, indicating some degree of impact on the specific weight matrix generated for an NPRNG. However, the overall distribution of passed NIST tests is qualitatively similaracross weights, with no generated weight matrix having failed less than 10 tests, and approximately half of all weights having passed all 15 NIST tests. It is possible to generate a non-random, but still balanced weight matrix that will generate poor quality random bitstreams (FIG. 8).

[0217] Next, it was sought to determine how the statistics of spiking impacted the quality of pseudorandom bit generation. Simulated networks of varying connection strengths, gq= 2−jfor j = 1,2,…16 and varying synaptic time constants τD= 2−i, for i = 1,2,… 8, and computed the mean coefficient of variation of the spike rasters generated (Materials and Methods, FIG. 1G). Over this parameter range, it was identified a coexisting between non-firing (small gq, TD), rate chaos (larger gq) and Poisson-like spiking (smaller gq) where the CVs are μcv< 5. Next, for the same parameter regimes the average number of NIST tests passed (FIG. 2H) was computed. In the rate-chaos regime, where the coefficient of variation is high, poorer quality bitstreams are produced (FIG. 2H). The average number of NIST tests passed was also strongly negatively correlated (ρ = −0.8863, p≪10−4), with the average coefficient of variation μcv(FIG. 8). Collectively, these results imply that the Poisson-like spiking regime is superior to the rate-chaos regime for generating random bitstreams, when a look-up table is used for T(s). Finally, to place these results into context, both quantized and non-quantized NPRNGs were compared to other PRNGs.

[0218] 1000 bitstreams of 106bits for each stream were generated with: the quadratic congruential PRNG, the modular exponentiation PRNG, the linear congruential PRNG, the Blum-Blum-Shub PRNG, and the Mersenne Twister. The quadratic congruential generator and modular exponentiation performed the worst, with no bit streams generated passing all 15 NIST tests, while the LCG, BBS, MT, and the two NPRNGs all performed comparably, with » 50% of all bitstreams generated passing all 15 NIST tests, an additional » 40% passing 14 NIST tests, and the remaining 10% of bit streams passing 10 or more tests. These results show that balanced spikingnetworks can serve as good PRNGs provided that the coupling strength between neurons is not too strong, and the neurons operate in the Poisson-like spiking regime NPRNGs in hardware run on less than 10 milliwatts of power

[0219] To showcase the energy efficiency of NPRNG, the digital design approach was exploited to realize a compact and low-power FPGA-based neuromorphic device. To meet the power consumption requirement (» 10 mW), an ultra low power FPGA, iCE40UP5K from Lattice Semiconductor, was selected which dictated the area requirement (the available FPGA resources). In the microarchitecture design, multiple techniques were applied to meet the area (FPGA resources) and performance (throughput) requirements (FIG. 15A). Concerning the available FPGA’s resources, the microarchitecture used shared hardware blocks for the synaptic dynamics (h[n] and r[n]) and LIF neurons (v[n]) to meet the area requirements. Spatial parallelism was used for multiply-accumulate (MAC) block to improve the throughput by performing the weight multiplications of each neuron in one clock cycle. The temporal parallelism (pipeline design) allowed an overall improvement of the throughput where in each clock cycle the output of one neuron is calculated. The full pipeline design also simplified the control unit where it was designed based on a modular counter-based block. The space complexity of the microarchitecture was determined by the growth of the FPGA’s resource usage when the number of neurons N increases. The time complexity was considered as increasing the number of clock per time-step. In each time-step the calculations for the discrete time A is performed. Table 1 summarizes the space and time complexity for each block. The overall complexity of space and time of the microarchitecture are O(n2) and O(n), respectively.

[0220] Due to the compactness of the FPGA and built-in components such as an oscillator and non-volatile configuration memory (NVCM), the fabricated board size was 1 cm x 1 cm (FIG. 15B). The FPGA only needed regulators for its full functionality.

[0221] The test setup included the neuromorphic device (device under test), an oscilloscope, a computer, and an interface device.

[0222] The interface protocols and signals are arbitrary and depend on the host interface. In this test setup, the serial protocol was used to send a seed from computer to the neuromorphic device (FIG. 15C). The generated random bits were captured by monitoring three signals of ready, data, and elk. The signal data provides a random bit at the rising edge of elk when ready is asserted.

[0223] According to the power calculator of Radiant Power Estimator, the power consumption of the FPGA can be as low as 3.24 mW at 6MHz (FIG. 15D). The fabricated device used a 12MHz internal oscillator where the simulated power consumption of the FPGA was 5.7 mW and the measured power consumption of the fabricated device was 12.9mW in the fully operational phase.

[0224] A comparison of the FPGA implementation of NPRNG and other PRNGs is provided in Table 2. As a complex dynamical system, NPRNG uses more resources while the absolute power consumption can be as low as 3.2 mW.Discussion

[0225] The ability to generate bit streams that are indistinguishable from truly random bit streams is difficult to achieve in practice. Some existing PRNGs are not provably random, and will produce poor pseudo-random bit streams, while others require substantial computational resources to implement in hardware. Here, we show that provable random spiking neural networks connected in a balanced configuration produce high-quality random bit streams that pass all 15 tests for the NIST SP800-22 package at similar or higher rates to established PRNGs. The NPRNGs considered here are also readily implemented in hardware, using as little as 3 milliwatts of power to generate a bit stream at a rate of 30 kilobits per second. NPRNGs also have a keyadvantage over other PRNGs: the number of unique NPRNGs grows exponentially with network size. For a network of N neurons, at least 2N²unique NPRNGs can be produced, which all operate differently due to the hyperchaotic dynamical state that an Excitatory / inhi bitory balanced network occupies.

[0226] This large parameter complexity space yields one important advantage to NPRNGs: they are more resistant to side channel attacks, where attackers glean the secret key that some PRNGs use through the leakage of information in hardware. For example, cryptographically secure PRNGs based on the advanced encryption standard are prone to these attacks where the secret key is determined by measuring the electrical draw of a chip, and converting deviations in the power amplitude to bits, thereby determining the secret key. Interestingly, side channel attacks have a kind of parallel in neuroscience: the local field potential, which corresponds to the average activity of a local population of neurons. A side channel attack in this context would imply that one could invert the LFP for the circuit that generated it, which thus far, has eluded neuroscientists.

[0227] The most immediate follow up on our work would be the construction of neuromorphic true random number generators (NTRNGs). True random number generators are an ongoing topic of study due to their widespread use in cryptographic applications as the mechanism for generating one-time-pads. While there are many instantiations of a putative NTRNG, a straightforward theoretical implementation would be of a Hodgkin-Huxley or conductance-based neuron model. The core functioning of spiking Hodgkin-Huxley networks would be basic electrical circuit elements: resistors, capacitors, and recently created memristors that would implement the gates on the voltage-gated ion channels. Synaptic connections could also be implemented with memristors, based on voltage-gated models of synaptic dynamics proposed byDestexhe. Further, the excitatory / inhibitory balanced state has also been confirmed to exist albeit with alternate scaling in networks with conductance-based coupling.MethodsSpiking Neural Networks and the Excitatory / inhibitory Balanced State

[0228] The network equations of a leaky-integrate-and-fire network of spiking neurons in the excitatory / inhibitory balanced regime are given byτmv̇i= −vi+ I + 1 (Equation 9)rj(t) = −rj / τd+ hj(Equation 10)h 'hj(t) = hj / τr+ (1 / τdτr)∑t<tδ(t − tjk) (Equation 11)The voltage dynamics are given by Equation 9 where vj(t) is the voltage of the jth neuron. When the neuron reaches a threshold, vj(t−) = vth, it is said to fire a spike and is reset to v(t+) = vreset. The membrane time constant τmcontrols how much the past history of currents arriving to neuron j is filtered in between spikes. The parameter I acts as a bias current to each neuron and sets the background firing rate of the neurons without any synaptic inputs. Every spike fired by a neuron is filtered by a double exponential synaptic filter, i t), implemented by Equations (10)-(11 ). Briefly, this acts to filter the kth spike fired by the jth neuron at time tjk with a synaptic current pulse. This pulse has a rise time given by trand a decay time given by τ_d.

[0229] The weight matrix Wy couples the jth neuron to the ith neuron and is randomly generated to elicit a well known, hyperchaotic state in both recurrent rate and recurrent spiking neural networks. In particular, the conditions on the moments of Wy that may elicit this state areE(ωij) = 0 (Equation 12)(Equation 13)

[0230] where g is sufficiently large. In spiking neural networks, the hyperchaos displayed can occur in two forms depending on the g parameter: rate chaos or Poisson-like irregular spiking. For larger g, the network enters into the rate chaos regime, with the specific transition point determinable with dynamic mean-field theories.

[0231] To satisfy the constraints in Equations (12)-(13), while simultaneously allowing for simple implementations in neuromorphic hardware, we use binary values of the weighs:ωij= ±g / √N (Equation 14)

[0232] Further, each neuron / receives exactly N / 2 positive weights (+g / √N) and N / 2 negative weights (−g / √N), which implies that Equation (12) holds exactly for each neuron / .Generating Uniform Random Bit Sequences from a Spiking Neural NetworkThe NIST-SP-800-22 Package for Testing PRNGs

[0233] NIST SP 800-22 is a set of statistical tests designed to evaluate the randomness of binary sequences generated by random number generators (RNGs). The document, titled " A Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic Applications," outlines a suite of tests to ensure that a RNG produces sequences that exhibit randomness properties critical for cryptographic applications. The goal of NIST SP 800-22 is to provide a standardized set of tests to assess whether a random number generator (RNG) is suitable for cryptographic use.Since many cryptographic functions rely on randomness (e.g., for key generation, initialization vectors, and nonces), ensuring the quality of randomness is critical.

[0234] NIST SP 800-22 includes 15 tests, each designed to evaluate different aspects of randomness in a binary sequence. The tests look for patterns or biases that could indicate the sequence is truly random or not. Here’s a summary of these tests:1. Frequency (Monobit) Test: The purpose of the test is to determine whether the numbers of 0’s and 1’s in the sequence are approximately equal. The test computes a p-value based on how close this count is to 50% of the total length. If the p-value is greater than a threshold (commonly 0.01 ), the sequence is considered to pass this test.2. Frequency Test within a Block: The sequence is divided into M blocks of equal size, and for each block the proportion of 1’s is computed, analyzing the randomness at the block level. The test produces a p-value for each block, if all or most of the p-values are above the threshold, the sequence passes.3. Runs Test: This test counts the runs (consecutive sequences of identical bits) of 1’s and 0’s in the sequence and compares them with the expected number for a truly random sequence. If the number of runs is within the expected range (based on the length of the sequence and the frequency of 1’s and 0’s), the sequence passes.4. Test for Longest Run of Ones in a Block: The sequence is divided into blocks, the longest run of 1’s in each block is determined and compared with the expected distribution. If the p-value from the statistical analysis of the longest runs is above the threshold, the test is passed.5. Binary Matrix Rank Test: The sequence is divided into blocks and each block is used to form a matrix of fixed size (e.g., 32x32). The rank of each matrix is computed, andthe ranks are statistically analyzed. If the frequency of full rank matrices falls within an expected range, then the sequence passes the test.6. Discrete Fourier Transform (Spectral) Test: The sequence is first transformed into the frequency domain using DFT. The purpose of this test is to find periodic patterns indicating the potential non-randomness, resulting in a low p-value. If the p-value from the spectral analysis is above the threshold, the sequence passes.7. Non-overlapping Template Matching Test: The sequence is scanned for specific bit patterns that are repeated more frequently than expected, using a specific template (e.g., 0000 or 1111 ). The test then analyzes how many times this pattern occurs without overlapping. The frequency of the pattern’s appearance is compared to the expected number. If the p-value is high enough, the test is passed.8. Overlapping Template Matching Test: This is similar to the Non-overlapping test, but allows for the same bit to be part of multiple occurrences of the pattern. The distribution of the number of overlapping occurrences is compared to the expected distribution. If they are close enough, the sequence passes the test.9. Maurer’s “Universal Statistical” Test: Random sequence in general is not compressible. This test measures the compressibility of the sequence. To measure the overall entropy of the sequence, the sequence is processed to determine how predictable each bit is, based on the previous bits. A p-value is computed from the test statistics. If this is greater than the threshold, the sequence passes.10. Linear Complexity Test: The sequence here is divided into blocks and the linear complexity of each block is calculated. The linear complexity measures how complex the sequence is in generating the block. If the linear complexity is in line with expected randomness, the sequence passes.11. Serial Test: The test analyzes the frequency of all possible bit patterns of length m, and compares this with the expected distribution. If the p-values of the bit patterns are greater than the threshold, the sequence passes.12. Approximate Entropy Test: The purpose of this test is to measure the entropy (randomness) in the sequence by calculating the frequency of all possible bit patterns of length m and m+1, then comparing the frequencies to measure how unpredictable the next bit is given the previous bits. If the entropy is within the expected range, the sequence passes.13. Cumulative Sums (Cusum) Test: Here the sequence is treated as a random walk, to detect deviations from the expected number of 0’s and 1’s in the sequence. The cumulative sum is calculated and if the sum remains within the expected bounds, the sequence passes.14. Random Excursions Test: This test analyses the number and distribution of excursions (move away from 0) in a random walk defined by the sequence. The distribution of excursions is compared to the expected distribution. If the match is sufficiently close, the sequence passes.15. Random Excursions Variant Test: This test is a detailed version of Random Excursion test, where it measures how many times each integer is revisited, not just how often it is reached. If the p-values associated with revisits to each state are within the expected range, the sequence passes.Pseudo Random Numbers

[0235] A sequence of numbers Xncould be called random if Xn+i cannot be predicted from X-i, X2, Xn. Thus, the very definition is clearly non-constructive in nature. In other words, it is not possible to generate a random number sequence usinga well-defined process. But sequences of random numbers are indispensable in any process which uses statistical tools. Thus, we introduce the concept of pseudo-random number sequences. By definition a pseudo-random number sequence Xnis generated algorithmically and is expected to follow the desired probability distribution.

[0236] To illustrate a simple example, we may mention a middle square method of Von Neumann which follows a very simple pattern. To attempt to generate 32-bit pseudorandom integer, we start with a 32 bit integer, square it and return the middle 32-bit integer. By iteration we get a sequence, which unfortunately is not a pseudorandom sequence as it does not follow the uniform distribution law.0.0.7 Generating Uniform Pseudorandom Numbers

[0237] It suffices to consider methods to generate pseudorandom sequence following a uniform distribution for any other distribution, one maps the uniformly distributed pseudorandom sequence using the corresponding probability distribution function.

[0238] In usual practice, one fixes a bound M and starts with a seed x-i, and the algorithm generates X2, X3,... following a mathematical procedure with all x is lying between 0 and M with the constraint that the sequence generated follows uniform distribution.

[0239] Next an example is given of such a generator - Linear Cogruential Generator which uses modular arithmetic. A large positive integer m is fixed. Choose a and c, where 0 < a < m and 0 < c < m. Start with the random seed value x-i, then xn+1is by:xn+i= (axn+ c)mod m (Equation 15)

[0240] Under suitable conditions on m, a, and c, this procedure gives rise to pseudorandom number sequence with uniform distribution. A classic instance is due to Park and Miller with values m = 231 -1, a = 16807 and c = 0.

[0241] Other examples for generating uniform Pseudorandom numbers are Mersenne Twisters, Xorshift and Variants, Counter based generators, etc.0.0.2 Chaotic maps

[0242] Another technique to generate PRNG is to use Chaotic maps. A typical class of Chaotic maps is given by the iterative sequence x, +1 = / x(1-x). Here xi is the seed and r is a real positive number less than 4 (to ensure that all the x' are between 0 and 1). Intuitively, a map is chaotic, if the iterates do not converge, i.e., they don’t exhibit any periodic behavior, which leads to the chaotic behavior. It can be shown that for suitable values of r and the seed xi the chaotic map results in generating pseudorandom numbers between 0 and 1 following uniform distribution.

[0243] Finally, we would like to mention the use of "normal numbers" to generate pseudorandom number integer sequences. A real number 0 < x < 1 is said to be normal if each digit between 0 and 9 occurs in its decimal expansion with uniform distribution.

[0244] Intuitively, if N is a very large positive integer, then, each digit occurs with probability approximately 1 / / V in the first N digits. It can be shown that most real numbers are normal, even though for specific real numbers like0.1 Testing Pseudorandom Generators

[0245] Testing pseudorandom number generators is not a straightforward process. In generally it requires a common framework to evaluate those algorithms. In this section, we shall discuss some of the classical and modem test suits used for testing pseudorandom number generators.0.1.1 Classical Randomness Tests

[0246] It is essential to subject any pseudorandom generator through statistical test for verifying that the algorithm is robust. For example, (x)2test is a standard test for testing fitness of the given set of observations. Given a set of n measurements x;, / = 1,2,...,n, (x)2is defined as:(Observed value-Expecte value)2(z)2= (Equation 16)Expected value

[0247] Intuitively (x)2measures the sum of the normalized errors occurring between the experimental value and the theoretical values as per the probability distribution. This value of (x)2along with a parameter called degrees of freedom is tested against a table value. The decision is made whether to accept the hypothesis or reject it. The hypothesis in this context is, the pseudorandomness of the observations x, following the uniform distribution.

[0248] Another classical randomness test is Kolmogorov-Smirov |(KS) test. It is an efficient nonparametric test to determine whether two samples are significantly different from each other. In other words, the Kolmogorov-Smirnov statistic measures or quantifies a distance between the empirical distribution function of the sample and the cumulative distribution function of the reference distribution, or between the empirical distribution functions of two samples.

[0249] There are other tests of the same nature as KS test: Shapiro-Wilk test and the Anderson-Darling test, which are considered more powerful than KS test. Other examples of classical statistical test are Serial test, Gap test, Permutation test, etc.

[0250] Customized software packages to testing pseudorandomness using the above-mentioned tests have been designed. For example, Dieharderand TestUOl are commonly in use.0.2 Cryptographically Secure Pseudorandom Number Generators

[0251] The Pseudorandom number generators mentioned in the previous section are insecure. This means that their operation makes no attempt to prevent an attacker from learning about the state of the generator in order to predict future output or learn earlier outputs. In this section some of the pseudorandom number generators that are considered "cryptographically secure" are discussed. A CSPRNG is a random number generator that passes the next-bit test: where an attacker’s knowledge of the state of the generator at time t is no guarantee for knowing the state at any previous time. Mathematically, the next-bit test is passed if, for bit / , there is no polynomial time algorithm operating on all previous bits, predicting the bit / with any probability better than 50%.Neuromorphic Microarchitecture of the NPRNGs implemented on Field Programmable Gate Arrays

[0252] The design process of digital systems involves in microarchitecture design, which is the organization of the basic hardware blocks. Since the network Equations, (9), (10), and (11), are translated to the main computation units, their complexity has a significant impact on the space or time complexity of the corresponding hardware blocks. Simplifying the multiply-accumulate (MAC) operations, as the fundamental but hardware-costly blocks of neural networks, will lead to efficient implementation of the microarchitecture. Specifically, the original equations were modified by moving multiplications in Equations (9) to (11) due to the linearity of the synaptic equations where the discritized equations are:v_i[n + 1] = v_i[n] + Δ / τ_m (−v_i[n] + r_i[n] + I_i^B[n]) Equation (17)rL[n + 1] = r([n] — A(— r([n] + hjn]) Equation (18)ht[n + 1] = ^i[«] +A(^i[«] + ^iy=iwijsln~n / J) Equation (19)F[n + 1] = modulo(i_spk + F[n], N) Equation (20)

[0253] where n and A are the time and duration of the time step.

[0254] FIG. 15A shows the microarchitecture of the PRNG comprising a data path unit and a control unit. The data path unit includes a memory and the computational blocks. The memory is used to store synaptic weights (v ) and input weights (w).

[0255] The input weight of a neuron is concatenated to the end of its synaptic weights. In the initialization phase, the input weight of a neuron is multiplied by the seed s[n] at time step n using the Seed Multiplication block and the result is applied to the block v[n] as a bias current. The bias current of neuron / in the time step n is lB / [n] = ws[n]. The input weights in the memory are one bit and are scaled by +A and -A using a multiplexer. Since the initialization phase is temporary, the second multiplexer is used to remove the seed and apply the constant bias current IB during the operational phase.

[0256] During the initialization phase and the operational phase, the synaptic weights are multiplied by the spikes. The synaptic weights are organized into a structure N x N, each location comprising one bit. To save memory space, one bit is used for each weight and the MLT block converts the binary values (0 and 1) to the signed values (-1 and +1) for weight multiplication. There are N multipliers in parallel that correspond to N weights per neuron. The truth table of the MLT block is shown in the FIG. 15A, where spk[ / ] is the spike of the neuron j at the current time-step. The multipliers pass the results to the adder tree that calculates the term wi;5[n -nJk] in Equation 19. An adder tree is a parallel computing architecture that efficientlycomputes the sum of multiple numbers by recursively adding pairs of numbers until a final sum is obtained.

[0257] The blocks of h[n], r[n], v[n] and 1[n] implement the corresponding equations. To reduce the hardware area, resource sharing was used in which each block was used for calculations of all synapses and neurons. The resource sharing reduces throughput by the order of N - the number of neurons. To compensate for throughput, the pipeline design was used to implement the synaptic and neuron’s dynamics. FIG.15A (right) shows the pipeline design of the synaptic and neuron’s dynamics (h[n], r[n] and v[n]). The pipeline architecture breaks the combinational circuits into smaller parts to increase the throughput of the system at the cost of a small increase in total circuit latency and consumption of a few registers. While the number of stages in h[n] block is two, the number of stages in the r[n] block and v[n] is taken equally (five) to simplify the control unit.

[0258] At each clock cycle, the calculation in each block is computed and fed into the next block. The values of h[n], r[n] and v[n] are stored in the Random Access Memory (RAM) to be used in the next time-step. The spikes in each clock cycle are also stored in a serial-in-parallel-out (SIPO) register to be used in the next time step. The index of the neurons generating spikes are sent to block F[n], which is implemented by a log2(N)-bit integer adder. Finally, the F[n] values are converted to output bits through the N *1 Look-Up Table (LUT).

[0259] The control unit controls the flow of computations in the data path unit, which is based on a modular block, counter module (CM), comprising a counter and two comparators. The counter is enabled through a pulse with the duration of at least one clock cycle at the ON pin and stays enabled until it receives a pulse at the OFF pin in which it is disabled, and the counter value resets to zero. In this block, the counter isalways disabled when the counter value reaches A / -1. The EN pin is 1 when the counter is enabled.

[0260] Since the read and write operation of the RAMs in the synaptic and neuron blocks are performed sequentially, the output of the CM1 block is used to generate the read address (W-R-add) of the weight memory, and it is also used as a reference block to trigger the other CM blocks. The A, B, C and D are related to the number of pipeline stages in the h[n] block (Hstage), r[n] and v[n] block (RVstage), and adder tree (Asfage): A = Astage~2, B=Astage H stage, C=A staged Hstage~2, D=Astage H stage RVstage-

[0261] Note that the constant value of -2 is used, since in FPGAs it usually takes two clock cycles after providing the address for the RAM memory to make the content of the memory available.Example 2: Ultra-Low Power Neuromorphic Pseudo-Random Number Generators Based on Balanced NetworksPseudo-random number generation often requires trade-offs among quality, power consumption, and bandwidth to produce unpredictable sequences of numbers. The brain, on the other hand, efficiently generates unpredictable output via complex network dynamics occurring in a high-dimensional state. This high-dimensional state may be hyperchaotic and relies on the balance between excitation and inhibition. Here, an investigation was performed to determine if such hyperchaotic states can be harnessed for Neuromorphic Pseudo-Random Number Generators (NPRNGs) in ultralow power hardware and software.A balanced Spiking Neural Network (SNN) model consisting of leaky-integrate-and-fire neurons was successfully constructed that could be readily implemented in ultra-low power FPGAs that can operate on low power (e.g. consume less than 5 milliwatts during operation) and used as an example NPRNG. The example NPRNG consumed4.45 milliwatts during operation, with quantized parameters and balanced weights, and produced pseudo-random numbers at 200 kbps. In both hardware and software instantiations, NPRNGs produce high-quality random numbers as validated by standard metrics for testing RNG quality from the National Institute of Standards and Technology (NIST SP-800-22). Further, the network structure of the NPRNG leads to a parameter search space that scales like O(2N), which is intrinsically resistant to brute-force duplication for even small networks.Introduction

[0262] Pseudo-random number generators (PRNGs) are important for modern computing. For example, PRNGs are used to solve advanced computational problems with Monte-Carlo methods, as streaming ciphers for secure communications, or as inputs for generative artificial intelligence. Many PRNGs operate as some form of a recurrence relation, wherein an initial state (the seed) is transformed by iteratively applied nonlinear operations to produce random looking but deterministic streams of bits. Unfortunately, the complex nonlinearity that enables good pseudo-random number generation is often resource and power intensive to implement in hardware like field-programmable gate arrays (FPGAs) or even in application specific integrated circuit (ASIC) chips.

[0263] In contrast, the brain produces unpredictability very efficiently. Experiments have shown that certain dynamical brain states high-dimensional and likely chaotic. Further, the balance between excitation and inhibition measured in cortical brain networks is well modeled by strong, but balanced coupling between neurons which leads to hyperchaotic dynamics. This dynamical state, in which the neurons fire asynchronously, is readily reproduced with randomly generated synaptic weights in both recurrent artificial neural networks, and recurrent spiking neural networks. As such networks increase in size, it is analytically provable that the constituent neuronsactivate as if they are independent and driven by noise. Finally, the entire brain operates on as little as 20 watts, suggesting that small to intermediate-sized networks engaged in specific tasks should operate in the milliwatt range. Collectively, the experimental and theoretical evidence suggest the possibility of efficient random number generation based on neuromorphic computing, in which aspects of brain computation, such as the firing of spikes by neurons, are emulated in hardware.

[0264] In this example, brain-based computing principles were analyzed to produce ultra-low power, neuromorphic pseudo-random number generators (NPRNGs). First, it is shown that relatively small networks of integrate-and-fire neurons under a balanced connectivity regime produce sufficient entropy in a hyperchaotic regime to act as good PRNGs, as validated with the National Institute of Standards and Testing (NIST) SP-800-22 testing package for PRNGs. Briefly, NIST SP-800-22 runs 15 separate statistical tests for randomness where the null hypothesis of each test is a completely random bit string. It was found that not all configurations of balanced spiking networks were suitable as PRNGs. The connectivity strength or "g" parameter critically determined the quality of pseudo-random number generation. If the connectivity strength is too high, the spiking neural networks transition to rate-chaos regimes which leads to poor pseudorandom bit streams. If the connectivity strength was sufficiently large but less than a critical threshold, then spike-chaos emerged, and small networks of neurons displayed Poisson like firing statistics. These spikes produced high quality pseudo-random number bit streams that match or exceed other established PRNGs. Due to the binary weights, each example NPRNG was unique and occupied a large parameter space of O(2N), rendering brute force searches to determine the parameterization of an NPRNG infeasible for even small numbers of neurons (N). Next, in this example, NPRNGs were implemented in hardware with ultra-low power FPGAs. These example hardware-based NPRNGs generated random numbers at 200kbps while using less than 5 milliwatts of power during operation.ResultsThe excitatory / inhibitory balanced state in quantized spiking neural networks

[0265] To investigate the capacity of chaotic spiking neural networks (SNNs) to serve as pseudo-random number generators, networks of Leaky Integrate and Fire (LIF) neurons in a balanced configuration were considered:= ~vi + ^7=1wijrj(t) + 1> 1 = 1,2,... N. (Equation 1)

[0266] where v(t) corresponds to the voltage of the itn neuron. A neuron is said to fire a spike when it reaches a threshold v,(f— ) = vth and is reset at v,(f+) = vreset. The spikes are filtered by a double-exponential post-synaptic filter ( / j(t)) for each neuron, and then multiplied by the weight matrix w to form a network. The LIF model was chosen as it is straightforward to apply in hardware and considered as a computational primitive in neuromorphic systems. The background current / drives an isolated neuron, V / (t) to fire spikes (Materials and Methods) and is set at the threshold for firing I = vthin the balanced configuration. Depending on the coupling weights, w, the SNN in equation (1) can display complex dynamics. One well studied dynamical regime is the so-called balanced state, where the excitatory weights (wy > 0) are counteracted by the inhibitory weights (wy < 0) by imposing the following conditions on the first two moments ofE = 0, E(OJT) OC i (Equation 2)

[0267] The parameter regime in Equation 2 is possibly one of the most well-studied coupling regimes for recurrent neural networks, as it produces hyperchaotic dynamics where the neurons asymptotically (N °°) as if they were uncoupled and independently driven by a filtered noise process. This noise process can be self-consistently derived and depends on the characteristics of the coupling and neuronal dynamics.

[0268] Here, the potential for balanced networks (Equation 1)-(Equation 2) was investigated as a basis for ultra-low power, neuromorphic pseudo-random number generators (NPRNGs), with the caveat that the networks considered may be modified to be implementable in hardware.

[0269] The first such modification considered is weight binarization:coij = +-j= (Equation 3)

[0270] where g is the overall coupling strength of the connections (FIG. 1A). This modification reduces the storage required for on-chip implementation. To investigate if binarizing the weights would impact the balanced state dynamics, a series of simulations were run with a network consisting of N = 256 neurons. It was confirmed that the irregular voltage and spiking dynamics (FIGs. 1A-1B), are still present, and the neurons fire spikes with a distribution of inter-spike intervals (ISIs) that is similar to a Poisson process with a refractory period (FIG. 1 D). The ISIs have a mean coefficient of variation of μcv= 0.99 (N = 256, σcv= 0.25, Materials and Methods), indicating Poisson like-spiking statistics. Further, for larger values of g, an SNN coupled with binarized weights still displays a transition to “rate-chaos" (FIG. 4).

[0271] Next, an analysis was conducted to determine if the network’s state trajectory was radically altered by the deletion of a single spike, which is a necessary feature of chaotic SNNs. Indeed, deleting a single spike (FIG. 1E) led to a completely different constellation of spikes as compared to a parameter matched and initial-state matched simulation without a deleted spike. The SNN with binarized weights also displays a sensitivity to the underlying parameters, like any chaotic system, in which a sign change of a single connection W21 leads to a different irregular trajectory (FIG. 1 F).

[0272] Next, we considered quantizing all of the network parameters to facilitate efficient hardware implementation. Quantization entails finding parameters that are of the form ±2 / c where k is an integer (FIG. 1 G) for all neuronal and network parameters. This includes the binary coupling strengthQuantization may be important for an efficient hardware implementation of the SNN because it converts all operations to the movements of bits. The quantized network still displays irregular spiking dynamics (FIGs. 1H-1I), in which the neurons display similar Poisson-like spiking as in the nonquantized network (FIG. 1 J), although with a smaller coefficient of variation for the parameters considered (JJCV = 0.68, Ocv = 0.16, N = 256). The quantized network also displays a transition to “rate chaos" as the coupling strength is varied (FIG. 5). In summary, the key modifications (quantization and weight binarization) used to implement a balanced network in neuromorphic hardware do not impact the overall dynamical features of the hyperchaotic state.Creating and Testing Random Bit Streams with Balanced SNNs

[0273] Next the mechanisms for translating the irregular firing of neurons in the SNN into a bit string for use as a pseudo-random number were considered. A preferred pseudo-random number generator produces its nth, output a bit (bn) as if it was independently drawn from an unbiased Bernoulli random-variable:0 with probability - I (Equation 4)11 with probability -

[0274] with bj and bk being statistically independent for any j = k. In practice, these two constraints are difficult to achieve with any pseudo-random number generator.

[0275] A conventional pseudo-random number generator (PRNG) operates by using an initial input, or seed, s = xo and some recursive operation, xn+1= f(xn) toproduce pseudorandom sequences of bits (FIG. 2A). For example, the Blum-Blum-Shub (BBS) PRNG uses the nonlinear recurrence relationshipxn+1= mod M (Equation 5)

[0276] where M = p · q is the product of two primes. When converted into bits, xn+1produces a pseudorandom bit string.

[0277] A Neuromorphic pseudorandom number generator NPRNG, has two key differences with conventional PRNGs (FIG. 2B). First, an NPRNG requires an initial state for each voltage, vi(t) and synaptic filter ri(t), rather than an integer seed. This produces challenges for hardware implementation owing to bandwidth limitations of most ultralow-power chips. However, a 1D time series can also be used as an input signal to initialize an NPRNG onto a chaotic spiking trajectory (FIG. 2B) and serve as a seed. Alternatively, an N-bit seed can initialize the network where the / th neuron’s initial condition is set to super-threshold (spiking) if the / th bit of an input seed is 1. If the / th bit of the input seed is 0, the initial condition for the neuron is v(t) = Vreset. This initialization may be used when implementing the SNN as a hardware-based NPRNG. The second difference between an NPRNG and a conventional PRNG is that the need to transform the spike-time sequence of all neurons, which is labelled with the n x 2 matrix s, where sn1= jn, the index of the neuron that fired the jthspike, and sn2= tn, the time at which the jth spike is fired. The time-series of spike times may be transformed into a bit string by the below noted method.

[0278] A series of 15 statistical tests developed by the National Institute of Standards and Technology (NIST, NIST-SP-800-22) were used to determine the quality of pseudo-random number bit strings generated by NPRNGs (FIG. 2C). These tests determine if a bit string is indistinguishable from an independent Bernoulli random variable, via various measures (e.g. repetition of sequences, frequency of bits, etc.).The average number of tests passed is considered based on 100 randomly generated bit strings, each with 1,000,000 bits.

[0279] Using the number of NIST tests passed as a metric for PRNG quality, the use of input signals as seeds, rather than predefined initial states was investigated. These input signals avoid requiring an NPRNG to store O(N x 2) initial seed vectors, and led to more efficient hardware implementations by allowing a streaming input to initialize the network onto a chaotic trajectory (FIG. 2D).

[0280] The input signal is applied to each neuron with a binary weight matrixτmvi(t) = −vi+ ∑Nj=1wijrj(t) + I + wiinc(t), i = 1,2,... N. (Equation 6)

[0281] where c(t) is the input signal, and wiin± 1 is a randomly generated weight. With this implementation, only O(N) bits of storage for (win) are required for the hardware implementation. Two separate input signals ci(t) and C2(t) can cause a network with the same initial conditions vi(0) = vreset, ri(0) = 0 to produce two different chaotic trajectories, and therefore, bit strings. Further, inputs can also be used to synchronize two NPRNGs that are on initially different chaotic trajectories, provided that c(t) is of sufficiently long duration (FIG. 6). This is partially a consequence of the stable but irregular nature of the chaotic trajectories displayed by balanced SNNs.

[0282] With a mechanism for seeding an NPRNG determined, how to generate bits with the spike raster through some transform, T(s) was investigated. One naive transform would be to take the nth spike index for a network of 2kneurons and convert it into a binary representation with k-bits, and group the resulting nk bits together into a bitstream. This turns out to produce bitstreams that are easily detectable by NIST as being different from the independent Bernoulli random bitstream hypothesis. In particular, this occurs because a neuron in a balanced network has a refractory periodthat follows each spike in which the neuron is unlikely to spike again (FIG. 7). This produces bit streams that appear as non-random, as the bits generated by a neuron’s index inherit the neuron’s refractory period.

[0283] To produce higher-quality PRNGs, a transform T(s) was implemented that would take into account the refractory period of firing. First, a counter variable ynis computed for the nth spike:yn= mod(yn-1+ sn, N) (Equation 7)

[0284] This variable accumulates the previous history of spiking by the entire network. Next, a static Lookup table / _( / ), / = 1,2,... N was defined which corresponds to N uniformly distributed bits. The nth reported bit is then given bybn = L(yn) (Equation 8)

[0285] The bits in the lookup table are static and are only ever generated once. The lookup table L, recurrent weight matrix w, and input weight matrix w / j collectively define an NPRNG, and act as the “secret key” for the NPRNG when used in cryptographic applications. This simple and memory-efficient transform T(s) with a single randomly generated weight matrix, with 65,536 separate inputs (Materials and Methods). Each input generated a bitstream consisting of 109bits. These 109bits were divided into 1000 individual streams of 106bits each and were tested with NIST (FIG. 2F). Approximately 50% of all initial inputs led to bitstreams that passed every NIST test, with another 40% passing 14 / 15 NIST tests, and only a small number of bitstreams passing 11 -13 of 15 tests.

[0286] Next, the impact of the individual weight matrix was considered. Separate weight matrices were generated, and a bitstream of 108bits for each weight (FIG. 2F). The population of weights on average produced slightly poorer quality bitstreams thanthe single randomly generated weight matrix considered, indicating some degree of impact on the specific weight matrix generated for an NPRNG. However, the overall distribution of passed NIST tests is qualitatively similar across weights, with no generated weight matrix having failed less than 10 tests or less across nearly 12.5 Terabytes of randomly generated bits. Additionally, approximately half of all weights passed all 15 NIST tests. It is possible to generate a non-random, but still technically “balanced” weight matrix that will generate poor-quality random bitstreams (FIG. 8) while still satisfying the conditions in (2) (FIG. 9).

[0287] While balanced SNNs are chaotic, the chaos can be of two different form: rate or spike chaos. It was sought to determine how the statistics of spiking in these different chaotic states impacted the quality of pseudorandom bit generation. Simulated networks of varying connection strengths, gq= 2−jfor j = 1,2,…16 and varying synaptic time constants τD= 2−i, for i = 1,2,… 8, and computed the mean coefficient of variation for the spike rasters generated (Materials and Methods, FIG. 1G).

[0288] Over this parameter range, a coexistence was identified between non-firing (small gq, TD), rate chaos (larger gq) and Poisson-like spiking (smaller gq) where the CVs are μcv< 5. Next, for the same parameter regimes the average number of NIST tests passed (FIG. 2H) was computed. In the rate-chaos regime, where the coefficient of variation is high, poorer quality bitstreams are produced (FIG. 2H). The average number of NIST tests passed was also strongly negatively correlated (ρ = −0.8863, p≪10−4), with the average coefficient of variation μcv(FIG. 8). Collectively, these results imply that the Poisson-like spiking regime is superior to the rate-chaos regime for generating random bitstreams, with the dynamic lookup table T(s). Finally, to place these results into context, both quantized and non-quantized NPRNGs were compared to other PRNGs.

[0289] 100 bitstreams of 106bits for each stream were generated with: the quadratic congruential PRNG, the modular exponentiation PRNG, the linear congruential PRNG, the Blum-Blum-Shub PRNG, and the Mersenne Twister. The quadratic congruential generator and modular exponentiation performed the worst, with no bit streams generated passing all 15 NIST tests, while the LCG, BBS, MT, and the two NPRNGs all performed comparably, with » 50% of all bitstreams generated passing all 15 NIST tests, an additional » 40% passing 14 NIST tests, and the remaining 10% of bit streams passing 10 or more tests. These results show that balanced spiking networks can serve as good PRNGs provided that the coupling strength between neurons is not too strong, and the neurons operate in the Poisson-like spiking regime NPRNGs in hardware run on less than 5 milliwatts of power

[0290] To test the real-world energy efficiency of NPRNGs, the neuromorphic model on FPGA. To meet the power consumption objective, an ultra-low power FPGA, iCE40UP5Kfrom Lattice Semiconductor, was selected. This dictated the area resource constraints (the available FPGA resources). In the microarchitecture design, multiple techniques were applied to meet the area (FPGA resources) and performance (throughput) requirements (FIG. 3A). First, the microarchitecture used shared hardware blocks for the synaptic dynamics (h[n] and r[^]) and LIF neurons (v[n]) to reduce resource usage. Moreover, since spikes were used in the data representation, the synaptic multiplications were converted into additions, resulting in further reduction of energy usage. Spatial parallelism was used for multiply-accumulate (MAC) block to improve the throughput by performing the weight multiplications of each neuron in one clock cycle. The temporal parallelism (pipeline design) allowed an overall improvement of the throughput so that the output of one neuron is calculated on each clock cycle. The fully pipeline design also simplified the control unit, which was designed based on a modular counter-based block. This allows scalability of the design without making major changes in the microarchitecture but setting parameters. The scalable designapproach allowed us to configure the network size to fit the FPGA. A network of N = 256 neurons was implemented utilizing 76 percent of the SLICES (look-up tables and flip-flops) on the FPGA iCE40UP5K. The maximum clock frequency of around 41 MHz was estimated for this FPGA by the software of Synopsys Synplify Pro - Lattice Edition. To meet the power consumption requirement, the minimum frequency of the built-in oscillator, 6 MHz, was used.

[0291] According to the power calculator of Lattice Radiant Software, the power consumption of the FPGA may be as low as 3.24 mW at 6MHz (FIG. 3D). The throughput of the NPRNG was estimated through simulation of the design using the software of Siemens ModelSim Lattice FPGA Edition. The NPRNG was simulated for 10000 time steps and the spike rate was calculated as 1 / 50 spikes per clock calculated by dividing the number of generated spikes to the total clock cycles. Since a random bit is generated per spike, the throughput of the NPRNG is the spike rate multiplied by the clock frequency, 6MHz, resulting in 120 kbps. The generated random bits were sampled every 5 bits before sending to the external device. To communicate with the external devices, the universal asynchronous receiver-transmitter protocol (UART) interface was used with an effective bit rate of 200 kbps.

[0292] To measure the power consumption during the operation, the current of the board was monitored as 1.65 mA at 3.3 v resulting in 4.45 mW of the total power consumption (FIG. 3C). Finally, the random bits generated by the hardware-based NPRNG were also used to approximate π with a Monte-Carlo method (FIG. 3D), with the resulting approximate being 3.1413 using 2.2 million randomly generated numbers from a uniform distribution on [0,1],

[0293] A comparison of the FPGA implementation of NPRNG and other PRNGs is provided in Table 1. As a complex dynamical system, NPRNG uses more resources while the absolute power consumption can be as low as 3.2 mW. This is within therange that can be passively powered by wireless energy sources (e.g. NFC). The low power consumption is not only because of using ultra-low power FPGA with a low oscillator frequency, but also using spikes in computations resulting in a multiplier-less synaptic operation block.Discussion

[0294] The ability to generate bit streams that are indistinguishable from truly random bit streams usually involves trade-offs. Some existing PRNGs are not provably random, and will produce poor pseudo-random bit streams, while others require substantial computational resources to implement in hardware. Here, it is shown that asymptotically provably random spiking neural networks connected in a balanced configuration produce high-quality random bit streams that pass all 15 tests for the NIST SP800-22 package at similar or higher rates to established PRNGs. The NPRNGs considered here are also readily implemented in ultra-low power FPGA hardware, using as little as 3.2 milliwatts of power to generate a bit stream at a rate of 30 kilobits per second. NPRNGs also have a key advantage over other PRNGs: the number of unique NPRNGs grows geometrically with network size. For a network of N neurons, O(2N) unique NPRNGs can be produced, which all operate differently due to the hyperchaotic dynamical state that an excitatory / inhibitory balanced network occupies.

[0295] This large parameter complexity space yields an additional important advantage to NPRNGs: when used for cryptographic applications, they are likely more resistant to side-channel attacks, where attackers glean the secret key that some PRNGs use through the leakage of information that occurs when implementing algorithms in hardware. For example, cryptographically secure PRNGs based on advanced encryption standard would be prone to side-channel attacks in hardware. NPRNGs have a more complex key using O(N2) bits (recurrent weights). The key isalso never accessed synchronously, only column by column as the neurons fire spikes. When implemented in this way, NPRNGs may provide side-channel resistance in cryptographic applications requiring random numbers.

[0296] The most immediate follow up on this work would be the construction of neuromorphic true random number generators (NTRNGs). True random number generators are an ongoing topic of study due to their widespread use in cryptography applications as the mechanism for generating one-time-pads. Although there are many instantiations of a putative NTRNG, a straightforward implementation would be of an analog spiking network built on basic electrical circuit elements: resistors, capacitors, and recently created memristors that would implement the gates on the voltage-gated ion channels involved in generating action potentials in neurons.

[0297] Collectively, these results demonstrate the feasibility of NPRNGs as ultralow power randomer number generators that use less than 5 milliwatts of power. We anticipate that NPRNGs will have applications in edge computing, where the low power and area constraints necessitate novel solutions.MethodsSpiking Neural Networks and the Excitatory / lnhibitory Balanced State

[0298] The network equations for a leaky-integrate-and-fire (LIF) network of spiking neurons in the excitatory / inhibitory balanced regime are given byτmv̇i(t) = −vi+ ∑Nj=1wijrj(t) + I (Equation 9)rj(t) = −rj / τd+ hj(Equation 10)hj(t) = hj / τr+ 1 / (τdτr) ∑t<tδ(t − tjk) (Equation 11)The voltage dynamics are given by Equation 9 where vj(t) is the voltage of the jth neuron. When the neuron reaches a threshold, vj(t−) = vth, it is said to fire a spike and is reset to v(t+) = vreset. The membrane time constant τmcontrols how much of the past history of currents arriving to neuron j is filtered in between spikes. The parameter I acts as a bias current to each neuron and sets the background firing rate of the neurons without any synaptic inputs. Every spike fired by a neuron is filtered by a double exponential synaptic filter, i t), implemented by Equations (10)-(11 ). Briefly, this acts to filter the kth spike fired by the jth neuron at time tjk with a synaptic current pulse. This pulse has a rise time given by trand a decay time given by τ_d.

[0299] The weight matrix w,j couples the jth neuron to the ith neuron and is randomly generated to elicit hyperchaotic dynamical state in both recurrent rate and recurrent spiking neural networks. In particular, the conditions on the moments of wtj that may elicit this state areE (ωij) = 0 (Equation 12)= V (Equation 13)

[0300] where g is sufficiently large. In spiking neural networks, the hyperchaos displayed can occur in two forms depending on the g parameter: rate chaos or Poisson-like irregular spiking. For larger g, the network enters into the rate chaos regime, with the specific transition point determinable with dynamic mean-field theories. For smaller g, the spikes having Poisson-like firing statistics, where the rate is homogeneous both across the network, and in time. Note that the irregular dynamics displayed in the “spike-chaos" are irregular, but exhibit a kind of stable chaos. This arises as perturbations to the voltages of the neurons may or may not cause a lasting change to an irregular spiking trajectory. In analytical systems that allow for the construction ofexact, event-based spike-to-spike simulations, the discrete spikes are shown to be chaotic.

[0301] To satisfy the constraints in Equations (12)-(13), while simultaneously allowing for simple implementations in neuromorphic hardware, we use binary values of the weights:ω_ij = ±g / √N (Equation 14)

[0302] Further, each neuron / receives exactly N / 2 positive weights (+g / √N) and N / 2 negative weights (−g / √N), which implies that Equation (12) holds exactly for each neuron / .Generating Uniform Random Bit Sequences from a Spiking Neural Network

[0303] Lookup tables are common tools in both cryptography and computer science. A dynamic lookup table was used to resolve the RNG quality issues that arise with the relative refractory period of spikes as follows. Let n denote the index of the nth spike fired by the network. Let ynbe defined as:yn= mod(yn-1+ sn, N) (Equation 15)

[0304] where N is the modulus operation and snis the index of the neuron that fired the nth spike. The variable ynincrements the indices of the n spikes fired modulo N. Then, the nth bit reported by the network is given bybn= L(yn) (Equation 16)

[0305] where L( / ) = b, and b is a randomly generated N x 1 binary vector containing N / 2 bits that are 0, and N / 2 bits that are 1, randomly permuted.The NIST-SP-800-22 Package for Testing PRNGs

[0306] NIST SP 800-22 is a set of statistical tests designed to evaluate the randomness of binary sequences generated by random number generators. NIST outlines a suite of tests to ensure that a PRNG produces sequences that exhibit statistics that cannot be distinguished from those derived from a truly random binary sequence.Neuromorphic Microarchitecture of the NPRNGs implemented on Field Programmable Gate Arrays

[0307] Since the network Equations, (9), (10), and (11), are translated into to the main computation blocks in the microarchitecture, their complexity has a significant impact on the space or time complexity of the corresponding hardware blocks and the overall microarchitecture. Simplifying the multiply-accumulate (MAC) operations, as the fundamental but hardware-costly blocks of neural networks, will lead to efficient implementation of the microarchitecture. Specifically, the original equations were modified by moving multiplications in Equations (9) to (11) due to the linearity of the synaptic equations. This resulted in multiplier-less synaptic operations in which the synaptic weights are added in the occurrence of spikes. Multiplier-less implementation of 329 synaptic operation is the immediate benefit of using spikes for processing. The discretized equations are:v_i[n + 1] = v_i[n] + Δ / τ_m (−v_i[n] + r_i[n] + I_i^B[n]) Equation (17)r_i[n + 1] = r_i[n] − Δ(1 / τ_d r_i[n] + h_i[n]) Equation (18)hi[n + 1] = hi [n] + A(— / i([n] -I — — Wj.-Afn — n,k]) Equation (19)Tr^r^dJF[n + 1] = modulo(ispk+ F[n], N~) Equation (20)

[0308] where n and A are the time and duration of the time step.

[0309] FIG. 3A shows the microarchitecture of the PRNG comprising a data path unit and a control unit. The data path unit includes a memory and the computational blocks. The memory is used to store synaptic weights (Wy). In the initialization phase, the seed with the size of N bits is stored in the SIPO shift register as the initial spikes for the first time step. For the subsequent time steps, the seed is zero.

[0310] During the operational phase, the synaptic weights are multiplied by the spikes. Due to the nature of spikes, the multiplication doesn’t require a multiplier, but a multiplexer (MUX). The synaptic weights are organized into a structure N x N, each location comprising one bit. To save memory space, one bit is used for each weight and the CONVERT block converts the binary values (0 and 1) to the signed values (-1 and +1). There are A / CONVERT and MUX blocks in parallel that correspond to A / weights per neuron. An adder tree is a parallel computing architecture that efficiently computes the sum of multiple numbers by recursively adding pairs of numbers until a final sum is obtained.

[0311] The blocks of h[n], r[n], v[n] and f[n] implement the corresponding equations of 19, 18, 17 and 20 respectively. To reduce the hardware area, resource sharing was used in which each block was used in each of these blocks for calculations of all synapses and neurons. The resource sharing reduces throughput by the order of N - the number of neurons. To compensate for throughput, the pipeline design was used to implement the synaptic and neuron’s dynamics. FIG. 3A (right) shows the pipeline design of the synaptic and neuron’s dynamics (h[n], r[n] and v[n]). The pipeline architecture breaks the combinational circuits into smaller parts to increase the throughput of the system at the cost of a small increase in total circuit latency andconsumption of a few registers. While the number of stages in h[n] block is two, the number of stages in the r[n] block and v[n] is taken equally (five).

[0312] At each clock cycle, the calculation in each block is computed and fed into the next block. The values of h[n], r[n] and v[n] are stored in the Random Access Memory (RAM) to be used in the next time-step. The spikes in each clock cycle are also stored in a serial-in-parallel-out (SIPO) register to be used in the next time step. The index of the neurons generating spikes are sent to block F[n], which is implemented by a log2(N)-bit integer adder. Finally, the F[n] values are converted to output bits through the N *1 Look-Up Table (LUT).

[0313] The control unit controls the flow of computations in the data path unit, which is based on a modular block, counter module (CM), comprising a counter and two comparators. The counter is enabled through a pulse with the duration of at least one clock cycle at the ON pin and stays enabled until it receives a pulse at the OFF pin in which it is disabled, and the counter value resets to zero. In this block, the counter is always disabled when the counter value reaches N−1. The EN pin is 1 when the counter is enabled.

[0314] Since the read and write operation of the RAMs in the synaptic and neuron blocks are performed sequentially, the output of the CM1 block is used to generate the read address (W-R-add) of the weight memory, and it is also used as a reference block to trigger the other CM blocks. The A, B, C and D are related to the number of pipeline stages in the h[n] block (Hstage), r[n] and v[n] block (RVstage),and adder tree (Astage) A = Astage~2, B=Astage^ Hstage, C=A staged Hstage~2, D=Astage H stage RVstage-

[0315] Note that the constant value of -2 is used, since in FPGAs it usually takes two clock cycles after providing the address for the RAM memory to make the content of the memory available.Supplemental Section: Parameter Complexity Space

[0316] For a network of N neurons with binary weights, there are N2 weights, each with a possible value ofwij= ±g / √N (Equation 21)

[0317] This implies 2N2possible configurations of the weights, in the case where each weight is a bernoulli random variable with possible configurations +g / N and -g / N.

[0318] However, for the NPRNGs considered here, each row of the weight matrix has exactly N / 2 positive values and N / 2 negative values, with every row being a permutation of the vectorw = [1,1,1,...1, -1, -1,... - 1]V / v

[0319] where the first N / 2 entries are g / N and the last N / 2 entries are - g / N For a single row, there are C(N, N / 2) unique configurations of wo, where C(N,k) = N! / ((N— k)!kl). As there are N rows in w, there areN N\Nw= C(N,-)N= (-TT—Y((?)!)2

[0320] possible weights. The limiting behavior of Nwcan be computed with Stirling’s asymptotic formula:Iog2(n!) = nlog2 n-nlog2(e)+O(log2(n))

[0321] withlog2(Nw) = N(log2(N!) − 2 log2((N / 2)!)) (Equation 22)log2(Nw) = N(N log2(N) − N log2(e) + O(log2N) − N log2(N / 2) + N log2(e) +O(log2((N / 2))) (Equation 23)log2(Nw) = N(N (log2(N) − log2(N / 2)) + O(log2(N))) (Equation 24)log2(Nw) = N(N − O(log2(N))) (Equation 25)log2(Nw) = N2− O(N log2(N)) (Equation 26)and thusNw~ 2N²−O(N log₂(N))N → ∞ (Equation 27)Thus, for large N we should expect that the number of weight matrices Nwsatisfying the constant-row sum condition scales like 2N²which effectively is identical to the scaling of now having any row-sum constraint at all.Supplemental Section: Simulations

[0322] To conduct the extensive simulations, it was ensured that the software implementation was consistent with the hardware. This was validated by running both the software and hardware using the same set of weights and seed values, then comparing their spike raster plots, which showed perfect alignment. Once confirmed, the software simulation was used to generate random numbers for the experiments. In total, approximately 108random bits were generated, divided into 100 bit streams of 106bits each. This division ensured compatibility with the NIST testing package, which requires at least 106bits per bit stream for some statistical tests. All experiments were executed using the Slurm job scheduler on the Digital Research Alliance of Canadaclusters: Beluga, Cedar, Graham, and Narval. According to the Digital Alliance, the total CPU usage for our experiments was equivalent to 65.49 core years, where a core year represents continuous computation on a single CPU core for one year.

[0323] For running each test, there are two separate phases. In the first phase, 108random bits are generated using a different set of network weights, a Look-Up Table, and a seed value. To ensure the generation of diverse random numbers, the network must be initialized with different seeds. While a variety of methods can be employed to generate seeds for the network, we used a 16-bit Linear Feedback Shift Register (LFSR) as a straightforward and effective approach to initialize the network with 216distinct configurations. The characteristic polynomial of the LFSR is as follows:P(x) = x16+ x15+ x13+ x4+ 1 (Equation 28)

[0324] Once the network is initialized and has run for a specified duration, we transition to the second phase: capturing the random bits. To standardize output across experiments, we define a file size threshold of 115 MB. The SNN, configured with different parameters, produces random bits at varying rates, and the simulation stops once this predefined size is achieved. In the second phase, the generated random bits were evaluated for their randomness using the NIST SP 800-22 testing package, as described in the Methods section. The results of the NIST tests were collected for each set of experiments and processed using Python scripts. First, the raw reports were parsed into CSV files for easier analysis. Final results were then generated by applying a strict evaluation metric: a test was considered "passed" only if all instances of that test met the minimum pass rate criteria for both the P-value and Proportion metrics as specified in the NIST documentation. This ensured that only experiments meeting the most stringent randomness requirements were reported as successful.Example 3 – Various Improvements to NPRNGs

[0325] In this example, some immediate extensions to the Neuromorphic PseudoRandom Number Generators (NPRNGS) will be considered.

[0326] In the first section, we will outline improvements in the model, while in the second section, a series of use-cases are outlined.Model Improvements to NPRNGs

[0327] Briefly, Neuromorphic Pseudo-Random Number Generators (NPRNGS) consist of spiking neural networks that may be implemented in the following instantiation:Tmvi = ~vi + 1 + (Equation 34)Trrj(t) = -n(t) (Equation 35)Vpeak ~ * ^i^ik) Preset’ ri{ttk) = + 1 (Equation 36)

[0328] where tik denotes the ktn spike fired by the itn neuron.

[0329] Each NPRNG may also use a transform T(s,a) of the spike train to a random bit string, where a is a vector of parameters.

[0330] The weights Wij are generated to induce a high-dimensional chaotic state. One such chaotic state is from the so-called balanced regimeE^wij) = 0, E(wiJ') oc Equation (37)

[0331] Several immediate improvements are considered that have one or more of the following features

[0332] Increased Side-channel resistance: They make NPRNGs more sidechannel resistant by increasing the complexity space of the brute force search and make the “secret key” larger.

[0333] Dynamical Parameters: They add dynamical features to the secret key rendering it difficult to determine at any point in time.

[0334] More nonlinear mixing: They increase the complexity of the system somehow so that the neurons implement more nonlinear operations and nonlinear mixing of prior history.

[0335] Larger complexity space: They add additional parameters to the secret key reguired to predict the output of an NPRNG, or make the network larger by successively doubling N, the network size, subject to hardware / software constraints.

[0336] Higher Freguency Updates: Increase the freguency of bit generation.Improvement 1: Heterogeneous Parameters for Each Neuron

[0337] Referring to FIG. 16, a NPRNG network may be configured with parameter dependent neurons.

[0338] One improvement on the NPRNGs considered previously is to make each NPRNG parameter dependent at the neuronal level. In particular, if we consider eguations (34)-(36), each neuron is parameterized by a vector pt= [tm, I, Tr, vpeak, vreseL] which corresponds to the membrane time constant, the background current, and the synaptic time constant, respectively.

[0339] In the instantiation of (34)-(36), pi = p for all i, and the neurons are homogeneous. A straightforward change that would increase the parameter complexity would be to have each neuron have slightly different parameters p =[Tm,i> Ii>Tr> >vpeak'i, vresetii]. In this way, the hyperchaotic state is still going to exist if each neuron’s parameters are slightly different from any other neuron, and an attacker has to determine what each parameter value is for each neuron. With k bits per parameter, and nPparameters for N neurons, the complexity space for each NPRNG increases multiplicatively by2Nnk

[0340] While this won’t increase the asymptotic order complexity of O(2N) (since the multiplicative term becomes linear in N in the exponent), this would render it more difficult for an attacker to statistically try to predict the NPRNG weights, as the weights alone are no longer sufficient to determine the output of a NPRNG.

[0341] The parameters for each neuron must be determined at the same time. If we consider the equations (34)-(36) with neuronal heterogeneity, thenτm,iv̇i= −vi+ Ii+ ∑j=1Nwijrj(t) (Equation 38)τr,iṙi(t) = −ri(t) (Equation 39)Vpeak.i ~ * ^i^ik) Preset, i> ^i(j-ik) T 1 (Equation 40)To summarize, NPRNGs can be improved by implementing different or slightly different parameters for each neuron. This increases the complexity space of a brute-force search while requiring an attacker to determine both the neuronal parameters and the network parameters simultaneously to reproduce the output of an NPRNG. This can substantially increase the parameter complexity of an NPRNG, and increase the frequency of bit generation by forcing the Neuron’s to fire spikes at a faster rate with altered parameters.Improvement 2: Different Nonlinearities and heterogeneities in the Neurons

[0342] If we consider equations (34)-(36), we can also increase the complexity space associated with the network by incorporating neuronal heterogeneity at the functional level:Tm,i A = Ff (v, £) + k + wor7(t) (Equation 41 )Tr,jr;(t) = -n(t) (Equation 42)Vpeak.i ~ * ^i^ik) Preset, i> ^i^Xik) ^i^ik) + 1 (Equation 43)

[0343] In networks (41 )-(43), each neuron now has its own nonlinearity

[0344] parameterized by the vector of parameters pi. Each Fi may be a different nonlinearity specified by the index of neuron i, for example

[0345] or alternatively the nonlinearity Fi need not be explicitly parameterized by the index of neuron i, but can be dependent on i. For example, a subset of neurons in set S maybe of the adaptive exponential integrate and fire typeFi(v) = exp(v) − v, i ∈ S

[0346] while another subset in U maybe of the quadratic-integrate-and-fire type= (v - i e U

[0347] This again makes it difficult for an attacker to predict the output of an NPRNG as now, every neuron can be any type of nonlinearity in the network, rendering prediction of the output of the NPRNG more difficult as the weight matrix co is not sufficient.

[0348] For example, if there are a total of q possible discrete nonlinearities to choose from, then the complexity space increases multiplicatively withqN

[0349] By incorporating this improvement to the NRPNG design, an attacker would need to determine, neuron by neuron, which nonlinearity the neuron uses to encode the past history of spiking, in addition to determining the network parameters.Improvement 3: Different Synaptic Filters and Heterogeneities for the Neurons

[0350] This improvement is identical to 2, only applied to the synaptic filters:= Fj(vp ft) + It + w0-r7-(t) (Equation 44)Tr>ifi(t)=GiC-TCT), *;) (Equation 45)Vpeak.i ~ Preset, i> T 1 (Equation 46)

[0351] Here, once again, each synaptic filter has its own nonlinearity Gi(n, Ki) parameterized by Ki. The nonlinearities Gi can be chosen as in Improvement 2.Improvement 4: Higher Dimensional Neurons

[0352] In this improvement, the neuron’s are higher than 1 -dimensional integrate-and-fire neuronsWi = Fi(VpXpjSi) + k + ^=1wiJrJ(t') (Equation 47)xt= G(%j, Vi, ^) (Equation 48)Vi’iCO=Hitri. Ki) (Equation 49)Vpeak.i ~ * ^i^ik) Preset, i> ^i^Xik) ^i^ik) T 1 (Equation 50)

[0353] In this instantiation, each isolated neuron consists of the equationsTm,i = F((v(,xi> Pi) + (Equation 51 )xt= Gifxi, Vi, ^) (Equation 52)

[0354] where Xi is a vector of k-dynamical variables that impact a single neurons dynamics. This endows a single neuron with a much more complex dynamical repertoire. For example, the Izhikevich neuron can be written in a dimensionless form of the above with xt= Wi t), Pi = liFi(vi, Xi, fti) = Vi — Wi + p (Equation 53)GjCvj, = cii(biVi — wj (Equation 54)

[0355] where Ki = [ai, bi] is the vector of parameters associated with the dynamics of Wi. This can endow a single neuron with more complex dynamics, such as have subthreshold oscillations, displaying a resonance frequency, or displaying spikefrequency adaptation (a non-stationary firing rate). All of these dynamics can increase the dynamical complexity of a coupled network. This renders it more difficult for an attacker to determine the additional parameters / dimensions associated with a neuron.Improvement 5: Time-dependent neuronal parameters

[0356] In this improvement, all parameters can explicitly depend on time= FiCvpXp^Ct)) + A(t) + gLi^r / t) (Equation 55)xt= G(%j, Vi, <j(t)) (Equation 56)Trj(t)r;(t) = HL(rL, Kj(t)) (Equation 57)Vpeak.i (t) Vi(tik) Preset,;(t)< ^(4) = n(tik) + 1 (Equation 58)

[0357] This time dependence can occur, for example, by having the parameters change according to the previous spike history. In one instantiation, a parameter, p(t) increases or decreases by a discrete amount ePi k) = Vi ii + (- 1 / e (Equation 59)

[0358] where i denotes the index of the kth spike. In this instantiation, neuron’s are constantly evolving dynamically according to the previous spike history. This requires an attacker to dynamically determine the parameter history, rather than just the parameters associated with each neuron at one point in time in order to predict the output of an NPRNG.Improvement 6: Weight Plasticity

[0359] In this instantiation, every synaptic weight Wij(t) is plastic and varies with time, in a possibly activity dependent way, that may or may not respect the balanced network criteriaE(wtj) = 0, E(w?j) oc N-1

[0360] in time. The network equations, with all other improvements / modifications are:Tn.iCOA = FiC^Xp^Ct)) + Ii(t) + ^1 Wij(t)rj(t) (Equation 56)xt= G(%j, Vi, <j(t)) (Equation 57)Trj(t)r;(t) = HL(rL, Kj(t)) (Equation 58)Vpeak.i (t) Vi(tik) Preset,;(t)< ^(4) = n(tik) + 1 (Equation 59)

[0361] One example of activity dependent weights is spike-timing-dependent plasticity, where a pair of auxiliary variables, rP(t) and r0(t) implement an STDP-based rule:+Aro^tj) (Equation 60)=wkj(tkd + Tlrp(t^) (Equation 61)Improvement 7; NTRNGs

[0362] In the final instantiation, we’ll consider NTRNGs either in completely analog or mixed digital / analog implementation. In one instantiation, we may consider= FiC^Xp^Ct)) + A(t) + w0(t)r7(t) + Ai(t) (Equation 62)xt= G(xi, vi, Ct (t)) (Equation 63)Trj(t)r;(t) = Hi(ji, Kj(t)) (Equation 64)Vpeak.i (t) Vi(ttk) Preset,;(t)> n(4) = + 1 (Equation 65)

[0363] where Ai(t) is a noisy variable that comes from a true-random number generator (TRNG). The noisy signal Ai(t) may be sparsely applied, and not applied to every neuron, or only applied at the initial time step in a simulation. This would createa partially true random number generator which can be used for the creation of rolling codes / one-time-pads.

[0364] In another instantiation, we can consider a network of analog neurons composed of different circuit elementsC = I - 9L(EL- Vd - g^mlh^V, - ENJ - - Ek) - ^=1g^V - E^'n) (Equation 66)dnt_ noo(Vi') - ntdt Tn(7j)dht_ h^tVi) - hi dt Th(Vi')drtiimoo(Vt) ~mt dt ^m(Vi)dSi ^ooC^i')sidt Ts(Vi)

[0365] where we have a voltage difference for each neuron Vi, along with a capacitor (C) and circuit elements (e.g. resistors / memristors) that collectively implement a Hodgkin-Huxley network. The conductances go for the coupling variables scale similarly to the weights. The embodiments described above are intended to be exemplary only. The scope of the invention is therefore intended to be limited solely by the appended claims.

Claims

CLAIMS1. A computer-implemented method for pseudo-random number generation, comprising:- providing, in a memory, a neuron comprising a synaptic weight and a current state;- receiving, at an integrator block in communication with the memory, an initial spike signal;- determining, at the integrator block, a state change of the neuron based on the synaptic weight of the neuron and the initial spike signal;- determining, at a neuron block in communication with the integrator block, an updated state of the neuron based on the current state of the neuron and the state change of the neuron;- if the updated state of the neuron exceeds a predetermined threshold:- generating, at the neuron block, a subsequent spike signal;- determining, at a function block in communication with the neuron block, a pseudo-random function value based on the subsequent spike signal; and- determining, at an output block in communication with the function block, an output bit based on pseudo-random function value.

2. The method of claim 1, wherein the determining, at the output block, the output bit comprises:- determining the output bit by converting the pseudo-random function value using a Look-Up Table (LUT) and an index of the neuron corresponding to the subsequent spike signal.

3. The method of any one of claims 1 or 2, further comprising:- determining, at a synaptic filter block in communication with the integrator block, an hi[n + 1] value for the neuron; and- determining, at the synaptic filter block, an ri[n + 1] value for the neuron based on the hi[n + 1] value for the neuron; and- wherein the determining, at the neuron block, the updated state of the neuron is further based on the ri[n + 1] value for the neuron.

4. The method of any one of claims 1 to 3, wherein the determining, at the neuron block, the updated state of the neuron is further based on a bias value.

5. The method of any one of claims 1 to 4, further comprising:- storing the subsequent spike signal in a Serial-ln-Parallel-Out (SIPO) register.

6. The method of any one of claims 1 to 5 further comprising:- generating, at a control unit, one or more control signals to operate the integrator block, the neuron block, the function block and the output block.

7. The method of any one of claims 4 to 6, wherein the memory further comprises:- an input weight of the neuron;- and wherein the method further comprises:- determining, at a seed multiplication block in communication with the memory and the neuron block, an initialization value of the neuron based on a seed value and the input weight of the neuron;- determining, at the neuron block, an initial state of the neuron by using the initialization value of the neuron as the bias value.

8. The method of any one of claims 4 to 6, further comprises:- receiving a streaming input signal;- and wherein the method further comprises:- determining, at a seed multiplication block in communication with the memory and the neuron block, an initialization value of the neuron based on the streaming input signal;- determining, at the neuron block, an initial state of the neuron by using the initialization value of the neuron as the bias value.

9. The method of claim 8, wherein the streaming input signal comprises a 1D time series signal.

10. The method of any one of claims 1 to 7 wherein the determining, at the integrator block, the state change of the neuron further comprises:- determining, at a Multi-Layer Temporal (MLT) block of the accumulator block, a converted synaptic weight of the neuron; and- determining, at the accumulator block, the state change of the neuron based on the converted synaptic weight of the neuron, and the initial spike signal.

11. The method of any one of claims 1 to 8 wherein the memory further comprises:- a Spiking Neural Network (SNN) model comprising the neuron.

12. The method of claim 8 wherein the SNN model comprises a Leaky-Integrate-and-Fire (LIF) model.

13. The method of any one of claims 1 to 10 wherein at least one selected from the group of the control unit, the integrator block, the neuron block, the function block and the output block are implemented in a Field-Programmable Gate Array (FPGA).

14. A system for pseudo-random number generation, the system comprising a memory and a processor, the processor configured to provide the method of any one of claims 1 to 13.

15. The system of claim 12, further comprising an encryption application receiving the output bit.

16. The system of claim 12, further comprising a generative artificial intelligence application receiving the output bit.

17. The system of claim 12, further comprising a Monte-Carlo simulation application receiving the output bit.

18. A computer-readable program product for a processor, the computer-readable program product comprising instructions for the processor that when executed perform the method of any one of claims 1 to 13.

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