Small-footprint inductor-based filters

Abstract

The present disclosure provides various techniques for implementing compact inductor-based ladder filters using shared-footprint inductive structures in integrated circuits. In some embodiments, series and shunt LC resonators of bandpass and bandstop filters can be realized with polygonal or circular inductors disposed on different metal layers and arranged so that multiple inductors vertically stack while occupying substantially the same inductor footprint in plan view. Individual inductors can define complementary partial loops that collectively form a composite polygonal shape, thereby enabling dense nesting of resonators and controlled in-phase magnetic coupling between stacked inductors. The shared-flux technique can increase effective inductance relative to non-stacked implementations and supports substantial reduction of inductor area for a given filter specification. The disclosed layouts can also be scalable by repeating a unit-cell structure and, in some embodiments, by rotating successive inductors, to achieve higher order.

Description

Attorney Docket No. EMTAR8002WO PATENTSMALL-FOOTPRINT INDUCTOR-BASED FILTERSCROSS REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 752,580, filed January 31, 2025, titled “Scalable Chebyshev Bandpass / Bandstop Filter in Single-Inductor Footprints,” the disclosure of which is incorporated herein by reference in its entirety.TECHNICAL FIELD

[0002] The present disclosure relates generally to electronic circuit design, and more specifically, to layout design for inductor-based filters (e.g., Chebyshev bandpass filters and bandstop filters) that use on-chip inductors and other passive components.BACKGROUND

[0003] Radio frequency (RF) systems and their applications including, e.g., sixth-generation (6G) and beyond telecommunications networks, Wi-Fi systems, satellite and non-terrestrial networks (NTN), integrated sensing and communication (ISAC), vehicle-to-everything (V2X) systems, Internet-of-Things (loT) applications, industrial and private networks, defense and aerospace systems, and medical and wearable devices, have become an integral part of modern society. Bandpass filters (BPFs) and bandstop filters (BSFs) are widely used in RF and mixed-signal systems to provide channel selection, harmonic suppression, and interference rejection. With the continued evolution of wireless communication systems, filters integrated in complementary metal-oxide-semiconductor (CMOS) technologies must satisfy increasingly stringent requirements on selectivity, insertion loss, and noise, while occupying minimal silicon area.

[0004] On-chip inductors are commonly used to form resonators (e.g., inductor-capacitor (LC) resonators) in such filters. Some monolithic inductive structures (e.g., spiral inductors) have been employed due to their reasonable quality factor (Q) and predictable electromagnetic (EM) behavior. However, inductors are typically among the largest passive components on a chip. As LC filters scale toAttorney Docket No. EMTAR8002WO PATENThigher orders, e.g., with T-type or TT-type ladder configurations, each additional resonator generally introduces another inductor that consumes its own planar footprint. This cumulative area consumption presents a challenge for integrating multi-resonator filters in RF integrated circuits (RFICs), where layout density is critical.

[0005] Conventional filter techniques, when implemented in CMOS processes, often require long conductive paths and can exhibit additional insertion loss due to substrate and dielectric interactions. As a result, they may not provide meaningful area savings over lumped LC filters for on-chip integration. In addition, while some prior works have explored inductors placed on different metal layers to increase inductance, these structures are typically designed to function as single inductors and are not arranged to support compact multi-resonator filter topologies.Conventional layouts generally maintain separate inductor footprints for each resonator and do not facilitate meaningful sharing of planar area between inductors in different resonator sections.

[0006] Accordingly, traditional approaches remain limited by inductor area, layout scalability, and the challenges of implementing multi-resonator LC filters within restricted silicon footprints.BRIEF DESCRIPTION OF THE DRAWINGS

[0007] One or more embodiments of the present disclosure are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements. These drawings are not necessarily drawn to scale.

[0008] FIG. 1 shows a block diagram of an example transceiver front-end architecture in which one or more inductor-based filter structures disclosed here can be implemented.

[0009] FIG. 2A shows a circuit schematic of an example n-th order filter in a T-type ladder configuration with corresponding series and shunt LC resonators.

[0010] FIG. 2B shows a circuit schematic of an example n-th order filter in a TT-type ladder configuration with corresponding series and shunt LC resonators.

[0011] FIG. 3A shows a circuit schematic of an example third-order bandpass filter arranged in a T-type ladder configuration.Attorney Docket No. EMTAR8002WO PATENT

[0012] FIG. 3B shows two example physical layouts for the two series LC resonators of the bandpass filter in FIG. 3A, illustrating the inductors in plan view.

[0013] FIG. 3C shows an example physical layout for the shunt LC resonator of the bandpass filter in FIG. 3A, illustrating the inductor in plan view.

[0014] FIG. 3D shows an example physical layout for the bandpass filter in FIG. 3A, including polygonal inductors disposed around a shared inductor footprint region and the arrangement of capacitors associated with the series and shunt paths.

[0015] FIG. 4A shows a circuit schematic of an example fifth-order bandpass filter arranged in a T-type ladder configuration.

[0016] FIG. 4B shows example physical layouts for inductors associated with the series resonators of FIG. 4A, including polygonal inductors disposed around a shared inductor footprint region and corresponding capacitor placements.

[0017] FIG. 4C shows example schematic connection points for inductors of the shunt resonators of FIG. 4A, including their coupling to intermediate nodes and ground.

[0018] FIG. 4D shows a combined layout corresponding to the layouts in FIG.4B, illustrating polygonal inductors on different metal layers and their arrangement within a shared inductor footprint region.

[0019] FIG. 5A shows a circuit schematic of an example (2k— 1 )-th order bandpass filter arranged in a T-type configuration.

[0020] FIG. 5B shows an example physical layout for the bandpass filter in FIG. 5A, including multiple polygonal inductors arranged around a common central region and illustrating capacitor placements for the resonator stages.

[0021] FIG. 6A shows a circuit schematic of another example third-order bandstop T-type filter.

[0022] FIG. 6B shows example physical layouts for the inductors and capacitors associated with the series and shunt LC resonators of the bandstop filter in FIG. 6A, illustrating the inductors in plan view.

[0023] FIG. 6C shows an example combined physical layout for the bandstop filter in FIG. 6A, illustrating polygonal inductors arranged around a shared inductor footprint region with corresponding capacitor placements.Attorney Docket No. EMTAR8002WO PATENT

[0024] FIG. 7A shows a circuit schematic of an example fifth-order bandstop filter arranged in a T-type ladder configuration.

[0025] FIG. 7B shows example physical layouts for inductors associated with the series resonators of FIG. 7A, including polygonal inductors disposed around a shared inductor footprint region and corresponding capacitor placements.

[0026] FIG. 7C shows example schematic connection points for inductors of the shunt resonators of FIG. 7A, including their coupling to intermediate nodes and ground.

[0027] FIG. 7D shows an example combined physical layout for the bandstop filter in FIG. 7A, illustrating multiple inductors arranged around a shared inductor footprint region.

[0028] FIG. 8A shows a circuit schematic of another example (2k— 1 )-th order bandstop filter arranged in a T-type ladder configuration.

[0029] FIG. 8B shows an example physical layout for the bandstop filter in FIG. 8A, including multiple polygonal inductors arranged as nested or concentric shapes within a shared inductor footprint region.

[0030] FIG. 9A shows a non-stacked layout of two inductors.

[0031] FIG. 9B shows a simulated inductance value for one of the two inductors in FIG. 9A.

[0032] FIG. 10A shows a stacked layout of the two inductors of FIG. 9A.

[0033] FIG. 10B shows a simulated total inductance value for the two inductors in FIG. 10A.DETAILED DESCRIPTION

[0034] Filters are widely used in electronic systems to selectively pass desired frequency components while attenuating unwanted interference or noise. Such filters appear in numerous applications, including wireless transceivers, sensor interfaces, power-management circuits, and mixed-signal processing chains.Depending on system requirements, filters may be implemented using active or passive components, on-chip or off-chip structures, and a variety of topologies tailored to bandwidth, insertion loss, linearity, and area constraints.

[0035] However, as described above, conventional on-chip inductor-based filters (e.g., inductor-capacitor (LC) Chebyshev filters) are constrained by the planarAttorney Docket No. EMTAR8002WO PATENTfootprint required for their inductive elements. In complementary metal-oxide-semiconductor (CMOS) technologies, inductors are typically implemented as spiral or polygonal structures occupying substantial silicon area, and each LC resonator in a ladder filter generally requires its own dedicated inductor footprint. As the order of the filter increases, the number of inductors increases correspondingly, causing area usage to scale up rapidly. Existing approaches such as microstrip-line resonators, stepped-impedance structures, or multi-layer inductors have been explored, but these solutions either consume significant area, introduce undesirable loss mechanisms, or are unsuitable for compact multi-resonator filter topologies that must fit within strict layout constraints of radio-frequency integrated circuits (RFICs).These limitations pose challenges when implementing higher-order bandpass filters (BPFs), bandstop filters (BSFs), and other LC-based spectral shaping circuits in dense semiconductor environments.

[0036] Introduced here, therefore, are techniques that can be used to implement compact inductor-based LC filters through the use of vertically stacked inductors that occupy substantially the same inductor footprint when viewed in plan. In the disclosed embodiments, the inductors of different resonators can be arranged on different metal layers, in different rotational orientations, or both, so that they can be overlaid within a shared footprint region. Certain embodiments can further employ inductive conductors having partially polygonal shapes that complement one another such that, when the inductors are vertically stacked, their combined shape forms a substantially complete polygonal or circular geometry. Additional embodiments allow shunt-resonator inductors and higher-order resonator inductors to be stacked in the same shared footprint region, enabling multi-resonator filter topologies, such as T-type and n-type ladder structures, to be implemented in a significantly more compact physical layout.

[0037] The techniques disclosed here can enable multiple inductors to share planar area in a controlled electromagnetic configuration while retaining distinct electrical roles in their respective resonators. The approach can be extended to higher-order filters by stacking inductors of successive resonator stages on additional metal layers and by rotating their polygonal or circular geometries relative to one another, thereby enabling efficient packing of multiple resonators around a common footprint region. Furthermore, in certain embodiments, series and shunt LCAttorney Docket No. EMTAR8002WO PATENTresonators can connect at inter-inductor tabs or inter-capacitor tabs, further allowing flexible filter architectures to be realized in limited area. The disclosed stacking and shaping methods can be applied to both BPF and BSF configurations, and across a range of different filter orders.

[0038] Overall, the embodiments of the present disclosure can provide inductor-based filters with substantially reduced silicon footprint, improved layout scalability, and increased flexibility in designing higher-order resonator structures within modern RFIC technologies. By enabling inductors of different resonators to be placed within the same footprint region without compromising functionality, the disclosed techniques support the design of compact bandpass and bandstop filters that can be more easily integrated into area-constrained semiconductor devices.

[0039] Furthermore, with various aspects of the present disclosure (e.g., by vertically stacking and single-footprint integrating inductors across resonator stages), the embodiments introduced here can benefit from enhanced mutual inductance and controllable magnetic coupling between stacked inductive conductor patterns to increase the effective inductance achievable within a given planar area. As a result, higher-order filters having more cascaded resonators can be implemented with a vastly reduced footprint compared to conventional layouts that allocate a separate inductor footprint to each resonator stage. This increased order and resonator density can yield sharper transition regions, improved selectivity, and higher effective spectral resolution for both bandpass filter and bandstop filter embodiments, including by making the response curve closer to an ideal “brick-wall” characteristic for the designed frequencies to pass or to reject. In addition, in Chebyshev-type implementations, the ability to implement higher-order responses in a compact layout can allow the filter characteristics to be shaped to achieve reduced ripple (e.g., in the passband of a bandpass filter or the stopband of a bandstop filter, depending on the selected response type) while maintaining the desired attenuation targets and roll-off performance.

[0040] In the following, numerous specific details are set forth to provide a thorough understanding of the presently disclosed techniques. In other embodiments, the techniques introduced here can be practiced without these specific details. In other instances, well-known features, such as specific fabrication techniques, are not described in detail in order to avoid unnecessarily obscuring theAttorney Docket No. EMTAR8002WO PATENTpresent disclosure. References in this description to “an embodiment,” “one embodiment,” or the like, mean that a particular feature, structure, material, or characteristic being described is included in at least one embodiment of the present disclosure. Thus, the appearances of such phrases in this specification do not necessarily all refer to the same embodiment. On the other hand, such references are not necessarily mutually exclusive either. Furthermore, the particular features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments. Also, it is to be understood that the various embodiments shown in the figures are merely illustrative representations and are not necessarily drawn to scale.

[0041] Certain details relating to structures or processes commonly associated with the integrated circuit design, including physical layouts of typical passive components, e.g., inductors, capacitors, resistors, filters, and related subcomponents, may not be set forth in the following description, as inclusion of such well-known details could obscure significant aspects of the disclosed techniques. Moreover, although the following disclosure sets forth several embodiments of different aspects of the present disclosure, several other embodiments can have different configurations or different components than those described in this section. Accordingly, the introduced techniques can have other embodiments with additional elements or without several of the elements described below.

[0042] For purposes of discussion here, the terms “coupled” and “connected,” along with their derivatives, can be used to describe structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” can be used to indicate that two or more elements are in direct contact with each other. Unless otherwise made apparent in the context, the term “coupled” can be used to indicate that two or more elements are in either direct or indirect (with other intervening elements between them) contact with each other, or that the two or more elements co-operate or interact with each other (e.g., as in a cause and effect relationship), or both. Notwithstanding the above, and unless otherwise specified or made clear by the context, references to components being “connected in series” orAttorney Docket No. EMTAR8002WO PATENT“connected in parallel” refer to their functional electrical relationship rather than requiring uninterrupted physical conductors.

[0043] For purposes of discussion here, the terms “plan view,” “viewed in plan,” “top view,” and “top plan view,” or wording to the equivalent, refer to a view of an integrated circuit layout projected onto a plane parallel to the surface of the semiconductor wafer, without regard to the vertical positions of elements on different metal layers. In such a view, elements disposed on different layers may appear to overlap or coincide, even though they can be physically separated in the vertical direction.

[0044] For purposes of discussion here, the terms “vertical” and “horizontal” are defined with respect to the surface of a semiconductor wafer on which an integrated circuit is fabricated. A vertical direction refers generally to a direction normal (perpendicular) to the plane of the wafer, while a horizontal direction refers generally to a direction parallel to the plane of the wafer.

[0045] For purposes of discussion here, the term “resonator” refers to a circuit element that exhibits a resonant impedance characteristic. A resonator can include an inductor, a capacitor, a resistor, or a suitable combination thereof.

[0046] For purposes of discussion here, the term “complementary in shape” refers to two or more geometric shapes that, when combined, overlapped, or arranged together (e.g., by vertical stacking and viewed in plan) collectively form a larger geometric pattern having an overall shape. The individual shapes need not be identical, symmetric, or continuous by themselves, and can include partial polygonal or circular segments, so long as their combined arrangement defines the intended composite shape.

[0047] For purposes of discussion here, the term “substantially the same inductor footprint” means that two or more inductors occupy largely overlapping planar regions (e.g., of an integrated circuit) and, when viewed in plan, even if the inductors are implemented on different metal layers, have different internal routing, or differ in minor geometric details. Inductors may be considered to occupy substantially the same footprint even if their outer boundaries are not perfectly coincident, provided that they are confined to a common footprint region.

[0048] For purposes of discussion here, the term “primarily,” when used to describe the disposition of a component on a particular layer or in a particularAttorney Docket No. EMTAR8002WO PATENTorientation, means that a larger portion of the component is disposed on that layer or in that orientation than on any other single layer or orientation, even if less than a majority of the component is so disposed.

[0049] For purposes of discussion here, “coplanar expansion” refers to implementing an inductor by extending an inductive conductor laterally within a same metal layer (or within a same set of metal layers without vertical stacking) in an X direction and / or a Y direction of the integrated circuit so as to increase inductive conductor length and / or to implement additional resonator sections.

[0050] For purposes of discussion here, “vertical stacking” refers to implementing inductive conductors on different metal layers and aligning at least a portion of those inductive conductors such that they overlap in plan view and occupy substantially a same planar footprint, while being separated by one or more interlayer dielectric regions.

[0051] FIG. 1 illustrates an example transceiver front-end architecture 100 in which one or more inductor-based filter structures disclosed here may be implemented. The transceiver front-end architecture 100 includes a receiver signal path and a transmitter signal path, each coupled to a shared antenna 190 through a transmit / receive (T / R) switch 180, a duplexer (not shown), or other suitable antenna interface components. As shown in FIG. 1 , filters can be incorporated into such front-end architectures to pass desired in-band signals while attenuating out-of-band interference, thereby improving overall system linearity, selectivity, and noise performance.

[0052] On the receiver side, radio-frequency (RF) signals received at the antenna 190 can be routed through the T / R switch 180 to a low-noise amplifier (LNA) 110. The LNA 110 can amplify weak incoming RF signals while adding minimal noise. The amplified RF signal is then provided to a bandpass filter 120, which can include one or more LC resonators arranged in a ladder or similar topology. Placing the bandpass filter 120 after the LNA 110 can help control the cumulative receiver noise figure by suppressing out-of-band interferers before they propagate into downstream circuitry. Because degradation of noise figure in the receiver path is particularly critical, the location of the bandpass filter 120 is selected to mitigate noise contributions from subsequent stages as well as to reduce sensitivity to accumulated distortion.Attorney Docket No. EMTAR8002WO PATENT

[0053] The filtered RF signal is then supplied to a mixer 130, which downconverts the RF signal to an intermediate-frequency (IF) signal using a local oscillator signal generated by a voltage-controlled oscillator (VCO) 140. Additional baseband or IF signal processing stages can follow, depending on the implementation.

[0054] On the transmitter side, an IF signal is up-converted to RF by a mixer 150, which can also use a local oscillator signal generated by the VCO 140. The up-converted RF signal then can be filtered by a bandpass filter 160, which can likewise employ inductor-based LC filter structures as disclosed here. Because the signal amplitude in the transmitter path is generally high, the noise contribution of the bandpass filter 160 can be negligible in comparison to the downstream power amplifier (PA) 170 gain, and the filter’s primary role is instead to suppress unwanted spectral components and meet emission mask requirements. After filtering, the RF signal is amplified by the PA 170 and routed through the T / R switch 180 to the antenna 190 for transmission.

[0055] It is noted that the bandpass filter 120 in the receiver path and the bandpass filter 160 in the transmitter path are representative logical locations within the transceiver front-end architecture 100 where the compact inductor-based filter techniques disclosed herein may be deployed. Besides their placement in the signal chain, the design of the bandpass filters 120 and 160 can involve additional considerations. For example, in addition to or as an alternative to the embodiments shown in FIG. 1 where the filters 120 and 160 are respectively employed at the RF stage between the mixer and a front-end power amplifier (PA) or low-noise amplifier (LNA), some other embodiments may implement the filters at an IF stage, with the filters respectively positioned after the mixer in a receiver signal path and before the mixer in a transmitter signal path, depending on the particular application requirements.

[0056] Passive filter implementations are advantageous in applications requiring low power consumption, reconfigurability, and reduced thermal sensitivity. However, as described above, one of the main challenges in implementing passive LC filters in CMOS technologies is the substantial silicon area consumed by on-chip inductors. Inductors are typically realized as spiral or polygonal structures, and each LC resonator section generally requires its own dedicated inductor footprint. AsAttorney Docket No. EMTAR8002WO PATENThigher-order filters are used to achieve increased roll-off rates, the number of LC sections increases, leading to a corresponding growth in total inductor area. This area scaling presents a significant bottleneck to realizing ideal higher-order filters within integrated transceiver architectures.

[0057] To address this issue, example resonator structures, filter schematics, and physical layout techniques that reduce overall inductor footprint while supporting a range of filter orders and configurations are introduced in the present disclosure in more detail below.

[0058] FIG. 2A shows a circuit schematic of an example n-th-order filter 200 arranged in a T-type ladder configuration with corresponding series and shunt LC resonators. FIG. 2B shows a circuit schematic of an example n-th-order filter 205 arranged in a n-type ladder configuration with corresponding series and shunt LC resonators. These figures illustrate representative ladder-filter platforms in which higher-order passive filtering functions may be implemented. These platforms are some of the examples in which the techniques disclosed here can be applied.

[0059] As discussed above, implementing high-order filters on a CMOS substrate can be challenging due to the dielectric loss of silicon and the comparatively large footprint required for on-chip spiral inductors. Substrate loss significantly reduces the quality factor (Q) of the inductors and contributes to degraded insertion loss and limited selectivity. These issues become increasingly pronounced in higher-order filters used in radio frequency (RF), millimeter-wave, terahertz (THz), and emerging 6G and beyond communication systems, where sharp roll-off and strong stopband attenuation are critical. While many designs have adopted stub-based or coupled-line transmission-line structures, such implementations occupy substantial chip area and introduce additional loss due to their electrical length, which further limits the achievable filter order and performance.

[0060] To address these challenges, ladder-type filters can be implemented using cascaded series and shunt LC resonators, such as shown in FIGS. 2A and 2B. Such structures can realize Chebyshev bandpass or bandstop responses, with ripple characteristics appearing in either the passband or stopband depending on the selected Chebyshev type. Compared to transmission-line-based approaches, theAttorney Docket No. EMTAR8002WO PATENTlumped LC resonator sections of FIGS. 2A and 2B can offer a more area-efficient and integration-friendly path for realizing higher-order responses.

[0061] Referring to FIG. 2A in more detail, the T-type ladder filter 200 includes resonators 230(1) through 230(n) disposed between an input port P1 and an output port P2. These resonators may be characterized according to the manner in which they are incorporated into the ladder network. Among them, series resonators are those that are connected in series and positioned directly along the signal path and include, for example, resonators 230(1), 230(3), ..., 230(n). Each series resonator can include a capacitor and an inductor connected in series. For instance, resonator 230(1) includes capacitor 210(1) and inductor 220(1), resonator 230(3) includes capacitor 210(3) and inductor 220(3), and resonator 230(n) includes capacitor 210(n) and inductor 220(n). Shunt resonators are coupled between the intermediate ladder nodes and ground and include, for example, resonators 230(2), ..., 230(n-1). Each shunt resonator includes a capacitor and an inductor connected in shunt. For instance, resonator 230(2) includes capacitor 210(2) and inductor 220(2), and resonator 230(n-1 ) includes capacitor 210(n-1 ) and inductor 220(n-1 ). Appropriate selection of the LC values within these resonators can allow the designer to shape the desired Chebyshev response and, in many cases, to introduce transmission zeros in the stopband, thereby improving harmonic rejection, which is a desirable feature for mitigating substrate-induced loss in CMOS processes.

[0062] Turning to FIG. 2B, the n-type ladder filter 205 also includes a group of resonators 235(1) through 235(n), but the placement of the series and shunt resonators is inverted relative to the T-type configuration in FIG. 2A. In this n-type topology, shunt resonators 235(1), 235(3), ..., 235(n) are connected between the ladder nodes and ground. Each shunt resonator includes a capacitor and a inductor that are connected in shunt. For example, resonator 235(1 ) includes capacitor 215(1 ) and inductor 225(1 ), resonator 235(3) includes capacitor 215(3) and inductor 225(3), and resonator 235(n) includes capacitor 215(n) and inductor 225(n). Series resonators 235(2), ..., 235(n— 1 ) are connected in series and disposed along the signal path between P1 and P2, and each includes a respective capacitor and inductor connected in series. For example, resonator 235(2) includes capacitor 215(2) and inductor 225(2), and resonator 235(n— 1 ) includes capacitor 215(n— 1) and inductor 225(n— 1 ). As with the T-type configuration, this n-type structure is capableAttorney Docket No. EMTAR8002WO PATENTof implementing Chebyshev bandpass or bandstop responses and can be selected based on impedance-matching considerations, insertion-loss requirements, or layout preferences.

[0063] Across both ladder configurations, inductors can constitute the dominant contributors to on-chip area and exert significant influence over insertion loss and filter selectivity due to their limited Q factor on CMOS substrates. The need to allocate substantial chip area for inductors has historically restricted the flexibility, performance, and achievable order of integrated bandpass and bandstop filters. These constraints provide the motivation for the compact inductor structures and layout techniques described in the following sections, which can be incorporated into filter architectures of the type illustrated in FIGS. 2A and 2B to reduce area and improve performance. Note that, for simplicity, the following discussion focuses on T-type ladder filters; however, the techniques introduced here are similarly applicable to TT-type ladder filter configurations.

[0064] FIG. 3A illustrates a circuit schematic of an example third-order bandpass filter 300 arranged in a T-type ladder configuration. The third-order bandpass filter 300 includes a first series LC resonator 330(1) formed by a first capacitor 310(1) (C1 ) and a first inductor 320(1 ) (L1 ) coupled between a first port P1 and an intermediate node 340, a second series LC resonator 330(3) formed by a third capacitor 310(3) (C3) and a third inductor 320(3) (L3) coupled between the intermediate node 340 and a second port P2, and a shunt LC resonator 330(2) formed by a second capacitor 310(2) (C2) and a second inductor 320(2) (L2) coupled between the intermediate node 340 and ground. On the left side of FIG. 3A, the resonators 330(1), 330(2), and 330(3) depict a T-type resonator structure connected at the intermediate node 340 between the input and output ports. This third-order T-type configuration can serve as a fundamental unit cell that can be extended and replicated to realize higher-order bandpass filters, as discussed with respect to various figures below.

[0065] FIG. 3B shows example physical layouts for the series LC resonators of the third-order bandpass filter 300, illustrating the first inductor 320(1) and the third inductor 320(3) in plan view. In the illustrated embodiment, each of the first inductor 320(1) and the third inductor 320(3) is implemented as a polygonal inductive conductor patterned on one or more metal layers of an integrated circuit. TheAttorney Docket No. EMTAR8002WO PATENTinductive conductors follow generally octagonal paths and are dimensioned to fit within a defined inductor footprint region. The upper portion of FIG. 3B schematically illustrates the first capacitor 310(1), the first inductor 320(1), and the intermediate node 340 in the first series LC path between the port P1 and the intermediate node 340, and the third capacitor 310(3), the third inductor 320(3), and the intermediate node 340 in the second series LC path between the intermediate node 340 and the port P2. As shown in FIG. 3B, in one or more implementations, the polygonal inductive conductor of the first inductor 320(1) can form only a partial portion of a full octagonal loop, and the polygonal inductive conductor of the third inductor 320(3) can form a complementary partial portion of the same octagonal loop. In this way, each of the first inductor 320(1) and the third inductor 320(3) has a shape that is partially polygonal, and the shapes are substantially complementary to one another.

[0066] Note that, in some embodiments, an inductive conductor pattern can be three-dimensional in nature and can extend across multiple metal layers. For example, in the layout of FIG. 3B, the first inductor 320(1) may be implemented primarily in a single metal layer, whereas the third inductor 320(3) may include conductor segments on two different metal layers that are connected together through a bridge section 350. The bridge section 350 can be implemented using one or more vertical conductors, such as a stack of metal vias and local interconnect segments, to electrically join the conductor segments on the different layers and thereby complete the inductive conductor pattern of the third inductor 320(3). This three-dimensional routing technique can allow the first inductor 320(1) and the third inductor 320(3) to cross or overlap in plan view without being unintentionally shorted together, while still enabling the single-footprint inductor layout techniques described in the present disclosure. Similar three-dimensional inductor implementations can be used in other embodiments wherever context permits (e.g., where there may be an “X” shape in the pattern when viewed in plan).

[0067] Although the layouts for the first inductor 320(1 ) and the third inductor 320(3) are illustrated side by side in FIG. 3B for clarity, they are configured so that, in an implemented design, they can be overlaid to occupy substantially the same inductor footprint when viewed in plan. Specifically, in some embodiments, the first inductor 320(1) and the third inductor 320(3) can be formed on different metal layers and / or in different rotational orientations and arranged such that the partial octagonalAttorney Docket No. EMTAR8002WO PATENTshapes defined by their respective inductive conductors together trace a composite inductive conductor pattern that is substantially a complete polygonal loop. For example, in the layouts shown in FIG. 3B, the polygonal inductive conductor of the first inductor 320(1) is routed in a generally counter-clockwise direction, whereas the polygonal inductive conductor of the third inductor 320(3) is routed in a generally clockwise direction, thereby providing different rotational orientations within a common inductor footprint region. In some embodiments, the composite polygonal loop is substantially symmetrical in geometry, for example forming an approximately regular square, hexagon, octagon, or circle when viewed in plan. This layout strategy allows the two series-path inductors to be vertically stacked and share planar area while still providing independent connections between the first capacitor 310(1) and the intermediate node 340, and between the third capacitor 310(3) and the intermediate node 340, at the periphery of the shared region. In this way, the series LC sections can form an extendable unit cell whose inductors are prepared for single-footprint implementation.

[0068] FIG. 3C illustrates an example physical layout for the shunt LC resonator of the third-order bandpass filter 300, showing the second capacitor 310(2) and the second inductor 320(2) in plan view. The upper portion of FIG. 3C schematically depicts a parallel LC path connected between the intermediate node 340 and ground through the second capacitor 310(2) and the second inductor 320(2). The second inductor 320(2) can be implemented as a polygonal inductive conductor, following a loop that can surround or partially envelop the composite polygonal region associated with the first inductor 320(1) and the third inductor 320(3). In some embodiments, the shape of the second inductor 320(2) at least partially tracks the outline of the complete polygonal shape formed together by the first inductor 320(1) and the third inductor 320(3), so that the second inductor 320(2) can be placed in close proximity and share substantially the same inductor footprint region when viewed in plan. The second capacitor 310(2) is coupled between the intermediate node 340 and a reference potential (e.g., an underlying ground plane), and it can be implemented as a metal-insulator-metal capacitor or another type of integrated capacitor structure. The second capacitor 310(2) can be located near a portion of the polygonal path of the second inductor 320(2) so that the shunt LCAttorney Docket No. EMTAR8002WO PATENTresonator connects to the intermediate node 340 through a relatively short routing path.

[0069] FIG. 3D shows an example combined physical layout for the third-order bandpass filter 300, illustrating how the first inductor 320(1), the second inductor 320(2), and the third inductor 320(3) can be integrated into a shared inductor footprint region together with the first capacitor 310(1 ), the second capacitor 310(2), the third capacitor 310(3), and the intermediate node 340. In the illustrated embodiment, the polygonal inductive conductor of the second inductor 320(2) can form an outer loop, while the polygonal inductive conductors of the first inductor 320(1) and the third inductor 320(3) form inner loops that are located within the outer loop. The partial polygonal shapes of the first inductor 320(1 ) and the third inductor 320(3) are arranged so that, when the inductors are vertically stacked and viewed in plan, they together define a composite inductive conductor pattern that is substantially a complete polygonal shape. In some implementations, the composite inductive conductor pattern can exhibit two (or more) substantially concentric octagonal loops corresponding to the first inductor 320(1) and the third inductor 320(3), and further with the second inductor 320(2) having a polygonal shape that at least partially tracks the outer boundary of the composite octagonal region. The intermediate node 340 can be located at the junction where the series LC paths between the port P1 and the port P2 meet and where the second capacitor 310(2) connects to the second inductor 320(2) toward ground.

[0070] According to one or more embodiments, the first inductor 320(1 ), the second inductor 320(2), and the third inductor 320(3) can be disposed on different metal layers such that they are vertically stacked while occupying substantially the same inductor footprint when viewed in plan. It is noted in the present disclosure that, because the first inductor 320(1) and the third inductor 320(3) are vertically stacked in this shared region, their magnetic fields can be arranged to share magnetic flux, which can in turn increase an effective inductance experienced by each stacked inductor compared to a corresponding non-stacked layout.

[0071] Overall, the combined layout shown in FIG. 3D shows an example implementation of single-footprint (or small-footprint) inductor-based filter techniques introduced in the present disclosure, in which multiple inductors belonging to different resonators can be confined to substantially the same planar region byAttorney Docket No. EMTAR8002WO PATENTstacking the inductors on different metal layers and selecting complementary polygonal geometries. By implementing the third-order bandpass filter 300 in this manner, the need to allocate separate inductor footprints for each resonator can be reduced or even eliminated, thereby decreasing the overall chip area devoted to inductors and creating an extendable unit cell that can be reused when constructing higher-order filters, while maintaining predictable inductance, coupling, and qualityfactor characteristics suitable for radio-frequency integrated circuits.

[0072] FIG. 4A illustrates a circuit schematic of an example fifth-order bandpass filter 400 arranged in a T-type ladder configuration. The fifth-order bandpass filter 400 builds on the third-order bandpass filter 300 of FIG. 3A by adding one additional series LC section and one additional shunt LC section. On the left side of FIG. 4A, resonator sections schematically represent a T-type ladder with three series resonator sections (i.e., resonators 430(1), 430(3), and 430(5)) and two shunt resonator sections (i.e., resonators 430(2) and 430(4)) coupled between ports P1 and P2. A first intermediate node 440 and a second intermediate node 442 are located between adjacent series sections and serve as connection points for the shunt resonators. On the right side of FIG. 4A, a first series LC resonator 430(1) formed by a first capacitor 410(1 ) (C1 ) and a first inductor 420(1 ) (L1 ) is coupled between the port P1 and the first intermediate node 440, a second series LC resonator 430(3) formed by a third capacitor 410(3) (C3) and a third inductor 420(3) (L3) is coupled between the first intermediate node 440 and the second intermediate node 442, and a third series LC resonator 430(5) formed by a fifth capacitor 410(5) (C5) and a fifth inductor 420(5) (L5) is coupled between the second intermediate node 442 and the port P2.

[0073] In addition, a first shunt LC resonator 430(2) formed by a second capacitor 410(2) (C2) and a second inductor 420(2) (L2) can be coupled between the first intermediate node 440 and ground. A second shunt LC resonator 430(4) formed by a fourth capacitor 410(4) (C4) and a fourth inductor 420(4) (L4) can be coupled between the second intermediate 442 and ground. Accordingly, the third series LC resonator 430(5) and the second shunt LC resonator 430(4) together form an additional pair of resonators relative to the third-order bandpass filter 300, thereby increasing an order of the filter circuit from third order to fifth order.Attorney Docket No. EMTAR8002WO PATENT

[0074] FIG. 4B shows example physical layouts for inductors associated with the series LC resonators of the fifth-order bandpass filter 400, including polygonal inductors disposed around a shared inductor footprint region and corresponding capacitor placements. The layouts in FIG. 4B correspond to the three series resonator sections 430(1), 430(3), and 430(5) shown schematically in FIG. 4A.

[0075] In FIG. 4B, the left-hand layout corresponds to the first series LC resonator 430(1 ) and includes the first inductor 420(1 ) implemented as a polygonal inductive conductor connected together in series with the first capacitor 410(1), which couples the first inductor 420(1 ) to the port P1. The polygonal path of the first inductor 420(1) includes a connection point corresponding to the first intermediate node 440, which is the node at which the first series resonator 430(1 ) connects to the first shunt resonator 430(2) and to the second series resonator 430(3).

[0076] The central layout of FIG. 4B corresponds to the second series LC resonator 430(3) and includes the third inductor 420(3) implemented as a polygonal inductive conductor connected together in series with the third capacitor 410(3). In this layout, the first intermediate node 440 is located at one end of the polygonal path of the third inductor 420(3), and the second intermediate node 442 is located at the opposite end of the polygonal path. These two connection points 440 and 442 illustrate how the second series resonator 430(3) is coupled between the first intermediate node 440 and the second intermediate node 442 in the ladder structure of FIG. 4A. In some embodiments, the third inductor 420(3) can include a bridge section 450 that connects conductor segments implemented on different metal layers, thereby completing the inductive conductor pattern while avoiding unintended electrical shorts to adjacent inductors in the shared footprint region.

[0077] The right-hand layout of FIG. 4B corresponds to the third series LC resonator 430(5) and illustrates the fifth inductor 420(5) implemented as a polygonal inductive conductor connected together in series with the fifth capacitor 410(5), which couples the fifth inductor 420(5) to the port P2. The second intermediate node 442 is located on the polygonal path of the fifth inductor 420(5), showing where the third series resonator 430(5) connects to the previous parts of the ladder. In the illustrated embodiment, the fifth inductor 420(5) follows a multi-loop polygonal path and may include a bridge section 452 that enables portions of the inductive conductor to be routed on different metal layers. Moreover, in certain embodiments,Attorney Docket No. EMTAR8002WO PATENTthe layout of the fifth inductor 420(5) can be rotated relative to the layouts of the first inductor 420(1 ) and the third inductor 420(3), e.g., by approximately 90 degrees, which can facilitate efficient and easier nesting of multiple series-path inductors within a common inductor footprint region while preserving the required electrical connections to the capacitors 410(3) and 410(5).

[0078] FIG. 4C shows example schematic connection points for inductors associated with the shunt LC resonators of FIG. 4A. On the left side of FIG. 4C, the first intermediate node 440 is shown as the connection point for the first shunt LC resonator 430(2), which includes the second capacitor 410(2) (C2) and the second inductor 420(2) (L2) coupled between the first intermediate node 440 and ground. On the right side of FIG. 4C, the second intermediate node 442 is shown as the connection point for the second shunt LC resonator 430(4), which includes the fourth capacitor 410(4) (C4) and the fourth inductor 420(4) (L4) coupled between the second intermediate node 442 and ground. It is noted that FIG. 4C is to clarify the electrical connection topology of the shunt resonators in the layout rather than to illustrate detailed physical inductor layouts; in various embodiments, the inductors 420(2) and 420(4) can be implemented using polygonal inductive conductor layout techniques similar to those described for resonators above.

[0079] FIG. 4D shows an example combined physical layout for the fifth-order bandpass filter 400, illustrating how the series-path inductors of FIG. 4B and the shunt-resonator connection points of FIG. 4C can be integrated into a shared inductor footprint region. The embodiment in FIG. 4D is explained with simultaneous reference to FIGS. 4A-4C.

[0080] On the left side of FIG. 4D, a simplified T-type ladder schematic highlights the three series resonator sections and two shunt resonator sections between the ports P1 and P2, with the first intermediate node 440 and the second intermediate node 442 indicated. On the right side of FIG. 4D, multiple polygonal inductive conductors corresponding to the inductors 420(1), 420(3), and 420(5) are arranged around a common central region. In one or more embodiments, the inductors 420(1), 420(3), and 420(5) can be disposed on different metal layers such that they are vertically stacked while occupying substantially the same inductor footprint when viewed in plan.Attorney Docket No. EMTAR8002WO PATENT

[0081] Specifically, in some embodiments, the fifth inductor 420(5) of the additional series LC resonator 430(5) can be vertically stacked with one or more inductors of lower-order series resonators, including the first inductor 420(1) and the third inductor 420(3), by disposing the fifth inductor 420(5) on an additional metal layer while maintaining substantially the same inductor footprint. When vertically stacked in this manner, the fifth inductor 420(5) can be positioned such that its magnetic field overlaps with magnetic fields generated by the first inductor 420(1 ) and the third inductor 420(3), thereby causing the inductors to share magnetic flux. According to some embodiments, the stacked inductors can be arranged for in-phase magnetic coupling, so that the shared magnetic flux increases an effective inductance of each of the stacked inductors relative to a corresponding non-stacked implementation.

[0082] The shunt inductors 420(2) and 420(4) are coupled to the shared layout through the first and second intermediate nodes 440 and 442, respectively, so that both shunt resonators fit within or closely around the same footprint used by the series-path inductors. In various embodiments, by utilizing the single-footprint layout techniques disclosed here, the shunt inductors 420(2) and 420(4) can also be disposed on metal layers different from those of the series inductors and can at least partially track the outline of the shared polygonal footprint region, enabling further area reuse without compromising the electrical separation between resonator sections.

[0083] Accordingly, as shown in the embodiments in FIGS. 4A-4D, the singlefootprint inductor-based techniques introduced in the present disclosure can be scalable to higher-order filter implementations. By adding an additional pair of resonators and vertically stacking the additional series inductor with inductors of lower-order resonators while sharing magnetic flux and occupying substantially the same inductor footprint, the fifth-order bandpass filter 400 can achieve improved selectivity and sharper roll-off while remaining suitable for integration in area-constrained radio-frequency integrated circuits.

[0084] FIG. 5A illustrates a circuit schematic of an example (2k— 1 )-th order bandpass filter 500 arranged in a T-type ladder configuration. The schematic shows a number of series LC resonators coupled in series between a first port P1 and a second port P2, and a number of shunt LC resonators coupled to ground fromAttorney Docket No. EMTAR8002WO PATENTintermediate nodes between adjacent series resonators. Shunt LC resonators can be coupled from inter-inductor nodes or inter-capacitor nodes along the ladder. It is noted here that FIG. 5A is to illustrate the electrical scalability of the ladder topology to higher odd-order bandpass filters; details that are similar to those described with respect to FIGS. 3A and 4A are not repeated here for simplicity.

[0085] FIG. 5B shows an example physical layout 505 implementing the (2k— 1 )-th order bandpass filter 500 of FIG. 5A using the single-footprint inductorbased layout techniques introduced with respect to FIGS. 3B-3D as well as in FIGS.4B-4D. In the illustrated embodiment, inductors associated with multiple series resonator stages can be implemented as polygonal inductive conductors disposed on different metal layers and vertically stacked so as to occupy substantially the same inductor footprint when viewed in plan. In some embodiments, the inductors can be laid out using substantially symmetrical polygonal geometries, which simplifies repetition of a unit-cell profile and facilitates predictable extension of the layout to higher-order filter implementations.

[0086] More specifically, similar to the embodiments described in FIG. 3B, individual inductors may each define only a partial polygonal or circular shape.When vertically stacked and viewed in plan, the partial shapes of inductors associated with different resonator stages can be substantially complementary, such that they collectively define a composite inductive conductor pattern that is substantially a complete and symmetrical polygonal or circular shape. In some implementations, the composite pattern can include nested or substantially concentric polygonal loops, enabling multiple inductors to share a common footprint region. In addition, and as introduced in the higher-order implementation of FIG. 4B, inductors associated with successive series resonators in FIG. 5B can be disposed on additional metal layers and, in some embodiments, arranged in different rotational orientations relative to inductors of lower-order resonators. Such rotational arrangements facilitate dense nesting of multiple inductors within a common footprint region and simplify routing of series capacitors while preserving electrical isolation between resonator stages. As shown in FIG. 5B, an inductor associated with a higher-order series resonator in FIG. 5B can be rotated, when viewed in plan, relative to an inductor of a lower-order series resonator by approximately 90Attorney Docket No. EMTAR8002WO PATENTdegrees, 180 degrees, or 270 degrees, so as to facilitate vertical stacking of successive resonator stages within the shared inductor footprint region.

[0087] Also, similar to those described with respect to FIGS. 3B and 4B, series capacitors associated with the series LC resonators can be routed from the shared inductor footprint region and integrated into the layout 505 without requiring dedicated planar areas comparable to the inductors. In addition, in some embodiments, the series capacitors can be merged into portions of the layout 505 corresponding to different rotational orientations of the stacked inductors, thereby enabling the series capacitors to be integrated within or adjacent to the same footprint region occupied by the inductors.

[0088] In one or more embodiments, shunt LC resonators in FIG. 5B can be coupled from the shared footprint region through inter-inductor and / or inter-capacitor connection points. For simplicity, the physical layouts of the shunt capacitors are not shown here. In various embodiments, each shunt capacitor (e.g., C2k) can be implemented as a metal-insulator-metal capacitor or as a coupling capacitor between a corresponding shunt inductor and an underlying ground plane.

[0089] As in the embodiments described with respect to FIGS. 3 and 4, vertically stacked inductors in FIG. 5B can be arranged to share magnetic flux. In a number of embodiments, by selecting the relative metal-layer ordering, vertical spacing, and polygonal geometry of the stacked inductors, the magnetic coupling factor between inductor levels can be controlled. In some embodiments, the stacked inductors can be arranged for in-phase magnetic coupling, increasing the effective inductance of each stacked inductor and enabling further miniaturization of higher-order filter implementations.

[0090] Overall, the embodiment shown in FIG. 5B can extend the disclosed layout methodology to higher-order bandpass filters by repeating a common unit-cell profile and stacking additional inductors within substantially the same planar footprint. This approach therefore can support scalable LC ladder filter designs that achieve improved selectivity and roll-off without proportional increases in inductor area, making the topology well suited for integration in area-constrained radiofrequency integrated circuits.

[0091] FIG. 6A illustrates a circuit schematic of an example third-order bandstop filter 600 arranged in a T-type ladder configuration. The third-orderAttorney Docket No. EMTAR8002WO PATENTbandstop filter 600 includes a first series resonator 630(1 ) formed by a first inductor 620(1 ) (L1 ) and a first capacitor 610(1) (C1 ) coupled between a first port P1 and an intermediate node 640, a second series resonator 630(3) formed by a third inductor 620(3) (L3) and a third capacitor 610(3) (C3) coupled between the intermediate node 640 and a second port P2, and a shunt resonator 630(2) formed by a second inductor 620(2) (L2) and a second capacitor 610(2) (C2) coupled between the intermediate node 640 and ground. In this bandstop configuration, each series resonator is implemented as a parallel LC resonator, while the shunt resonator is implemented as a series LC resonator, such that the filter presents a high impedance in a stopband and a low impedance outside the stopband.

[0092] More specifically, on the left side of FIG. 6A, the resonators 630(1), 630(2), and 630(3) schematically depict a T-type resonator structure connected at the intermediate node 640 between the input and output ports. This third-order T-type bandstop configuration corresponds structurally to the third-order bandpass configuration of FIG. 3A, with the roles of series and shunt capacitors interchanged to achieve a stopband response rather than a passband response.

[0093] FIG. 6B shows example physical layouts for the resonators of the third-order bandstop filter 600, illustrating the first inductor 620(1), the second inductor 620(2), and the third inductor 620(3) in plan view together with their associated capacitors. The left portion of FIG. 6B corresponds to the first series resonator 630(1) and shows the first inductor 620(1) implemented as a polygonal inductive conductor together with the first capacitor 610(1), which is connected in parallel with the first inductor 620(1) between the port P1 and the intermediate node 640. The polygonal path of the first inductor 620(1 ) can define only a partial portion of a polygonal loop and is dimensioned to fit within a predefined inductor footprint region.

[0094] The center portion of FIG. 6B corresponds to the second series resonator 630(3) and shows the third inductor 620(3) implemented as a polygonal inductive conductor together with the third capacitor 610(3), which is connected in parallel with the third inductor 620(3) between the intermediate node 640 and the port P2. Similar to the embodiments described with respect to FIG. 3B, the polygonal inductive conductor of the third inductor 620(3) can form a complementary partial portion of the same polygonal loop as the first inductor 620(1 ). In some embodiments, the third inductor 620(3) can include a bridge section 650 thatAttorney Docket No. EMTAR8002WO PATENTconnects conductor segments implemented on different metal layers, allowing the inductive conductor pattern to be completed without creating unintended electrical shorts to other inductors occupying the shared footprint region.

[0095] The right portion of FIG. 6B corresponds to the shunt resonator 630(2) and shows the second inductor 620(2) implemented as a polygonal inductive conductor together with the second capacitor 610(2), which is connected in series with the second inductor 620(2) between the intermediate node 640 and ground. The second inductor 620(2) can be shaped to at least partially track the outline of the composite polygonal region associated with the first inductor 620(1) and the third inductor 620(3), thus enabling the shunt resonator to be placed in close proximity to the series resonators while remaining electrically distinct.

[0096] FIG. 6C shows an example combined physical layout for the third-order bandstop filter 600, illustrating how the first inductor 620(1), the second inductor 620(2), and the third inductor 620(3) can be integrated into a shared inductor footprint region together with the first capacitor 610(1 ), the second capacitor 610(2), the third capacitor 610(3), and the intermediate node 640. In the illustrated embodiment, the polygonal inductive conductor of the second inductor 620(2) forms an outer loop, while the polygonal inductive conductors of the first inductor 620(1) and the third inductor 620(3) form inner loops located within the outer loop.

[0097] As in the bandpass embodiments described with respect to FIGS. 3 and 4, the partial polygonal shapes of the first inductor 620(1) and the third inductor 620(3) can be arranged such that, when the inductors are vertically stacked and viewed in plan, they together define a composite inductive conductor pattern that is substantially a complete polygonal or circular shape. In some embodiments, the composite shape is substantially symmetrical in geometry, for example forming an approximately regular square, hexagon, octagon, or circle. The inductors 620(1), 620(2), and 620(3) can be disposed on different metal layers such that they are vertically stacked while occupying substantially the same inductor footprint when viewed in plan.

[0098] It is noted in the present disclosure that, because the first inductor 620(1) and the third inductor 620(3) are vertically stacked within the shared footprint region, their magnetic fields can be arranged to share magnetic flux. In some embodiments, the stacked inductors are arranged for in-phase magnetic coupling,Attorney Docket No. EMTAR8002WO PATENTincreasing the effective inductance of each stacked inductor relative to a corresponding non-stacked implementation. This shared-flux behavior enables further miniaturization of the bandstop filter layout while maintaining the desired stopband characteristics.

[0099] As shown in the combined layout shown in FIG. 6C, the singlefootprint, vertically stacked inductor techniques introduced in the present disclosure can be equally applicable to bandstop filter topologies. By reusing the same shared-footprint inductor structures across different resonator roles and LC configurations, the third-order bandstop filter 600 can achieve compact layout, predictable electromagnetic behavior, and scalability to higher-order bandstop filters, as described in subsequent figures.

[0100] FIG. 7A illustrates a circuit schematic of an example fifth-order bandstop filter 700 arranged in a T-type ladder configuration. The fifth-order bandstop filter 700 includes three series resonator sections (i.e., resonators 730(1), 730(3), and 730(5)) and two shunt resonator sections (i.e., resonators 730(2) and 730(4)) coupled between a first port P1 and a second port P2. As shown on the right side of FIG. 7A, a first series resonator 730(1 ) formed by a first inductor 720(1 ) (L1 ) and a first capacitor 710(1) (C1) is coupled between the first port P1 and a first intermediate node 740. A second series resonator 730(3) formed by a third inductor 720(3) (L3) and a third capacitor 710(3) (C3) is coupled between the first intermediate node 740 and a second intermediate node 742. A third series resonator 730(5) formed by a fifth inductor 720(5) (L5) and a fifth capacitor 710(5) (C5) is coupled between the second intermediate node 742 and the second port P2. In contrast to the bandpass filter embodiments described above, each series resonator in FIG. 7A is configured such that its inductor and capacitor are connected in parallel, thereby presenting a high impedance at a stopband center frequency.

[0101] In addition, a first shunt resonator 730(2) formed by a second inductor 720(2) (L2) and a second capacitor 710(2) (C2) is coupled between the first intermediate node 740 and ground, and a second shunt resonator 730(4) formed by a fourth inductor 720(4) (L4) and a fourth capacitor 710(4) (C4) is coupled between the second intermediate node 742 and ground. In the illustrated bandstop configuration, each shunt resonator includes its inductor and capacitor connected in series so as to present a low impedance path to ground at the stopband centerAttorney Docket No. EMTAR8002WO PATENTfrequency. On the left side of FIG. 7A, the resonators 730(1 )-730(5) are also shown in a compact symbolic form to emphasize the T-type ladder arrangement and the placement of the intermediate nodes 740 and 742 as tap points for the shunt resonators.

[0102] FIG. 7B shows example physical layouts for inductors associated with the series resonators of the fifth-order bandstop filter 700. The layouts correspond to the first series resonator 730(1), the second series resonator 730(3), and the third series resonator 730(5) shown schematically in FIG. 7A. In the upper portion of FIG.7B, simplified schematic segments for 730(1), 730(3), and 730(5) indicate the respective locations of the first intermediate node 740 and the second intermediate node 742 along the series path between the ports P1 and P2. In the lower portion of FIG. 7B, each of the inductors 720(1), 720(3), and 720(5) is implemented as a polygonal inductive conductor patterned on one or more metal layers of an integrated circuit. The polygonal conductors can follow generally octagonal paths sized to fit within a defined inductor footprint region, with associated capacitors 710(1), 710(3), and 710(5) connected in parallel with the respective inductors.

[0103] More specifically, the left-hand layout of FIG. 7B corresponds to the first inductor 720(1), which is coupled in parallel with the first capacitor 710(1) between the port P1 and the first intermediate node 740. The polygonal path of the first inductor 720(1) includes a connection point at the first intermediate node 740 representing the junction where the first series resonator 730(1) meets the remainder of the ladder network.

[0104] The central layout of FIG. 7B corresponds to the third inductor 720(3), which includes two connection points respectively corresponding to the first intermediate node 740 and the second intermediate node 742, thereby coupling the second series resonator 730(3) between adjacent ladder stages. The third inductor 720(3) is also coupled in parallel with the third capacitor 710(3). In some embodiments, the inductive conductor pattern of the third inductor 720(3) can include a bridge section 750 that connects conductor segments implemented on different metal layers using vertical interconnect structures, such as metal vias, enabling conductor paths to cross in plan view without creating unintended electrical shorts.

[0105] The right-hand layout of FIG. 7B corresponds to the fifth inductor 720(5) of the third series resonator 730(5), which is coupled in parallel with the fifthAttorney Docket No. EMTAR8002WO PATENTcapacitor 710(5) between the second intermediate node 742 and the port P2. The polygonal path of the fifth inductor 720(5) includes a connection point corresponding to the second intermediate node 742 and can be arranged to nest around or within portions of the footprint used by the inductors 720(1 ) and 720(3). In some implementations, the fifth inductor 720(5) can include a bridge section 752 that joins different conductor segments and facilitates routing on multiple metal layers while maintaining electrical isolation from the other inductors in the shared footprint region.

[0106] In one or more embodiments, the inductive conductor patterns shown in FIG. 7B can be implemented using partial polygonal shapes that are substantially complementary when viewed in plan. Individual inductors may each define only a portion of a full polygonal loop, while a combination of inductors associated with different resonator stages (e.g., when vertically stacked on different metal layers) can together define a composite inductive conductor pattern that is substantially a complete polygonal or circular shape. By selecting appropriate metal layers, polygonal shapes, and bridge sections such as 750 and 752, the inductors 720(1), 720(3), and 720(5) can be overlaid to occupy substantially the same inductor footprint while supporting the parallel connections to capacitors 710(1), 710(3), and 710(5) at the edges of the footprint.

[0107] FIG. 7C shows example schematic connection points for inductors associated with the shunt resonators of FIG. 7A. On the left side of FIG. 7C, the first intermediate node 740 is depicted as the connection point for the first shunt resonator 730(2), which includes the second capacitor 710(2) (C2) and the second inductor 720(2) (L2) connected in series between the node 740 and ground. On the right side of FIG. 7C, the second intermediate node 742 is depicted as the connection point for the second shunt resonator 730(4), which includes the fourth capacitor 710(4) (C4) and the fourth inductor 720(4) (L4) connected in series between the node 742 and ground. It is noted that FIG. 7C is to clarify the electrical connection topology of the shunt resonators in the layout rather than to illustrate detailed physical inductor layouts; in various embodiments, the inductors 720(2) and 720(4) can be implemented using polygonal inductive conductor layout techniques similar to those described for resonators above.

[0108] FIG. 7D shows an example combined physical layout for the fifth-order bandstop filter 700, illustrating how the series-path inductors of FIG. 7B and theAttorney Docket No. EMTAR8002WO PATENTshunt-resonator connection points of FIG. 7C can be integrated into a shared inductor footprint region. The embodiment in FIG. 7D is explained with simultaneous reference to FIGS. 7A-7C.

[0109] On the left side of FIG. 7D is a simplified representation where the three series resonator sections and two shunt resonator sections are shown in compact form along the path from P1 to P2, with the first intermediate node 740 and the second intermediate node 742 labeled as shunt tap locations. On the right side of FIG. 7D, multiple polygonal inductive conductors corresponding to the inductors 720(1), 720(3), and 720(5) are arranged around a common central region and disposed on different metal layers so as to be vertically stacked while occupying substantially the same inductor footprint when viewed in plan. The shunt resonators 730(2) and 730(4) are connected from the intermediate nodes 740 and 742, respectively, toward a centrally located ground region through their series-connected capacitors 710(2), 710(4) and inductors 720(2), 720(4), allowing the shunt paths to be realized without requiring separate, dedicated inductor footprints.

[0110] In some embodiments, inductors associated with higher-order series resonators (e.g., the inductor 720(5)) are disposed on additional metal layers and arranged in different rotational orientations relative to inductors of lower-order resonators, for example rotated by approximately 90 degrees, 180 degrees, or 270 degrees when viewed in plan. These rotational arrangements facilitate dense nesting of multiple inductors within a shared footprint region and simplify routing of the parallel-connected series capacitors while preserving electrical isolation between resonator stages. When vertically stacked in this manner, the inductors can be positioned such that their magnetic fields overlap and share magnetic flux. In certain implementations, the stacked inductors are arranged for in-phase magnetic coupling, thereby increasing the effective inductance of each stacked inductor relative to a non-stacked implementation and enabling further miniaturization of higher-order bandstop filters.

[0111] Accordingly, as shown in the embodiments shown in FIGS. 7A-7D, the single-footprint, vertically stacked inductor layout techniques introduced in the present disclosure can be applicable not only to bandpass filters but also to bandstop filters, and are scalable to higher-order ladder configurations. By stacking inductors associated with different resonator stages within substantially the sameAttorney Docket No. EMTAR8002WO PATENTplanar footprint while controlling rotational orientation, layer ordering, and magnetic coupling, higher-order bandstop filters can be realized with improved spectral rejection characteristics without proportional increases in silicon area.

[0112] FIG. 8A shows a circuit schematic of an example (2k— 1 ) -th order bandstop filter 800 arranged in a T-type ladder configuration. In the illustrated embodiment, a number of series resonator sections are coupled in series between a first port P1 and a second port P2, and a plurality of shunt resonator sections are coupled between intermediate ladder nodes and ground. Each series resonator section can include an inductor and a capacitor connected in parallel so as to present a high impedance at a desired stopband center frequency, while each shunt resonator section can include an inductor and a capacitor connected in series so as to present a low-impedance path to ground at approximately the same stopband center frequency. Intermediate nodes between adjacent series resonators serve as tap points from which corresponding shunt resonator sections are driven. As with the third-order and fifth-order bandstop examples described above, the generalized (2k— 1 )-th order topology of FIG. 8A is shown primarily to illustrate the electrical scalability of the ladder structure; details that are similar to those described with respect to FIGS. 6A and 7A are not repeated here for simplicity.

[0113] FIG. 8B shows an example physical layout 805 for implementing the (2k— 1 )-th order bandstop filter 800 of FIG. 8A using the single-footprint inductorbased layout techniques introduced in the present disclosure. In the illustrated embodiment, a set of inductors associated with multiple series resonator stages can be implemented as polygonal inductive conductors 820(1), 820(3), 820(5), ..., 820(2k-1) disposed on different metal layers of an integrated circuit and vertically stacked so as to occupy substantially the same inductor footprint when viewed in plan. The polygonal inductive conductors can be arranged as nested or substantially concentric shapes around a shared central region, thereby defining a common footprint region in which a number of series-resonator inductors for different stages are co-located.

[0114] In one or more embodiments, each individual inductor 820(1), 820(3), 820(5), and so forth, may define only a partial polygonal shape when viewed in plan. When these partial shapes are vertically stacked and overlapped within the shared footprint region, their combined pattern can form a composite inductive conductorAttorney Docket No. EMTAR8002WO PATENTshape that is substantially a complete polygonal or circular loop. In some implementations, the composite loop is substantially symmetrical in geometry, for example being approximated by a regular square, hexagon, octagon, or circle. As in embodiments introduced above, one or more of the inductors in layout 805 can include bridge sections that connect conductor segments implemented on different metal layers through vertical interconnect structures such as metal vias, thereby allowing conductor paths to cross in plan view without creating unintended electrical shorts while still maintaining the desired inductive behavior.

[0115] In the generalized layout of FIG. 8B, inductors corresponding to higher-order series resonators can be formed on additional metal layers and rotated relative to inductors of lower-order resonators so as to facilitate dense nesting and routing. In one or more illustrative embodiments, and for simplicity of presentation in the drawings, the rotation angle between successive series-resonator inductors is selected to be approximately 90 degrees. More generally, however, the layout can combine rotated inductor elements using other suitable rotation angles or angle patterns (including, e.g., rotations of approximately 180 degrees or 270 degrees, or non-orthogonal angle choices) selected to satisfy routing, isolation, or coupling constraints for a particular implementation. By rotating and stacking the inductors in this manner while maintaining substantially the same inductor footprint, successive resonator stages of the (2k— 1 )-th order bandstop ladder can be realized without requiring proportionally larger planar area.

[0116] Shunt resonator sections in FIG. 8B can be coupled from the shared footprint region using inter-inductor and / or inter-capacitor connection points, e.g., from intermediate ladder nodes between adjacent series resonators. For clarity of illustration, the physical layouts of the shunt capacitors are omitted here, and the shunt sections (e.g., I_2k and C2k in FIG. 8A) can be represented by dashed lines indicating connections from the intermediate nodes toward a central ground region. In various embodiments, a shunt capacitor can be implemented as a metal-insulator-metal capacitor or a coupling capacitor between a corresponding shunt inductor and an underlying ground plane disposed near the center of the layout. The associated shunt inductors can be implemented using polygonal inductive conductor patterns that at least partially track or surround the composite polygonal region defined by the series-path inductors, thereby allowing the shunt resonators to fit within or closelyAttorney Docket No. EMTAR8002WO PATENTaround the same shared footprint while preserving the desired series-shunt relationships of the ladder.

[0117] As with the bandpass embodiments described above, stacking the coplanar inductors in FIG. 8B defines a magnetic coupling factor between the different inductor levels. By choosing the order of the vertical stacking (e.g., which inductor resides on which metal layer), the vertical spacing between layers, and the relative lateral positioning of the nested loops, the designer can establish a desired coupling factor k between inductors corresponding to different resonator stages. In some embodiments, the stacked inductors are arranged for in-phase magnetic coupling, causing the inductors to share magnetic flux in a manner that increases the effective inductance of each stacked inductor relative to a corresponding nonstacked implementation. In this manner, the techniques disclosed here can enable additional miniaturization of the overall bandstop filter profile while maintaining the required stopband characteristics.

[0118] It is noted that, for a given semiconductor technology, there can be a practical upper bound on the number of inductors that may be vertically stacked within a single shared footprint region, e.g., due to constraints on metal density, via count, electromigration limits, or design-rule margins. In some embodiments, when this maximum number of single-footprint inductors has been reached for a particular footprint region, further increases in filter order can be obtained by instantiating an additional shared inductor footprint region implemented on another vertical stack or repeated layout cell. In this way, the layout of FIG. 8B can be extended to higher-order bandstop filters by repeating a previously defined fundamental section in appropriate rotation angles and, when necessary, by distributing successive groups of stacked inductors across multiple shared-footprint regions, thereby preserving the compact-area benefits of the disclosed techniques while accommodating process limitations.

[0119] FIG. 9A illustrates an example non-stacked inductor layout 900 used to evaluate the benefits of vertical stacking. In the illustrated embodiment, two inductors are implemented as generally polygonal (e.g., octagonal) spiral conductors placed side by side in a coplanar fashion on one or more metal layers of an integrated circuit. Each inductor can correspond to a series inductor used in the Chebyshev ladder filters described above. The two inductors are routed so that theyAttorney Docket No. EMTAR8002WO PATENToccupy separate inductor footprint regions and do not significantly share magnetic flux with one another, thereby representing a conventional layout approach in which each resonator section is allocated its own dedicated inductor area.

[0120] FIG. 9B shows an example simulation result 905 for one of the two non-stacked inductors of FIG. 9A. Note that the two non-stacked inductors on FIG.9A each roughly have the same inductance value. In the illustrated plot, the horizontal axis represents frequency over a band of interest (e.g., around 10-11 GHz), and the vertical axis represents the simulated inductance seen from one of the two inductors of FIG. 9A before cascading. In one representative implementation, each individual inductor exhibits an inductance of approximately 350 pH, resulting in a total cascaded inductance of approximately 750 pH when the inductors are connected in series. The simulation results of the non-stacked inductors shown in FIG. 9B establish a baseline for comparison of total inductance with stacked implementations, as discussed below with respect to FIGS. 10A and 10B.

[0121] FIG. 10A illustrates an example stacked inductor layout 1000 derived from the non-stacked inductors of FIG. 9A. In this embodiment, the two inductors are re-implemented as vertically stacked polygonal inductive conductors that, when viewed in plan, occupy substantially the same inductor footprint. One of the inductors is disposed on a first metal layer, and the other inductor is disposed on a different metal layer above or below the first, with suitable vertical interconnect structures (e.g., vias and local interconnect segments) used to form continuous current paths. The three-dimensional view in FIG. 10A illustrates how the stacked inductors are arranged so that their magnetic fields substantially overlap, enabling the inductors to share magnetic flux within the common footprint region.

[0122] FIG. 10B shows an example simulation result 1005 for the stacked inductors of FIG. 10A. As with FIG. 9B, the horizontal axis represents frequency, and the vertical axis represents total series inductance. In one representative implementation, the stacked configuration yields an effective total series inductance of approximately 1 ,700 pH over the band of interest, more than doubling the total inductance obtained from the non-stacked configuration of FIG. 9B. In other words, stacking the inductors to share magnetic flux can increase the effective inductance by more than 100% compared to the corresponding coplanar layout using the same individual inductors. For a given target inductance value in the Chebyshev filterAttorney Docket No. EMTAR8002WO PATENTdesigns described herein, this increase in effective inductance can be traded for additional footprint reduction. For example, the same inductance can be realized using stacked inductors occupying on the order of 50% of the planar area that would otherwise be required for non-stacked inductors, with the precise reduction depending on the specific inductor shapes and layout constraints.

[0123] Therefore, FIGS. 9A-10B collectively illustrate how the techniques disclosed here, with vertical stacking and shared magnetic flux, can increase effective inductance and enable further miniaturization of the inductor-based bandpass and bandstop filter topologies disclosed in the present specification.

[0124] The foregoing description of various embodiments of the claimed subject matter has been provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit the claimed subject matter to the precise forms disclosed. Many modifications and variations will be apparent to one skilled in the art. Embodiments were chosen and described in order to best describe the principles of the invention and its practical applications, thereby enabling those skilled in the relevant art to understand the claimed subject matter, the various embodiments, and the various modifications that are suited to the particular uses contemplated.

[0125] Although the Detailed Description describes certain embodiments and the best mode contemplated, the technology can be practiced in many ways no matter how detailed the Detailed Description appears. Embodiments may vary considerably in their implementation details, while still being encompassed by the specification. Particular terminology used when describing certain features or aspects of various embodiments should not be taken to imply that the terminology is being redefined herein to be restricted to any specific characteristics, features, or aspects of the technology with which that terminology is associated. In general, the terms used in the following claims should not be construed to limit the technology to the specific embodiments disclosed in the specification, unless those terms are explicitly defined herein. Accordingly, the actual scope of the technology encompasses not only the disclosed embodiments, but also all equivalent ways of practicing or implementing the embodiments.

[0126] The language used in the specification has been principally selected for readability and instructional purposes. It may not have been selected to delineateAttorney Docket No. EMTAR8002WO PATENTor circumscribe the subject matter. It is therefore intended that the scope of the technology be limited not by this Detailed Description, but rather by any claims that issue on an application based hereon. Accordingly, the disclosure of various embodiments is intended to be illustrative, but not limiting, of the scope of the technology as set forth in the following claims. Further, it should be noted that the various circuits disclosed herein may be described using computer-aided design tools and expressed (or represented), as data and / or instructions embodied in various computer-readable media, in terms of their behavioral, register transfer, logic component, transistor, layout geometries, and / or other characteristics. Formats of files and other objects in which such circuit expressions may be implemented include, but are not limited to, formats supporting behavioral languages such as C, Verilog, and VHDL; formats supporting register- 1 eve I description languages like RTL; formats supporting geometry description languages such as GDSII, GDSIII, GDSIV, CIF, MEBES; and any other suitable format or language. Computer-readable media in which such formatted data and / or instructions may be embodied include, but are not limited to, non-volatile storage media in various forms (e.g., optical, magnetic, or semiconductor storage media).

Claims

1. Attorney Docket No. EMTAR8002WO PATENT CLAIMSWhat is claimed is:1 . An inductor-based filter circuit comprising:a first series resonator coupled between a first port and an intermediate node; a second series resonator coupled between the intermediate node and a second port; anda first shunt resonator coupled between the intermediate node and ground, wherein the first series resonator includes a first inductor implemented as a polygonal or circular inductive conductor disposed on one or more metal layers of an integrated circuit,wherein the second series resonator includes a second inductor implemented as a polygonal or circular inductive conductor,wherein the first inductor is primarily disposed on a first metal layer, and wherein the second inductor is primarily disposed on a second metal layer different from the first metal layer such that the first and second inductors are vertically stacked and that each of the first and second inductors occupies substantially a same inductor footprint when viewed in plan.

2. The circuit of claim 1 , wherein the first and second inductors are vertically stacked in a manner such that the first and second inductors share magnetic flux so as to increase an effective inductance for each stacked inductor.

3. The circuit of claim 1 ,wherein the first inductor has a shape that is partially polygonal or circular, andwherein the second inductor has a shape that is partially polygonal or circular and substantially complementary to the shape of the first inductor such that, when the first and second inductors are vertically stacked and viewed in plan, the shapes of the first and second inductors together define a composite inductive conductor pattern that is substantially a complete polygonal or circular shape.

4. The circuit of claim 3, wherein the complete polygonal or circular shape is symmetrical in geometry.Attorney Docket No. EMTAR8002WO PATENT5. The circuit of claim 3, wherein the complete polygonal or circular shape includes a hexagon, an octagon, or a circle.

6. The circuit of claim 3, wherein the composite inductive conductor pattern exhibits two or more substantially concentric octagons.

7. The circuit of claim 1 , wherein the first shunt resonator includes a third inductor implemented as a polygonal or circular inductive conductor that is vertically stacked with the first and / or the second inductor.

8. The circuit of claim 7, wherein the third inductor is at least partially disposed on a metal layer different from that of the first and / or the second inductor.

9. The circuit of claim 7, wherein the third inductor occupies substantially the same inductor footprint as the first inductor and / or the second inductor when viewed in plan.

10. The circuit of claim 7, wherein the third inductor has a shape that at least partially tracks the complete polygonal or circular shape formed together by the first and second inductors.

11. The circuit of claim 1 , further comprising:an additional pair of resonators including an additional series resonator and an additional shunt resonator, wherein the additional pair of resonators increases an order of the filter circuit.

12. The circuit of claim 11 , wherein the additional series resonator includes an additional inductor that is vertically stacked with one or more inductors of lower-order resonators.

13. The circuit of claim 12, wherein the additional inductor is vertically stacked in a manner such that the additional inductor shares magnetic flux with the first andAttorney Docket No. EMTAR8002WO PATENTsecond inductors so as to increase an effective inductance for each stacked inductor.

14. The circuit of claim 11 , wherein the additional series resonator includes an additional inductor implemented as a polygonal or circular inductive conductor disposed, at least partially, on an additional metal layer such that, when viewed in plan, the additional inductor occupies substantially the same inductor footprint as an inductor in a previous stage.

15. The circuit of claim 11 , wherein one or more inductors of a higher-order resonator, when viewed in plan, are rotated relative to inductors of lower-order resonators by approximately 90, 180, or 270 degrees.

16. The circuit of claim 1 , wherein the first and second series resonators each include a capacitor connected in series with a corresponding inductor.

17. The circuit of claim 16, wherein the first shunt resonator includes a capacitor connected in parallel with its inductor.

18. The circuit of claim 17, wherein the filter circuit is a bandpass filter.

19. The circuit of claim 1 , wherein the first and second series resonators each include a capacitor connected in parallel with a corresponding inductor.

20. The circuit of claim 19, wherein the first shunt resonator includes a capacitor connected in series with its inductor.

21. The circuit of claim 20, wherein the filter circuit is a bandstop filter.

22. An inductor-based filter circuit comprising:a first series resonator coupled between a first port and a second port;a first shunt resonator coupled between the first port and ground; and a second shunt resonator coupled between the second port and the ground;Attorney Docket No. EMTAR8002WO PATENTwherein the first shunt resonator includes a first inductor implemented as a polygonal or circular inductive conductor disposed on one or more metal layers of an integrated circuit,wherein the second shunt resonator includes a second inductor implemented as a polygonal or circular inductive conductor,wherein the first inductor is primarily disposed on a first metal layer, and wherein the second inductor is primarily disposed on a second metal layer different from the first metal layer such that the first and second inductors are vertically stacked and that each of the first and second inductors occupies substantially a same inductor footprint when viewed in plan.

23. An inductor-based filter circuit comprising:a first resonator and a second resonator coupled between a first port and a second port;wherein the first resonator includes a first inductor implemented as a polygonal or circular inductive conductor disposed on one or more metal layers of an integrated circuit,wherein the second resonator includes a second inductor implemented as a polygonal or circular inductive conductor,wherein the first inductor is primarily disposed on a first metal layer and in a first rotational orientation, andwherein the second inductor is primarily disposed on a second metal layer different from the first metal layer, or in a second rotational orientation different from the first rotational orientation, or both, such that the first and second inductors are vertically stacked and that each of the first and second inductors occupies substantially a same inductor footprint when viewed in plan.

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