Organic wiring board and method for manufacturing organic wiring board

Abstract

Provided is an organic wiring board (1) with which it is possible to achieve both high density of wiring and suppression of crosstalk. This organic wiring board (1) is provided with a plurality of laminated insulating resin films (40), and vias formed in the insulating resin films (40). When the direction in which the insulating resin films (40) are laminated is defined as a lamination direction (1020), the thickness of the insulating resin films (40) in the lamination direction (1020) is greater than the equivalent circle diameter in a cross-section orthogonal to the lamination direction (1020) at the center position of the vias (20) in the lamination direction (1020), and the thickness of the insulating resin films (40) is less than 10 μm.

Description

Organic Wiring Substrate and Method for Manufacturing the Same

[0001] The present invention relates to an organic wiring substrate provided with high-density wiring.

[0002] With the progress of fine processing technology for semiconductor chips, a plurality of individual chips are mounted on a wiring substrate on which wiring layers are formed to produce a chiplet package. As an example of such a wiring substrate, there is an interposer on which a redistribution layer is formed. Further, as a type of organic wiring substrate in which an insulating layer is formed of resin, there is an organic interposer.

[0003] Regarding the organic interposer, for example, Patent Document 1 discloses an organic interposer in which a photosensitive resin is used for the insulating layer.

[0004] U.S. Patent Publication US11018026B2

[0005] By the way, in order to increase the density of wiring in an organic wiring substrate, it is required to reduce the via diameter. However, when the via diameter is reduced, the wiring resistance increases and crosstalk is likely to occur. Thus, there is a problem that it is difficult to achieve both high-density wiring and suppression of crosstalk in a conventional organic wiring substrate.

[0006] Therefore, an object of the present invention is to provide an organic wiring substrate capable of achieving both high-density wiring and suppression of crosstalk.

[0007] The organic wiring substrate of the present invention is an organic wiring substrate including a plurality of laminated insulating resin films and vias formed in the insulating resin films. When the direction in which the insulating resin films are laminated is defined as the lamination direction, the thickness of the insulating resin film in the lamination direction is larger than the equivalent circle diameter in the cross section orthogonal to the lamination direction at the central position of the via in the lamination direction, and the thickness of the insulating resin film is less than 10 μm.

[0008] According to the present invention, it is possible to provide an organic wiring substrate capable of achieving both high-density wiring and suppression of crosstalk.

[0009] Figure 1 is a cross-sectional view of a chiplet package including an organic wiring board according to this embodiment. Figure 2 is an enlarged view of the portion corresponding to the framed area in Figure 1. Figure 3 is a cross-sectional view of a via according to this embodiment. Figure 4A is a cross-sectional view of carrier glass, etc., showing the manufacturing process of the organic wiring board according to this embodiment. Figure 4B is a cross-sectional view of carrier glass, etc., showing the manufacturing process of the organic wiring board according to this embodiment, following Figure 4A. Figure 4C is a cross-sectional view of carrier glass, etc., showing the manufacturing process of the organic wiring board according to this embodiment, following Figure 4B. Figure 4D is a cross-sectional view of carrier glass, etc., showing the manufacturing process of the organic wiring board according to this embodiment, following Figure 4C. Figure 4E is a cross-sectional view of carrier glass, etc., showing the manufacturing process of the organic wiring board according to this embodiment, following Figure 4D. Figure 4F is a cross-sectional view of carrier glass, etc., showing the manufacturing process of the organic wiring board according to this embodiment, following Figure 4E. Figure 4G is a cross-sectional view of carrier glass, etc., showing the manufacturing process of the organic wiring board according to this embodiment, following Figure 4F. Figure 4H is a cross-sectional view of carrier glass, etc., showing the manufacturing process of the organic wiring board according to this embodiment, following Figure 4G. Figure 4I is a cross-sectional view of carrier glass, etc., showing the manufacturing process of the organic wiring board according to this embodiment, following Figure 4H. Figure 4J is a cross-sectional view of carrier glass, etc., showing the manufacturing process of the organic wiring board according to this embodiment, following Figure 4I. Figure 4K is a cross-sectional view of carrier glass and other components showing the manufacturing process of the organic wiring board of this embodiment, following Figure 4J. Figure 4L is a cross-sectional view of carrier glass and other components showing the manufacturing process of the organic wiring board of this embodiment, following Figure 4K. Figure 4M is a cross-sectional view of carrier glass and other components showing the manufacturing process of the organic wiring board of this embodiment, following Figure 4L. Figure 4N is a cross-sectional view of carrier glass and other components showing the manufacturing process of the organic wiring board of this embodiment, following Figure 4M. Figure 4O is a cross-sectional view of carrier glass and other components showing the manufacturing process of the organic wiring board of this embodiment, following Figure 4N. Figure 4P is a cross-sectional view of carrier glass and other components showing the manufacturing process of the organic wiring board of this embodiment, following Figure 4O. Figure 4Q is a cross-sectional view of carrier glass and other components showing the manufacturing process of the organic wiring board of this embodiment, following Figure 4P. Figure 4R is a cross-sectional view of carrier glass and other components showing the manufacturing process of the organic wiring board of this embodiment, following Figure 4Q.

[0010] (Organic Wiring Substrate) An organic wiring substrate 1 according to an embodiment of the present invention will be described with reference to the drawings. Figure 1 is a cross-sectional view of a chiplet package 100. A component on which a semiconductor chip 90 is mounted on the organic wiring substrate 1 is defined as a chiplet package 100. The organic wiring substrate 1 is a substrate on which a semiconductor chip or the like is mounted. An example of the organic wiring substrate 1 is an organic interposer. A redistribution layer (RDL) 70 is formed on the organic wiring substrate 1. The redistribution layer 70 will be described later.

[0011] In the example of the chiplet package 100 shown in Figure 1, two semiconductor chips 90 are mounted on the organic wiring board 1. However, the number of semiconductor chips 90 mounted on the organic wiring board 1 is not limited to two.

[0012] In the organic wiring board 1, the side on which the semiconductor chip 90 is mounted is defined as the wiring board surface 11. In the organic wiring board 1, the main surface opposite to the wiring board surface 11 is defined as the wiring board back surface 12.

[0013] The semiconductor chip 90 is connected to the surface 11 of the wiring board via solder bumps. The solder bumps connecting the semiconductor chip 90 and the surface 11 of the wiring board are defined as chip solder bumps 94. Solder bumps are provided on the back surface 12 of the wiring board. The solder bumps provided on the back surface 12 of the wiring board are defined as substrate solder bumps 14. The chiplet package 100 is connected to other boards, etc., via the substrate solder bumps 14.

[0014] In the chiplet package 100, sealing members 98 are placed around the semiconductor chip 90, between semiconductor chips 90 and other semiconductor chips 90, and between the semiconductor chip 90 and the wiring board surface 11.

[0015] (Definition of direction) The direction parallel to the surface 11 of the wiring board is defined as the planar direction 1010. The direction perpendicular to the planar direction 1010 is defined as the stacking direction 1020. The direction from the back surface 12 of the wiring board toward the surface 11 of the wiring board is defined as the surface direction 1021. The direction opposite to the surface direction 1021 is defined as the back surface direction 1022. The surface direction 1021 and the back surface direction 1022 are parallel to the stacking direction 1020.

[0016] (Insulating resin film and wiring layer) The organic wiring substrate 1 includes a plurality of insulating resin films 40 and a plurality of wiring layers 30. The insulating resin films 40 and the wiring layers 30 are laminated in the lamination direction 1020. The insulating resin film 40 is also called an interlayer insulating film.

[0017] The organic wiring substrate 1 further includes vias 20. The vias 20 are formed in the insulating resin film 40. The vias 20 connect adjacent wiring layers 30 in the stacking direction 1020. The rewiring layer 70 is composed of a plurality of wiring layers 30 connected by vias 20.

[0018] The shape of via 20 will be explained with reference to Figure 2. Figure 2 is an enlarged view of the area corresponding to the framed area 72 in Figure 1.

[0019] (Insulating resin film thickness) The insulating resin film thickness Y is defined as the thickness of the insulating resin film 40 in the stacking direction 1020 between two wiring layers 30 that are adjacent in the stacking direction 1020 and connected by vias 20. The insulating resin film thickness Y is equal to the length of the via 20 in the stacking direction 1020.

[0020] (Via diameter) The via diameter X is defined as the equivalent diameter of a circle in a cross-section perpendicular to the stacking direction of via 20. Via diameter X is the equivalent diameter of a circle at the center of via 20 in the stacking direction 1020. In other words, via diameter X is measured at a position Y / 2 away from the wiring layer 30 to which via 20 is connected in the surface direction 1021 or the back direction 1022.

[0021] In the organic wiring substrate 1 of this embodiment, the insulating resin film thickness Y is greater than the via diameter X. This allows for higher density wiring. The density of wiring in the redistribution layer 70 and the like largely depends on the via diameter X. The ratio of insulating resin film thickness Y / via diameter X in a cross section parallel to the planar direction 1010 and the stacking direction 1020 is defined as the aspect ratio of the via 20. In the organic wiring substrate 1 of this embodiment, by setting insulating resin film thickness Y > via diameter X, it becomes easier to increase the aspect ratio of the via 20. As a result, the arrangement density of vias 20 can be increased, and consequently, the wiring density can be increased.

[0022] The narrower the spacing between vias and the longer the via length, the more likely crosstalk is to occur between vias. When vias are densely arranged while keeping the via diameter the same to increase the density of organic interposers, crosstalk occurs between vias. Also, reducing the via diameter increases the wiring resistance. Therefore, by making the insulating resin film 10 μm or less (preferably 5 μm or less) and setting Y > X, it is possible to suppress the increase in wiring resistance and suppress crosstalk.

[0023] (Vertical Via) The angle of the via side surface 22 of the via 20 will be explained with reference to Figure 3. Figure 3 is a cross-sectional view of the via 20 of this embodiment in a plane parallel to the stacking direction 1020. In the cross-section of the via 20 parallel to the stacking direction 1020, the outer surface of the via 20 that intersects with the planar direction 1010 is defined as the via side surface 22. One of the planes perpendicular to the stacking direction 1020 is defined as the reference plane 1110. The angle between the via side surface 22 and the reference plane 1110 in the cross-sectional view parallel to the stacking direction 1020 is defined as the taper angle A. In the via 20 of this embodiment, the via side surface 22 includes a portion where the taper angle A is 80 degrees or more and 90 degrees or less. In other words, in at least a part of the via side surface 22 of the via 20, the taper angle A is 80 degrees or more and 90 degrees or less. For example, at the central position in the stacking direction, the taper angle A may be 80 degrees or more and 90 degrees or less.

[0024] In the organic wiring substrate 1 of this embodiment, the taper angle A is 80 degrees or more and 90 degrees or less. That is, for example, if the shape of the cross-section perpendicular to the stacking direction of the via 20 is circular, the shape of the via 20 approaches that of a cylinder. Therefore, it is possible to increase the arrangement density of the vias 20 and, consequently, the wiring density, while suppressing an increase in the wiring resistance within the vias 20.

[0025] (Insulating resin film) The material of the insulating resin film 40 will be described. The material of the insulating resin film 40 can be, for example, an epoxy resin, a polyimide resin, or a polybenzoxazole.

[0026] Furthermore, the material of the insulating resin film 40 can be a non-photosensitive resin. As will be explained later, in the manufacturing method of the organic wiring board 1 of this embodiment, when forming the vias 20, the via holes 122 are formed with a laser. In other words, photolithography is not used to form the via holes 122. Therefore, the insulating resin film 40 can be formed with a non-photosensitive resin.

[0027] (Filler-free) The insulating resin film 40 can be made filler-free. By making the insulating resin film 40 filler-free, the elongation of the insulating resin film 40 can be increased. As a result, it is possible to suppress the likelihood of cracks occurring in the insulating resin film 40 due to the effects of thermal history.

[0028] Furthermore, because it does not contain fillers, it is not affected by dielectric loss that occurs at the interface between the filler and the resin.

[0029] (Filler Content) On the other hand, the insulating resin film 40 may contain fillers with an average particle size of approximately 0.15 μm or less. Here, "approximately" means including a range that has a similar effect. "Approximately" has the same meaning as "substantially". By containing fillers with an average particle size of approximately 0.15 μm or less in the insulating resin film 40, the overall coefficient of thermal expansion (CTE) of the insulating resin film 40 can be reduced. As a result, the difference in the coefficient of thermal expansion between the organic wiring substrate 1 and the semiconductor chip 90 can be reduced. Consequently, the occurrence of problems caused by a mismatch in the coefficient of thermal expansion, such as the generation of stress between the organic wiring substrate 1 and the semiconductor chip 90, can be suppressed.

[0030] (Method for measuring average particle size) The average particle size of the filler can be determined, for example, as follows: Obtain a microscopic image of the cross-section of the insulating resin film 40. Perform image analysis on the microscopic image to separate and extract multiple fillers. Then, calculate the average of the circular equivalent diameters of the multiple fillers. The calculated value is taken as the average particle size.

[0031] (Method for Manufacturing an Organic Wiring Substrate) The method for manufacturing the organic wiring substrate 1 of this embodiment will be described with reference to Figures 4A to 4R. Figures 4A to 4R are, in order, cross-sectional views of the carrier glass 110 and the like showing the manufacturing process of the organic wiring substrate 1. In the following description, the surface direction 1021 will be considered as the upward direction.

[0032] First, prepare the carrier glass 110 as shown in Figure 4A. The carrier glass 110 can be, for example, 600 mm square.

[0033] (Release Material Coating Process) Figure 4B shows the carrier glass 110 after the release material coating process. The release material coating process is a process of coating one main surface of the carrier glass 110 with a release material for temporary bonding. The release material can be coated using, for example, a slit coater. The release material coating process forms a release layer 112 on one main surface of the carrier glass 110.

[0034] (Sacrificial layer formation process) Figure 4C shows the carrier glass 110 after the sacrificial layer formation process. The sacrificial layer formation process is a process of forming a sacrificial layer 32 on the release layer 112. The sacrificial layer 32 can be formed by sputtering titanium and copper. The sacrificial layer formation process forms a sacrificial layer 32 containing titanium and copper on the release layer 112.

[0035] (Insulating layer formation process) Figure 4D shows the carrier glass 110, etc., after the insulating layer formation process. The insulating resin film formation process is a process of forming an insulating layer 42 on the sacrificial layer 32. The insulating layer 42 is formed by coating the insulating layer 42 material using a slit coater or the like, or by laminating the material that forms the insulating layer 42 after it has been formed. The insulating layer 42 is formed on the sacrificial layer 32 by the insulating layer formation process.

[0036] (Seed sputtering process for C4 bumps) Figure 4E shows the carrier glass 110, etc., after the seed sputtering process for C4 (Controlled Collapse Chip Connection) bumps. The seed sputtering process for C4 bumps is a process of forming a first seed layer 120 on the insulating layer 42. The first seed layer 120 can be formed by sputtering titanium and copper. The first seed layer 120 is formed on the insulating layer 42 by the seed sputtering process for C4 bumps. The first seed layer 120 is processed into a wiring layer 30 for C4 bump connection, as will be explained below.

[0037] (Insulating Resin Film Formation Process) Figure 4F shows the carrier glass 110, etc., after the insulating resin film formation process. The insulating resin film formation process is a process of forming an insulating resin film 40 on the wiring layer 30. Before the insulating resin film formation process, the first seed layer 120 is processed into a wiring layer 30 for C4 bump connection by patterning or the like. The insulating resin film 40 is formed by coating the wiring layer 30 with a material for forming the insulating resin film 40 using a slit coater or the like, or by laminating the material for forming the formed insulating resin film 40 onto the wiring layer 30. The material for forming the insulating resin film 40 is a non-photosensitive material. The insulating resin film 40 is formed on the wiring layer 30 by the insulating resin film formation process.

[0038] (Via Opening Process) Figure 4G shows the carrier glass 110 after the via opening process. The via opening process is a process of opening via holes 122 in the insulating resin film 40. The via holes 122 are opened using an excimer laser. The laser irradiation of the insulating resin film 40 can be performed using a mask scan laser. In the via opening process, as explained above, via holes 122 are opened in the insulating resin film 40 such that the shape of the via 20 is such that the insulating resin film thickness Y > via diameter X.

[0039] In the via opening process, an excimer laser is used to open via holes 122, making it easy to form vias 20 having the desired insulating resin thickness Y, via diameter X, and taper angle A. The oscillation wavelength of the excimer laser can be between 193 nm and 351 nm.

[0040] The excimer laser is preferably a krypton fluoride (KrF) laser. The oscillation wavelength of the krypton fluoride laser can be 248 nm.

[0041] The average output of the excimer laser is preferably 300 W. Also, the pulse energy of the excimer laser is preferably 70 mJ or more and 80 mJ or less.

[0042] By opening the via hole 122 using the excimer laser as described above, the via 20 having a desired shape can be formed more reliably.

[0043] When a photosensitive resin is used as the insulating resin film and the via hole is opened by photolithography, compared with the case where the via hole is opened using a laser, the number of processes can be reduced, and an organic wiring board can be manufactured at low cost.

[0044] (Seed sputtering process for wiring layer) Fig. 4H shows the carrier glass 110 and the like after the seed sputtering process for the wiring layer. The seed sputtering process for the wiring layer is a process of forming a second seed layer 124 on the surface of the insulating resin film 40 in which the via hole 122 is formed. The second seed layer 124 can be formed by sputtering titanium and copper. By the seed sputtering process for the wiring layer, the second seed layer 124 is formed on the insulating layer 42. As shown in Fig. 4J, the second seed layer 124 is used as a seed layer in the copper plating process for forming a wiring layer or the like.

[0045] (Photoresist process) Fig. 4I shows the carrier glass 110 and the like after the photoresist process. The photoresist process is a process of forming a photoresist layer 130 on the second seed layer 124. The formation of the photoresist layer 130 is performed through coating, exposure, and development of a photoresist material. The coating of the photoresist material can be performed, for example, with a slit coater. By the photoresist process, a photoresist layer 130 having a desired pattern is formed on the second seed layer 124.

[0046] (Copper plating process) Figure 4J shows the carrier glass 110 etc. after the copper plating process. The copper plating process is a process of forming a copper plating layer 126 on the second seed layer 124. The copper plating layer 126 is formed by plating using the second seed layer 124 as a seed layer. The copper plating layer 126 formed in the via hole 122 constitutes the via 20. Also, the copper plating layer 126 formed on the insulating resin film 40 via the second seed layer 124 becomes the wiring layer 30. The boundary line between the second seed layer 124 and the copper plating layer 126 is not shown.

[0047] (Photoresist stripping and seed layer etching process) Figure 4K shows the carrier glass 110 etc. after the photoresist stripping and seed layer etching process. The photoresist stripping and seed layer etching process is a process of removing the remaining photoresist layer 130 and the second seed layer 124 by etching or the like. This process can be performed by a dry process. By performing it by a dry process, the environmental load caused by the production of the organic wiring board 1 can be reduced. By the photoresist stripping and seed layer etching process, the photoresist layer 130 and the second seed layer 124 are removed, and the insulating resin film 40 and the wiring layer 30 are exposed.

[0048] As described above, the organic wiring board 1 of this embodiment is manufactured by a semi - additive process (SAP: Semi - Additive Process). In the manufacturing method of the organic wiring board 1 of this embodiment, the insulating resin film forming process to the photoresist stripping and seed layer etching process described above can be repeated a plurality of times. By repeating these processes a plurality of times, an organic wiring board 1 in which a plurality of wiring layers 30 and insulating resin films 40 are laminated can be manufactured.

[0049] Figures 4L to 4Q show the same processes as those shown in Figures 4F to 4K. Figures 4L to 4Q respectively correspond to those of Figures 4F to 4K. By performing the processes shown in Figures 4L to 4Q, the insulating resin film 40 and the wiring layer 30 can be further laminated. These processes can be repeated any number of times.

[0050] (Insulating Layer Formation Process) Figure 4L shows the carrier glass 110, etc., after the insulating layer formation process. The insulating resin film formation process shown in Figure 4L is the same as the insulating layer formation process shown in Figure 4D. After forming a predetermined number of insulating resin films 40 and wiring layers 30, an insulating layer 140 is formed. This forms the laminated wiring portion that constitutes, for example, the rewiring layer 70 in the organic wiring substrate 1.

[0051] After the insulating layer formation process, the organic wiring substrate 1 can be manufactured by, as appropriate, forming pads for bump connection with the semiconductor chip 90, or peeling off the carrier glass 110 with the release layer 112.

[0052] The embodiments of the present invention have been described above. The present invention is not limited to the embodiments described above, and various modifications, variations, and combinations are possible.

[0053] <1> An organic wiring substrate comprising a plurality of laminated insulating resin films and vias formed in the insulating resin films, wherein, when the direction in which the insulating resin films are laminated is defined as the lamination direction, the thickness of the insulating resin films in the lamination direction is greater than the equivalent diameter of a circle in a cross section perpendicular to the lamination direction at the central position of the via in the lamination direction, and the thickness of the insulating resin films is less than 10 μm.

[0054] <2> The insulating resin film is an organic wiring substrate according to <1>, without fillers.

[0055] <3> The insulating resin film is composed of epoxy resin and a filler with an average particle size of approximately 0.15 μm or less, the organic wiring substrate of <1>.

[0056] <4> An organic wiring substrate according to any one of <1> to <3>, wherein in a cross-section of the via on a plane parallel to the stacking direction, the side surface of the via includes a portion where the angle with a plane perpendicular to the stacking direction is 80 degrees or more and 90 degrees or less.

[0057] <5> The insulating resin film is formed of a non-photosensitive resin, the organic wiring substrate according to any one of <1> to <4>.

[0058] <6> A method for manufacturing an organic wiring substrate comprising an insulating resin film and vias formed in the insulating resin film, the method comprising the steps of: forming the insulating resin film; and forming vias in the insulating resin film, wherein the insulating resin film is non-photosensitive, and the via holes of the vias are formed using an excimer laser.

[0059] <7> The method for manufacturing an organic wiring substrate according to <6>, wherein the excimer laser is a krypton fluoride laser.

[0060] <8> The method for manufacturing an organic wiring substrate according to <6> or <7>, wherein the average output of the excimer laser is 300 W.

[0061] <9> The method for manufacturing an organic wiring substrate according to any one of <6> to <8>, wherein the pulse energy of the excimer laser is 70 mJ or more and 80 mJ or less.

[0062] 1 Organic wiring board 11 Wiring board surface 12 Wiring board back surface 14 Substrate solder bump 20 Via 22 Via side surface 30 Wiring layer 32 Sacrificial layer 40 Insulating resin film 42 Insulating layer 70 Rewiring layer 90 Semiconductor chip 94 Chip solder bump 98 Encapsulation material 100 Chiplet package 110 Carrier glass 112 Release layer 120 First seed layer 122 Via hole 124 Second seed layer 126 Copper plating layer 130 Photoresist layer 1010 Planar direction 1020 Lamination direction 1021 Surface direction 1022 Back direction 1110 Reference plane

Claims

1. An organic wiring substrate comprising a plurality of laminated insulating resin films and vias formed in the insulating resin films, wherein, when the direction in which the insulating resin films are laminated is defined as the lamination direction, the thickness of the insulating resin films in the lamination direction is greater than the equivalent diameter of a circle in a cross section perpendicular to the lamination direction at the central position of the via in the lamination direction, and the thickness of the insulating resin films is less than 10 μm.

2. The organic wiring substrate according to claim 1, wherein the insulating resin film does not contain fillers.

3. The organic wiring substrate according to claim 1, wherein the insulating resin film is composed of an epoxy resin and a filler having an average particle size of substantially 0.15 μm or less.

4. The organic wiring substrate according to claim 1, wherein in a cross-section of the via on a plane parallel to the stacking direction, the side surface of the via includes a portion where the angle with a plane perpendicular to the stacking direction is 80 degrees or more and 90 degrees or less.

5. The organic wiring substrate according to claim 1, wherein the insulating resin film is formed of a non-photosensitive resin.

6. A method for manufacturing an organic wiring substrate comprising an insulating resin film and vias formed in the insulating resin film, the method comprising the steps of: forming the insulating resin film; and forming vias in the insulating resin film, wherein the insulating resin film is non-photosensitive, and the via holes of the vias are formed using an excimer laser.

7. The method for manufacturing an organic wiring substrate according to claim 6, wherein the excimer laser is a krypton fluoride laser.

8. The method for manufacturing an organic wiring substrate according to claim 6, wherein the average output of the excimer laser is 300 W.

9. The method for manufacturing an organic wiring substrate according to claim 6, wherein the pulse energy of the excimer laser is 70 mJ or more and 80 mJ or less.

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