Multi-chip module and method for manufacturing same

Abstract

A multi-chip module according to the present disclosure comprises: N package substrates that are arranged in the horizontal direction; a plurality of logic ICs that are arranged on the package substrates; an EIC that is arranged on the package substrates; a photoelectric conversion IC that is connected to a plurality of the EICs; and a reinforcement frame that is arranged between the package substrates.

Description

Multi-chip module and method for manufacturing the same

[0001] The present disclosure relates to a multi-chip module in which logic ICs are integrated and a method for manufacturing the same.

[0002] In large-scale parallel signal processing, a large number of logic ICs such as GPUs and accelerators are used. In order to process logic ICs in cooperation at high speed, it is important to reduce the time required for data transmission between logic ICs, that is, to reduce latency (Non-Patent Document 1, Non-Patent Document 2).

[0003] In order to connect logic ICs with low latency, it is effective to mount a plurality of logic ICs on the same package and shorten the distance between each logic IC.

[0004] Hisa Ando, “NVIDIA's Next-Generation Research Chip for AI is a Scalable Inference Accelerator,” September 30, 2013, Internet, <URL: https: / / news.mynavi.jp / techplus / article / hotchips31_ml-13 / > Will Knight, “Clustering Giant Chips, the Potential of Technology to Dramatically Enhance the Capabilities of AI,” September 7, 2021, Internet, <URL: https: / / wired.jp / 2021 / 09 / 07 / cerebras-chip-cluster-neural-networks-ai / > Problems to be Solved by the Present Disclosure

[0005] However, there are restrictions on the size of the package substrate from the viewpoints of warping of the package substrate and wiring formation. As a result, the number of logic ICs that can be connected with low latency is limited.

[0006] In addition, the larger the logic IC, the more arithmetic devices can be mounted on the logic IC, so that the arithmetic ability can be improved. However, when the logic IC is enlarged, the number of logic ICs that can be mounted on the same package substrate decreases.

[0007] Thus, the problem has been that a large number of logic ICs with high arithmetic ability cannot be integrated on the package substrate.

[0008] To solve the problems described above, the multi-chip module according to this disclosure comprises N package substrates arranged horizontally, a plurality of logic ICs arranged on the package substrates, an EIC arranged on the package substrates, a photoelectric conversion IC connected to the plurality of EICs, and a reinforcing fixing frame arranged between the package substrates.

[0009] Furthermore, the method for manufacturing a multi-chip module mounting substrate according to this disclosure comprises the steps of: mounting an EIC and a plurality of logic ICs on a package substrate; fixing N of the package substrates via a reinforcing fixing frame; mounting a photoelectric conversion IC connected to the EIC; and mounting the N of the package substrates fixed via the reinforcing fixing frame onto a printed circuit board. Effects of this Disclosure

[0010] According to this disclosure, it is possible to provide a multi-chip module that can integrate a large number of logic ICs and connect each logic IC with low latency, as well as a method for manufacturing the same.

[0011] Figure 1A is a schematic top view showing the configuration of a multi-chip module according to the first embodiment of this disclosure. Figure 1B is a schematic cross-sectional view showing the configuration of a multi-chip module mounting substrate on which the multi-chip module according to the first embodiment of this disclosure is mounted. Figure 1C is a schematic cross-sectional view showing the configuration of a reinforcing fixing frame in a multi-chip module according to the first embodiment of this disclosure. Figure 2 is a schematic side cross-sectional view for illustrating the configuration of a conventional multi-chip module. Figure 3A is a schematic top view for illustrating the manufacturing method of a multi-chip module according to the first embodiment of this disclosure. Figure 3B is a schematic side cross-sectional view for illustrating the manufacturing method of a multi-chip module according to the first embodiment of this disclosure. Figure 4A is a schematic top view for illustrating the manufacturing method of a multi-chip module according to the first embodiment of this disclosure. Figure 4B is a schematic side cross-sectional view for illustrating the manufacturing method of a multi-chip module according to the first embodiment of this disclosure. Figure 5A is a schematic top view for illustrating the manufacturing method of a multi-chip module according to the first embodiment of this disclosure. Figure 5B is a schematic cross-sectional view for illustrating the manufacturing method of a multi-chip module according to the first embodiment of this disclosure. Figure 6A is a schematic side cross-sectional view for illustrating a conventional multi-chip module manufacturing method. Figure 6B is a schematic cross-sectional view illustrating a conventional method for manufacturing a multi-chip module. Figure 7A is a schematic top view showing the configuration of a multi-chip module according to a second embodiment of the present disclosure. Figure 7B is a schematic cross-sectional view showing the configuration of a multi-chip module mounting substrate on which the multi-chip module according to a second embodiment of the present disclosure is mounted. Figure 8A is a schematic top view illustrating a method for manufacturing a multi-chip module according to a second embodiment of the present disclosure. Figure 8B is a schematic side cross-sectional view illustrating a method for manufacturing a multi-chip module according to a second embodiment of the present disclosure. Figure 9A is a schematic top view illustrating a method for manufacturing a multi-chip module according to a second embodiment of the present disclosure. Figure 9B is a schematic side cross-sectional view illustrating a method for manufacturing a multi-chip module according to a second embodiment of the present disclosure. Figure 10A is a schematic top view illustrating a method for manufacturing a multi-chip module according to a second embodiment of the present disclosure.Figure 10B is a schematic cross-sectional view illustrating a method for manufacturing a multi-chip module according to a second embodiment of the present disclosure. Forms for implementing this disclosure

[0012] <First Embodiment> A multi-chip module according to the first embodiment of this disclosure will be described with reference to Figures 1 to 7B.

[0013] <Configuration of the Multi-Chip Module> As shown in Figures 1A and 1B, the multi-chip module 10 according to this embodiment comprises a plurality (N) of package substrates 11, a logic IC 12, an electronic integrated circuit (EIC) 13, a photoelectric conversion IC 14, and a reinforcing fixing frame 15.

[0014] Multiple package substrates 11 are arranged on a horizontal plane. Hereinafter, "horizontal direction" refers to the direction parallel to the upper surface of the package substrate 11. "Vertical direction" refers to the direction perpendicular to the upper surface of the package substrate 11.

[0015] The size of the package substrate 11 may be, for example, about 10 cm x 10 cm. The thickness of the package substrate 11 may be, for example, about 1.5 mm. The spacing between the package substrates 11 arranged on a horizontal plane may be, for example, about 0.5 cm to 1.0 cm.

[0016] As shown in Figure 1B, the package substrate 11 is provided with an electrical connection section 16 on its bottom surface. The package substrate 11 is electrically connected to the power supply and signal transmission electrical wiring of the printed circuit board (PCB) 101 via the electrical connection section 16. The electrical connection section 16 may be BGA, PGA, or LGA, or other electrical connection methods may be used. In this way, the multi-chip module mounting board is constructed from the multi-chip module 10 and the printed circuit board (PCB) 101.

[0017] Multiple logic ICs 12 are arranged on the package substrate 11. The size of the logic ICs 12 may be approximately 3 cm x 3 cm. The thickness of the logic ICs 12 may be, for example, approximately 0.8 mm. The logic ICs 12 may be arranged at intervals of, for example, approximately 0.5 μm.

[0018] The photoelectric conversion IC 14 performs the conversion of optical signals to electrical signals and transmits and receives optical signals between the package substrate 11. The photoelectric conversion IC 14 comprises a photoelectric conversion device 141 that converts optical signals to electrical signals and optical wiring 142 that connects the photoelectric conversion devices 141. For example, in the photoelectric conversion IC 14, a semiconductor laser or photodiode mounted as the photoelectric conversion device 141 on the SOI substrate may be optically connected by a Si waveguide (optical wiring 142). The size of the photoelectric conversion IC 14 may be, for example, about 3 cm × 3 cm to 4 cm × 4 cm. The thickness of the photoelectric conversion IC 14 may be, for example, about 0.5 mm.

[0019] For example, as shown in Figure 1A, three logic ICs 12 and one photoelectric conversion IC 14 are arranged in a 2x2 configuration. This configuration reduces the distance difference between the photoelectric conversion IC 14 and each logic IC 12, thereby suppressing differences in transmission characteristics between the photoelectric conversion IC 14 and each logic IC 12. Furthermore, the distance between the photoelectric conversion IC 14 and each logic IC 12 can be made approximately equal, resulting in approximately equal transmission characteristics between the photoelectric conversion IC 14 and each logic IC 12.

[0020] At least one electronic integrated circuit (EIC) 13 is placed on the package substrate 11 and is electrically connected to the photoelectric conversion IC 14. The EIC 13 is placed in the vicinity of each of the N adjacent vertices of the N package substrates 11. For example, as shown in Figure 1A, in a configuration where four package substrates 11 are placed adjacently in a 2x2 arrangement, the EIC 13 is placed in the vicinity of each of the four adjacent vertices of each package substrate 11.

[0021] In this way, the photoelectric conversion IC 14 is electrically connected via the electronic integrated circuit (EIC) 13 to the vicinity of each adjacent vertex (such as electrical wiring) on ​​each of the multiple package substrates 11.

[0022] The reinforcing fixing frame 15 is made of metal or resin. A metal construction of the reinforcing fixing frame 15 can improve heat dissipation. The reinforcing fixing frame 15 is placed between multiple package substrates 11 and fixes (attaches) the package substrates 11 to each other. This allows multiple package substrates 11 to be integrated. The reinforcing fixing frame 15 may be configured in a grid pattern when viewed from above, as shown in Figure 1A.

[0023] More specifically, as shown in Figure 1C, the reinforcing fixing frame 15 comprises a base portion and a beam portion. The reinforcing fixing frame 15 may have a T-shaped cross-section.

[0024] The base portion 151 extends perpendicularly to the upper surface of the package substrate 11 (the surface on which the logic IC 12 and EIC 13 are mounted) and is positioned between opposing end faces of adjacent package substrates 11. The width of the base portion 151 is, for example, about 0.5 mm to 1.0 mm. The base portion 151 may also be positioned on the outer periphery of the multi-chip module 10.

[0025] The beam portion 152 is provided at one end of the base portion 151 and extends perpendicular to the opposing end faces of the adjacent package substrates 11. The beam portion 152 extends toward both adjacent package substrates 11. The beam portion 152 is positioned such that its bottom surface abuts against the upper surface of the adjacent package substrates 11. In the reinforcing fixing frame 15, the beam portion 152 provided on the base portion 151, which is positioned on the outer periphery of the multi-chip module 10, may extend horizontally only toward the inside of the multi-chip module 10.

[0026] This allows the upper surfaces of the package substrate 11 to be defined on substantially the same horizontal plane. As a result, the heights of the EIC 13 can be made uniform. That is, the upper surfaces of the EIC 13 can be set on substantially the same horizontal plane. "Substantially the same horizontal plane" includes the same horizontal plane and includes a range of about 10 μm in the vertical direction.

[0027] In a multi-chip module, data is transmitted between logic ICs 12 on the same package substrate 11 via electrical wiring. Data is transmitted between logic ICs 12 on different package substrates via photoelectric conversion IC 14.

[0028] <Effects> The effects of the multi-chip module 10 according to this embodiment will be explained with reference to Figure 2.

[0029] First, for comparison, the configuration of a conventional multi-chip module 20 will be described. In a conventional multi-chip module 20, signals are transmitted and received using only electrical wiring without the use of a photoelectric conversion IC. Figure 2 shows the communication path between logic ICs 22 on different package substrates 21 in a conventional multi-chip module. In this configuration, as an example, the package substrate 21 and PCB 201 are connected by solder balls 27.

[0030] In this configuration, the communication path includes not only package substrate wiring but also solder balls 27, PCB wiring 202, and PCB through-holes 203. PCB wiring 202 consists only of the wiring layers on the inside of PCB 201. Furthermore, through-holes 203 are formed on PCB 201, connecting from the side on which the package substrate 21 is mounted to the wiring layers inside the PCB, penetrating through all the wiring layers of the PCB. As a result, an excess portion 204 is created in the through-hole 203 (the portion enclosed by the dotted line in the figure). The parasitic elements (capacitance) of this excess portion 204 degrade the signal quality when the bit rate increases during communication between logic ICs 22.

[0031] On the other hand, in the multi-chip module according to this embodiment, signals between package substrates 11 are transmitted and received via the photoelectric conversion IC 14, and electrical wiring is arranged only within the package substrate 11. As a result, high-speed electrical wiring in the PCB is unnecessary, and signal quality can be easily ensured.

[0032] <Manufacturing Method for Multi-Chip Modules> The manufacturing method for multi-chip modules according to this embodiment will be described with reference to Figures 3A to 5B. Figures 3A, 4A, and 5A show schematic top views of the structure in each process. Figures 3B, 4B, and 5B show cross-sectional side views of the structure in each process.

[0033] First, the logic IC 12 and EIC 13 are mounted on the package substrate 11 (Figures 3A and 3B).

[0034] Next, the base portion 151 of the reinforcing fixing frame 15 is inserted (fitted) between the opposing end faces of the adjacent package substrates 11, thereby fixing (securing) the package substrates 11 and the reinforcing fixing frame 16. Multiple package substrates 11 are then integrated, aligning the positions of the optical I / O and optical connection portions in the horizontal and vertical directions (Figures 4A and 4B).

[0035] In the assembly of the package substrate 11, the package substrate 11 and the reinforcing fixing frame 15 may be bonded together. Alternatively, metal may be placed around the package substrate 11 and on the contact surface of the reinforcing fixing frame 15 with the package substrate 11, and then fixed in place with solder or the like.

[0036] Finally, the photoelectric conversion IC 14 is placed on the EIC on each package substrate 11 and electrically connected (Figures 5A and 5B). For the electrical connection, solder bump processing or Cu pillar formation may be used, or other methods may be used. Since the photoelectric conversion IC 14 is equipped with optical wiring 142 that connects the photoelectric conversion devices 141, optical connections between optical components are unnecessary.

[0037] <Effects> The effects of the multi-chip module 10 according to this embodiment and its manufacturing method are described below.

[0038] First, for comparison, the process of mounting a conventional multi-chip module onto a PCB will be explained with reference to Figures 6A and 6B.

[0039] First, the logic IC 32 and EIC 33 are mounted on the package substrate 31 at a scale of C4 bumps (approximately 150 μm pitch).

[0040] Next, the package substrate 31 is mounted onto the PCB 301 (Figure 6A).

[0041] In the electrical connection between the package substrate 31 and the PCB 301, solder balls and the like placed between the top surface of the PCB 301 and the bottom surface of the package substrate 31 are fabricated with a scale of approximately 1 mm pitch. This scale is larger than the scale of the C4 bumps (approximately 150 μm pitch) in the electrical connection between the logic IC 32 and the package substrate 31. Thus, high positional accuracy is not required for the electrical connection on the PCB 301 (the positional accuracy is loose).

[0042] Finally, a photoelectric conversion IC 34 is mounted on an EIC 33 mounted on a package substrate 31 on the PCB 301 (FIG. 6B). In this mounting process, for the electrical connection between the EIC 33 and the photoelectric conversion IC 34, the accuracy equivalent to a C4 bump is required.

[0043] Thus, in the conventional method, the logic IC 32 and the EIC 33 are mounted on the package substrate 31 with high precision, and after performing an electrical connection with loose positional accuracy, an optical connection that requires high precision again is performed.

[0044] In this case, for example, after entrusting the mounting process of the logic IC and the EIC to a manufacturing company A having high-precision mounting technology, a process with loose accuracy (the process of mounting on the PCB) is entrusted to another manufacturing company (a manufacturing company having cost competitiveness) B at low cost, and furthermore, it is necessary to entrust the optical connection process to the manufacturing company A again. As a result, the manufacturing process becomes complicated and the manufacturing cost increases.

[0045] Also, in the conventional multi-chip module 30, at the height of each EIC 33 (the position in the vertical direction of the upper surface of the EIC 33) mounted on the package substrate mounted on the PCB, the individual differences in the height of the electrical connection portion 16 of the package substrate and the individual differences in the thickness of the package substrate are superimposed. As a result, the variation in the height of the EIC 33 increases.

[0046] Further, due to the warpage of the PCB 301, the package substrate 31, and the photoelectric conversion IC 34, the variation in the height of the EIC 33 further increases.

[0047] Due to these, the tolerance of the height variation required for the electrical connection between the EIC 33 and the photoelectric conversion IC 34 increases, and the mounting becomes difficult. As a result, it is difficult to perform the optical connection process after mounting on the PCB 301.

[0048] Next, the mounting process of the multi-chip module 10 according to the present embodiment on the PCB 101, that is, the manufacturing process of the multi-chip module mounting substrate, will be described with reference to FIG. 1B. FIG. 1B shows a cross-sectional view of the multi-chip module mounting substrate.

[0049] As described above, the multi-chip module 10 is manufactured by first mounting the logic IC 12 and EIC 13 on the package substrate 11 on a C4 bump scale (approximately 150 μm pitch), and then connecting the package substrates 11 with high precision using the photoelectric conversion IC 14. Next, the multi-chip module 10 is mounted on the PCB 101 on a scale of approximately 1 mm pitch.

[0050] In this way, after the high-precision manufacturing process of the multi-chip module 10 using the C4 bump scale mounting process and the optical connection process, the PCB mounting (electrical connection) process, which requires less precise positioning, is carried out, thus separating the processes that require high precision from those that require less precision.

[0051] This allows, for example, a manufacturing company with high-precision mounting technology to handle the optical connection process, and then another manufacturing company (one with cost competitiveness) to handle the less precise process (the PCB mounting process) at a lower cost. This reduces the cost of manufacturing multi-chip modules.

[0052] Furthermore, in the multi-chip module 10, the bottom surface of the beam portion of the reinforcing fixing frame 15 contacts the top surface of the package substrate, thereby aligning the vertical position of the mounting structure of each package substrate.

[0053] Furthermore, by having the side surface of the base of the reinforcing fixing frame contact the end face of the package substrate, the horizontal position of the mounting structure of each package substrate can be aligned. As a result, the horizontal position of the optical I / O and optical connection parts can be aligned.

[0054] Furthermore, variations in the tilt of the optical I / O and optical connection parts can be suppressed.

[0055] As a result, variations in the vertical and horizontal position and tilt of the mounting structure of each package substrate can be reduced, and the tolerance for position and tilt variations required for the electrical connection between the EIC 13 and the photoelectric conversion IC 14 can be reduced. This allows for easy optical connection between each package substrate. Furthermore, the optical connection process can be performed before mounting on the PCB 101.

[0056] According to this embodiment, the number of integrated logic ICs in a multi-chip module can be increased, and the connections between each logic IC can be made with low latency.

[0057] Furthermore, in the manufacturing of multi-chip modules, the integration process of multiple package substrates, which requires high positional accuracy, can be separated from the mounting process on PCBs, which requires less precise positional accuracy.

[0058] Furthermore, according to this embodiment, since there is no need to connect optical components that require high alignment accuracy, the yield can be improved and costs can be reduced.

[0059] In the embodiments of this disclosure, an example is shown in which one EIC and three logic ICs are arranged on the same logic board, but the number of logic ICs is not limited to this, and multiple logic ICs may be arranged. Also, although an example is shown in which four package boards are arranged, two or other package boards may be arranged.

[0060] <Second Embodiment> A multi-chip module according to the second embodiment of the present disclosure will be described with reference to Figures 7A to 10B.

[0061] <Configuration of the Multi-Chip Module> As shown in Figures 7A and 7B, the multi-chip module 40 according to this embodiment comprises a plurality of package substrates 41, a logic IC 42, an electronic integrated circuit (EIC) 43, a photoelectric conversion IC 44, and a reinforcing fixing frame 45.

[0062] As shown in Figure 7B, the package substrate 41 has an electrical connection portion 46 on its bottom surface. The package substrate 41 is mounted on the printed circuit board (PCB) 401 via the electrical connection portion 46.

[0063] At least one electronic integrated circuit (EIC) 43 is placed on the package substrate 41 and is electrically connected to the photoelectric conversion IC 44.

[0064] The EIC 43 may be positioned near the center of the package substrate 41. Multiple logic ICs 42 may be positioned around the EIC 43. The EIC 43 may be positioned near the center of the area surrounded by the multiple logic ICs 42. This reduces the difference in distance between the EIC 43 and each logic IC 42, and suppresses the difference in transmission characteristics between the EIC 43 and each logic IC 42. In addition, the distance between the EIC 43 and each logic IC 42 can be made approximately equal, and the transmission characteristics between the EIC 43 and each logic IC 42 can be made approximately equal.

[0065] More specifically, the "center of the region enclosed by multiple logic ICs 42" may be the region enclosed by lines connecting the centers of the multiple logic ICs 42. The "near the center" includes a predetermined range from the center, and may be, for example, a range of about half the size of the logic IC 42 from the center, or a range of 1.0 cm to 2.0 cm from the center.

[0066] The photoelectric conversion IC 44 includes a photoelectric conversion device 441 that converts optical signals to electrical signals, and optical wiring 442 that connects the photoelectric conversion devices 441.

[0067] The photoelectric conversion IC 44 includes a plurality of metal vias 443. The metal vias 443 penetrate between the top and bottom surfaces of the photoelectric conversion IC 44, and one end of each metal via 443 is connected to the logic IC 42.

[0068] In conventional multi-chip modules and the multi-chip module according to the first embodiment, the logic IC 42 on the package substrate 41 is exposed to the outside air, so the heat generated by the logic IC 42 can be easily dissipated.

[0069] On the other hand, as described above, in a configuration where multiple logic ICs 42 are arranged between the photoelectric conversion IC 44 and the package substrate 41, if the photoelectric conversion IC 44 does not have metal vias, the heat generated by the logic ICs 42 is blocked by the photoelectric conversion IC 44 and cannot be easily dissipated. As a result, the device characteristics deteriorate.

[0070] In the multi-chip module 40 according to this embodiment, the heat generated by the multiple logic ICs 42 between the photoelectric conversion IC 44 and the package substrate 41 can be easily dissipated by the metal via 443 of the photoelectric conversion IC 44. The multi-chip module 40 may also have a heat dissipation portion (such as metal) to which the other end of the metal via 443 is connected. Alternatively, the other end of the metal via 443 may be connected to an external cooling device.

[0071] In this embodiment, the configuration other than that described above is the same as in the first embodiment.

[0072] The multi-chip module 40 according to this embodiment may be manufactured in the same manner as the first embodiment, as shown in Figures 8A to 10B.

[0073] First, the logic IC 42 and EIC 43 are mounted on the package substrate 41 (Figures 8A and 8B).

[0074] Next, the base of the reinforcing fixing frame 45 is inserted (fitted) between the opposing end faces of the adjacent package substrates 41, thereby fixing (securing) the package substrates 41 and the reinforcing fixing frame 45 (Figures 9A and 9B).

[0075] Finally, the photoelectric conversion IC 44 is placed on the EIC 43 on each package substrate 41 and electrically connected (Figures 10A and 10B).

[0076] According to this embodiment, the number of integrated logic ICs in a multi-chip module can be increased, and the connections between each logic IC can be made with low latency.

[0077] Furthermore, in the manufacturing of multi-chip modules, the integration process of multiple package substrates, which requires high positional accuracy, can be separated from the mounting process on PCBs, which requires less precise positional accuracy.

[0078] Furthermore, according to this embodiment, since there is no need to connect optical components that require high alignment accuracy, the yield can be improved and costs can be reduced.

[0079] Furthermore, according to this embodiment, the transmission characteristics between the EIC connected to the photoelectric conversion IC and the multiple logic ICs can be equalized.

[0080] In this embodiment, an example is shown in which eight logic ICs are arranged around the EIC, but the number of logic ICs is not limited to this, and multiple logic ICs may be arranged. Also, an example is shown in which four package substrates are arranged, but the number of package substrates is not limited to this, and multiple package substrates may be arranged.

[0081] The implementation structure according to the embodiments of this disclosure may be used in communication devices. Alternatively, it may be used in devices such as arithmetic units, computing devices (computers), and signal processing devices. A device equipped with the implementation structure according to this embodiment may be used in a data center. Multiple devices may be connected to form a network.

[0082] In the embodiments described herein, an example is shown in which the EIC and logic IC are arranged in the same pattern on each of the multiple package substrates, but the invention is not limited to this. The EIC and logic IC may be arranged in different patterns on each of the multiple package substrates.

[0083] In the embodiments described herein, examples of the structure, dimensions, materials, etc., of each component in the configuration and manufacturing method of a multi-chip module are shown, but the invention is not limited thereto. Any configuration that allows the multi-chip module to perform its function and achieve its intended effect is acceptable.

[0084] It should be noted that this disclosure is not limited to the embodiments described above, and it is evident that many modifications and combinations are possible within the technical concept of this disclosure by a person with ordinary skill in the art.

[0085] Some or all of the embodiments described above, or examples thereof, may also be described as follows, but are not limited to these.

[0086] (Note 1) A multi-chip module comprising: N package substrates arranged horizontally; a plurality of logic ICs arranged on the package substrates; an EIC arranged on the package substrates; photoelectric conversion ICs connected to the plurality of EICs; and a reinforcing fixing frame arranged between the package substrates.

[0087] (Note 2) The multichip module according to Note 1, wherein the photoelectric conversion IC comprises a photoelectric conversion device connected to the EIC and optical wiring connected to the photoelectric conversion device.

[0088] (Note 3) The multi-chip module according to Note 1 or Note 2, wherein each of the N EICs is located near each of the N adjacent vertices of the N package substrates.

[0089] (Note 4) The multichip module according to Note 1 or Note 2, wherein the EIC is located near the center of the region surrounded by the plurality of logic ICs.

[0090] (Note 5) The multichip module according to any one of Notes 1 to 4, wherein the photoelectric conversion IC is provided with metal vias that penetrate the upper and lower surfaces of the photoelectric conversion IC, and one end of the metal vias is connected to the logic IC.

[0091] (Appendix 6) An apparatus comprising a multi-chip module as described in any of Appendix 1 to 5.

[0092] (Note 7) A data center equipped with the devices described in Note 6.

[0093] (Note 8) A method for manufacturing a multi-chip module mounting substrate, comprising the steps of: mounting an EIC and a plurality of logic ICs on a package substrate; fixing N of the package substrates via a reinforcing fixing frame; mounting a photoelectric conversion IC connected to the EIC; and mounting the N of the package substrates fixed via the reinforcing fixing frame onto a printed circuit board.

[0094] (Note 9) The multichip module according to any one of Notes 1 to 5, wherein the reinforcing fixing frame comprises a base and a beam, the base extending perpendicularly to the upper surface of the package substrate and positioned between opposing end faces of adjacent package substrates, and the beam being provided at one end of the base, extending perpendicularly to the end face, and positioned so that the bottom surface of the beam abuts the upper surface of the package substrate.

[0095] (Note 10) A multichip module mounting board comprising a multichip module as described in any of Notes 1 to 5 or 9, and a printed circuit board, wherein the multichip module is provided with an electrical connection part, and the multichip module is arranged on the printed circuit board via the electrical connection part.

[0096] (Note 11) The method for manufacturing a multi-chip module mounting substrate according to Note 8, wherein the photoelectric conversion IC comprises a photoelectric conversion device connected to the EIC and optical wiring connected to the photoelectric conversion device.

[0097] (Note 12) A method for manufacturing a multi-chip module mounting substrate according to Note 8 or Note 11, wherein each of the plurality of EICs is arranged near adjacent vertices among the vertices of the plurality of package substrates.

[0098] (Note 13) A method for manufacturing a multichip module mounting substrate according to any one of Notes 8, 11, or 12, wherein the photoelectric conversion IC is provided with metal vias that penetrate the upper and lower surfaces of the photoelectric conversion IC, and one end of the metal vias is connected to the logic IC.

[0099] (Note 14) A method for manufacturing a multichip module mounting substrate according to any one of Notes 8, 11 to 13, wherein the EIC is located near the center of the region surrounded by the plurality of logic ICs.

[0100] This disclosure relates to a multichip module and a method for manufacturing the same, and can be applied to communication devices, computing devices, computers, signal processing devices, and the like.

[0101] 10 Multi-chip module 11 Package substrate 12 Logic IC 13 EIC 14 Photoelectric conversion IC 15 Reinforcement fixing frame

Claims

1. A multi-chip module comprising: N package substrates arranged horizontally; a plurality of logic ICs arranged on the package substrates; an EIC arranged on the package substrates; photoelectric conversion ICs connected to the plurality of EICs; and a reinforcing fixing frame arranged between the package substrates.

2. The multichip module according to claim 1, wherein the photoelectric conversion IC comprises a photoelectric conversion device connected to the EIC and optical wiring connected to the photoelectric conversion device.

3. The multi-chip module according to claim 1 or claim 2, wherein each of the N EICs is located near each of the N adjacent vertices of the N package substrates.

4. The multichip module according to claim 1 or claim 2, wherein the EIC is located near the center of the region surrounded by the plurality of logic ICs.

5. The multichip module according to claim 1 or 2, wherein the photoelectric conversion IC is provided with metal vias that penetrate the upper and lower surfaces of the photoelectric conversion IC, and one end of the metal vias is connected to the logic IC.

6. An apparatus comprising the multi-chip module described in claim 1 or claim 2.

7. A data center comprising the apparatus described in claim 6.

8. A method for manufacturing a multi-chip module mounting substrate, comprising the steps of: mounting an EIC and a plurality of logic ICs on a package substrate; fixing N of the package substrates via a reinforcing fixing frame; mounting a photoelectric conversion IC connected to the EIC; and mounting the N of the package substrates fixed via the reinforcing fixing frame onto a printed circuit board.

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