Semiconductor device
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- HITACHI HIGH TECH CORP
- Filing Date
- 2025-01-30
- Publication Date
- 2026-08-06
Smart Images
Figure JP2025002916_06082026_PF_FP_ABST
Abstract
Description
Semiconductor equipment
[0001] This disclosure relates to a semiconductor device on which a TEG is implemented.
[0002] In the manufacturing process of semiconductor devices, the importance of testing the electrical characteristics of elements such as transistors, wiring, and contact plugs is increasing. Semiconductor wafers are equipped with Testing Element Groups (TEGs) for process control purposes. TEGs are groups of evaluation elements used to evaluate the elements that make up integrated circuits, and are formed independently for each evaluation unit (hereinafter referred to as "evaluation element") to facilitate evaluation. To avoid reducing the integration density of the semiconductor wafer, they are often formed in scribe regions between chips. The electrical characteristics of evaluation elements of TEGs mounted on semiconductor wafers are also evaluated using in-line inspection and measurement equipment.
[0003] On the other hand, scanning electron microscopy (SEM) potential contrast method is used for inline electrical characteristic inspection of semiconductor devices. Electron beam irradiation causes charging, generating a potential on the sample surface. Since the brightness of the SEM image depends on the difference in surface potential, potential contrast is produced. The potential contrast method can identify electrical defects (open circuits, short circuits) based on the potential difference generated in the sample pattern. Patent Document 1 discloses a method for inspecting electrical characteristic defects using potential contrast with a TEG (Thermal Energy Generator).
[0004] Japanese Patent Publication No. 2010-45379
[0005] The sensitivity of potential contrast in electrical property testing depends on the difference in surface potential between sample patterns formed by an electron beam. However, for elements with low resistance of less than megaohms or minute capacitance of less than femtof, the electron beam irradiation dose from a normal scanning electron microscope is insufficient to form a surface potential, resulting in a small difference in the surface potential of the elements. As a method to improve the sensitivity of potential contrast, intermittent electron beam irradiation, which utilizes the difference in transient changes in surface potential, has been proposed. However, for patterns of elements with low resistance or minute capacitance, the surface potential that can be formed is too low, so the difference in surface potential cannot be greatly expanded, resulting in insufficient sensitivity for electrical property testing.
[0006] One embodiment of the present disclosure is a semiconductor device on which a Test Element Group (TEG) is mounted, the electrical characteristics of which of the main elements are inspected by an inspection device, the inspection device inspects the electrical characteristics of the main elements based on the contrast of an image formed by scanning a pulsed charged particle beam, the TEG has an evaluation element, the evaluation element includes a main element and a sub-element, the first terminal of the main element is open to allow irradiation with a pulsed charged particle beam, the second terminal of the main element is connected to the first terminal of the sub-element, the second terminal of the sub-element is grounded, and the electrical characteristics of the sub-element are designed such that the combined electrical characteristics obtained by combining the electrical characteristics of the main element and the electrical characteristics of the sub-element fall within the range of electrical characteristics that the inspection device can inspect.
[0007] The present invention provides a semiconductor device capable of highly sensitively inspecting the electrical characteristics of a main element to be inspected. Other challenges and novel features will become apparent from the description herein and the accompanying drawings.
[0008] This figure shows an example of the configuration of a semiconductor testing apparatus. This figure shows an example of the hardware configuration of a control device. This is a schematic diagram of an example of the configuration of an evaluation element. This is an example of the structure of a TEG evaluation element. This is the equivalent circuit of evaluation element 302. This is a diagram for explaining the principle of this disclosure. This figure shows the inspection flow. This is a graph showing the dependence of the brightness L of a specified area on the interval time. This is a diagram for explaining the principle of this disclosure. This is an example of the structure of a TEG evaluation element. This is the equivalent circuit of evaluation element 702. This is a schematic diagram of an example of the configuration of an evaluation element. This is an example of the structure of a TEG evaluation element. This is the equivalent circuit of evaluation element 802. This is a schematic diagram of an example of the configuration of an evaluation element. This is an example of the structure of a TEG evaluation element. This is the equivalent circuit of evaluation element 902. This is a schematic diagram of an example of the configuration of an evaluation element. This is an example of the structure of a TEG evaluation element. This is the equivalent circuit of evaluation element 1002.
[0009] Figure 1A shows an example configuration of a semiconductor inspection apparatus for inspecting the electrical characteristics of a semiconductor wafer (semiconductor device) in this embodiment. Here, the electrical characteristics to be inspected are feature quantities calculated based on resistance, capacitance, and time constant. The semiconductor inspection apparatus 100 includes a charged particle optical system (in this case, an electron optical system), a stage mechanism system, a detection system, and a control system that controls these.
[0010] The electron optical system includes, as its main components, an electron source 102, an intermittent irradiator 103 that pulses the electron beam from the electron source 102, a deflector 104 that scans the electron beam over the sample 108, and an objective lens 105 that focuses the electron beam onto the sample 108. The intermittent irradiator 103 is implemented to control the surface potential of the sample 108 caused by the charging from electron beam irradiation. As the electron source 102, a photo-excited electron source that can easily emit a pulsed electron beam from the electron source itself may be used. The stage mechanism system includes a stage 107 on which the sample 108 to be inspected is placed. The detection system includes a detector 106 that detects signal electrons emitted when the electron beam is irradiated onto the sample 108, and an image forming unit 111 that forms an image based on the irradiation position of the electron beam on the sample 108 and the output signal from the detector 106. The electron optical system, detector 106, and stage mechanism system are housed in a housing 101, and the inside of the housing 101 is a vacuum environment.
[0011] The electron optical system, stage mechanism system, and detection system are controlled by a control system. The control system includes a control device 120 and an electron beam control unit 110. Here, the set of controllers that control each component (electron source 102, intermittent irradiator 103, etc.) housed in the housing 101 is referred to as the electron beam control unit 110. The electron beam control unit 110 controls each component according to the control signals from the device control unit 121 that are output according to user settings from the input unit 131. Specifically, it controls each component housed in the housing 101 so that the electron beam irradiation conditions and intermittence conditions 103a set by the user are met.
[0012] In Figure 1A, the control device 120, which constitutes the control system, is shown with its functions represented by functional blocks. The control device 120 has many functions, but here, the device control unit 121, which controls the electron optical system, the stage mechanism system, and the detection system, and the functional block that performs inspection of semiconductor elements are shown.
[0013] The control device 120 is implemented as a computer, primarily comprising a processor (Central Processing Unit: CPU) 141, memory 142, storage device 143, input interface (I / F) 144, output I / F 145, communication I / F 146, and bus 147, as shown in Figure 1B. The processor 141 functions as a functional unit (functional block) that provides predetermined functions by executing processing according to a program loaded into the memory 142. The storage device 143 stores data and programs used by the functional unit. The input I / F 144 is connected to an input unit 131 such as a keyboard, pointing device, or operation panel, and the output I / F 145 is connected to an output unit 132 such as a display. The communication I / F 146 enables communication with other information processing devices via a network. These are connected to each other via the bus 147.
[0014] In the following explanation, when describing processing by a program, the program or functional unit may be described as the main component. However, the main hardware component is the processor, or the computer that includes such a processor. The computer, using the processor as appropriate, executes processing according to the program read into memory, utilizing resources such as memory and communication interfaces. Figure 1B shows an example of a CPU as the processor, but a GPU (Graphical Processing Unit) or the like may also be used. Furthermore, the processing to realize the function is not limited to software program processing; it can also be implemented with dedicated circuits. Applicable dedicated circuits include FPGAs (Field Programmable Gate Arrays) and ASICs (Application Specific Integrated Circuits). In addition, some of the functions of the control device 120, for example, some or all of the function that performs semiconductor element inspection, may be implemented as an application on cloud computing.
[0015] Figure 2 schematically shows the configuration of the evaluation element constituting the TEG of this embodiment. The evaluation element 200 includes a main element 201, which is the object to be tested, as well as a sub-element 211. For connection with other circuit elements, the main element 201 is provided with a first terminal 202 and a second terminal 203, and the sub-element 211 is provided with a first terminal 212 and a second terminal 213.
[0016] As a comparative example, suppose the evaluation element is configured such that the first terminal 202 of the main element 201 is open and exposed from the sample surface 220, and the second terminal 203 of the main element 201 is connected to a reference potential point (0V) with a low resistance (hereinafter also referred to as "grounded"). When evaluating the electrical characteristics of the main element 201 using the potential contrast method, as described above, if the main element 201 is an element with extremely small electrical characteristics, the difference in surface potential obtained by the electron beam irradiation current is too small, and the contrast appearing in the SEM image is also small, making proper inspection difficult.
[0017] In contrast, the evaluation element 200 in this embodiment electrically superimposes the electrical characteristics of the sub-element 211 onto the main element 201, which is the object of inspection. The evaluation element 200 shown in Figure 2 grounds the main element 201 via the sub-element 211. That is, the second terminal 203 of the main element 201 is connected to the first terminal 212 of the sub-element 211, and the second terminal 213 of the sub-element 211 is grounded.
[0018] Figure 3A shows an example of the cross-sectional structure of a semiconductor wafer (semiconductor device) on which a TEG is mounted. The TEG 301 is composed of an evaluation element 302 whose main element is an MTJ (Magnetic Tunnel Junction) element. The main element, the MTJ element 310, has a structure in which a tunnel insulating layer 312 is sandwiched between magnetic layers 311. The upper magnetic layer 311a corresponds to the first terminal 202, and the lower magnetic layer 311b corresponds to the second terminal 203. On the other hand, the sub-element is a PN junction element composed of a P-type substrate 313 and an N-type layer 314, where the N-type layer 314 corresponds to the first terminal 212, and the P-type substrate 313 corresponds to the second terminal 213. The lower magnetic layer 311b of the MTJ element 310 and the N-type layer 314 of the PN junction element are connected with low resistance by a plug 316. In addition, the evaluation elements 302 are separated from each other by an insulating layer 315.
[0019] In the stage of performing in-line inspection on the TEG of the semiconductor wafer shown in Figure 3A, the upper surface of the upper magnetic layer 311a is at least open to allow irradiation by a pulsed electron beam, and the potential of the P-type substrate 313 is used as the reference potential. Since the electron beam has strong material penetration properties, the upper magnetic layer 311a does not need to be exposed to the outside and may be covered with an insulating film for the purpose of protecting the element. Figure 3B is the equivalent circuit of the evaluation element 302 shown in Figure 3A. The evaluation element 302 has an impedance, which is an electrical characteristic composed of different resistances R and capacitances C for both the main element 201 and the sub-element 211. The MTJ element has a resistance R on the order of kiloohms. ａ and the capacity C of the F order ａ It has such properties that it is difficult to perform a highly sensitive potential contrast test on its own. Therefore, the sub-element 211 is connected in series, and the evaluation element with the combined impedance is tested using the potential contrast method.
[0020] Incidentally, FIG. 3A shows, as an example of a defect expected to be detected by inspection, an example in which the magnetic layers 311 of the MTJ element 310 are connected to each other at the side wall of the tunnel insulating layer 312 as the evaluation element 302b. For such a defective MTJ element, its resistance R ａ and capacitance C ａ are different, so a potential contrast different from that of a normal MTJ element appears in the SEM image.
[0021] Using FIG. 4, the principle that the evaluation element 200 of the present embodiment can be inspected with high sensitivity by the semiconductor inspection apparatus 100 will be described. The electrical characteristics of the main element that can be inspected by the potential contrast method using the semiconductor inspection apparatus 100 depend on the performance of the semiconductor inspection apparatus 100 as a charged particle beam apparatus. The region of electrical characteristics that the semiconductor inspection apparatus 100 can detect is a region 401 defined by the range of detectable resistance R and capacitance C shown in FIG. 4.
[0022] Here, in the present invention, it is an inspection based on a transient potential change by a pulsed electron beam, and in the present invention, the electrical characteristics that affect the transient characteristics are expressed as impedance. The impedance that the semiconductor inspection apparatus 100 can detect is determined by (Equation 1) to (Equation 4). The resistance R in (Equation 1) to (Equation 4) is the detectable resistance, the capacitance C is the detectable electrostatic capacitance, and the time constant τ is the detectable time constant. τ ｄ is the discharge time constant, and τ ｃ represents the charging time constant.
[0023] R = V / I [[ID= nineteen ]] ｐ ・・・(Equation 1) C = I ｐ ・T ｐ / V ・・・(Equation 2) τ ｄ = RC = -T ｉ / (ln(V)) ・・・(Equation 3) τ ｃ = RC = -T ｐ / (ln(1 - V)) ・・・(Equation 4) Here, V is the surface potential of the sample that can be detected as the potential contrast, I ｐ is the irradiation current of the pulsed electron beam, and T ｐ is the pulse width (irradiation time) of the pulsed electron beam, and T ｉV, I are the intervals between pulsed electron beams. ｐ , T ｐ , T ｉ These are device-specific parameters whose range of possible values is limited. Region 401 is determined as the region that satisfies all of the constraints: the constraint range 402 due to the resistance R shown in (Equation 1), the constraint range 403 due to the capacitance C shown in (Equation 2), and the constraint range 404 due to the time constant τ shown in (Equation 3) and (Equation 4).
[0024] The impedance of the main element is outside region 401, and the semiconductor testing device 100 cannot perform electrical characteristic testing on it. However, by configuring the evaluation element with a main element and a sub-element as shown in Figure 2, and designing the sub-element so that the combined impedance of the main element and the sub-element is included in region 401, the semiconductor testing device 100 can perform electrical characteristic testing on the evaluation element 200. From the test results of the evaluation element 200, the electrical characteristics of the main element, such as impedance, can be extracted.
[0025] Figure 5A shows the inspection flow by the semiconductor inspection apparatus 100. First, the TEG information setting unit 122 sets the TEG evaluation element information input from the input unit 131 (S101). It is assumed that the SPICE model of the evaluation element that simulates the surface potential is used as the evaluation element information to be set here. In the case of the equivalent circuit of the evaluation element 302, as shown in Figure 3B, the main element 201 has a resistance component R ａ , capacitive component C ａ , time constant τ1 (=R ａ C ａ ) has a sub-element 211 which has a resistive component R ｂ , capacitive component C ｂ , time constant τ² (=R ｂ C ｂ ) is also included. Furthermore, the sub-element 211 is designed such that the relationship time constant τ1 < time constant τ2 holds true, so that the combined impedance of the main element and sub-element of the evaluation element 302 is included in the inspectable region 401 of the semiconductor inspection device 100 (see Figure 4).
[0026] Subsequently, the device control unit 121 sets the irradiation conditions and intermittent conditions of the electron beam input from the input unit 131 (S102, S103), controls the electron beam control unit 110 to irradiate the sample 108 with a pulsed electron beam, and the image forming unit 111 forms a SEM image (S104). Examples of the irradiation conditions of the electron beam include acceleration voltage, irradiation current, irradiation position, etc. Examples of the intermittent conditions of the electron beam include pulse width, interval time between pulses, etc. By defining several combinations of predetermined irradiation conditions and predetermined intermittent conditions of the electron beam in advance, registering each as an inspection recipe, and selecting any one of them, it is possible to easily set and reset the irradiation conditions and intermittent conditions of the electron beam.
[0027] The luminance analysis processing unit 127 analyzes the luminance of the specified region from the acquired SEM image (S105), and analyzes the dependence of the luminance on the irradiation conditions or intermittent conditions (S106). The specified region is specified by the user to determine whether the SEM image is an appropriate image for inspection. Alternatively, one point of the inspection location may be arbitrarily selected from the inspection recipe. For example, when acquiring while changing the interval time (interval), which is one of the intermittent conditions of the electron beam, an SEM image can be acquired in which the luminance of the specified region decreases as the interval time becomes longer. This is because the amount of charge discharge of the MTJ element 310 due to the irradiation of the pulsed electron beam increases as the interval time becomes longer. FIG. 5B is a graph showing the dependence of the luminance L of the specified region on the interval time. The horizontal axis is the interval time, and the vertical axis is the luminance of the specified region. Here, it is desirable that the analysis result is displayed on the output unit 132 and the user visually determines whether the amplitude of the change in the dependence of the luminance on the irradiation conditions or intermittent conditions is sufficient (S107). Alternatively, a threshold value for determining the quality of the amplitude of the change may be determined in advance, and the luminance analysis processing unit 127 may determine the quality. If it is determined (negative determination) that the change is insufficient, the process returns to step S102 to reset the irradiation conditions or intermittent conditions of the electron beam. It is preferable that the device control unit 121 selects another inspection recipe in which different irradiation conditions and intermittent conditions of the electron beam are defined according to the reason for the negative determination. If it is determined (positive determination) that the change is sufficient, the process proceeds to the next step S108.
[0028] The feature quantity setting unit 123 sets the first and second feature quantities input from the input unit 131 (S108). The first feature quantity is a feature quantity correlated with the electrical characteristics of the main element, and the second feature quantity is a feature quantity correlated with the electrical characteristics of the sub-element, and is a feature quantity that can be extracted from the dependence of brightness on the illumination conditions or intermittence conditions. Here, the first feature quantity is set as the time constant τ1, and the second feature quantity as the time constant τ2. At this time, the brightness L (objective variable) of the image of the MTJ element 310 shown in Figure 5B can be expressed as (Equation 5) with the first feature quantity τ1 and the second feature quantity τ2 as explanatory variables.
[0029] L = (1 - a)e (－ｔ／τ１) +ae (－ｔ／τ２) ... (Equation 5) Here, a is a coefficient and t is the interval time. Furthermore, in this embodiment, as shown in Figure 5B, the result shows a characteristic where brightness decreases with respect to the interval time, whereas depending on the pattern of the element, brightness may tend to increase with respect to the interval time. In that case, the equation (Equation 5) used with the first feature quantity τ1 and the second feature quantity τ2 as explanatory variables is the one that expresses the increasing trend.
[0030] The luminance analysis processing unit 127 and the feature analysis unit 128 perform feature analysis at multiple locations on the sample based on the inspection recipe (S109). For the inspection locations specified in the inspection recipe, the luminance analysis processing unit 127 determines the change characteristics of the luminance L at the inspection location, which changes depending on the irradiation conditions or intermittence conditions of the pulsed electron beam, and by fitting (Equation 5) to these change characteristics, it obtains a first feature quantity τ1 and a second feature quantity τ2 for each inspection location.
[0031] Furthermore, the feature amount analysis unit 128 determines whether the inspection result is good or bad based on the data distribution of the inspection target feature amount (here, the first feature amount τ1) (S110). For the determination of whether the data distribution is good or bad, the data distribution of the inspection target feature amount may be displayed on the output unit 132 for the user to visually determine, or the determination conditions for determining whether the data distribution is good or bad may be determined in advance, and the feature amount analysis unit 128 may perform the determination of whether it is good or bad. If the determination is negative, the process returns to step S102 to reset the irradiation condition or intermittent condition of the electron beam. The apparatus control unit 121 may select another inspection recipe in which different irradiation conditions and intermittent conditions of the electron beam are defined according to the reason for the negative determination. If the determination is positive, the process proceeds to the next step S111.
[0032] The normal / defect determination unit 126 statistically analyzes the data distribution of the time constant τ1 obtained for each inspection location, determines the normal main element and the main element having a defect, stores the inspection result in the data storage unit 129, and outputs it to the output unit 132 (S111). For example, a Q-Q plot is created for the first feature amount (time constant τ1) to discriminate between a normal main element and a main element having a defect. A Q-Q plot is a graph for comparing data with a theoretical distribution and examining their similarity, and has the feature that the plotted points line up in a straight line if they are similar. Assuming that the frequency distribution of the time constant τ1 of a normal main element follows a normal distribution, a Q-Q plot for comparison with the normal distribution is created. When the existence of a plurality of distributions is recognized, one of the distributions is considered to be the distribution of a normal main element, and the others are considered to be the distributions of main elements having defects.
[0033] Regarding which distribution indicates the data distribution of a normal main element, it is discriminated according to the conditions set by the normal / defect determination condition setting unit 125. For example, information on the frequency distribution of the time constant τ1 measured for evaluation elements having normal main elements and evaluation elements having defective main elements in the development stage of the inspection target element (MTJ element) is collected, and based on this information, the user sets the discrimination conditions. Alternatively, information for setting the discrimination conditions may be obtained by inspecting whether the main element was finally normal or had a defect with respect to the time constant τ1 of the main element obtained by the method of this embodiment in another lot.
[0034] In Figure 4, an example is shown in which the range detectable by the semiconductor inspection device 100 is defined by impedance. However, in the case of an evaluation element shown in Figure 3A, where both the main element and the sub-element have a resistive component R and a capacitive component C, the discharge time constant τ is determined based on (Equation 3) and (Equation 4). ｄ and the charging time constant τ ｃ This may define the region that the semiconductor inspection device 100 can detect. In the example shown in Figure 6, the region that the semiconductor inspection device 100 can detect is region 601.
[0035] The following describes a modified configuration of the TEG evaluation element.
[0036] (Modification 1) Modification 1 shows an example in which the sub-element is configured as a capacitor. Figure 7A shows an example of the cross-sectional structure of a semiconductor wafer on which the evaluation circuit of Modification 1 is mounted. The plug 316 is formed slightly apart from the P-type substrate 313, and a capacitor is formed between the plug 316 and the P-type substrate 313. Figure 7B is the equivalent circuit of the evaluation element 702 shown in Figure 7A.
[0037] (Modification 2) Figure 8A is a schematic diagram showing the configuration of the evaluation element 200B of Modification 2. The second terminals 203 of a plurality of main elements 201 are connected in parallel to the first terminals 212 of sub-elements 211, and each main element 201 is connected in series with a sub-element 211.
[0038] Figure 8B shows an example of the cross-sectional structure of a semiconductor wafer on which the evaluation element 802 of the modified example 2 is mounted. Plugs 316a, 316b, and 316c, which are connected to multiple MTJ elements 310, are commonly connected to the N-type layer 314. Figure 8C is the equivalent circuit of the evaluation element 802 shown in Figure 8B.
[0039] (Modification 3) Figure 9A is a schematic diagram showing the configuration of the evaluation element 200C of Modification 3. A contact terminal 911 is provided that connects the second terminal 203 of the main element 201 and the first terminal 212 of the sub-element 211. By, for example, contacting a probe with the contact terminal 911, it becomes possible to measure the electrical characteristics of the sub-element 211. Based on the measured values of the electrical characteristics of the sub-element 211, it becomes possible to detect the electrical characteristics of the main element 201 with higher accuracy.
[0040] Figure 9B shows an example of the cross-sectional structure of a semiconductor wafer on which the evaluation element 902 of Modified Example 3 is mounted. Here, the sub-element is SiO between the polysilicon layer 913 and the P-type substrate 313. ２ A capacitor is formed with layer 914 in between. Note that a metal layer may be used instead of the polysilicon layer, or SiO ２ The layers may be insulating layers made of different materials. Furthermore, a wiring layer 912 connecting the capacitor and the main element is electrically connected to the contact terminal 911. The contact terminal 911 is formed in the same layer as the upper magnetic layer 311a of the MTJ element 310, which corresponds to the first terminal of the main element. This makes it possible to contact the contact terminal 911 with a probe before, during, or after inspection by the semiconductor inspection device 100. Figure 9C is an equivalent circuit of the evaluation element 902 shown in Figure 9B.
[0041] (Modification 4) Figure 10A is a schematic diagram showing the configuration of the evaluation element 200D of Modification 4. In addition to the first terminal 212 and second terminal 213 of the sub-element 211, it has a control terminal 214, and the electrical characteristics of the sub-element are adjustable.
[0042] Figure 10B shows an example of the cross-sectional structure of a semiconductor wafer on which the evaluation element 1002 of Modified Example 4 is mounted. Here, a FET (field-effect transistor) is used as a sub-element with adjustable electrical characteristics. N-type layers 1012 and 1013, which will serve as the source or drain, are provided on a P-type substrate 313. The N-type layer 1013 (drain) is connected to the main element, an MTJ element 310, via a plug 316. A gate 1014 is provided between the N-type layer 1012 (source) and the N-type layer 1013 (drain) via a gate insulating film 1015. The gate 1014 is connected to a control terminal 1011, and by applying a predetermined voltage to the gate 1014 from the control terminal 1011, the size of the depletion layer formed in the channel is controlled, thereby changing the electrical characteristics of the FET (sub-element). The control terminal 1011 is formed in the same layer as the upper magnetic layer 311a of the MTJ element 310, which is the first terminal of the main element. Figure 10C is the equivalent circuit of the evaluation element 1002 shown in Figure 10B.
[0043] Here, we have shown an example of a sub-element whose electrical characteristics can be adjusted, namely an FET, but this is not the only example. For example, it is also possible to adjust the resistance value by using a chain resistor as the sub-element and controlling the number of resistors connected in series.
[0044] The above embodiments and modifications are described in detail for the purpose of making this disclosure easier to understand, and are not necessarily limited to those having all the configurations described. Furthermore, it is possible to replace parts of the configuration of one embodiment or modification with the configuration of another embodiment or modification, and it is also possible to add the configuration of another embodiment or modification to the configuration of one embodiment or modification. In addition, it is possible to add, delete, or replace parts of the configuration of each embodiment or modification with other configurations. Furthermore, although the example was described using an MTJ element as the main element, it may also be an element or structure such as a field-effect transistor, contact plug, or wiring.
[0045] 100: Semiconductor inspection device, 101: Housing, 102: Electron source, 103: Intermittent irradiator, 103a: Intermittent conditions, 104: Deflector, 105: Objective lens, 106: Detector, 107: Stage, 108: Sample, 110: Electron beam control unit, 111: Image forming unit, 120: Control device, 121: Device control unit, 122: TEG information setting unit, 123: Feature quantity setting unit, 125: Normal / defect judgment condition setting unit, 126: Normal / defect judgment unit, 127: Brightness analysis processing unit, 128: Feature quantity analysis unit, 129: Data storage unit, 131: Input unit, 132: Output unit, 141: Processor, 142: Memory, 143: Storage device, 144: Input I / F, 145: Output I / F, 146: Communication I / F, 147: Bus, 200, 200B, 200C, 200D: Evaluation element, 201: Main element, 202: First terminal, 203: Second terminal, 211: Sub-element, 212: First terminal, 213: Second terminal, 214: Control terminal, 220: Sample surface, 302: Evaluation element, 310: MTJ element, 311: Magnetic layer, 312: Tunnel insulating layer, 313: P-type substrate, 314: N-type layer, 315: Insulating layer, 316: Plug, 401, 601: Region, 702: Evaluation element, 802: Evaluation element, 902: Evaluation element, 911: Contact terminal, 912: Wiring layer, 913: Polysilicon layer, 914: SiO ２Layer, 1002: evaluation element, 1011: control terminal, 1012, 1013: N-type layer, 1014: gate, 1015: gate insulating film.
Claims
1. A semiconductor device equipped with a Test Element Group (TEG) whose electrical characteristics of a main element are inspected by an inspection device, wherein the inspection device inspects the electrical characteristics of the main element based on the contrast of an image formed by scanning a pulsed charged particle beam, the TEG has an evaluation element, the evaluation element includes the main element and a sub-element, the first terminal of the main element is open to allow irradiation of the pulsed charged particle beam, the second terminal of the main element is connected to the first terminal of the sub-element, the second terminal of the sub-element is grounded, and the electrical characteristics of the sub-element are designed such that the combined electrical characteristics obtained by combining the electrical characteristics of the main element and the electrical characteristics of the sub-element fall within the range of electrical characteristics that the inspection device can inspect.
2. The semiconductor device according to claim 1, wherein the electrical characteristics of the main element inspected by the inspection device are the resistance, capacitance, and characteristic quantities calculated based on the resistance and / or capacitance of the main element.
3. The semiconductor device according to claim 1, wherein the region of electrical characteristics that the inspection device can inspect is defined by the range of detectable resistance and capacitance.
4. The semiconductor device according to claim 1, wherein the region of electrical characteristics that the inspection device can inspect is defined by the range of detectable charge time constants and discharge time constants.
5. The semiconductor device according to claim 1, wherein the evaluation element includes a plurality of main elements, and the second terminals of the plurality of main elements are connected in parallel to the first terminal of the sub-element.
6. The semiconductor device according to claim 1, wherein the evaluation element has a contact terminal, the contact terminal is connected to the second terminal of the main element and the first terminal of the sub-element, and is formed in the same layer as the first terminal of the main element.
7. The semiconductor device according to claim 1, wherein the sub-element comprises an adjustment structure for adjusting its electrical characteristics.
8. The semiconductor device according to claim 7, wherein the sub-element is a field-effect transistor, the first terminal of the sub-element is the drain of the field-effect transistor, the second terminal of the sub-element is the source of the field-effect transistor, the gate of the field-effect transistor is connected to a control terminal, and the control terminal is formed in the same layer as the first terminal of the main element.
9. The semiconductor device according to claim 1, wherein the sub-element is a PN junction element, a capacitor, a field-effect transistor, and a chain resistor.
10. The semiconductor device according to claim 1, wherein the first terminal of the main element is covered with an insulating film.