Semiconductor optical integrated element and method for manufacturing semiconductor optical integrated element

Abstract

A semiconductor optical integrated element (100, 110) according to the present disclosure comprises: a semiconductor substrate (1); a striped mesa structure (21) that is provided on the semiconductor substrate (1) with a gap (20) therebetween; a plurality of supporting insulating films (30) that are periodically formed on both side surfaces of the mesa structure (21) while maintaining a constant interval between the films in the direction of the stripes, and that have one lower end in contact with the semiconductor substrate (1); and a heater electrode (11, 11a) that is provided to the upper surface of the mesa structure (21) along the direction of the stripes.

Description

Semiconductor optical integrated device and method for manufacturing semiconductor optical integrated device

[0001] The present disclosure relates to a semiconductor optical integrated device and a method for manufacturing a semiconductor optical integrated device.

[0002] With the progress of digital transformation that utilizes digital information, the development of communication networks that exchange digital information and data centers that perform data storage and processing has been remarkable. Optical communication is used for communication networks and intra-data center communication, and has made remarkable progress in recent years in terms of high speed and large capacity.

[0003] One of the key devices for optical communication is a phase modulator. As an example of a phase modulator, there is a method of adjusting the phase by changing the refractive index of an optical waveguide layer or a diffraction grating layer of an optical waveguide structure by heating with a heater electrode (for example, Patent Document 1).

[0004] In the waveguide structure described in Patent Document 1, a heat insulation gap extending from one side of the waveguide ridge is provided between the waveguide ridge and the substrate, and the waveguide ridge is supported by vias on the other side. In such a waveguide structure, the heat insulation property of the waveguide ridge is improved by the heat insulation gap, so that efficient optical phase adjustment can be realized by the heat from the heater provided on the upper part of the waveguide ridge.

[0005] Japanese Patent Application Laid-Open No. 2019-530978

[0006] However, in the waveguide structure described in Patent Document 1, since it is supported by vias only from one side of the waveguide ridge, there is a problem that it is structurally unstable. The structural instability of the element structure may reduce the product yield during manufacturing and the reliability of the product.

[0007] The present disclosure has been made to solve the above problems, and an object thereof is to obtain a semiconductor optical integrated device that is structurally stable as an element structure and is easy to manufacture, and a manufacturing method that can easily manufacture a structurally stable semiconductor optical integrated device.

[0008] The semiconductor optical integrated element according to this disclosure comprises: a semiconductor substrate; a stripe-shaped mesa structure provided on the semiconductor substrate with air gaps between them; a plurality of support insulating films periodically formed on both sides of the mesa structure along the stripe direction, with one lower end in contact with the semiconductor substrate; and a heater electrode provided on the upper surface of the mesa structure along the stripe direction.

[0009] A method for manufacturing a semiconductor optical integrated element according to the present disclosure comprises the steps of: growing at least a sacrificial layer, a first cladding layer, an optical waveguide layer, and a second cladding layer on a semiconductor substrate; forming a pair of mesa grooves on the sacrificial layer by etching, thereby forming a mesa structure on the sacrificial layer; selectively removing the sacrificial layer exposed on the bottom surface of the pair of mesa grooves by selective etching, and selectively removing a portion of the sacrificial layer on the lower side of the mesa structure from both sides of the mesa structure; forming insulating films on both sides of the mesa structure; periodically removing the insulating films in a stripe direction to form a plurality of support insulating films; and selectively removing the remaining sacrificial layer on the lower side of the mesa structure by selective etching the sacrificial layer from portions on both sides of the mesa structure where the support insulating films have not been formed, thereby forming a void between the mesa structure and the semiconductor substrate.

[0010] The semiconductor optical integrated element and the method for manufacturing the semiconductor optical integrated element described herein offer the advantages of obtaining a semiconductor optical integrated element that enables efficient phase adjustment of light and is structurally stable, as well as providing a manufacturing method that allows for easy production of a structurally stable semiconductor optical integrated element.

[0011] This is an overview diagram of a semiconductor optical integrated element according to Embodiment 1. This is a top view of a semiconductor optical integrated element according to Embodiment 1. This is a cross-sectional view of the semiconductor optical integrated element according to Embodiment 1, along the line C-C in Figure 2. This is a cross-sectional view of the semiconductor optical integrated element according to Embodiment 1, along the line A-A in Figure 2. This is a cross-sectional view of the semiconductor optical integrated element according to Embodiment 1, along the line B-B in Figure 2. This is a cross-sectional view showing a method for manufacturing the semiconductor optical integrated element according to Embodiment 1. This is a cross-sectional view showing a method for manufacturing the semiconductor optical integrated element according to Embodiment 1. This is a cross-sectional view showing a method for manufacturing the semiconductor optical integrated element according to Embodiment 1. This is a schematic diagram of a semiconductor optical integrated element in which a semiconductor laser is further integrated into the semiconductor optical integrated element according to Embodiment 1. This is a cross-sectional view showing a method for manufacturing a semiconductor optical integrated element according to a modified example of Embodiment 1. This is a cross-sectional view showing a method for manufacturing a semiconductor optical integrated element according to a modified example of Embodiment 1. This is a cross-sectional view showing a method for manufacturing a semiconductor optical integrated element according to a modified example of Embodiment 1. This is a top view of a semiconductor optical integrated element according to Embodiment 2. This is a cross-sectional view of the semiconductor optical integrated element according to Embodiment 2, along the line A-A in Figure 14. This is a cross-sectional view of the semiconductor optical integrated device according to Embodiment 2, along the line B-B in Figure 14.

[0012] Embodiment 1. Figure 1 is an overview view of the semiconductor optical integrated element 100 according to Embodiment 1. Figure 2 is a top view of the semiconductor optical integrated element 100 according to Embodiment 1. Figure 3 is a cross-sectional view of the semiconductor optical integrated element 100 according to Embodiment 1, along the line C-C in Figure 2. Figure 4 is a cross-sectional view of the semiconductor optical integrated element 100 according to Embodiment 1, along the line A-A in Figure 2. Figure 5 is a cross-sectional view of the semiconductor optical integrated element 100 according to Embodiment 1, along the line B-B in Figure 2.

[0013] <Structure of the semiconductor optical integrated element according to Embodiment 1> As shown in the overview diagram of Figure 1, the semiconductor optical integrated element 100 according to Embodiment 1 comprises an n-type InP substrate 1, a stripe-shaped mesa structure 21 provided on the n-type InP substrate 1 with air gaps 20 between them, a plurality of support insulating films 30 formed on both sides of the mesa structure 21 at predetermined intervals along the stripe direction, with one lower end in contact with the n-type InP substrate 1 to support the mesa structure 21, a surface protection insulating film 31 to protect the surface of the semiconductor layer, a heater electrode 11 provided on the upper surface of the mesa structure 21 along the stripe direction, and a wiring electrode 12 for supplying power to the heater electrode 11.

[0014] Note that the support insulating film 30 is covered by the surface protective insulating film 31 and is therefore not visible in the overview view of Figure 1, but it is shown for the sake of explanation. Also, the direction from the surface of the semiconductor optical integrated element 100 toward the surface of the n-type InP substrate 1 is referred to as the downward direction.

[0015] The mesa structure 21 comprises an InP first cladding layer 2, an optical waveguide layer 3, an InP second cladding layer 4, and a first current blocking layer 5a and a second current blocking layer 5b formed at both ends of the optical waveguide layer 3. A diffraction grating 2a is provided inside the InP first cladding layer 2. The first current blocking layer 5a and the second current blocking layer 5b are collectively referred to as current blocking layers.

[0016] A pair of mesa grooves 22a and 22b are formed on both sides of the mesa structure 21, along the stripe direction. The area other than the mesa structure 21 and the pair of mesa grooves 22a and 22b has a laminated structure consisting of a sacrificial layer 10 formed on the n-type InP substrate 1, an InP first cladding layer 2, a first current blocking layer 5a, a second current blocking layer 5b, and an InP second cladding layer 4. The surface of the area including the mesa structure 21 and the pair of mesa grooves 22a and 22b is covered with a surface protective insulating film 31.

[0017] n-type InP substrate 1 is just one example of a semiconductor substrate; other semiconductor substrates besides n-type InP substrate 1 may also be used. The conductivity type of the InP substrate may be p-type or semi-insulating.

[0018] Specific examples of materials constituting the optical waveguide layer 3 include quaternary semiconductors such as InGaAsP and InGaAlAs. Specific examples of materials constituting the sacrificial layer 10 include, for example, In 1-X-Y Ga X Al Y One example is As (0 ≤ X < 0.75, Y > 0.25).

[0019] Platinum (Pt) is an example of a material that constitutes the heater electrode 11. Gold (Au) is an example of a material that constitutes the wiring electrode 12. Silicon dioxide (SiO2) is an example of a material that constitutes the support insulating film 30 and the surface protective insulating film 31.

[0020] The following are specific examples of the layer thickness of each layer of the semiconductor optical integrated element 100 according to Embodiment 1. The substrate thickness of the n-type InP substrate 1 is 100 μm. The layer thickness of the sacrificial layer 10 is 0.2 μm. The width of the mesa structure 21, i.e., the mesa width, is 6 μm. The width of the optical waveguide layer 3 is 1.5 μm. The opening widths of the pair of mesa grooves 22a and 22b are each 10 μm. The thickness of the void 20 is 0.2 μm, which is equal to the layer thickness of the sacrificial layer 10. The thickness of the void 20, i.e., the layer thickness of the sacrificial layer 10, is preferably in the range of 0.1 μm to 0.5 μm. This is because when the thickness of the void 20 is within this range, the etching solution of the sacrificial layer 10 can penetrate sufficiently, and the insulating film formed on the side surface can be connected without difficulty.

[0021] The thickness of the support insulating film 30 and the surface protective insulating film 31 is 0.5 μm each. The width of the heater electrode 11, i.e., the electrode width, is 4.0 μm, and the thickness of the electrode 11 is 0.2 μm. The width of the wiring electrode 12, i.e., the electrode width, is 10 μm.

[0022] The values ​​listed above are merely examples and can be changed to more suitable values ​​as appropriate.

[0023] Figure 2 is a top view of a semiconductor optical integrated element 100 according to Embodiment 1. Note that the support insulating film 30 is covered by the surface protective insulating film 31 and is not normally visible in the top view, but it is shown for the sake of explanation. Multiple support insulating films 30 are formed periodically at regular intervals along the stripe direction on both sides of the mesa structure 21. A heater electrode 11 is provided on the top surface of the mesa structure 21 along the stripe direction. Wiring electrodes 12 for supplying power to the heater electrode 11 are formed perpendicular to the stripe direction.

[0024] Multiple support insulating films 30 are formed on both sides of the mesa structure 21 to support the mesa structure 21. In an example of the semiconductor optical integrated element 100 according to Embodiment 1 shown in Figure 2, two support insulating films 30 are provided on each side of the mesa structure 21 at predetermined intervals along the stripe direction.

[0025] Two support insulating films 30 are provided on each side of the mesa structure 21, and are positioned opposite each other on both sides of the mesa structure 21. The spacing between adjacent support insulating films 30, i.e., the preset spacing, is 20 μm as an example. The width of the support insulating films 30 in the stripe direction is also 20 μm as an example.

[0026] If three or more support insulating films 30 are provided in the stripe direction, the spacing between adjacent support insulating films 30 may be set to a constant interval. That is, the support insulating films 30 may be provided periodically along the stripe direction.

[0027] Figure 3 is a cross-sectional view of the semiconductor optical integrated element 100 according to Embodiment 1, along the line C-C in Figure 2. The direction along the line C-C is both the stripe direction and the optical guidance direction.

[0028] As shown in Figure 3, the bottom surface of the first InP cladding layer 2 constituting the mesa structure 21 is exposed on the n-type InP substrate 1 via a gap 20. In other words, the bottom surface of the mesa structure 21 is positioned opposite the surface of the n-type InP substrate 1 via the gap 20. As described above, the mesa structure 21 has a laminated structure consisting of the first InP cladding layer 2, the optical waveguide layer 3, and the second InP cladding layer 4.

[0029] A surface protective insulating film 31 is formed on the surface of the InP second cladding layer 4, that is, on the upper surface of the mesa structure 21. Furthermore, a heater electrode 11 is provided on the surface protective insulating film 31, and a wiring electrode 12 is provided so as to be in contact with a part of the heater electrode 11.

[0030] Figure 4 is a cross-sectional view of the semiconductor optical integrated element 100 according to Embodiment 1, along the line A-A in Figure 2. In other words, Figure 4 shows a cross-sectional view of the area where a supporting insulating film 30, provided to support the mesa structure 21, is formed on both sides of the mesa structure 21. As can be seen from Figure 4, the mesa structure 21 is supported by one lower end of the supporting insulating film 30 provided on both sides of the mesa structure 21 contacting the n-type InP substrate 1. The surface of the region including the mesa structure 21 and a pair of mesa grooves 22a and 22b, including the supporting insulating film 30, is covered with a surface protective insulating film 31. The heater electrode 11 is provided on the surface protective insulating film 31 formed on the upper surface of the mesa structure 21, along the stripe direction.

[0031] Figure 5 is a cross-sectional view of the semiconductor optical integrated element 100 according to Embodiment 1, along the line B-B in Figure 2. In other words, Figure 5 shows a cross-sectional view of the area where the supporting insulating film 30 is not formed on both sides of the mesa structure 21. The surface of the region including the mesa structure 21 and a pair of mesa grooves 22a and 22b is covered with the surface protective insulating film 31.

[0032] <Method for manufacturing a semiconductor optical integrated element according to Embodiment 1> The characteristic manufacturing process of the semiconductor optical integrated element according to Embodiment 1 is described below.

[0033] Figures 6 to 9 are cross-sectional views showing a method for manufacturing a semiconductor optical integrated element 100 according to Embodiment 1. Note that all of Figures 6 to 9 are cross-sectional views of the area where the support insulating film 30 is formed.

[0034] A resist 33 is applied to the surface of the wafer after the mesa structure 21 has been formed, and openings are made in the region where a pair of mesa grooves 22a and 22b are to be formed using photolithography and etching techniques. The resist 33 is etched from the openings until the surface of the sacrificial layer 10 is exposed, thereby forming a pair of mesa grooves 22a and 22b.

[0035] When forming a pair of mesa grooves 22a and 22b by wet etching, an etchant is used that etches all layers except the sacrificial layer 10, but not the sacrificial layer 10. An example of an etchant with such properties is a mixture of hydrochloric acid and phosphoric acid. When etching by dry etching, etching is performed using an etching gas with similar properties. Figure 6 is a cross-sectional view after etching.

[0036] Next, a portion of the sacrificial layer 10 is selectively etched. In this case, the other layers are not etched, but an etchant or etching gas is used that selectively etches only the sacrificial layer 10. Figure 7 is a cross-sectional view after a portion of the sacrificial layer 10 has been etched. An example of an etchant for selective etching of the sacrificial layer 10 is a mixture of tartaric acid and hydrogen peroxide.

[0037] An insulating film is formed on both sides of the mesa structure 21. An example of an insulating film is an SiO2 film. After the insulating film is formed, the insulating film formed on both sides of the mesa structure 21, except for the areas where the supporting insulating film 30 is planned, is removed by an etching method such as dry etching. Note that the insulating film 30a formed on areas other than both sides of the mesa structure 21 is not removed and is left as is. Figure 8 is a cross-sectional view of the mesa structure 21 after insulating films have been formed on both sides.

[0038] The sacrificial layer 10 on the underside of the mesa structure 21 is completely removed by selective etching. During selective etching, the etchant enters the underside of the mesa structure 21 from areas on both sides of the mesa structure 21 where the supporting insulating film 30 is not provided. As a result, the mesa structure 21 is supported by the supporting insulating film 30, and the sacrificial layer 10 can be removed over the entire underside of the mesa structure 21. Figure 9 is a cross-sectional view of the mesa structure 21 after the sacrificial layer 10 on the underside has been completely removed.

[0039] By completely removing the sacrificial layer 10 on the lower side of the mesa structure 21, a gap 20 is formed between the lower side of the mesa structure 21 and the surface of the n-type InP substrate 1, and the mesa structure 21 is supported by the supporting insulating film 30, thus completing the characteristic element structure of the semiconductor optical integrated element 100 according to Embodiment 1.

[0040] According to the method for manufacturing a semiconductor optical integrated element according to Embodiment 1, the sacrificial layer 10 is selectively etched from the areas on both sides of the mesa structure 21 where the supporting insulating film 30 is not provided. This makes it easy to completely remove the sacrificial layer 10 on the lower side of the mesa structure 21 while supporting the mesa structure 21 with the supporting insulating film 30, thus providing the advantage of easily manufacturing the semiconductor optical integrated element 100 according to Embodiment 1.

[0041] <Operation of the semiconductor optical integrated element according to Embodiment 1> The operation of the semiconductor optical integrated element 100 according to Embodiment 1 will be described below. When power is supplied from the wiring electrode 12 to the heater electrode 11, the heater electrode 11 generates heat. The generated heat is conducted to the side of the mesa structure 21 and spreads from the InP second cladding layer 4 to the optical waveguide layer 3, the InP second cladding layer 4, and the InP first cladding layer 2.

[0042] When the temperature of the optical waveguide layer 3 rises due to conducted heat, its optical properties, such as the refractive index, change, making it possible to shift the spectrum of light propagating within the optical waveguide layer 3. In other words, it becomes possible to adjust the phase of the propagating light.

[0043] The greater the temperature change of the optical waveguide layer 3, the greater the change in optical properties such as the refractive index. That is, the degree of phase adjustment becomes greater. In the semiconductor optical integrated device 100 according to Embodiment 1, since the gap 20 is provided between the mesa structure 21 and the n-type InP substrate 1, the heat conducted inside the mesa structure 21 is difficult to conduct to the n-type InP substrate 1 side. This is because the thermal conductivity of the air in the gap 20 is much smaller than that of the semiconductor layer. That is, the gap 20 functions as a heat insulation structure.

[0044] Therefore, when the gap 20 is provided on the lower surface side of the mesa structure 21, the degree of temperature rise of the optical waveguide layer 3 due to the heat of the heater electrode 11 becomes significantly larger compared to the case where there is no gap 20. As a result, the change in optical properties such as the refractive index of the optical waveguide layer 3 also becomes larger, and thus it becomes possible to shift the spectrum of the light propagating in the optical waveguide layer 3 more significantly. That is, according to the configuration of the semiconductor optical integrated device 100 according to Embodiment 1, there is an effect that the phase adjustment of the light propagating through the optical waveguide layer 3 can be realized more efficiently.

[0045] The semiconductor optical integrated device 100 according to Embodiment 1 may be configured as a single semiconductor optical integrated device by combining, for example, a modulator, a semiconductor laser, etc. FIG. 10 is a schematic diagram of a semiconductor optical integrated device 200 in which a semiconductor laser 150 is further integrated into the semiconductor optical integrated device 100 according to Embodiment 1.

[0046] <Effect of Embodiment 1> As described above, according to the semiconductor optical integrated device and the method for manufacturing the semiconductor optical integrated device according to Embodiment 1, since a plurality of support insulating films are provided on both side surfaces of the mesa structure at a preset interval along the stripe direction, a gap can be stably formed on the lower surface side of the mesa structure. Therefore, an efficient optical phase adjustment is possible, and there is an effect that a structurally stable semiconductor optical integrated device can be obtained. There is also an effect that such a semiconductor optical integrated device can be easily manufactured.

[0047] Modification example of Embodiment 1. As a modification example of Embodiment 1, the device structure is the same as that of the semiconductor optical integrated device 100 according to Embodiment 1, but a manufacturing method different from the manufacturing method of the semiconductor optical integrated device according to Embodiment 1 will be described below.

[0048] Figures 11 to 13 are cross-sectional views showing a method for manufacturing a semiconductor optical integrated element according to a modified example of Embodiment 1. In Figures 11 to 13, the left-hand view is a cross-sectional view of a portion where the support insulating film 30 is not formed, and the right-hand view is a cross-sectional view of a portion where the support insulating film 30 is formed.

[0049] A resist is applied to the surface of the wafer after the mesa structure 21 has been formed, and an opening is created in the region where a pair of mesa grooves 22a and 22b are to be formed using photolithography and etching techniques. Etching is performed from this opening until the surface of the sacrificial layer 10 is exposed, thereby forming a pair of mesa grooves 22a and 22b. When etching by wet etching, an etchant is used that etches each layer except the sacrificial layer 10, but not the sacrificial layer 10. When etching by dry etching, etching is performed using an etching gas with similar properties.

[0050] After the formation of the pair of mesa grooves 22a and 22b, the areas where the supporting insulating film 30 will not be formed are covered with a resist or the like, and the sacrificial layer 10 is selectively etched in the areas where the supporting insulating film 30 is to be formed. In this case, the other layers are not etched, but an etchant or etching gas is used that selectively etches only the sacrificial layer 10. Figure 11 is a cross-sectional view of each area after the sacrificial layer 10 has been selectively etched in part.

[0051] Next, insulating films are deposited on both sides of the mesa structure 21. An example of an insulating film is an SiO2 film. After the deposition of the insulating film, the insulating film on both sides of the mesa structure 21, except for the areas where the supporting insulating film 30 is planned, is removed by an etching method such as dry etching. Figure 12 is a cross-sectional view of each part of the mesa structure 21 after insulating films have been formed on both sides.

[0052] Selective etching completely removes the sacrificial layer 10 on the underside of the mesa structure 21. During selective etching, the etchant enters the underside of the mesa structure 21 from areas on both sides of the mesa structure 21 where the supporting insulating film 30 is not provided. Therefore, the sacrificial layer 10 can be removed over the entire underside of the mesa structure 21 while the mesa structure 21 is supported by the supporting insulating film 30. Figure 13 is a cross-sectional view of each part after the sacrificial layer 10 on the underside of the mesa structure 21 has been completely removed.

[0053] By completely removing the sacrificial layer 10 on the lower side of the mesa structure 21, a gap 20 is formed between the lower side of the mesa structure 21 and the surface of the n-type InP substrate 1, and the mesa structure 21 is supported by the supporting insulating film 30, thus completing the characteristic device structure of the semiconductor optical integrated device 100.

[0054] According to the method for manufacturing a semiconductor optical integrated element according to a modification of Embodiment 1, the sacrificial layer 10 is selectively etched from the areas on both sides of the mesa structure 21 where the supporting insulating film 30 is not provided. This makes it easy to completely remove the sacrificial layer 10 on the lower side of the mesa structure 21, thus providing the advantage of easily manufacturing the semiconductor optical integrated element according to Embodiment 1.

[0055] Embodiment 2. The semiconductor optical integrated element 110 according to Embodiment 2 is characterized by the shape of the heater electrode 11a. The only difference between the semiconductor optical integrated element 110 according to Embodiment 2 and the semiconductor optical integrated element 100 according to Embodiment 1 is the shape of the heater electrode 11a. Therefore, the following description will focus solely on the heater electrode 11a, and the description of other components will be omitted.

[0056] Figure 14 is a top view of the semiconductor optical integrated element 110 according to Embodiment 2. Figure 15 is a cross-sectional view of the semiconductor optical integrated element 110 according to Embodiment 2, along the line A-A in Figure 14. Figure 16 is a cross-sectional view of the semiconductor optical integrated element 110 according to Embodiment 2, along the line B-B in Figure 14. Note that the support insulating film 30 is covered by the surface protective insulating film 31 and is not normally visible from the top view, but it is shown for the sake of explanation.

[0057] As shown in the top view of Figure 14, the electrode width W1 of the heater electrode 11a in the areas where the supporting insulating film 30 is provided on both sides of the mesa structure 21 is preset to be smaller than the electrode width W2 of the heater electrode 11a in the areas where the supporting insulating film 30 is not provided on both sides of the mesa structure 21.

[0058] The reason for changing the electrode width of the heater electrode 11a depending on the presence or absence of the supporting insulating film 30 on both sides is to adjust the amount of heat generated by the heater electrode 11a according to the difference in heat dissipation due to the presence or absence of the supporting insulating film 30.

[0059] In areas where the support insulating film 30 is provided, heat dissipation becomes more difficult due to the presence of the support insulating film 30, so the electrode width W1 of the heater electrode 11a is relatively reduced to reduce the amount of heat generated. On the other hand, in areas where the support insulating film 30 is not provided, heat dissipation is higher than in areas where the support insulating film 30 is provided, so the electrode width W2 of the heater electrode 11a is relatively increased to increase the amount of heat generated.

[0060] This configuration of the heater electrode 11a ensures that the temperature distribution in the stripe direction of the mesa structure 21 is made uniform, thereby preventing problems such as thermal stress distribution and non-uniform refractive index distribution in the stripe direction.

[0061] <Effects of Embodiment 2> As described above, the semiconductor optical integrated element according to Embodiment 2 has the effect of providing a semiconductor optical integrated element that can achieve more efficient phase adjustment, in addition to the effects of the semiconductor optical integrated element according to Embodiment 1, because the temperature distribution in the stripe direction is made uniform.

[0062] While this disclosure describes various exemplary embodiments, the various features, aspects, and functions described in one or more embodiments are not limited to the application of a particular embodiment, but can be applied individually or in various combinations to the embodiments.

[0063] Accordingly, countless variations not illustrated are conceivable within the scope of the art of this disclosure. These include, for example, modifying, adding or omitting at least one component, or extracting at least one component and combining it with components of other embodiments.

[0064] 1 n-type InP substrate, 2 InP first cladding layer, 2a diffraction grating, 3 optical waveguide layer, 4 InP second cladding layer, 5a first current blocking layer, 5b second current blocking layer, 10 sacrificial layer, 11, 11a heater electrodes, 12 wiring electrodes, 20 void, 21 mesa structure, 22a, 22b mesa grooves, 30 support insulating film, 30a insulating film, 31 surface protection insulating film, 33 resist, 100, 110, 200 semiconductor optical integrated device, 150 semiconductor laser, W1, W2 electrode width

Claims

1. A semiconductor optical integrated element comprising: a semiconductor substrate; a stripe-shaped mesa structure provided on the semiconductor substrate with air gaps between them; a plurality of support insulating films periodically formed on both sides of the mesa structure along the stripe direction, with one lower end in contact with the semiconductor substrate; and a heater electrode provided on the upper surface of the mesa structure along the stripe direction.

2. The semiconductor optical integrated element according to claim 1, characterized in that the plurality of supporting insulating films are provided at regular intervals along the stripe direction.

3. The semiconductor optical integrated element according to claim 1 or 2, characterized in that the plurality of supporting insulating films are provided at opposing positions on both sides of the mesa structure.

4. The semiconductor optical integrated device according to any one of claims 1 to 3, characterized in that the mesa structure includes at least a first cladding layer, an optical waveguide layer, and a second cladding layer.

5. The semiconductor optical integrated element according to claim 4, characterized in that a diffraction grating is provided inside the first cladding layer.

6. The semiconductor optical integrated element according to any one of claims 1 to 5, characterized in that the electrode width of the heater electrode in the portion where the supporting insulating film is provided on both sides of the mesa structure is smaller than the electrode width of the heater electrode in the portion where the supporting insulating film is not provided on both sides of the mesa structure.

7. The semiconductor optical integrated element according to any one of claims 1 to 6, characterized in that both sides of the mesa structure are further covered with a surface protective insulating film.

8. A method for manufacturing a semiconductor optical integrated element, comprising: growing at least a sacrificial layer, a first cladding layer, an optical waveguide layer, and a second cladding layer on a semiconductor substrate; forming a pair of mesa grooves on the sacrificial layer by etching, thereby forming a mesa structure on the sacrificial layer; selectively removing the sacrificial layer exposed on the bottom surface of the pair of mesa grooves by selective etching, and selectively removing a portion of the sacrificial layer on the lower side of the mesa structure from both sides of the mesa structure; forming insulating films on both sides of the mesa structure; periodically removing the insulating films in a stripe direction to form a plurality of support insulating films; and selectively removing the remaining sacrificial layer on the lower side of the mesa structure by selective etching the sacrificial layer from portions on both sides of the mesa structure where the support insulating films have not been formed, thereby forming a void between the mesa structure and the semiconductor substrate.

9. A method for manufacturing a semiconductor optical integrated element, comprising: growing at least a sacrificial layer, a first cladding layer, an optical waveguide layer, and a second cladding layer on a semiconductor substrate; forming a pair of mesa grooves on the bottom surface of the sacrificial layer by etching to form a mesa structure on the sacrificial layer; covering portions on both sides of the mesa structure where a supporting insulating film is not to be formed with a resist, and selectively removing the sacrificial layer exposed on the bottom surface of the mesa grooves and a portion of the sacrificial layer on the lower side of the mesa structure in the portions where the supporting insulating film is to be formed by selective etching; depositing insulating films on both sides of the mesa structure; periodically removing the insulating films in a stripe direction to form a plurality of supporting insulating films; and selectively removing the remaining sacrificial layer on the lower side of the mesa structure by selective etching to form a void between the mesa structure and the semiconductor substrate.

10. The method for manufacturing a semiconductor optical integrated element according to claim 8 or 9, further comprising the step of forming a heater electrode on the upper surface of the mesa structure along the stripe direction.

11. The method for manufacturing a semiconductor optical integrated element according to claim 10, characterized in that the electrode width of the heater electrode in the portion of the mesa structure where the supporting insulating film is provided on both sides of the mesa structure is made smaller than the electrode width of the heater electrode in the portion of the mesa structure where the supporting insulating film is not provided on both sides of the mesa structure.

12. A method for manufacturing a semiconductor optical integrated element according to any one of claims 8 to 11, further comprising the step of forming current blocking layers at both ends of the optical waveguide layer.

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