Semiconductor module

Abstract

In a semiconductor module (1), a first gate pattern (62b-1) of a wiring board (60) is directly connected to a portion of semiconductor elements from among a plurality of semiconductor elements (50) via a gate wiring line (W2), and extends in a first direction (d1) parallel to an arrayed direction of these semiconductor elements (50). The second gate pattern (62b-2) is directly connected to another portion of semiconductor elements from among the plurality of semiconductor elements (50) via the gate wiring line (W2), and extends in the first direction (d1). A first resistance chip (R1) is mounted on the gate pattern in a current path from a gate terminal (41) to the first gate pattern (62b-1). A second resistance chip (R2) is mounted on the gate pattern in a current path from the gate terminal (41) to the second gate pattern (62b-2).

Description

Semiconductor module

[0001] The present invention relates to a semiconductor module including a plurality of semiconductor elements and a wiring board.

[0002] Conventionally, in a semiconductor module used in a power conversion device or the like, a semiconductor element such as a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is mounted on a wiring board. This wiring board has a gate pattern connected to the gate electrode of the semiconductor element by a gate wiring (see, for example, Patent Documents 1 and 2).

[0003] Japanese Patent Application Laid-Open No. 2024-019841 International Publication No. 2019 / 044748

[0004] By mounting a resistance chip on the gate pattern, oscillation of the gate voltage can be suppressed. Therefore, from the viewpoint of suppressing oscillation of the gate voltage, it is desirable to increase the number of resistance chips. However, when the number of resistance chips is increased, the wiring space on the wiring board is limited.

[0005] In one aspect, an object of the present invention is to provide a semiconductor module capable of suppressing oscillation of a gate voltage while securing a wiring space.

[0006] In one embodiment, the semiconductor module comprises a plurality of semiconductor elements, a wiring board having a wiring pattern layer on which the plurality of semiconductor elements are mounted, a main current terminal, and a gate terminal, wherein the wiring pattern layer has a main current pattern on which the plurality of semiconductor elements are mounted and connected to the main current terminal, and a gate pattern connected to the gate terminal, and the gate pattern includes a first gate pattern directly connected to some of the plurality of semiconductor elements via gate wiring and extending in a first direction parallel to the arrangement direction of the some of the semiconductor elements, and a second gate pattern directly connected to some of the other semiconductor elements of the plurality of semiconductor elements via gate wiring and extending in the first direction, and further comprises a first resistor chip mounted on the gate pattern in the current path from the gate terminal to the first gate pattern, and a second resistor chip mounted on the gate pattern in the current path from the gate terminal to the second gate pattern.

[0007] According to the above embodiment, it is possible to suppress gate voltage oscillation while securing wiring space.

[0008] This is a plan view showing a semiconductor module according to the first embodiment. This is a plan view showing the internal structure of the semiconductor module according to the first embodiment. This is a plan view showing the wiring board of the upper arm in the first embodiment. This is a plan view showing the wiring board of the lower arm in the first embodiment. This is a circuit diagram showing an example of the circuit configuration of the semiconductor module according to the first embodiment. This is a plan view for explaining the oscillation loop in the wiring board of the upper arm in the first embodiment. This is a table showing the presence or absence of oscillation of the gate voltage during a short circuit in the first embodiment and comparative examples. This is a plan view showing the internal structure of a semiconductor module according to the second embodiment. This is a plan view showing the wiring board of the upper arm in the second embodiment. This is a plan view showing the wiring board of the lower arm in the second embodiment. This is a plan view showing the internal structure of a semiconductor module according to the third embodiment. This is a plan view showing the wiring board of the upper arm in the third embodiment. This is a plan view for explaining the oscillation loop in the wiring board of the upper arm in the third embodiment.

[0009] Hereinafter, with reference to the drawings, the semiconductor module 1 according to the first embodiment of the present invention, the semiconductor module 2 according to the second embodiment, and the semiconductor module 3 according to the third embodiment will be described in detail. The X, Y, and Z axes in the referenced figures are shown for the purpose of defining the directions and surfaces of the example semiconductor module 1, etc. The X, Y, and Z axes are orthogonal to each other and form a right-handed system. In the following description, the Z direction may be referred to as the up and down direction. Also, the surface including the X and Y axes may be referred to as the top surface or bottom surface. These directions and surfaces are terms used for convenience of explanation, and the correspondence with the X, Y, and Z directions may change depending on the mounting orientation of the semiconductor modules 1, 2, etc. For example, in this specification, the surface facing the positive Z direction (+Z direction) of the components constituting the semiconductor modules 1, 2 is referred to as the top surface, and the surface facing the negative Z direction (-Z direction) is referred to as the bottom surface. However, the surface facing the negative Z direction may be referred to as the top surface, and the surface facing the positive Z direction may be referred to as the bottom surface. Furthermore, in this specification, a plan view refers to the view of the upper surface (XY plane) of semiconductor modules 1, 2, etc., from the positive Z-direction to the negative Z-direction.

[0010] The aspect ratios and relative sizes of components in each diagram are purely illustrative and do not necessarily correspond to the actual relationships in the manufactured semiconductor modules 1 and 2. For explanatory purposes, the relative sizes of components may be exaggerated in some cases. Furthermore, the shape of the same component may differ between different diagrams.

[0011] In the following description, semiconductor modules 1 and 2 are described as devices applied to power conversion equipment such as inverter devices for industrial or automotive motors. For this reason, detailed descriptions of configurations, functions, operations, assembly methods, etc., that are the same as or similar to known semiconductor modules are omitted in the following description.

[0012] <First Embodiment> Figure 1 is a plan view showing a semiconductor module 1 according to the first embodiment.

[0013] Figure 2 is a plan view showing the internal structure of semiconductor module 1.

[0014] As shown in Figure 1, the semiconductor module 1 comprises a case 10, a base plate 20, main current terminals 31-33, gate terminals 41-42, and auxiliary terminals 43-48. Also, as shown in Figure 2, the semiconductor module 1 comprises a plurality of semiconductor elements 50, four wiring boards 60, and two auxiliary wiring boards 70.

[0015] The case 10 shown in Figure 1 is formed using a thermoplastic resin material such as PPS (Polyphenylene Sulfide) or PA (Polyamide), and is insulating. The case 10 is fixed to the periphery of the upper surface of the base plate 20 by adhesive, and the internal space is sealed with an insulating material such as epoxy resin or silicone gel while housing the four wiring boards 60, which will be described later.

[0016] The base plate 20 has a rectangular shape in plan view, and as shown in Figure 2, four wiring boards 60 and two auxiliary wiring boards 70 are joined to it. Through holes 21 are provided at the four corners of the base plate 20. The base plate 20 is fastened to a cooler (not shown) at the through holes 21 at the four corners. The base plate 20 functions as a heat conductive plate that conducts the heat generated by the semiconductor elements 50 mounted on the wiring boards 60 to the cooler. The base plate 20 is formed from a metal plate such as a copper plate or an aluminum plate.

[0017] As shown in Figure 1, the main current terminals 31-33 are exposed to the outside at the top of the case 10. The gate terminals 41, 42 and auxiliary terminals 43-48 are, for example, insert-molded into the case 10 and exposed to the outside at the top surface of the case 10.

[0018] The two main current terminals 31 (D1 terminal: power supply (+) terminal) shown in Figure 1 are joined to the main current pattern 62a of the two wiring boards 60 on the positive side in the Y direction shown in Figure 2 at terminal joints j1. The main current terminal 32 (S2 terminal: power supply (-) terminal) is joined to the main current pattern 62a of the two wiring boards 60 on the negative side in the Y direction at terminal joints j2. The three main current terminals 33 (D2S1 terminals: intermediate terminals (output terminals)) are joined to the main current pattern 62a of the two wiring boards 60 on the positive side in the Y direction at two terminal joints j3 each. Each of the main current terminals 31 to 33 is joined to the main current pattern 62a by a joining part such as ultrasonic bonding or solder bonding.

[0019] The gate terminal 41 (G1 terminal) shown in Figure 1 is joined to the gate pattern 72a of the auxiliary wiring board 70 on the positive Y-direction side shown in Figure 2 at terminal joint j4. The gate terminal 42 (G2 terminal) is joined to the gate pattern 72a of the auxiliary wiring board 70 on the negative Y-direction side at terminal joint j5. The auxiliary terminals 43 to 48 are joined to the main current pattern 62a of the wiring board 60 or the auxiliary pattern 72b of the auxiliary wiring board 70 at terminal joints j6 to j11. For example, auxiliary terminal 43 (S1 terminal) is joined to the auxiliary pattern 72b of the auxiliary wiring board 70 on the positive side in the Y direction at terminal joint j6, auxiliary terminal 44 (D1-1 terminal) is joined to the main current pattern 62a of the wiring board 60 on the negative side in the X direction and on the positive side in the Y direction at terminal joint j8, auxiliary terminal 45 (S2-1 terminal) is joined to the main current pattern 62a of the wiring board 60 on the negative side in the X direction and on the negative side in the Y direction at terminal joint j9, auxiliary terminal 46 (D2-1 terminal) is joined to the main current pattern 62a of the wiring board 60 on the positive side in the X direction and on the positive side in the Y direction at terminal joint j11, auxiliary terminal 47 (T1 terminal) is joined to the auxiliary pattern 72b of the auxiliary wiring board 70 on the negative side in the Y direction at terminal joint j10, and auxiliary terminal 48 (S2 terminal) is joined to the auxiliary pattern 72b of the auxiliary wiring board 70 on the negative side in the Y direction at terminal joint j7. The gate terminals 41, 42 and auxiliary terminals 43-48 are joined to the main current pattern 62a, etc., by a joining portion such as ultrasonic bonding or solder bonding.

[0020] As shown in Figure 2, eight semiconductor elements 50 are mounted on each of the four wiring boards 60. The semiconductor elements 50 include, for example, MOSFETs, IGBT (Insulated Gate Bipolar Transistor) elements, RC (Reverse Conducting)-IGBT elements that integrate the functions of IGBT and FWD (Free Wheeling Diode) elements, and diodes. The semiconductor elements 50 are formed in a planar rectangular shape on a semiconductor substrate using a wide bandgap (WBG) semiconductor such as SiC (silicon carbide) or gallium nitride (GaN), or on a Si (silicon) substrate.

[0021] As shown in Figure 3, the semiconductor element 50 has a surface electrode (main electrode) 51 provided on most of the upper surface of the semiconductor element 50 and a gate electrode 52 provided on a part of the upper surface of the semiconductor element 50.

[0022] The surface electrode 51 and the gate electrode 52 are thin films made of aluminum, an aluminum alloy, or the like. For example, if the semiconductor element 50 is a MOSFET, the surface electrode 51 is the source electrode; if the semiconductor element 50 is an IGBT, the surface electrode 51 is the emitter electrode. A back electrode (not shown) is provided on the lower surface of the semiconductor element 50 and is joined to the upper surface of the circuit layer 23, for example, via solder. The back electrode is the drain electrode if the semiconductor element 50 is a MOSFET; if the semiconductor element 50 is an IGBT, it is the collector electrode.

[0023] As shown in Figure 2, the four wiring boards 60 and the two auxiliary wiring boards 70 are joined to a common single base plate 20 on their lower surfaces by a bonding material such as solder. Of the four wiring boards 60, two adjacent wiring boards 60 in the X direction on the positive Y direction side have substantially identical configurations, and two adjacent wiring boards 60 in the X direction on the negative Y direction side also have substantially identical configurations. Furthermore, the two wiring boards 60 on the positive Y direction side (see Figure 3) constitute the upper arm, and the two wiring boards 60 on the negative Y direction side (see Figure 4) constitute the lower arm. The wiring boards 60 may be, for example, DCB (Direct Copper Bonding) boards or AMB (Active Metal Brazing) boards. The wiring boards 60 may also be called laminated boards, insulating circuit boards, insulating heat dissipation circuit boards, etc.

[0024] As shown in Figure 5, the semiconductor element 50 (shown on the upper side of Figure 5) mounted on the wiring board 60 constituting the upper arm has its drain connected to the main current terminal 31 (two D1 terminals) and auxiliary terminal 44 (D1-1 terminal), and its source connected to the main current terminal 32 (three D2S1 terminals) and auxiliary terminal 43 (S1 terminal). The semiconductor element 50 (shown on the lower side of Figure 5) mounted on the wiring board 60 constituting the lower arm has its drain connected to the main current terminal 33 (three D2S1 terminals) and auxiliary terminal 46 (D2-1 terminal), and its source connected to the main current terminal 32 (two S2 terminals), auxiliary terminal 48 (S2 terminal), auxiliary terminal 47 (T1 terminal), and auxiliary terminal 45 (S2-1 terminal). Therefore, in the upper arm, the main current flows from the main current terminal 31 (D1 terminal) through the semiconductor element 50 to the main current terminal 33 (D2S1 terminal), as shown by the dotted arrow in Figure 5, in the first current path C1. Furthermore, in the lower arm, the main current flows from the main current terminal 33 (D2S1 terminal) through the semiconductor element 50 to the main current terminal 32 (S2 terminal), as shown by the dotted arrow in Figure 5, in the second current path C2. For example, the auxiliary terminal 47 (T1 terminal) of the thermistor is joined at the terminal joint j10 to one of the two auxiliary patterns 72b connected by the auxiliary resistor chip R5 of the auxiliary wiring board 70 on the negative side in the Y direction, as shown in Figure 2.

[0025] Incidentally, the state in which both the semiconductor element 50 on the upper arm and the semiconductor element 50 on the lower arm, as shown in Figure 5, go from being off to being on can be called turn-on. During this turn-on, current flows through the first current path C1 or the second current path C2. Also, the state in which both the semiconductor element 50 on the upper arm and the semiconductor element 50 go from being on to being off can be called turn-off. During this turn-off, no current flows. Furthermore, the state in which both the semiconductor element 50 on the upper arm and the semiconductor element 50 go from being on to being on, and current flows through both the semiconductor element 50 on the upper arm and the semiconductor element 50 on the lower arm, as shown by the dashed arrow in Figure 5 (third current path C3), can be called a short circuit. During this short circuit, a large current and high voltage are applied, causing the semiconductor element 50 to be destroyed by energy. However, if oscillation is observed, the destruction will occur in a shorter time, so it is desirable to suppress oscillation.

[0026] As shown in Figure 2, the wiring board 60 has an insulating layer 61, a wiring pattern layer 62 formed on the upper surface of the insulating layer 61, and a heat dissipation layer 63 formed on the lower surface of the insulating layer 61.

[0027] The insulating layer 61 is formed in a rectangular shape in plan view using an insulating material such as ceramic or resin. The insulating layer 61 may also be called an insulating plate or insulating film. The insulating material of the insulating layer 61 may be, for example, alumina (Al ２ O ３ ), aluminum nitride (AlN), silicon nitride (Si ３ N ４ Ceramic materials such as ), resin materials such as epoxy, or resin materials using ceramic materials as fillers are used.

[0028] The heat dissipation layer 63 functions as a heat conductive member that conducts heat generated in the inverter circuit to the base plate 20, and is composed of a metal layer of a predetermined thickness formed from copper foil or the like on the lower surface of the insulating layer 61. The heat dissipation layer 63 may also be called a heat sink, metal plate, or metal layer. Since the heat dissipation layer 63 has a rectangular shape in plan view that covers most of the lower surface of the insulating layer 61, its reference numeral is shown in parentheses along with the reference numeral of the insulating layer 61 in Figures 2 to 4.

[0029] The wiring pattern layer 62 is composed of a metal layer of a predetermined thickness formed from copper foil or the like, and functions, for example, as a wiring member in an inverter circuit. The wiring pattern layer 62 may also be called a conductive layer, circuit board, circuit pattern, etc. The wiring pattern layer 62 has a main current pattern 62a, a gate pattern 62b, and an auxiliary pattern 62c. These main current pattern 62a, gate pattern 62b, and auxiliary pattern 62c are arranged separately from each other.

[0030] As shown in Figure 2, auxiliary wiring boards 70 are provided at the positive and negative ends in the Y direction of the base plate 20. The auxiliary wiring board 70 has an insulating layer 71, one gate pattern 72a and three auxiliary patterns 72b formed on the upper surface of the insulating layer 71, and a heat dissipation layer 73 formed on the lower surface of the insulating layer 71.

[0031] The insulating layer 71 can be the same as the insulating layer 61 of the wiring board 60. Similarly, the heat dissipation layer 73 can be the same as the heat dissipation layer 63 of the wiring board 60. Therefore, since the heat dissipation layer 73 has a rectangular shape in plan view that covers most of the lower surface of the insulating layer 71, its reference numeral is shown in parentheses along with the reference numeral of the insulating layer 71 in Figure 2.

[0032] On the auxiliary wiring board 70 on the positive side in the Y direction of the base plate 20, a gate terminal 41 (G1 terminal) is joined at the terminal joint j4 of the gate pattern 72a, and an auxiliary terminal 43 (S1 terminal) is joined at the terminal joint j6 of one auxiliary pattern 72b.

[0033] Furthermore, on the auxiliary wiring board 70 on the negative side in the Y direction of the base plate 20, a gate terminal 42 (G2 terminal) is joined at the terminal joint j5 of the gate pattern 72a, and an auxiliary terminal 48 (S2 terminal) is joined at the terminal joint j7 of one auxiliary pattern 72b.

[0034] In the upper arm wiring board 60 shown in Figure 3, three main current patterns 62a are arranged. One of these, the main current pattern 62a in the center in the X direction, has eight semiconductor elements 50 mounted on it, and is connected by a main current terminal 31 (D1 terminal) joined at a terminal junction j1. Each of the remaining two main current patterns 62a is connected to four semiconductor elements 50 (surface electrodes 51) by main current wiring W1. These two main current patterns 62a are also connected by a main current terminal 33 (D2S1 terminal) joined at a terminal junction j3. Furthermore, as shown in Figure 2, each of the two main current patterns 62a is connected to the main current pattern 62a of the wiring board 60 constituting the lower arm by main current wiring W1. The main current wiring W1, gate wiring W2, and auxiliary wiring W3 are wires made of, for example, aluminum, aluminum alloy, copper, copper alloy, etc.

[0035] As shown in Figure 3, the eight semiconductor elements 50 mounted on the main current pattern 62a are arranged such that three semiconductor elements 50 are arranged in the first direction d1 (Y direction) on the positive X-direction side of the wiring board 60, and three semiconductor elements 50 are arranged in the first direction d1 (Y direction) on the negative X-direction side of the wiring board 60. The remaining two semiconductor elements 50 are located further to the positive Y-direction and positive X-direction than the three semiconductor elements 50, and further to the positive Y-direction and negative X-direction than the three semiconductor elements 50. These eight semiconductor elements 50 as a whole can be considered to be arranged to form a T-shape in a plan view.

[0036] In the upper arm wiring board 60 shown in Figure 3, the gate patterns 62b (first gate pattern 62b-1, second gate pattern 62b-2, and third gate pattern 62b-3) are connected to the gate pattern 72a of the auxiliary wiring board 70 shown in Figure 2 via gate wiring W2, thereby connecting to the gate terminal 41 (G1 terminal) joined to the gate pattern 72a at the terminal joint j4. Specifically, the third gate pattern 62b-3 is connected to the gate pattern 72a of the auxiliary wiring board 70 by gate wiring W2, to the first resistor chip R1 mounted on the first gate pattern 62b-1 by gate wiring W2, and to the second resistor chip R2 mounted on the second gate pattern 62b-2 by gate wiring W2. Thus, the third gate pattern 62b-3 can be said to be provided in the current path from the gate terminal 41 (G1 terminal) to the first gate pattern 62b-1 and the second gate pattern 62b-2.

[0037] As shown in Figure 3, the first gate pattern 62b-1 is directly connected via gate wiring W2 to three semiconductor elements 50 (gate electrodes 52) arranged in the first direction d1 (Y direction) on the positive X-direction side of the wiring board 60, and to a semiconductor element 50 (gate electrode 52) located at both the positive Y-direction end and the positive X-direction end of the wiring board 60.

[0038] The second gate pattern 62b-2 is directly connected via gate wiring W2 to three semiconductor elements 50 (gate electrodes 52) arranged in the first direction d1 (Y direction) on the negative X-side of the wiring board 60, and to a semiconductor element 50 (gate electrode 52) located at both the positive Y-side end and the negative X-side end of the wiring board 60.

[0039] The first gate pattern 62b-1 and the second gate pattern 62b-2 extend in the first direction d1. Furthermore, the first gate pattern 62b-1 and the second gate pattern 62b-2 are provided in the second direction d2 (X direction), which is perpendicular to the first direction d1, between three semiconductor elements 50 arranged in the first direction d1 on the positive X side of the wiring board 60 and three semiconductor elements 50 arranged in the first direction d1 on the negative X side of the wiring board 60.

[0040] On the first gate pattern 62b-1, the first resistance chip R1 is mounted at a bulging portion that bulges in the positive X direction at the positive Y-direction end. Also, on the second gate pattern 62b-2, the second resistance chip R2 is mounted at a bulging portion that bulges in the negative X direction at the positive Y-direction end.

[0041] As described above, the third gate pattern 62b-3 is connected by the gate wiring W2 to the first resistance chip R1, the second resistance chip R2, and the gate pattern 72a of the auxiliary wiring board 70 shown in FIG. 2. Also, the third gate pattern 62b-3 is located more on the positive Y side than the first gate pattern 62b-1 and the second gate pattern 62b-2, and extends in the second direction d2 (X direction) orthogonal to the first direction d1 (Y direction). Thereby, the gate pattern 62b (the first gate pattern 62b-1, the second gate pattern 62b-2, and the third gate pattern 62b-3) can be regarded as presenting a T shape that is the same orientation as the T shape of the semiconductor element 50 in a plan view as a whole.

[0042] In the wiring board 60 of the upper arm shown in FIG. 3, the auxiliary pattern 62c (composed of two, the first auxiliary pattern 62c-1 and the third auxiliary pattern 62c-3) is connected to the auxiliary pattern 72b of the auxiliary wiring board 70 shown in FIG. 2 via the auxiliary wiring W3, and thus is connected to the auxiliary terminal 43 (S1 terminal) joined to the auxiliary pattern 72b at the terminal joint j6. Specifically, the third auxiliary pattern 62c-3 is connected by the auxiliary pattern 72b of the auxiliary wiring board 70 and the auxiliary wiring W3, and is connected by the first auxiliary pattern 62c-1 and the auxiliary wiring W3. Thereby, it can be said that the third auxiliary pattern 62c-3 is provided in the current path from the auxiliary terminal 43 (S1 terminal) to the first auxiliary pattern 62c-1.

[0043] As shown in Figure 3, the first auxiliary pattern 62c-1 is directly connected via auxiliary wiring W3 to three semiconductor elements 50 (surface electrodes 51) arranged in a first direction d1 (Y direction) on the positive X side of the wiring board 60, and to three semiconductor elements 50 (surface electrodes 51) arranged in a first direction d1 (Y direction) on the negative X side of the wiring board 60. Furthermore, the third auxiliary pattern 62c-3 is directly connected via auxiliary wiring W3 to semiconductor elements 50 (surface electrodes 51) located at both the positive Y end and the positive X end of the wiring board 60, and to semiconductor elements 50 (surface electrodes 51) located at both the positive Y end and the negative X end of the wiring board 60.

[0044] The first auxiliary pattern 62c-1 extends in the first direction d1. The first auxiliary pattern 62c-1 is also provided in the second direction d2 (X direction), which is perpendicular to the first direction d1, between three semiconductor elements 50 arranged in the first direction d1 on the positive X side of the wiring board 60 and three semiconductor elements 50 arranged in the first direction d1 on the negative X side of the wiring board 60. Furthermore, the first auxiliary pattern 62c-1 is adjacent to the first gate pattern 62b-1 and the second gate pattern 62b-2 in the second direction d2 (X direction), and is provided between these first gate pattern 62b-1 and second gate pattern 62b-2.

[0045] As described above, the third auxiliary pattern 62c-3 is connected to the auxiliary pattern 72b of the auxiliary wiring board 70 shown in Figure 2 by auxiliary wiring W3. Furthermore, the third auxiliary pattern 62c-3 is located on the positive side in the Y direction compared to the first auxiliary pattern 62c-1, and extends in the second direction d2 (X direction) which is perpendicular to the first direction d1 (Y direction). As a result, the auxiliary patterns 62c (the first auxiliary pattern 62c-1 and the third auxiliary pattern 62c-3) as a whole can be considered to exhibit a T-shape in the same orientation as the T-shape of the semiconductor element 50 and the gate pattern 62b in a plan view.

[0046] In the wiring board 60 of the lower arm shown in FIG. 4, two main current patterns 62a are arranged. Among them, eight semiconductor elements 50 are mounted on the main current pattern 62a that呈a U shape in a plan view. The remaining one main current pattern 62a is connected by joining the main current terminal 32 (S2 terminal) at the terminal joint j2, and is connected by eight semiconductor elements 50 (surface electrodes 51) and the main current wiring W1.

[0047] As shown in FIG. 4, among the eight semiconductor elements 50 mounted on the main current pattern 62a, three semiconductor elements 50 are arranged in the first direction d1 (Y direction) on the positive side in the X direction of the wiring board 60, and three semiconductor elements 50 are arranged in the first direction d1 (Y direction) on the negative side in the X direction of the wiring board 60. Also, the remaining two semiconductor elements 50 are semiconductor elements 50 that are arranged side by side in the X direction on the negative side in the Y direction and on the central side in the X direction compared to the three semiconductor elements 50 each. These eight semiconductor elements 50 can be regarded as being arranged so as to呈a U shape in a plan view as a whole.

[0048] In the lower arm wiring board 60 shown in Figure 4, the gate patterns 62b (first gate pattern 62b-1, second gate pattern 62b-2, third gate pattern 62b-3, fourth gate pattern 62b-4, and fifth gate pattern 62b-5) are connected to the gate pattern 72a of the auxiliary wiring board 70 shown in Figure 2 via gate wiring W2, thereby connecting to the gate terminal 42 (G2 terminal) joined to the gate pattern 72a at the terminal joint j5. Specifically, the third gate pattern 62b-3 is connected to the gate pattern 72a by gate wiring W2, the first resistor chip R1 mounted on the fourth gate pattern 62b-4 is connected by gate wiring W2, and the second resistor chip R2 mounted on the fifth gate pattern 62b-5 is connected by gate wiring W2. Furthermore, the fourth gate pattern 62b-4 is connected to the first gate pattern 62b-1 by gate wiring W2, and the fifth gate pattern 62b-5 is connected to the second gate pattern 62b-2 by gate wiring W2. Thus, the third gate pattern 62b-3 can be said to be provided in the current path from the gate terminal 41 (G1 terminal) to the first gate pattern 62b-1 and the second gate pattern 62b-2. Furthermore, the fourth gate pattern 62b-4 can be said to be provided in the current path from the third gate pattern 62b-3 to the first gate pattern 62b-1. Furthermore, the fifth gate pattern 62b-5 can be said to be provided in the current path from the third gate pattern 62b-3 to the second gate pattern 62b-2.

[0049] As shown in Figure 4, the first gate pattern 62b-1 is directly connected via gate wiring W2 to three semiconductor elements 50 (gate gates 52) arranged in the first direction d1 (Y direction) on the positive X side of the wiring board 60. The fourth gate pattern 62b-4 is directly connected via gate wiring W2 to a semiconductor element 50 (gate gate 52) located at the negative Y end of the wiring board 60 and near the positive center in the X direction.

[0050] The second gate pattern 62b-2 is directly connected via gate wiring W2 to three semiconductor elements 50 (gate electrodes 52) arranged in the first direction d1 (Y direction) on the negative X side of the wiring board 60. The fifth gate pattern 62b-5 is also directly connected via gate wiring W2 to a semiconductor element 50 (gate electrode 52) located at the negative Y end of the wiring board 60 and near the negative center in the X direction.

[0051] The first gate pattern 62b-1 and the second gate pattern 62b-2 extend in the first direction d1. The first gate pattern 62b-1 is provided on one side (positive side in the X direction) of the eight semiconductor elements 50 in the second direction d2 (X direction), and the second gate pattern 62b-2 is provided on the other side (negative side in the X direction) of the eight semiconductor elements 50 in the second direction d2 (X direction).

[0052] The third gate pattern 62b-3 is located on the negative side in the Y direction compared to the first gate pattern 62b-1 and the second gate pattern 62b-2, and extends in the second direction d2 (X direction) which is perpendicular to the first direction d1 (Y direction). As a result, the gate patterns 62b (first gate pattern 62b-1, second gate pattern 62b-2, and third gate pattern 62b-3) as a whole can be considered to exhibit a U-shape in the same orientation as the U-shape of the semiconductor element 50 in a plan view. The fourth gate pattern 62b-4 and the fifth gate pattern 62b-5 exhibit a plan view rectangle shape small enough to accommodate the mounting of the first resistor chip R1 or the second resistor chip R2.

[0053] In the lower arm wiring board 60 shown in Figure 4, the auxiliary patterns 62c (consisting of three auxiliary patterns: a first auxiliary pattern 62c-1, a second auxiliary pattern 62c-2, and a third auxiliary pattern 62c-3) are connected to the auxiliary pattern 72b of the auxiliary wiring board 70 shown in Figure 2 via auxiliary wiring W3, thereby connecting to the auxiliary terminal 48 (S2 terminal) joined to the auxiliary pattern 72b at the terminal joint j7. Specifically, the third auxiliary pattern 62c-3 is connected to the auxiliary pattern 72b of the auxiliary wiring board 70 by auxiliary wiring W3, and to the first auxiliary pattern 62c-1 by auxiliary wiring W3. Thus, the third auxiliary pattern 62c-3 can be said to be provided in the current path from the auxiliary terminal 48 (S2 terminal) to the first auxiliary pattern 62c-1.

[0054] As shown in Figure 4, the first auxiliary pattern 62c-1 is directly connected via auxiliary wiring W3 to three semiconductor elements 50 (surface electrodes 51) arranged in the first direction d1 (Y direction) on the positive X-side of the wiring board 60. The second auxiliary pattern 62c-2 is directly connected via auxiliary wiring W3 to three semiconductor elements 50 (surface electrodes 51) arranged in the first direction d1 (Y direction) on the negative X-side of the wiring board 60. The third auxiliary pattern 62c-3 is directly connected via auxiliary wiring W3 to two semiconductor elements 50 (surface electrodes 51) located at the negative Y-side end of the wiring board 60.

[0055] The first auxiliary pattern 62c-1 and the second auxiliary pattern 62c-2 extend in the first direction d1. The first auxiliary pattern 62c-1 is provided on one side (positive X-direction side) of the eight semiconductor elements 50 in the second direction d2 (X-direction), and the second auxiliary pattern 62c-2 is provided on the other side (negative X-direction side) of the eight semiconductor elements 50 in the second direction d2 (X-direction). The first auxiliary pattern 62c-1 is adjacent to the first gate pattern 62b-1 in the second direction d2 (X-direction) and is located on the negative X-direction side of the first gate pattern 62b-1. The second auxiliary pattern 62c-2 is adjacent to the second gate pattern 62b-2 in the second direction d2 (X-direction) and is located on the positive X-direction side of the second gate pattern 62b-2. In other words, the first auxiliary pattern 62c-1 and the second auxiliary pattern 62c-2 are adjacent to the first gate pattern 62b-1 and the second gate pattern 62b-2, and are provided between these first gate pattern 62b-1 and the second gate pattern 62b-2.

[0056] As described above, the third auxiliary pattern 62c-3 is connected to the auxiliary pattern 72b of the auxiliary wiring board 70 shown in Figure 2 by auxiliary wiring W3. Furthermore, the third auxiliary pattern 62c-3 is located on the negative side in the Y direction compared to the first auxiliary pattern 62c-1 and extends in the second direction d2 (X direction), which is perpendicular to the first direction d1 (Y direction). As a result, the auxiliary patterns 62c (first auxiliary pattern 62c-1, second auxiliary pattern 62c-2, and third auxiliary pattern 62c-3) as a whole can be considered to exhibit a U-shape in the same orientation as the U-shape of the semiconductor element 50 and the gate pattern 62b in a plan view.

[0057] In the first embodiment described above, the semiconductor module 1 comprises a plurality of semiconductor elements 50, a wiring board 60 having a wiring pattern layer 62 on which these plurality of semiconductor elements 50 are mounted, main current terminals 31, 32, 33, and gate terminals 41, 42. The wiring pattern layer 62 has a main current pattern 62a on which the plurality of semiconductor elements 50 are mounted and connected to the main current terminals 31 to 33, and a gate pattern 62b connected to the gate terminals 41, 42. This gate pattern 62b includes a first gate pattern 62b-1 that is directly connected to some of the plurality of semiconductor elements 50 via gate wiring W2 and extends in a first direction d1 parallel to the arrangement direction of the plurality of semiconductor elements 50, and a second gate pattern 62b-2 that is directly connected to other of the plurality of semiconductor elements 50 via gate wiring W2 and extends in the first direction d1. The semiconductor module 1 further includes a first resistor chip R1 mounted on the gate pattern 62b in the current path from gate terminals 41 and 42 to the first gate pattern 62b-1, and a second resistor chip R2 mounted on the gate pattern 62b in the current path from gate terminals 41 and 42 to the second gate pattern 62b-2.

[0058] Incidentally, for example, during a short circuit, as shown in Figure 6, a short-circuit oscillation occurs in a loop passing through semiconductor elements 50 that are far apart from each other, such as the first loop L1 (shown by a dashed line) which includes a semiconductor element 50 located at both the positive Y-direction end and the positive X-direction end, and a semiconductor element 50 located at both the positive Y-direction end and the negative X-direction end (a loop passing through the first gate pattern 62b-1, the second gate pattern 62b-2, the third gate pattern 62b-3, and the third auxiliary pattern 62c-3). In this respect, in this embodiment, since two resistor chips, the first resistor chip R1 and the second resistor chip R2, are mounted on the gate pattern 62b in the first loop L1, the short-circuit oscillation can be suppressed in the oscillation path of the short-circuit oscillation. For example, as shown in Figure 7, in the comparative example where there was only one resistor chip, when the junction temperature Tvj of the semiconductor element 50 was 25 [°C], a short-circuit oscillation occurred at a power supply voltage Vcc of 1400 [V], and the experiment at a power supply voltage Vcc of 1500 [V] was interrupted. Also, in the comparative example where there was only one resistor chip, when the junction temperature Tvj of the semiconductor element 50 was 150 [°C], a short-circuit oscillation occurred at a power supply voltage Vcc of 1100 [V], and the experiment at a power supply voltage Vcc of 1200 [V] or higher was interrupted. On the other hand, in this embodiment, since the first resistor chip R1 and the second resistor chip R2 are provided, no short-circuit oscillation occurred under any of the conditions.

[0059] Furthermore, for example, during turn-on, as shown in Figure 6, oscillation occurs in loops passing through semiconductor elements 50 that are close to each other, such as the second loop L2 (shown as a dashed line) that passes only through two adjacent semiconductor elements 50 arranged in the first direction d1 (a loop passing through the first gate pattern 62b-1 or the second gate pattern 62b-2 and the first auxiliary pattern 62c-1). In this respect, in this embodiment, the first gate pattern 62b-1 and the second gate pattern 62b-2 are directly connected to the semiconductor elements 50 via gate wiring W2. Therefore, compared to an embodiment in which the gate pattern 62b (or auxiliary pattern 62c) is connected in series to multiple semiconductor elements 50 by a single gate wiring W2 (or auxiliary wiring W3), the oscillation path loop during turn-on can be enlarged, the resonant frequency can be lowered, and oscillation can be suppressed.

[0060] Furthermore, in this embodiment, the first gate pattern 62b-1 and the second gate pattern 62b-2 extend in a first direction d1 parallel to the arrangement direction of the semiconductor element 50. Therefore, in a narrow space, the first gate pattern 62b-1 and the second gate pattern 62b-2 can be directly connected to the semiconductor element 50 by gate wiring W2.

[0061] Based on the above, this embodiment makes it possible to suppress gate voltage oscillation while securing wiring space.

[0062] Furthermore, in this embodiment, as shown in the upper arm wiring board 60 in Figure 3, the first gate pattern 62b-1 and the second gate pattern 62b-2 are provided between some semiconductor elements 50 and other semiconductor elements 50 in a second direction d2 (X direction) that is perpendicular to the first direction d1 (Y direction), which is the arrangement direction of the semiconductor elements 50.

[0063] This allows the first gate pattern 62b-1 and the second gate pattern 62b-2 to be arranged in a narrow space, and the wiring distance of the gate wiring W2 between the gate pattern 62b and the semiconductor element 50 to be shortened.

[0064] Furthermore, in this embodiment, as shown in the lower arm wiring board 60 in Figure 4, the first gate pattern 62b-1 is provided on one side of the plurality of semiconductor elements 50 in the second direction d2 (X direction) which is perpendicular to the first direction d1 (Y direction), which is the arrangement direction of the semiconductor elements 50, and the second gate pattern 62b-2 is provided on the other side of the plurality of semiconductor elements 50 in the second direction d2 (X direction) which is perpendicular to the first direction d1 (Y direction), which is the arrangement direction of the semiconductor elements 50.

[0065] This allows the first gate pattern 62b-1 and the second gate pattern 62b-2 to be arranged in a narrow space, and the wiring distance of the gate wiring W2 between the gate pattern 62b and the semiconductor element 50 to be shortened.

[0066] Furthermore, in this embodiment, as shown in the wiring board 60 of the upper arm in Figure 3 and the wiring board 60 of the lower arm in Figure 4, the gate pattern 62b further includes a third gate pattern 62b-3 provided in the current path from the gate terminals 41, 42 to the first gate pattern 62b-1 and the second gate pattern 62b-2, and this third gate pattern 62b-3 extends in a second direction d2 perpendicular to the first direction d1. For example, as shown in the wiring board 60 of the upper arm in Figure 3, the gate pattern 62b has a T-shape in plan view, and the plurality of semiconductor elements 50 are arranged so as to have a T-shape in the same orientation as the T-shape of the gate pattern 62b in plan view. Also, as shown in the wiring board 60 of the lower arm in Figure 4, the gate pattern 62b has a U-shape in plan view, and the plurality of semiconductor elements 50 are arranged so as to have a U-shape in the same orientation as the U-shape of the gate pattern 62b in plan view.

[0067] By arranging the third gate pattern 62b-3 so as to extend perpendicularly to the first gate pattern 62b-1 and the second gate pattern 62b-2, the third gate pattern 62b-3 can be placed in a narrow space, and the wiring distance of the gate wiring W2 between the first gate pattern 62b-1 and the second gate pattern 62b-2 and the third gate pattern 62b-3 can be shortened.

[0068] In this embodiment, the semiconductor module 1 further comprises auxiliary terminals 43 and 48, and the wiring pattern layer 62 further comprises auxiliary patterns 62c connected to the auxiliary terminals 43 and 48. As shown in the wiring board 60 of the upper arm in Figure 3 and the wiring board 60 of the lower arm in Figure 4, the auxiliary patterns 62c include a first auxiliary pattern 62c-1 that is directly connected to a plurality of semiconductor elements 50 via auxiliary wiring W3 and extends in a first direction d1.

[0069] As a result, for example, when oscillation occurs in a loop passing through semiconductor elements 50 that are close to each other, such as a second loop L2 that passes only through two adjacent semiconductor elements 50 arranged in the first direction d1, as shown in Figure 6, the first auxiliary pattern 62c-1 is directly connected to the semiconductor elements 50 via auxiliary wiring W3. This increases the size of the oscillation path loop at turn-on, lowers the coaxial frequency, and suppresses oscillation. Furthermore, since the first auxiliary pattern 62c-1 extends in the first direction d1 parallel to the first gate pattern 62b-1 and the second gate pattern 62b-2, the auxiliary pattern 62c can be arranged in a narrow space.

[0070] Furthermore, in this embodiment, as shown in the upper arm wiring board 60 in Figure 3, the first auxiliary pattern 62c-1 is provided between some semiconductor elements 50 and other semiconductor elements 50 in a second direction d2 that is perpendicular to the first direction d1.

[0071] This allows the first auxiliary pattern 62c-1 to be placed in a narrow space, and the wiring distance of the auxiliary wiring W3 between the first auxiliary pattern 62cx-1 and the semiconductor element 50 to be shortened.

[0072] Furthermore, in this embodiment, as shown in the wiring board 60 in Figure 4, the auxiliary pattern 62c further includes a second auxiliary pattern 62c-2 extending in a first direction d1, the first auxiliary pattern 62c-1 is provided on one side of the plurality of semiconductor elements 50 in a second direction d2 perpendicular to the first direction d1, and the second auxiliary pattern 62c-2 is provided on the other side of the plurality of semiconductor elements 50 in the second direction d2.

[0073] This allows the first auxiliary pattern 62c-1 and the second auxiliary pattern 62c-2 to be arranged in a narrow space, and the wiring distance of the auxiliary wiring W3 between the first auxiliary pattern 62c-1 and the second auxiliary pattern 62c-2 and the semiconductor element 50 to be shortened.

[0074] Furthermore, in this embodiment, as shown in the wiring board 60 of the upper arm in Figure 3 and the wiring board 60 of the lower arm in Figure 4, the auxiliary pattern 62c further includes a third auxiliary pattern 62c-3 provided in the current path from the auxiliary terminals 43, 48 to the first auxiliary pattern 62c-1. This third auxiliary pattern 62c-3 extends in a second direction d2 perpendicular to the first direction d1. For example, as shown in the wiring board 60 of the upper arm in Figure 3, each of the gate pattern 62b and the auxiliary pattern 62c exhibits a T-shape with the same orientation in a plan view, and the plurality of semiconductor elements 50 are arranged to exhibit a T-shape with the same orientation as the T-shape of the gate pattern 62b and the auxiliary pattern 62c in a plan view. Furthermore, as shown in Figure 4, the lower arm wiring board 60, the gate pattern 62b and the auxiliary pattern 62c each exhibit a U-shape with the same orientation in a plan view, and the multiple semiconductor elements 50 are arranged to exhibit a U-shape with the same orientation as the U-shape of the gate pattern 62b and the auxiliary pattern 62c in a plan view.

[0075] By providing the third auxiliary pattern 62c-3 in such a way that it extends perpendicularly to the first auxiliary pattern 62c-1, the third auxiliary pattern 62c-3 can be placed in a narrow space, and the wiring distance of the auxiliary wiring W3 between the first auxiliary pattern 62c-1 and the third auxiliary pattern 62c-3 can be shortened.

[0076] Furthermore, in this embodiment, as shown in the upper arm wiring board 60 in Figure 3, the first resistor chip R1 is mounted on the first gate pattern 62b-1, and the second resistor chip R2 is mounted on the second gate pattern 62b-2.

[0077] As a result, with a simple configuration in which the first resistor chip R1 and the second resistor chip R2 are placed on the first gate pattern 62b-1 and the second gate pattern 62b-2, oscillation of the gate voltage during a short circuit can be suppressed as described above.

[0078] Furthermore, in this embodiment, as shown in the lower arm wiring board 60 in Figure 4, the gate pattern 62b includes a fourth gate pattern 62b-4 provided in the current path from the third gate pattern 62b-3 to the first gate pattern 62b-1, and a fifth gate pattern 62b-5 provided in the current path from the third gate pattern 62b-3 to the second gate pattern 62b-2. The first resistor chip R1 is mounted on the fourth gate pattern 62b-4, and the second resistor chip R2 is mounted on the fifth gate pattern 62b-5.

[0079] As a result, the oscillation of the gate voltage during a short circuit can be suppressed as described above, with a simple configuration in which the first gate pattern 62b-1 and the second gate pattern 62b-2, which do not have the first resistor chip R1 and the second resistor chip R2 mounted on them, are elongated in the first direction d1.

[0080] <Second Embodiment> Figure 8 is a plan view showing the internal structure of the semiconductor module 2.

[0081] The configuration of the semiconductor module 2 shown in Figure 8 can be the same as that of the semiconductor module 1 of the first embodiment described above, except for the shape of the wiring pattern layer 62 and the arrangement of the semiconductor elements 50 on the wiring board 60 of the upper arm shown in Figure 9 and the wiring board 60 of the lower arm shown in Figure 10. Therefore, explanations of overlapping items will be omitted, and the differences will be explained.

[0082] In the upper arm wiring board 60 shown in Figure 9, three main current patterns 62a are arranged. One of these, the main current pattern 62a in the center in the X direction, has eight semiconductor elements 50 mounted on it, and is connected by a main current terminal 31 (D1 terminal) joined at terminal junction j1. Each of the remaining two main current patterns 62a is connected to four semiconductor elements 50 (surface electrodes 51) by main current wiring W1. These two main current patterns 62a are also connected by a main current terminal 33 (D2S1 terminal) joined at terminal junction j3. Furthermore, as shown in Figure 8, each of the two main current patterns 62a is connected to the main current pattern 62a of the wiring board 60 constituting the lower arm by main current wiring W1.

[0083] As shown in Figure 9, the eight semiconductor elements 50 mounted on the main current pattern 62a are arranged such that four semiconductor elements 50 are arranged in the first direction d1 (Y direction) on the positive X-direction side of the wiring board 60, and four semiconductor elements 50 are arranged in the first direction d1 (Y direction) on the negative X-direction side of the wiring board 60. These four semiconductor elements 50 are arranged in two rows in the first direction d1 with a gap in between in the second direction d2 which is orthogonal to the first direction d1, and can be considered to be arranged so as to present two I-shapes in a plan view.

[0084] In the upper arm wiring board 60 shown in Figure 9, the gate patterns 62b (first gate pattern 62b-1, second gate pattern 62b-2, and third gate pattern 62b-3) are connected to the gate pattern 72a of the auxiliary wiring board 70 shown in Figure 8 via gate wiring W2, thereby connecting to the gate terminal 41 (G1 terminal) joined to the gate pattern 72a at the terminal joint j4. Specifically, the third gate pattern 62b-3 is connected to the gate pattern 72a of the auxiliary wiring board 70 by gate wiring W2, and is connected to the first resistor chip R1 mounted on the first gate pattern 62b-1 and the second resistor chip R2 mounted on the second gate pattern 62b-2 by gate wiring W2. Thus, the third gate pattern 62b-3 can be said to be provided in the current path from the gate terminal 41 (G1 terminal) to the first gate pattern 62b-1 and the second gate pattern 62b-2.

[0085] As shown in Figure 9, the first gate pattern 62b-1 is directly connected to the four semiconductor elements 50 (gate electrodes 52) on the positive Y-direction side of the wiring board 60 via gate wiring W2.

[0086] The second gate pattern 62b-2 is directly connected to the four semiconductor elements 50 (gate electrodes 52) on the negative Y-direction side of the wiring board 60 via gate wiring W2.

[0087] The first gate pattern 62b-1 and the second gate pattern 62b-2 extend in the first direction d1. The first gate pattern 62b-1 is located on the positive side in the Y direction than the second gate pattern 62b-2 and extends in the first direction d1. Furthermore, the first gate pattern 62b-1 and the second gate pattern 62b-2 are provided between the four semiconductor elements 50 on the positive side in the X direction of the wiring board 60 and the four semiconductor elements 50 on the negative side in the X direction of the wiring board 60 in the second direction d2 (X direction) which is perpendicular to the first direction d1. The first gate pattern 62b-1 and the second gate pattern 62b-2 can be considered to exhibit an I-shape in the same orientation as the two I-shapes of the semiconductor element 50 in a plan view.

[0088] A first resistor chip R1 is mounted on the first gate pattern 62b-1. A second resistor chip R2 is mounted on the second gate pattern 62b-2.

[0089] As described above, the third gate pattern 62b-3 is connected by gate wiring W2 to the first resistor chip R1, the second resistor chip R2, and the gate pattern 72a of the auxiliary wiring board 70 shown in Figure 2. Furthermore, the third gate pattern 62b-3 is located on the positive side in the Y direction compared to the first gate pattern 62b-1 and the second gate pattern 62b-2, and extends in the second direction d2 (X direction) which is perpendicular to the first direction d1 (Y direction). As a result, the gate pattern 62b (first gate pattern 62b-1, second gate pattern 62b-2, and third gate pattern 62b-3) can be considered to have a T-shape in plan view as a whole.

[0090] In the upper arm wiring board 60 shown in Figure 9, the auxiliary pattern 62c (consisting of two auxiliary patterns, a first auxiliary pattern 62c-1 and a third auxiliary pattern 62c-3) is connected to the auxiliary pattern 72b of the auxiliary wiring board 70 shown in Figure 2 via auxiliary wiring W3, thereby connecting to the auxiliary terminal 43 (S1 terminal) joined to the auxiliary pattern 72b at the terminal joint j6. Specifically, the third auxiliary pattern 62c-3 is connected to the auxiliary pattern 72b of the auxiliary wiring board 70 by auxiliary wiring W3, and to the first auxiliary pattern 62c-1 by auxiliary wiring W3. Thus, the third auxiliary pattern 62c-3 can be said to be provided in the current path from the auxiliary terminal 43 (S1 terminal) to the first auxiliary pattern 62c-1.

[0091] As shown in Figure 9, the first auxiliary pattern 62c-1 is directly connected to all eight semiconductor elements 50 via auxiliary wiring W3.

[0092] The first auxiliary pattern 62c-1 has an E-shape in a plan view, sandwiching the first gate pattern 62b-1 and the second gate pattern 62b-2 in the Y direction, and extends in the first direction d1. The first auxiliary pattern 62c-1 is also provided in the second direction d2 (X direction), which is perpendicular to the first direction d1, between the four semiconductor elements 50 arranged in the first direction d1 on the positive X side of the wiring board 60 and the four semiconductor elements 50 arranged in the first direction d1 on the negative X side of the wiring board 60. In a plan view, the first auxiliary pattern 62c-1 can be considered to have an I-shape that is in the same orientation as the two I-shapes of the semiconductor elements 50.

[0093] As described above, the third auxiliary pattern 62c-3 is connected to the auxiliary pattern 72b of the auxiliary wiring board 70 shown in Figure 8 by auxiliary wiring W3. Furthermore, the third auxiliary pattern 62c-3 is located on the positive side in the Y direction compared to the first auxiliary pattern 62c-1, and extends in the second direction d2 (X direction) which is perpendicular to the first direction d1 (Y direction). As a result, the auxiliary patterns 62c (the first auxiliary pattern 62c-1 and the third auxiliary pattern 62c-3) as a whole can be considered to exhibit a T-shape in the same orientation as the T-shape of the gate pattern 62b in a plan view.

[0094] In the lower arm wiring board 60 shown in Figure 10, three main current patterns 62a are arranged, and four semiconductor elements 50 are mounted on two of these main current patterns 62a. The remaining main current pattern 62a is provided between the two main current patterns 62a in the X direction. This single main current pattern 62a is connected by a main current terminal 32 (S2 terminal) being joined at the terminal junction j2, and is connected to eight semiconductor elements 50 (surface electrodes 51) by main current wiring W1.

[0095] As shown in Figure 10, the eight semiconductor elements 50 mounted on the main current pattern 62a are arranged such that four semiconductor elements 50 are arranged in the first direction d1 (Y direction) on the positive X-direction side of the wiring board 60, and four semiconductor elements 50 are arranged in the first direction d1 (Y direction) on the negative X-direction side of the wiring board 60. These four semiconductor elements 50 are arranged in two rows in the first direction d1 with a gap in between in the second direction d2 which is orthogonal to the first direction d1, and can be considered as being arranged to form two I-shapes in a plan view as a whole.

[0096] In the lower arm wiring board 60 shown in Figure 10, the gate patterns 62b (first gate pattern 62b-1, second gate pattern 62b-2, and third gate pattern 62b-3) are connected to the gate pattern 72a of the auxiliary wiring board 70 shown in Figure 8 via gate wiring W2, thereby connecting to the gate terminal 42 (G2 terminal) joined to the gate pattern 72a at the terminal joint j5. Specifically, the third gate pattern 62b-3 is connected to the gate pattern 72a of the auxiliary wiring board 70 by gate wiring W2, with a first resistor chip R1 mounted on the positive end in the X direction and a second resistor chip R2 mounted on the negative end in the X direction. The first resistor chip R1 and the first gate pattern 62b-1 are connected by gate wiring W2, and the second resistor chip R2 and the second gate pattern 62b-2 are connected by gate wiring W2. Therefore, it can be said that the third gate pattern 62b-3 is provided in the current path from the gate terminal 42 (G2 terminal) to the first gate pattern 62b-1 and the second gate pattern 62b-2.

[0097] As shown in Figure 10, the first gate pattern 62b-1 is directly connected via gate wiring W2 to four semiconductor elements 50 (gate electrodes 52) arranged in the first direction d1 (Y direction) on the positive X-direction side of the wiring board 60.

[0098] The second gate pattern 62b-2 is directly connected via gate wiring W2 to four semiconductor elements 50 (gate electrodes 52) arranged in the first direction d1 (Y direction) on the negative X-direction side of the wiring board 60.

[0099] The first gate pattern 62b-1 and the second gate pattern 62b-2 extend in the first direction d1. The first gate pattern 62b-1 is provided on one side (positive side in the X direction) of the eight semiconductor elements 50 in the second direction d2 (X direction), and the second gate pattern 62b-2 is provided on the other side (negative side in the X direction) of the eight semiconductor elements 50 in the second direction d2 (X direction). Each of the first gate pattern 62b-1 and the second gate pattern 62b-2 can be considered to exhibit an I-shape in the same orientation as the two I-shapes of the semiconductor element 50 in a plan view.

[0100] The third gate pattern 62b-3 is located on the negative side in the Y direction compared to the first gate pattern 62b-1 and the second gate pattern 62b-2, and extends in the second direction d2 (X direction) which is perpendicular to the first direction d1 (Y direction). As a result, the gate patterns 62b (first gate pattern 62b-1, second gate pattern 62b-2, and third gate pattern 62b-3) as a whole can be considered to exhibit a U-shape in the same orientation as the U-shape of the auxiliary pattern 62c in a plan view.

[0101] In the lower arm wiring board 60 shown in Figure 10, the auxiliary patterns 62c (consisting of three auxiliary patterns: a first auxiliary pattern 62c-1, a second auxiliary pattern 62c-2, and a third auxiliary pattern 62c-3) are connected to the auxiliary pattern 72b of the auxiliary wiring board 70 shown in Figure 8 via auxiliary wiring W3, thereby connecting to the auxiliary terminal 48 (S2 terminal) joined to the auxiliary pattern 72b at the terminal joint j7. Specifically, the third auxiliary pattern 62c-3 is connected to the auxiliary pattern 72b of the auxiliary wiring board 70 by auxiliary wiring W3, and to the first auxiliary pattern 62c-1 by auxiliary wiring W3. Thus, the third auxiliary pattern 62c-3 can be said to be provided in the current path from the auxiliary terminal 48 (S2 terminal) to the first auxiliary pattern 62c-1.

[0102] As shown in Figure 10, the first auxiliary pattern 62c-1 is directly connected to the four semiconductor elements 50 (surface electrodes 51) on the positive X-direction side of the wiring board 60 via auxiliary wiring W3. The second auxiliary pattern 62c-2 is also directly connected to the four semiconductor elements 50 (surface electrodes 51) on the negative X-direction side of the wiring board 60 via auxiliary wiring W3. The third auxiliary pattern 62c-3 is connected to the first auxiliary pattern 62c-1 and the second auxiliary pattern 62c-2 via auxiliary wiring W3.

[0103] The first auxiliary pattern 62c-1 and the second auxiliary pattern 62c-2 extend in the first direction d1. The first auxiliary pattern 62c-1 is provided on one side (positive X-direction side) of the eight semiconductor elements 50 in the second direction d2 (X-direction), and the second auxiliary pattern 62c-2 is provided on the other side (negative X-direction side) of the eight semiconductor elements 50 in the second direction d2 (X-direction). The first auxiliary pattern 62c-1 is adjacent to the first gate pattern 62b-1 in the second direction d2 (X-direction) and is located on the negative X-direction side of the first gate pattern 62b-1. The second auxiliary pattern 62c-2 is adjacent to the second gate pattern 62b-2 in the second direction d2 (X-direction) and is located on the positive X-direction side of the second gate pattern 62b-2. In other words, the first auxiliary pattern 62c-1 and the second auxiliary pattern 62c-2 are adjacent to the first gate pattern 62b-1 and the second gate pattern 62b-2, and are provided between these first gate pattern 62b-1 and the second gate pattern 62b-2. Each of the first auxiliary pattern 62c-1 and the second auxiliary pattern 62c-2 can be considered to exhibit an I-shape in the same orientation as the two I-shapes of the semiconductor element 50 in a plan view.

[0104] As described above, the third auxiliary pattern 62c-3 is connected to the auxiliary pattern 72b of the auxiliary wiring board 70 shown in Figure 8 by auxiliary wiring W3. Furthermore, the third auxiliary pattern 62c-3 is located on the negative side in the Y direction compared to the first auxiliary pattern 62c-1, and extends in the second direction d2 (X direction) which is perpendicular to the first direction d1 (Y direction). As a result, the auxiliary patterns 62c (first auxiliary pattern 62c-1, second auxiliary pattern 62c-2, and third auxiliary pattern 62c-3) as a whole can be considered to exhibit a U-shape in the same orientation as the U-shape of the gate pattern 62b in a plan view.

[0105] With the semiconductor module 2 according to the second embodiment described above, the same effects as those of the semiconductor module 1 according to the first embodiment described above can be obtained, namely, the effect of suppressing gate voltage oscillation while securing wiring space.

[0106] Furthermore, in the first aspect of this embodiment, as shown in the upper arm wiring board 60 in Figure 9, the gate pattern 62b exhibits a T-shape in plan view, and the plurality of semiconductor elements 50 are arranged in two rows in the first direction d1 with a gap in the second direction d2 perpendicular to the first direction d1, so as to exhibit two I-shapes in plan view. Furthermore, in the second aspect, as shown in the upper arm wiring board 60 in Figure 9, the gate pattern 62b and the auxiliary pattern 62c each exhibit a T-shape oriented in the same direction in plan view, and the plurality of semiconductor elements 50 are arranged in two rows in the first direction d1 with a gap in the second direction d2 perpendicular to the first direction d1, so as to exhibit two I-shapes in plan view. Furthermore, from a third perspective, as shown in the lower arm wiring board 60 in Figure 10, the gate pattern 62b exhibits a U-shape in plan view, and the multiple semiconductor elements 50 are arranged in two rows in the first direction d1 with a gap in the second direction d2 perpendicular to the first direction d1, so as to exhibit two I-shapes in plan view. Furthermore, from a fourth perspective, as shown in the lower arm wiring board 60 in Figure 10, the gate pattern 62b and the auxiliary pattern 62c each exhibit a U-shape in the same direction in plan view, and the multiple semiconductor elements 50 are arranged in two rows in the first direction d1 with a gap in the second direction d2 perpendicular to the first direction d1, so as to exhibit two I-shapes in plan view.

[0107] As a result, even with this embodiment, the gate pattern 62b and auxiliary pattern 62c can be arranged in a narrow space, and the wiring distance of the main current wiring W1, gate wiring W2, and auxiliary wiring W3 can be shortened.

[0108] Furthermore, in this embodiment, as shown in the lower arm wiring board 60 in Figure 10, the first resistor chip R1 and the second resistor chip R2 are mounted on the third gate pattern 62b-3.

[0109] As a result, the oscillation of the gate voltage during a short circuit can be suppressed as described above, with a simplified configuration in which the width of the first gate pattern 62b-1 and the second gate pattern 62b-2 in the second direction d2 (X direction) is narrowed, in which the first resistor chip R1 and the second resistor chip R2 are not mounted.

[0110] <Third Embodiment> Figure 11 is a plan view showing the internal structure of the semiconductor module 3.

[0111] The configuration of the semiconductor module 3 shown in Figure 11 can be the same as that of the semiconductor module 1 of the first embodiment described above, except for the shape of the wiring pattern layer 62 and the arrangement of the semiconductor elements 50 on the wiring board 60 of the upper arm shown in Figure 12 and the wiring board 60 of the lower arm shown in Figure 13. Therefore, explanations of overlapping items will be omitted, and the differences will be explained.

[0112] In the upper arm wiring board 60 shown in Figure 12, three main current patterns 62a are arranged. One of these, the main current pattern 62a in the center in the X direction, has eight semiconductor elements 50 mounted on it, and is connected by a main current terminal 31 (D1 terminal) joined at terminal junction j1. Each of the remaining two main current patterns 62a is connected to four semiconductor elements 50 (surface electrodes 51) by main current wiring W1. These two main current patterns 62a are also connected by a main current terminal 33 (D2S1 terminal) joined at terminal junction j3. Furthermore, as shown in Figure 11, each of these two main current patterns 62a is connected to the main current pattern 62a of the wiring board 60 constituting the lower arm by main current wiring W1. As shown in Figure 11, the wiring boards 60 of the two upper arms on the positive side in the Y direction are preferably connected by a main current wiring W1 between the main current pattern 62a on the negative side in the X direction of the wiring board 60 on the positive side in the X direction and the main current pattern 62a on the positive side in the X direction of the wiring board 60 on the negative side in the X direction. The wiring boards 60 of the two lower arms on the negative side in the Y direction are preferably connected by a main current wiring W1 between the main current pattern 62a on the negative side in the X direction of the wiring board 60 on the positive side in the X direction and the main current pattern 62a on the positive side in the X direction of the wiring board 60 on the negative side in the X direction. Furthermore, the wiring boards 60 of the two lower arms on the negative side in the Y direction are preferably connected by a main current wiring W1 between the main current pattern 62a in the center in the X direction of the wiring board 60 on the positive side in the X direction and the main current pattern 62a in the center in the X direction of the wiring board 60 on the negative side in the X direction.

[0113] As shown in Figure 12, the eight semiconductor elements 50 mounted on the main current pattern 62a are arranged such that three semiconductor elements 50 are arranged in the first direction d1 (Y direction) on the positive X-direction side of the wiring board 60, and three semiconductor elements 50 are arranged in the first direction d1 (Y direction) on the negative X-direction side of the wiring board 60. The remaining two semiconductor elements 50 are located further to the positive Y-direction and positive X-direction than the three semiconductor elements 50, and further to the positive Y-direction and negative X-direction than the three semiconductor elements 50. These eight semiconductor elements 50 as a whole can be considered to be arranged to form a T-shape in a plan view.

[0114] In the upper arm wiring board 60 shown in Figure 12, the gate patterns 62b (first gate pattern 62b-1, second gate pattern 62b-2, third gate pattern 62b-3, sixth gate pattern 62b-6, and seventh gate pattern 62b-7) are connected to the gate pattern 72a of the auxiliary wiring board 70 shown in Figure 11 via gate wiring W2, thereby connecting to the gate terminal 41 (G1 terminal) joined to the gate pattern 72a at the terminal joint j4. Specifically, the third gate pattern 62b-3 is connected to the gate pattern 72a of the auxiliary wiring board 70 by gate wiring W2. Furthermore, the third gate pattern 62b-3 is connected by gate wiring W2 to the first resistor chip R1 mounted on the first gate pattern 62b-1, the second resistor chip R2 mounted on the second gate pattern 62b-2, the third resistor chip R3 mounted on the sixth gate pattern 62b-6, and the fourth resistor chip R4 mounted on the seventh gate pattern 62b-7.

[0115] Therefore, it can be said that the third gate pattern 62b-3 is provided in the current path from the gate terminal 41 (G1 terminal) to the first gate pattern 62b-1, the second gate pattern 62b-2, the sixth gate pattern 62b-6, and the seventh gate pattern 62b-7. Furthermore, it can be said that the first gate pattern 62b-1, the second gate pattern 62b-2, the sixth gate pattern 62b-6, and the seventh gate pattern 62b-7 are provided in parallel. Thus, it can also be said that the sixth gate pattern 62b-6 is provided in parallel with the first gate pattern 62b-1, and the seventh gate pattern 62b-7 is provided in parallel with the second gate pattern 62b-2.

[0116] As shown in Figure 12, the first gate pattern 62b-1 is directly connected via gate wiring W2 to two semiconductor elements 50 (gate gates 52) on the negative Y-direction side of three semiconductor elements 50 arranged in the first direction d1 (Y-direction) on the positive X-direction side of the wiring board 60. The sixth gate pattern 62b-6 is directly connected via gate wiring W2 to one semiconductor element 50 (gate gate 52) on the positive Y-direction side of three semiconductor elements 50 arranged in the first direction d1 (Y-direction) on the positive X-direction side of the wiring board 60, and to a semiconductor element 50 (gate gate 52) located at both the positive Y-direction end and the positive X-direction end of the wiring board 60. In the configuration where semiconductor elements 50 are arranged in fours in the first direction d1 (Y-direction), as shown in the lower arm wiring board 60 in Figure 13, the sixth gate pattern 62b-6 is preferably connected to two semiconductor elements 50 (gate gates 52) on the positive Y-direction side of the four semiconductor elements 50.

[0117] The second gate pattern 62b-2 is directly connected via gate wiring W2 to two semiconductor elements 50 (gate gates 52) on the negative Y side of three semiconductor elements 50 arranged in the first direction d1 (Y direction) on the negative X side of the wiring board 60. The seventh gate pattern 62b-7 is directly connected via gate wiring W2 to one semiconductor element 50 (gate gate 52) on the positive Y side of three semiconductor elements 50 arranged in the first direction d1 (Y direction) on the negative X side of the wiring board 60, and to a semiconductor element 50 (gate gate 52) located at both the positive Y end and the negative X end of the wiring board 60. In the configuration where semiconductor elements 50 are arranged in fours each in the first direction d1 (Y direction), as shown in the lower arm wiring board 60 in Figure 13, the seventh gate pattern 62b-7 is preferably connected to two semiconductor elements 50 (gate gates 52) on the positive Y side of the four semiconductor elements 50.

[0118] The first gate pattern 62b-1 and the second gate pattern 62b-2 extend in the first direction d1. The sixth gate pattern 62b-6 and the seventh gate pattern 62b-7 have a triangular shape in plan view. The first gate pattern 62b-1 and the second gate pattern 62b-2 are provided between three semiconductor elements 50 arranged in the first direction d1 on the positive X-side of the wiring board 60 and three semiconductor elements 50 arranged in the first direction d1 on the negative X-side of the wiring board 60. The sixth gate pattern 62b-6 is provided between a semiconductor element 50 located at both the positive Y-side end and the positive X-side end of the wiring board 60 and the positive Y-side end of the first gate pattern 62b-1. Furthermore, the seventh gate pattern 62b-7 is provided between the semiconductor element 50 located at the positive Y-direction end and the negative X-direction end of the wiring board 60 and the positive Y-direction end of the second gate pattern 62b-2.

[0119] A first resistor chip R1 is mounted on the first gate pattern 62b-1 in a bulging portion that extends to the positive X direction at the positive Y direction end. A second resistor chip R2 is mounted on the second gate pattern 62b-2 in a bulging portion that extends to the negative X direction at the positive Y direction end.

[0120] As described above, the third gate pattern 62b-3 is connected by gate wiring W2 to the first resistor chip R1, the second resistor chip R2, the third resistor chip R3, the fourth resistor chip R4, and the gate pattern 72a of the auxiliary wiring board 70 shown in Figure 11. Furthermore, the third gate pattern 62b-3 is located on the positive side in the Y direction more than the first gate pattern 62b-1, the second gate pattern 62b-2, the sixth gate pattern 62b-6, and the seventh gate pattern 62b-7, and extends in the second direction d2 (X direction) which is perpendicular to the first direction d1 (Y direction). As a result, the gate patterns 62b (the first gate pattern 62b-1, the second gate pattern 62b-2, the third gate pattern 62b-3, the sixth gate pattern 62b-6, and the seventh gate pattern 62b-7) can be considered to exhibit a T-shape in the same orientation as the T-shape of the semiconductor element 50 when viewed from above.

[0121] The upper arm wiring board 60 shown in Figure 12 has only one auxiliary pattern 62c in this embodiment. This auxiliary pattern 62c is connected to the auxiliary pattern 72b of the auxiliary wiring board 70 shown in Figure 11 via auxiliary wiring W3, thereby connecting to the auxiliary terminal 43 (S1 terminal) joined to the auxiliary pattern 72b at the terminal joint j6. Furthermore, the auxiliary pattern 62c is located on the positive side in the Y direction of the third gate pattern 62b-3 and extends in the second direction d2 (X direction) which is perpendicular to the first direction d1 (Y direction).

[0122] As shown in Figure 12, the auxiliary pattern 62c is directly connected via auxiliary wiring W3 to the semiconductor element 50 (surface electrode 51) at the positive Y-direction end of three semiconductor elements 50 arranged in the first direction d1 (Y-direction) on the positive X-direction side of the wiring board 60, and to the semiconductor element 50 (surface electrode 51) at the positive Y-direction end of three semiconductor elements 50 arranged in the first direction d1 (Y-direction) on the negative X-direction side of the wiring board 60. Furthermore, the auxiliary pattern 62c is directly connected via auxiliary wiring W3 to the semiconductor element 50 (surface electrode 51) located at both the positive Y-direction end and the positive X-direction end of the wiring board 60, and to the semiconductor element 50 (surface electrode 51) located at both the positive Y-direction end and the negative X-direction end of the wiring board 60. The three semiconductor elements 50 arranged in the first direction d1 (Y-direction) on the positive X-direction side of the wiring board 60 are connected to each other by auxiliary wiring W3 between adjacent semiconductor elements 50 (surface electrodes 51) in the Y-direction. Furthermore, the three semiconductor elements 50 arranged in the first direction d1 (Y direction) on the negative X-direction side of the wiring board 60 are connected to each other by auxiliary wiring W3 between adjacent semiconductor elements 50 (surface electrodes 51) in the Y direction. In other words, the auxiliary pattern 62c is connected in series via auxiliary wiring W3 to the three semiconductor elements 50 arranged in the first direction d1 (Y direction) on the positive X-direction side and the three semiconductor elements 50 arranged in the first direction d1 (Y direction) on the negative X-direction side.

[0123] In the lower arm wiring board 60 shown in Figure 13, three main current patterns 62a are arranged, and four semiconductor elements 50 are mounted on two of these main current patterns 62a. The remaining main current pattern 62a is provided between the two main current patterns 62a in the X direction. This single main current pattern 62a is connected by a main current terminal 32 (S2 terminal) being joined at the terminal junction j2, and is connected to eight semiconductor elements 50 (surface electrodes 51) by main current wiring W1.

[0124] As shown in Figure 13, the eight semiconductor elements 50 mounted on the two main current patterns 62a are arranged such that four semiconductor elements 50 are arranged in the first direction d1 (Y direction) on the positive X-direction side of the wiring board 60, and four semiconductor elements 50 are arranged in the first direction d1 (Y direction) on the negative X-direction side of the wiring board 60. These four semiconductor elements 50 are arranged in two rows in the first direction d1 with a gap in the second direction d2 which is orthogonal to the first direction d1, and can be considered to be arranged so as to form two I-shapes in a plan view. More precisely, the two semiconductor elements 50 on the negative Y-direction side are slightly shifted towards the center of the wiring board 60 in the X-direction compared to the two semiconductor elements 50 on the positive Y-direction side, but they can still be said to be arranged in groups of four in the Y direction.

[0125] In the lower arm wiring board 60 shown in Figure 13, the gate patterns 62b (first gate pattern 62b-1, second gate pattern 62b-2, third gate pattern 62b-3, fourth gate pattern 62b-4, and fifth gate pattern 62b-5) are connected to the gate pattern 72a of the auxiliary wiring board 70 shown in Figure 11 via gate wiring W2, thereby connecting to the gate terminal 42 (G2 terminal) joined to the gate pattern 72a at the terminal joint j5. Specifically, the third gate pattern 62b-3 is connected to the gate pattern 72a of the auxiliary wiring board 70, the third resistor chip R3 mounted on the fourth gate pattern 62b-4, and the fourth resistor chip R4 mounted on the fifth gate pattern 62b-5 by gate wiring W2. Furthermore, the third resistor chip R3 is connected to the first resistor chip R1 mounted on the first gate pattern 62b-1 by gate wiring W2, and the fourth resistor chip R4 is connected to the second resistor chip R2 mounted on the second gate pattern 62b-2 by gate wiring W2. Thus, the third gate pattern 62b-3 can be said to be provided in the current path from the gate terminal 41 (G1 terminal) to the first gate pattern 62b-1 and the second gate pattern 62b-2. Furthermore, the fourth gate pattern 62b-4 can be said to be provided in the current path from the third gate pattern 62b-3 to the first gate pattern 62b-1. Furthermore, the fifth gate pattern 62b-5 can be said to be provided in the current path from the third gate pattern 62b-3 to the second gate pattern 62b-2. Furthermore, a first resistor chip R1 is mounted on the first gate pattern 62b-1 in a bulging portion that protrudes to the negative X direction at the negative Y-side end. Similarly, a second resistor chip R2 is mounted on the second gate pattern 62b-2 in a bulging portion that protrudes to the positive X direction at the negative Y-side end. The width in the X direction of the bulging portions of the first gate pattern 62b-1 and the second gate pattern 62b-2 is the same as the width in the X direction of the fourth gate pattern 62b-4 and the fifth gate pattern 62b-5, which are rectangular in plan view.Furthermore, the positive X-direction end of the first gate pattern 62b-1 and the positive X-direction end of the fourth gate pattern 62b-4 are at the same position in the X-direction. Also, the negative X-direction end of the second gate pattern 62b-2 and the negative X-direction end of the fifth gate pattern 62b-5 are at the same position in the X-direction.

[0126] As shown in Figure 13, the first gate pattern 62b-1 is directly connected via gate wiring W2 to two semiconductor elements 50 (gate electrodes 52) on the positive Y side of four semiconductor elements 50 arranged in the first direction d1 (Y direction) on the positive X side. The fourth gate pattern 62b-4 is directly connected via gate wiring W2 to two semiconductor elements 50 (gate electrodes 52) on the negative Y side of four semiconductor elements 50 arranged in the first direction d1 (Y direction) on the positive X side. In the configuration where semiconductor elements 50 are arranged in groups of three in the first direction d1 (Y direction), as shown in the upper arm wiring board 60 in Figure 12, the fourth gate pattern 62b-4 only needs to be connected to one semiconductor element 50 (gate electrode 52) on the negative Y side of the three semiconductor elements 50, and to a semiconductor element 50 (gate electrode 52) located at both the negative Y end and the positive X end of the wiring board 60.

[0127] The second gate pattern 62b-2 is directly connected via gate wiring W2 to two semiconductor elements 50 (gate electrodes 52) on the positive side of the Y direction among four semiconductor elements 50 arranged in the first direction d1 (Y direction) on the negative side of the X direction. The fifth gate pattern 62b-5 is directly connected via gate wiring W2 to two semiconductor elements 50 (gate electrodes 52) on the negative side of the Y direction among four semiconductor elements 50 arranged in the first direction d1 (Y direction) on the negative side of the X direction. In the configuration where semiconductor elements 50 are arranged in groups of three in the first direction d1 (Y direction), as shown in the upper arm wiring board 60 in Figure 12, the fifth gate pattern 62b-5 only needs to be connected to one semiconductor element 50 (gate electrode 52) on the negative side of the Y direction among the three semiconductor elements 50, and to a semiconductor element 50 (gate electrode 52) located at both the negative end of the Y direction and the negative end of the X direction of the wiring board 60.

[0128] The first gate pattern 62b-1 and the second gate pattern 62b-2 extend in the first direction d1. The fourth gate pattern 62b-4 extends in the first direction d1 (Y direction) on the negative Y direction side of the first gate pattern 62b-1. The fifth gate pattern 62b-5 extends in the first direction d1 (Y direction) on the negative Y direction side of the second gate pattern 62b-2. Furthermore, the first gate pattern 62b-1 and the fourth gate pattern 62b-4 are provided on one side (positive X direction side) of the eight semiconductor elements 50 in the second direction d2 (X direction), and the second gate pattern 62b-2 and the fifth gate pattern 62b-5 are provided on the other side (negative X direction side) of the eight semiconductor elements 50 in the second direction d2 (X direction). Each of the first gate pattern 62b-1, the second gate pattern 62b-2, the fourth gate pattern 62b-4, and the fifth gate pattern 62b-5 can be considered to exhibit an I-shape in the same orientation as the two I-shapes of the semiconductor element 50 in a plan view. Furthermore, the first gate pattern 62b-1 and the fourth gate pattern 62b-4 can be considered to exhibit an I-shape together, and the second gate pattern 62b-2 and the fifth gate pattern 62b-5 can be considered to exhibit an I-shape together.

[0129] The third gate pattern 62b-3 is located on the negative side in the Y direction compared to the first gate pattern 62b-1, the second gate pattern 62b-2, the fourth gate pattern 62b-4, and the fifth gate pattern 62b-5, and extends in the second direction d2 (X direction) which is perpendicular to the first direction d1 (Y direction). As a result, the gate patterns 62b (first gate pattern 62b-1, second gate pattern 62b-2, third gate pattern 62b-3, fourth gate pattern 62b-4, and fifth gate pattern 62b-5) as a whole can be considered to exhibit a U-shape in plan view.

[0130] The lower arm wiring board 60 shown in Figure 13 has only one auxiliary pattern 62c in this embodiment. This auxiliary pattern 62c is connected to the auxiliary pattern 72b of the auxiliary wiring board 70 shown in Figure 11 via auxiliary wiring W3, thereby connecting to the auxiliary terminal 48 (S2 terminal) joined to the auxiliary pattern 72b at the terminal joint j7. Furthermore, the auxiliary pattern 62c is located on the negative side in the Y direction compared to the third gate pattern 62b-3 and extends in the second direction d2 (X direction) which is perpendicular to the first direction d1 (Y direction).

[0131] As shown in Figure 13, the auxiliary pattern 62c is directly connected via auxiliary wiring W3 to the semiconductor element 50 (surface electrode 51) at the negative Y-direction end of the four semiconductor elements 50 arranged in the first direction d1 (Y-direction) on the positive X-direction side, and to the semiconductor element 50 (surface electrode 51) at the negative Y-direction end of the four semiconductor elements 50 arranged in the first direction d1 (Y-direction) on the negative X-direction side. The four semiconductor elements 50 arranged in the first direction d1 (Y-direction) on the negative X-direction side are connected to each other by auxiliary wiring W3 between adjacent semiconductor elements 50 (surface electrodes 51) in the Y-direction. Also, the four semiconductor elements 50 arranged in the first direction d1 (Y-direction) on the positive X-direction side are connected to each other by auxiliary wiring W3 between adjacent semiconductor elements 50 (surface electrodes 51) in the Y-direction. In other words, the auxiliary pattern 62c is connected in series via the auxiliary wiring W3 to four semiconductor elements 50 arranged in the first direction d1 (Y direction) on the positive X side and four semiconductor elements 50 arranged in the first direction d1 (Y direction) on the negative X side.

[0132] With the semiconductor module 3 according to the third embodiment described above, the same effects as those of the semiconductor modules 1 and 2 according to the first or second embodiment described above can be obtained, namely, the effect of suppressing gate voltage oscillation while securing wiring space. Furthermore, by having the gate pattern 62b exhibit a T-shape in plan view, as in the wiring board 60 of the upper arm shown in Figure 12, or the gate pattern 62b exhibit a U-shape in plan view, as in the wiring board 60 of the lower arm shown in Figure 13, and arranging the multiple semiconductor elements 50 to exhibit a T-shape or I-shape in the same orientation as the T-shape of the gate pattern 62b in plan view, the wiring distance of the gate wiring W2 can be shortened or wiring space can be secured.

[0133] Furthermore, in this embodiment, as shown in the upper arm wiring board 60 in Figure 12, the gate pattern 62b further includes a sixth gate pattern 62b-6 provided in parallel with the first gate pattern 62b-1 and a seventh gate pattern 62b-7 provided in parallel with the second gate pattern 62b-2, the first resistor chip R1 is mounted on the first gate pattern 62b-1 and the second resistor chip R2 is mounted on the second gate pattern 62b-2. The semiconductor module 3 further includes a third resistor chip R3 mounted on the sixth gate pattern 62b-6 and a fourth resistor chip R4 mounted on the seventh gate pattern R7. Furthermore, as shown in Figure 13, the lower arm wiring board 60 includes a gate pattern 62b, a fourth gate pattern 62b-4 provided in the current path from the third gate pattern 62b-3 to the first gate pattern 62b-1, and a fifth gate pattern 62b-5 provided in the current path from the third gate pattern 62b-3 to the second gate pattern 62b-2. The first resistor chip R1 is mounted on the first gate pattern 62b-1, the second resistor chip R2 is mounted on the second gate pattern 62b-2, and the semiconductor module 3 further includes a third resistor chip R3 mounted on the fourth gate pattern 62b-4 and a fourth resistor chip R4 mounted on the fifth gate pattern 62b-5.

[0134] With these configurations, one resistor chip R1 to R4 is placed for every two semiconductor elements 50, so compared to the comparative example shown in Figure 7 (one resistor chip for every eight semiconductor elements 50) and the first embodiment (one resistor chip R1, R2 for every four semiconductor elements 50), short-circuit oscillation can be suppressed even further. This short-circuit oscillation occurs, for example, in loops that pass through semiconductor elements 50 that are far apart from each other, such as the third loop L3 shown in Figure 14 (shown by a dashed line) (for example, a loop that passes through the sixth gate pattern 62b-6, the third gate pattern 62b-3, the seventh gate pattern 62b-7, and the auxiliary pattern 62c).

[0135] Furthermore, in this embodiment, as shown in the upper arm wiring board 60 in Figure 12, the multiple semiconductor elements 50 are arranged in two rows of three or more in each row in the first direction d1, spaced apart in the second direction d2 which is orthogonal to the first direction d1. The first gate pattern 62b-1 is directly connected to two semiconductor elements 50 in one row arranged in the first direction d1 via gate wiring W2, the sixth gate pattern 62b-6 is directly connected to at least one semiconductor element 50 in one row via gate wiring W2, the second gate pattern 62b-2 is directly connected to two semiconductor elements 50 in the other row arranged in the first direction d1 via gate wiring W2, and the seventh gate pattern 62b-7 is directly connected to at least one semiconductor element 50 in the other row via gate wiring G2. Furthermore, as shown in the lower arm wiring board 60 in Figure 13, the multiple semiconductor elements 50 are arranged in two rows of three or more in each row in the first direction d1, spaced apart in the second direction d2 which is orthogonal to the first direction d1. The first gate pattern 62b-1 is directly connected to two semiconductor elements 50 in one row arranged in the first direction d1 via gate wiring W2, the fourth gate pattern 62b-4 is directly connected to at least one semiconductor element 50 in one row via gate wiring W2, the second gate pattern 62b-2 is directly connected to two semiconductor elements 50 in the other row arranged in the first direction d1 via gate wiring W2, and the fifth gate pattern 62b-5 is directly connected to at least one semiconductor element 50 in the other row via gate wiring W2.

[0136] These configurations allow for, for example, during turn-on, the number of loops that cause oscillation by passing through semiconductor elements 50 that are close to each other, such as the fourth loop L4 (shown as a dashed line) that passes through two adjacent semiconductor elements 50 arranged in the first direction d1 as shown in Figure 14, to be reduced compared to a configuration in which three or more semiconductor elements 50 connected to a single gate pattern 62b are arranged in the first direction d1. Therefore, according to this embodiment, gate voltage oscillation can be further suppressed. Specifically, it is as follows: The fourth loop L4 shown in Figure 14 passes through the semiconductor element 50 on the negative side in the Y direction and the semiconductor element 50 in the center in the Y direction, among the three semiconductor elements 50 arranged in the Y direction (first direction d1) on the positive side in the X direction of the wiring board 60. Furthermore, although not shown in the diagram, a loop is also generated on the negative X-direction side of the wiring board 60, passing through the semiconductor element 50 on the negative Y-direction side and the semiconductor element 50 in the center of the Y-direction among the three semiconductor elements 50 arranged in the Y-direction. On the other hand, the loop passing through the semiconductor element 50 on the positive Y-direction side and the semiconductor element 50 in the center of the Y-direction among the three semiconductor elements 50 arranged in the Y-direction is divided and enlarged by the first or second resistor chips R1, R2 and the third or fourth resistor chips R3, R4, and the resonant frequency is lowered, making it less likely to be subject to turn-on oscillation. In addition, the semiconductor element 50 on the positive Y-direction side among the three semiconductor elements 50 arranged in the Y-direction and the semiconductor element 50 located at the positive Y-direction end (and positive or negative X-direction end) of the wiring board 60 are positioned at an angle, resulting in a greater distance between them, and the auxiliary wiring W3 is not directly connected, so the loop becomes larger and is less likely to be subject to turn-on oscillation. Therefore, in the example shown in Figure 14, the loop where turn-on oscillation is relatively likely to occur is the only one (fourth loop L4) that passes through the semiconductor element 50 on the negative side in the Y direction and the semiconductor element 50 in the center in the Y direction, out of the three semiconductor elements 50 arranged in the Y direction.On the other hand, in the example of Figure 6 (the wiring board 60 of the upper arm of the semiconductor module 1 in the first embodiment), the second loop L2 is shown to pass through the semiconductor element 50 on the positive side in the Y direction and the semiconductor element 50 in the center in the Y direction, of the three semiconductor elements 50 arranged in the Y direction. However, it also occurs as a loop passing through the semiconductor element 50 on the negative side in the Y direction and the semiconductor element 50 in the center in the Y direction, of the three semiconductor elements 50 arranged in the Y direction. Therefore, there are two loops on both the positive and negative sides in the X direction of the wiring board 60 where turn-on oscillation is relatively likely to occur. Consequently, in the example of Figure 14, the number of loops where turn-on oscillation is relatively likely to occur can be halved compared to the example of Figure 6. By reducing the number of loops where turn-on oscillation is relatively likely to occur in this way, turn-on oscillation can be suppressed. In the example of Figure 4 (the wiring board 60 of the lower arm of the semiconductor module 1 in the first embodiment), similar to the example of Figure 6, the number of loops in which turn-on oscillation is relatively likely to occur is two, due to the three semiconductor elements 50 arranged in the Y direction on both the positive and negative X sides of the wiring board 60. Also, in the example of Figure 9 (the wiring board 60 of the upper arm of the semiconductor module 2 in the second embodiment), the number of loops in which turn-on oscillation is relatively likely to occur is two, due to the four semiconductor elements 50 arranged in the Y direction on both the positive and negative X sides of the wiring board 60 (two loops: one passing through the first and second elements from the positive Y side, and another passing through the third and fourth elements. The loop between the second and third elements from the positive Y side is divided and enlarged by the first and second resistor chips R1 and R2). Furthermore, in the example shown in Figure 10 (the wiring board 60 of the lower arm of the semiconductor module 1 in the second embodiment), on both the positive and negative sides of the wiring board 60 in the X direction, the number of loops in which turn-on oscillation is relatively likely to occur is three (a loop passing through the first and second elements from the positive side in the Y direction, a loop passing through the second and third elements, and a loop passing through the third and fourth elements). In the example shown in Figure 13 (the wiring board 60 of the lower arm of the semiconductor module 3 in this third embodiment), on both the positive and negative sides of the wiring board 60 in the X direction, the number of loops in which turn-on oscillation is relatively likely to occur is two (a loop passing through the first and second elements from the positive side in the Y direction, and a loop passing through the third and fourth elements).The second and third resistors from the positive side in the Y direction are divided and enlarged by the first or second resistor chips R1, R2 and the third or fourth resistor chips R3, R4. However, as for the semiconductor module 3 as a whole, as described above, the number of loops on the upper arm wiring board 60 (Figures 12 and 14) is small, with only one on each of the positive and negative sides in the X direction of the wiring board 60, so the number of loops can be reduced.

[0137] In this embodiment, the semiconductor module 3 further comprises auxiliary terminals 43 and 48, and the wiring pattern layer 62 further comprises an auxiliary pattern 62c connected to the auxiliary terminals 43 and 48. This auxiliary pattern 62c extends in a second direction d2 perpendicular to the first direction d1, and multiple semiconductor elements 50 are connected in series via auxiliary wiring W3.

[0138] Therefore, by arranging the auxiliary pattern 62c in a narrow space, wiring space can be secured, especially in configurations where the four resistor chips R1 to R4 described above are arranged. Furthermore, the auxiliary pattern 62c can be placed at the positive or negative Y-direction end of the wiring board 60. As a result, it is possible to secure sufficient width in the X-direction of the main current pattern 62a and suppress heat generation. Note that the fourth loop L4 of the oscillation path during turn-on shown in Figure 14 is smaller than the second loop L2 shown in Figure 6 because the adjacent semiconductor element 50 is directly connected by auxiliary wiring W3 without going through the auxiliary pattern 62c. As a result, the resonant frequency of the fourth loop L4 is higher and the oscillation is larger compared to the second loop L2 shown in Figure 6. However, since adjacent semiconductor elements 50 are connected by gate wiring W2 via gate pattern 62b (first gate pattern 62b-1 or second gate pattern 62b-2), the loop becomes larger and the resonant frequency can be reduced compared to the configuration in which adjacent semiconductor elements 50 are directly connected by both gate wiring W2 and auxiliary wiring W3, so the oscillation of the fourth loop L4 does not become that large.

[0139] The semiconductor module according to the present invention is not limited to the embodiments described above, and may be modified, substituted, or transformed in various ways without departing from the spirit of the technical idea. Furthermore, if the technical idea can be realized in a different way by technological advancements or other derived technologies, it may be implemented by that method. Accordingly, the claims cover all embodiments that may fall within the scope of the technical idea.

[0140] The following are some of the inventions described in the specification and drawings of this application.

[0141] <Note 1> A semiconductor module comprising: a plurality of semiconductor elements; a wiring board having a wiring pattern layer on which the plurality of semiconductor elements are mounted; a main current terminal; and a gate terminal, wherein the wiring pattern layer has a main current pattern on which the plurality of semiconductor elements are mounted and connected to the main current terminal, and a gate pattern connected to the gate terminal, wherein the gate pattern includes a first gate pattern that is directly connected to some of the plurality of semiconductor elements via gate wiring and extends in a first direction parallel to the arrangement direction of the some of the semiconductor elements, and a second gate pattern that is directly connected to some of the other semiconductor elements of the plurality of semiconductor elements via gate wiring and extends in the first direction, and further comprising: a first resistor chip mounted on the gate pattern in the current path from the gate terminal to the first gate pattern; and a second resistor chip mounted on the gate pattern in the current path from the gate terminal to the second gate pattern.

[0142] <Note 2> The semiconductor module according to Note 1, characterized in that the first gate pattern and the second gate pattern are provided between some semiconductor elements and some other semiconductor elements in a second direction perpendicular to the first direction.

[0143] <Note 3> The semiconductor module according to Note 1, characterized in that the first gate pattern is provided on one side of the plurality of semiconductor elements in a second direction perpendicular to the first direction, and the second gate pattern is provided on the other side of the plurality of semiconductor elements in the second direction.

[0144] <Note 4> The semiconductor module according to Note 1, wherein the gate pattern further includes a third gate pattern provided in the current path from the gate terminal to the first gate pattern and the second gate pattern, and the third gate pattern extends in a second direction perpendicular to the first direction.

[0145] <Note 5> The semiconductor module according to Note 1, characterized in that the gate pattern exhibits a T-shape in a plan view, and the plurality of semiconductor elements are arranged to exhibit a T-shape in the same orientation as the T-shape of the gate pattern in a plan view.

[0146] <Note 6> The semiconductor module according to Note 1, characterized in that the gate pattern exhibits a T-shape in plan view, and the plurality of semiconductor elements are arranged in two rows in the first direction with spacing in a second direction perpendicular to the first direction, so as to exhibit two I-shapes in plan view.

[0147] <Note 7> The semiconductor module according to Note 1, characterized in that the gate pattern exhibits a U-shape in a plan view, and the plurality of semiconductor elements are arranged to exhibit a U-shape in the same orientation as the U-shape of the gate pattern in a plan view.

[0148] <Note 8> The semiconductor module according to Note 1, characterized in that the gate pattern exhibits a U-shape in plan view, and the plurality of semiconductor elements are arranged in two rows in the first direction with spacing between them in a second direction perpendicular to the first direction, so as to exhibit two I-shapes in plan view.

[0149] <Note 9> The semiconductor module according to Note 1, further comprising auxiliary terminals, wherein the wiring pattern layer further comprises auxiliary patterns connected to the auxiliary terminals, and the auxiliary patterns include a first auxiliary pattern that is directly connected to the plurality of semiconductor elements via auxiliary wiring and extends in the first direction.

[0150] <Note 10> The semiconductor module according to Note 9, characterized in that the first auxiliary pattern is provided between some of the semiconductor elements and some of the other semiconductor elements in a second direction perpendicular to the first direction.

[0151] <Note 11> The semiconductor module according to Note 9, wherein the auxiliary pattern further includes a second auxiliary pattern extending in the first direction, the first auxiliary pattern is provided on one side of the plurality of semiconductor elements in a second direction perpendicular to the first direction, and the second auxiliary pattern is provided on the other side of the plurality of semiconductor elements in the second direction.

[0152] <Note 12> The semiconductor module according to Note 9, wherein the auxiliary pattern further includes a third auxiliary pattern provided in the current path from the auxiliary terminal to the first auxiliary pattern, and the third auxiliary pattern extends in a second direction perpendicular to the first direction.

[0153] <Note 13> The semiconductor module according to Note 9, characterized in that each of the gate pattern and the auxiliary pattern exhibits a T-shape with the same orientation in a plan view, and the plurality of semiconductor elements are arranged to exhibit a T-shape with the same orientation as the T-shape of the gate pattern and the auxiliary pattern in a plan view.

[0154] <Note 14> The semiconductor module according to Note 9, characterized in that each of the gate pattern and the auxiliary pattern exhibits a T-shape with the same orientation in a plan view, and the plurality of semiconductor elements are arranged in two rows in the first direction with spacing in a second direction perpendicular to the first direction, so as to exhibit two I-shapes in a plan view.

[0155] <Note 15> The semiconductor module according to Note 9, characterized in that each of the gate pattern and the auxiliary pattern exhibits a U-shape with the same orientation in a plan view, and the plurality of semiconductor elements are arranged to exhibit a U-shape with the same orientation as the U-shape of the gate pattern and the auxiliary pattern in a plan view.

[0156] <Note 16> The semiconductor module according to Note 9, characterized in that each of the gate pattern and the auxiliary pattern exhibits a U-shape with the same orientation in a plan view, and the plurality of semiconductor elements are arranged in two rows in the first direction with spacing in a second direction perpendicular to the first direction, so as to exhibit two I-shapes in a plan view.

[0157] <Note 17> The semiconductor module according to Note 1, characterized in that the first resistor chip is mounted on the first gate pattern, and the second resistor chip is mounted on the second gate pattern.

[0158] <Note 18> The semiconductor module according to Note 4, characterized in that the gate pattern includes a fourth gate pattern provided in the current path from the third gate pattern to the first gate pattern, and a fifth gate pattern provided in the current path from the third gate pattern to the second gate pattern, the first resistor chip is mounted on the fourth gate pattern, and the second resistor chip is mounted on the fifth gate pattern.

[0159] <Note 19> The semiconductor module according to Note 4, characterized in that the first resistor chip and the second resistor chip are mounted on the third gate pattern.

[0160] <Note 20> The semiconductor module according to Note 4, wherein the gate pattern further includes a sixth gate pattern provided in parallel with the first gate pattern and a seventh gate pattern provided in parallel with the second gate pattern, the first resistor chip is mounted on the first gate pattern, the second resistor chip is mounted on the second gate pattern, and the semiconductor module further comprises a third resistor chip mounted on the sixth gate pattern and a fourth resistor chip mounted on the seventh gate pattern.

[0161] <Note 21> The semiconductor module according to Note 20, characterized in that the plurality of semiconductor elements are arranged in two rows of three or more in each row in the first direction, spaced apart in a second direction orthogonal to the first direction, the first gate pattern is directly connected to two of the semiconductor elements in one of the rows arranged in the first direction via the gate wiring, the sixth gate pattern is directly connected to at least one of the semiconductor elements in one of the rows via the gate wiring, the second gate pattern is directly connected to two of the semiconductor elements in the other row arranged in the first direction via the gate wiring, and the seventh gate pattern is directly connected to at least one of the semiconductor elements in the other row via the gate wiring.

[0162] <Note 22> The semiconductor module according to Note 4, wherein the gate pattern includes a fourth gate pattern provided in the current path from the third gate pattern to the first gate pattern, and a fifth gate pattern provided in the current path from the third gate pattern to the second gate pattern, the first resistor chip is mounted on the first gate pattern, the second resistor chip is mounted on the second gate pattern, and the semiconductor module further comprises a third resistor chip mounted on the fourth gate pattern and a fourth resistor chip mounted on the fifth gate pattern.

[0163] <Note 23> The semiconductor module according to Note 22, characterized in that the plurality of semiconductor elements are arranged in two rows of three or more in each row in the first direction, spaced apart in a second direction orthogonal to the first direction, the first gate pattern is directly connected to two of the semiconductor elements in one of the rows arranged in the first direction via the gate wiring, the fourth gate pattern is directly connected to at least one of the semiconductor elements in one of the rows via the gate wiring, the second gate pattern is directly connected to two of the semiconductor elements in the other row arranged in the first direction via the gate wiring, and the fifth gate pattern is directly connected to at least one of the semiconductor elements in the other row via the gate wiring.

[0164] <Note 24> The semiconductor module according to Note 1, further comprising auxiliary terminals, wherein the wiring pattern layer further comprises auxiliary patterns connected to the auxiliary terminals, the auxiliary patterns extend in a second direction perpendicular to the first direction, and the plurality of semiconductor elements are connected in series via auxiliary wiring.

[0165] As described above, the present invention has the effect of suppressing gate voltage oscillation while securing wiring space, and is particularly useful for industrial or electrical inverter devices.

[0166] This application is based on Japanese Patent Application No. 2025-012873, filed on January 29, 2025. All of its contents are included herein.

[0167] 1, 2, 3 Semiconductor module 10 Case 20 Base plate 21 Through hole 31 Main current terminal (D1 terminal) 32 Main current terminal (S2 terminal) 33 Main current terminal (D2S1 terminal) 41, 42 Gate terminals 43-48 Auxiliary terminals 50 Semiconductor element 51 Surface electrode 52 Gate terminal 60 Wiring board 61 Insulating layer 62 Wiring pattern layer 62a Main current pattern 62b Gate pattern 62b-1 First gate pattern 62b-2 Second gate pattern 62b-3 Third gate pattern 62b-4 Fourth gate pattern 62b-5 Fifth gate pattern 62b-6 Sixth gate pattern 62b-7 Seventh gate pattern 62c Auxiliary pattern 62c-1 First auxiliary pattern 62c-2 Second auxiliary pattern 62c-3 Third auxiliary pattern 63 Heat dissipation layer 70 Auxiliary wiring board 71 Insulation layer 72a Gate pattern 72b Auxiliary pattern 73 Heat dissipation layer C1 First current path C2 Second current path C3 Third current path d1 First direction d2 Second direction j1-j11 Terminal junction L1 First loop L2 Second loop L3 Third loop L4 Fourth loop R1 First resistor chip R2 Second resistor chip R3 Third resistor chip R4 Fourth resistor chip R5 Auxiliary resistor chip W1 Main current wiring W2 Gate wiring W3 Auxiliary wiring

Claims

1. A semiconductor module comprising: a plurality of semiconductor elements; a wiring board having a wiring pattern layer on which the plurality of semiconductor elements are mounted; a main current terminal; and a gate terminal, wherein the wiring pattern layer has a main current pattern on which the plurality of semiconductor elements are mounted and connected to the main current terminal, and a gate pattern connected to the gate terminal, and the gate pattern includes a first gate pattern that is directly connected to some of the plurality of semiconductor elements via gate wiring and extends in a first direction parallel to the arrangement direction of the plurality of semiconductor elements, and a second gate pattern that is directly connected to some of the other plurality of semiconductor elements via gate wiring and extends in the first direction, and further comprising: a first resistor chip mounted on the gate pattern in the current path from the gate terminal to the first gate pattern; and a second resistor chip mounted on the gate pattern in the current path from the gate terminal to the second gate pattern.

2. The semiconductor module according to claim 1, characterized in that the first gate pattern and the second gate pattern are provided between some semiconductor elements and some other semiconductor elements in a second direction orthogonal to the first direction.

3. The semiconductor module according to claim 1, characterized in that the first gate pattern is provided on one side of the plurality of semiconductor elements in a second direction perpendicular to the first direction, and the second gate pattern is provided on the other side of the plurality of semiconductor elements in the second direction.

4. The semiconductor module according to claim 1, wherein the gate pattern further includes a third gate pattern provided in the current path from the gate terminal to the first gate pattern and the second gate pattern, and the third gate pattern extends in a second direction perpendicular to the first direction.

5. The semiconductor module according to claim 1, characterized in that the gate pattern exhibits a T-shape in a plan view, and the plurality of semiconductor elements are arranged to exhibit a T-shape in the same orientation as the T-shape of the gate pattern in a plan view.

6. The semiconductor module according to claim 1, characterized in that the gate pattern exhibits a T-shape in plan view, and the plurality of semiconductor elements are arranged in two rows in the first direction with spacing in a second direction perpendicular to the first direction, so as to exhibit two I-shapes in plan view.

7. The semiconductor module according to claim 1, characterized in that the gate pattern exhibits a U-shape in a plan view, and the plurality of semiconductor elements are arranged to exhibit a U-shape in the same orientation as the U-shape of the gate pattern in a plan view.

8. The semiconductor module according to claim 1, characterized in that the gate pattern exhibits a U-shape in plan view, and the plurality of semiconductor elements are arranged in two rows in the first direction with spacing between them in a second direction perpendicular to the first direction, so as to exhibit two I-shapes in plan view.

9. The semiconductor module according to claim 1, further comprising auxiliary terminals, wherein the wiring pattern layer further comprises auxiliary patterns connected to the auxiliary terminals, and the auxiliary patterns include a first auxiliary pattern extending in the first direction and directly connected to the plurality of semiconductor elements via auxiliary wiring.

10. The semiconductor module according to claim 9, characterized in that the first auxiliary pattern is provided between some of the semiconductor elements and some of the other semiconductor elements in a second direction perpendicular to the first direction.

11. The semiconductor module according to claim 9, wherein the auxiliary pattern further includes a second auxiliary pattern extending in the first direction, the first auxiliary pattern is provided on one side of the plurality of semiconductor elements in a second direction perpendicular to the first direction, and the second auxiliary pattern is provided on the other side of the plurality of semiconductor elements in the second direction.

12. The semiconductor module according to claim 9, wherein the auxiliary pattern further includes a third auxiliary pattern provided in the current path from the auxiliary terminal to the first auxiliary pattern, and the third auxiliary pattern extends in a second direction perpendicular to the first direction.

13. The semiconductor module according to claim 9, characterized in that each of the gate pattern and the auxiliary pattern exhibits a T-shape with the same orientation in a plan view, and the plurality of semiconductor elements are arranged to exhibit a T-shape with the same orientation as the T-shape of the gate pattern and the auxiliary pattern in a plan view.

14. The semiconductor module according to claim 9, characterized in that each of the gate pattern and the auxiliary pattern exhibits a T-shape with the same orientation in a plan view, and the plurality of semiconductor elements are arranged in two rows in the first direction with spacing in a second direction perpendicular to the first direction, so as to exhibit two I-shapes in a plan view.

15. The semiconductor module according to claim 9, characterized in that each of the gate pattern and the auxiliary pattern exhibits a U-shape with the same orientation in a plan view, and the plurality of semiconductor elements are arranged to exhibit a U-shape with the same orientation as the U-shape of the gate pattern and the auxiliary pattern in a plan view.

16. The semiconductor module according to claim 9, characterized in that each of the gate pattern and the auxiliary pattern exhibits a U-shape with the same orientation in a plan view, and the plurality of semiconductor elements are arranged in two rows in the first direction with spacing in a second direction perpendicular to the first direction, so as to exhibit two I-shapes in a plan view.

17. The semiconductor module according to claim 1, characterized in that the first resistor chip is mounted on the first gate pattern, and the second resistor chip is mounted on the second gate pattern.

18. The semiconductor module according to claim 4, wherein the gate pattern includes a fourth gate pattern provided in the current path from the third gate pattern to the first gate pattern, and a fifth gate pattern provided in the current path from the third gate pattern to the second gate pattern, the first resistor chip is mounted on the fourth gate pattern, and the second resistor chip is mounted on the fifth gate pattern.

19. The semiconductor module according to claim 4, characterized in that the first resistor chip and the second resistor chip are mounted on the third gate pattern.

20. The semiconductor module according to claim 4, wherein the gate pattern further includes a sixth gate pattern provided in parallel with the first gate pattern and a seventh gate pattern provided in parallel with the second gate pattern, the first resistor chip is mounted on the first gate pattern, the second resistor chip is mounted on the second gate pattern, and the semiconductor module further comprises a third resistor chip mounted on the sixth gate pattern and a fourth resistor chip mounted on the seventh gate pattern.

21. The semiconductor module according to claim 20, characterized in that the plurality of semiconductor elements are arranged in two rows of three or more in each row in the first direction, spaced apart in a second direction orthogonal to the first direction, the first gate pattern is directly connected to two of the semiconductor elements in one of the rows arranged in the first direction via the gate wiring, the sixth gate pattern is directly connected to at least one of the semiconductor elements in one of the rows via the gate wiring, the second gate pattern is directly connected to two of the semiconductor elements in the other row arranged in the first direction via the gate wiring, and the seventh gate pattern is directly connected to at least one of the semiconductor elements in the other row via the gate wiring.

22. The semiconductor module according to claim 4, wherein the gate pattern includes a fourth gate pattern provided in the current path from the third gate pattern to the first gate pattern, and a fifth gate pattern provided in the current path from the third gate pattern to the second gate pattern, the first resistor chip is mounted on the first gate pattern, the second resistor chip is mounted on the second gate pattern, and the semiconductor module further comprises a third resistor chip mounted on the fourth gate pattern and a fourth resistor chip mounted on the fifth gate pattern.

23. The semiconductor module according to 22, characterized in that the plurality of semiconductor elements are arranged in two rows of three or more in each row in the first direction, spaced apart in a second direction orthogonal to the first direction, the first gate pattern is directly connected to two of the semiconductor elements in one of the rows arranged in the first direction via the gate wiring, the fourth gate pattern is directly connected to at least one of the semiconductor elements in one of the rows via the gate wiring, the second gate pattern is directly connected to two of the semiconductor elements in the other row arranged in the first direction via the gate wiring, and the fifth gate pattern is directly connected to at least one of the semiconductor elements in the other row via the gate wiring.

24. The semiconductor module according to claim 1, further comprising auxiliary terminals, wherein the wiring pattern layer further comprises auxiliary patterns connected to the auxiliary terminals, the auxiliary patterns extend in a second direction perpendicular to the first direction, and the plurality of semiconductor elements are connected in series via auxiliary wiring.

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