Semiconductor device and method for manufacturing same, and semiconductor module and method for manufacturing same

Abstract

Provided is a technique for reducing warping of a semiconductor substrate and ensuring adhesion between a nickel layer and a protective layer. This semiconductor device has a semiconductor substrate and an upper electrode provided on an upper surface of the semiconductor substrate. The upper electrode has an electrode layer in contact with the semiconductor substrate. The upper electrode is provided on the electrode layer and has a first nickel layer composed of nickel containing phosphorus. The upper electrode has a second nickel layer that is provided on the first nickel layer, is composed of nickel containing phosphorus, has a higher phosphorus concentration than the first nickel layer, and has a higher internal stress than the first nickel layer. The upper electrode is provided on the second nickel layer and has a protective layer made of gold.

Description

Semiconductor Device, Method for Manufacturing the Same, Semiconductor Module, and Method for Manufacturing the Same

[0001] (Cross - reference to related applications) This application is a related application of Japanese Patent Application No. 2025 - 015012 filed on January 31, 2025. It claims the priority based on this Japanese patent application, and all the contents described in this Japanese patent application are incorporated herein by reference as part of the present specification.

[0002] The technology disclosed in this specification relates to a semiconductor device, a method for manufacturing the same, a semiconductor module, and a method for manufacturing the same.

[0003] Japanese Patent Publication No. 2011 - 211057 (hereinafter referred to as Patent Document 1) discloses a device having a substrate, an electrode, and a nickel layer. The electrode is provided on the substrate. The nickel layer is provided on the electrode. The nickel layer contains phosphorus.

[0004] In some cases, a nickel layer containing phosphorus and a protective layer made of gold are provided on the surface electrode of a semiconductor substrate. The protective layer is formed on the surface of the nickel layer. The protective layer serves to prevent oxidation of the nickel layer. When the phosphorus concentration of the nickel layer is high, the adhesion with the protective layer becomes high. However, when the phosphorus concentration of the nickel layer is high, the internal stress of the nickel layer becomes large, and the semiconductor substrate may be warped. In this specification, a technique for reducing the warp of the semiconductor substrate and ensuring the adhesion between the nickel layer and the protective layer is provided.

[0005] The semiconductor device disclosed in this specification may have a semiconductor substrate and an upper electrode provided on the upper surface of the semiconductor substrate. Further, the upper electrode may have an electrode layer in contact with the semiconductor substrate and a first nickel layer provided on the electrode layer and composed of nickel containing phosphorus. The upper electrode may have a second nickel layer provided on the first nickel layer, composed of nickel containing phosphorus, having a higher phosphorus concentration than the first nickel layer, and having a higher internal stress than the first nickel layer. The upper electrode may have a protective layer provided on the second nickel layer and made of gold.

[0006] In the semiconductor device described above, a protective layer is provided on the second nickel layer. The phosphorus concentration of the second nickel layer is higher than that of the first nickel layer. Therefore, high adhesion is obtained between the second nickel layer and the protective layer. Furthermore, in the semiconductor device described above, a first nickel layer with a low phosphorus concentration is provided between the second nickel layer and the semiconductor substrate. The internal stress of the first nickel layer is lower than that of the second nickel layer. As a result, warping of the semiconductor substrate caused by the internal stress of the nickel layer can be suppressed.

[0007] This is a schematic diagram of a semiconductor device. This diagram shows the relationship between the phosphorus concentration in the nickel layer and the internal stress generated within the nickel layer when the nickel layer is formed by plating. This is a schematic diagram of a semiconductor module. This is a method for manufacturing a semiconductor device according to an example. This is a method for manufacturing a semiconductor device according to an example.

[0008] In one example semiconductor device disclosed herein, the thickness of the first nickel layer may be greater than the thickness of the second nickel layer.

[0009] An example semiconductor device disclosed herein may include a semiconductor substrate and an upper electrode provided on the upper surface of the semiconductor substrate. The upper electrode may have an electrode layer in contact with the semiconductor substrate. The upper electrode may have a first nickel layer provided on the electrode layer, composed of phosphorus-containing nickel, with a phosphorus concentration of less than 4 wt%. The upper electrode may have a second nickel layer provided on the first nickel layer, composed of phosphorus-containing nickel, with a phosphorus concentration of 4 wt% or more and less than 8 wt%. The upper electrode may have a protective layer provided on the second nickel layer, composed of gold.

[0010] This configuration reduces warping of the semiconductor substrate and ensures good adhesion between the second nickel layer and the protective layer.

[0011] The semiconductor device 10 shown in Figure 1 has a semiconductor substrate 12, an insulating film 50, an upper electrode 14, and a lower electrode 16. The semiconductor substrate 12 is made of silicon. The semiconductor substrate 12 may also be made of semiconductor materials such as silicon carbide or nitride semiconductors. An IGBT (insulated gate bipolar transistor) is formed on the semiconductor substrate 12.

[0012] An upper electrode 14 and an insulating film 50 are provided on the upper surface 12a of the semiconductor substrate 12. The upper electrode 14 is located in the center of the semiconductor substrate 12. The insulating film 50 covers the outer edge of the upper electrode 14. The insulating film 50 is made of, for example, polyimide.

[0013] The upper electrode 14 has an electrode layer 18, a first nickel layer 20, a second nickel layer 22, and a protective layer 24. The electrode layer 18 is provided on the upper surface 12a of the semiconductor substrate 12. The electrode layer 18 is in contact with the upper surface 12a. The electrode layer 18 is made of a metal such as aluminum.

[0014] The first nickel layer 20 is provided on the electrode layer 18. The lower surface of the first nickel layer 20 is in contact with the electrode layer 18. The first nickel layer 20 is composed of a material containing nickel and phosphorus. The first nickel layer 20 is a plating layer. The phosphorus concentration of the first nickel layer 20 is low. For example, the phosphorus concentration of the first nickel layer 20 is less than 4 wt%. Because the phosphorus concentration of the first nickel layer 20 is low, the crystallinity of the first nickel layer 20 is high.

[0015] The second nickel layer 22 is provided on the first nickel layer 20. The lower surface of the second nickel layer 22 is in contact with the first nickel layer 20. The second nickel layer 22 is composed of a material containing nickel and phosphorus. The second nickel layer 22 is a plating layer. The phosphorus concentration of the second nickel layer 22 is higher than that of the first nickel layer 20. The phosphorus concentration of the second nickel layer 22 is, for example, 4 wt% or more and less than 8 wt%. The thickness of the second nickel layer 22 is thinner than the thickness of the first nickel layer 20.

[0016] Figure 2 shows the relationship between the phosphorus concentration in a nickel layer and the internal stress generated within the nickel layer when the nickel layer is formed by plating. As shown in the figure, the internal stress reaches a peak value P1 at a predetermined phosphorus concentration. When the phosphorus concentration is lower than the peak value P1, the internal stress decreases as the phosphorus concentration decreases. The phosphorus concentration at the peak value P1 varies depending on the composition of impurities contained in the nickel layer, but is between 4 wt% and 8 wt%. The phosphorus concentration of the second nickel layer 22 (between 4 wt% and 8 wt%) is within the range that includes the peak value P1, and the phosphorus concentration of the first nickel layer 20 (less than 4 wt%) is lower than the phosphorus concentration of the second nickel layer 22. Therefore, the internal stress of the second nickel layer 22 is greater than the internal stress of the first nickel layer 20.

[0017] The upper electrode 14 has a protective layer 24. The protective layer 24 is provided on the second nickel layer 22. The lower surface of the protective layer 24 is in contact with the second nickel layer 22. The protective layer 24 is made of gold (i.e., Au). The protective layer 24 is provided on the outermost surface of the upper electrode 14 and prevents oxidation of the second nickel layer 22.

[0018] The semiconductor device 10 has a lower electrode 16. The lower electrode 16 is in contact with the lower surface 12b of the semiconductor substrate 12.

[0019] As described above, the protective layer 24 is provided on the second nickel layer 22. The phosphorus concentration of the second nickel layer 22 is higher than that of the first nickel layer 20. The higher the phosphorus concentration in the nickel layer, the better the adhesion between the gold and the nickel layer. Therefore, high adhesion is obtained between the second nickel layer 22 and the protective layer 24. As a result, delamination between the second nickel layer 22 and the protective layer 24 is unlikely to occur.

[0020] Furthermore, as described above, the nickel layer is composed of a first nickel layer 20 with low internal stress and a second nickel layer 22 with high internal stress. As a result, the internal stress generated in the nickel layer is reduced. Consequently, the warping of the semiconductor substrate 12 caused by the internal stress of the nickel layer is reduced. In particular, in this embodiment, since the thickness of the second nickel layer 22 is thinner than the thickness of the first nickel layer 20, the internal stress generated in the nickel layer is reduced more effectively. Consequently, the warping of the semiconductor substrate 12 caused by the internal stress of the nickel layer is reduced. In addition, since the first nickel layer 20 with low internal stress is provided between the semiconductor substrate 12 and the second nickel layer 22 with high internal stress, stress is less likely to be transmitted from the second nickel layer 22 to the semiconductor substrate 12. This further reduces the warping of the semiconductor substrate 12 more effectively.

[0021] Figure 3 shows a semiconductor module 100 on which a semiconductor device 10 is mounted. The semiconductor module 100 has a conductive spacer 30, surface metal bodies 32, 34, solder layers 40, 42, and solder layer 44. The conductive spacer 30 is located on top of the semiconductor device 10. The conductive spacer 30 is made of a metal such as copper. The solder layer 40 is located between the upper electrode 14 and the conductive spacer 30. The solder layer 40 joins the conductive spacer 30 to the protective layer 24 provided on the outermost surface of the upper electrode 14. That is, the conductive spacer 30 is joined to the upper electrode 14 via the solder layer 40. The conductive spacer 30 is electrically connected to the upper electrode 14 via the solder layer 40.

[0022] The surface metal body 34 is positioned on top of the conductive spacer 30. The surface metal body 34 is made of a metal such as copper. The solder layer 44 is positioned between the conductive spacer 30 and the surface metal body 34. The solder layer 44 joins the conductive spacer 30 and the surface metal body 34. The surface metal body 34 is electrically connected to the upper electrode 14 via the conductive spacer 30. The surface metal body 34 is also electrically connected to a main electrode (not shown).

[0023] The surface metal body 32 is located at the bottom of the semiconductor device 10. The surface metal body 32 is made of a metal such as copper. The solder layer 42 is located between the lower electrode 16 and the surface metal body 32. The solder layer 42 joins the lower electrode 16 and the surface metal body 32. That is, the surface metal body 32 is joined to the lower electrode 16 via the solder layer 42. The surface metal body 32 is electrically connected to the lower electrode 16 via the solder layer 42. The surface metal body 32 is also electrically connected to a main electrode (not shown).

[0024] The semiconductor module 100 has a sealing member 52. As shown in Figure 3, the sealing member 52 seals the semiconductor device 10. The sealing member 52 is made of an insulating material. The sealing member 52 is made of a thermosetting resin material such as epoxy resin.

[0025] As described above, the semiconductor substrate 12 of the semiconductor device 10 has little warping. Therefore, good adhesion can be ensured between the semiconductor device 10 and the conductive spacer 30, and between the semiconductor device 10 and the surface metal body 32, so gaps are less likely to occur at the interface.

[0026] During use of semiconductor devices, the heat generated can cause electromigration, leading to mutual diffusion between nickel and solder, and potentially forming an alloy layer at the interface between the nickel layer and the solder layer. In contrast, in this embodiment, the first nickel layer 20 has high crystallinity, making electromigration less likely and thus less likely to form an alloy layer at the interface between the upper electrode 14 and the solder layer 40. As a result, the upper electrode 14 is less likely to peel off from the solder layer 40.

[0027] (Method for manufacturing the semiconductor device 10) Next, the method for manufacturing the semiconductor device 10 will be described. In the following, the process of forming the upper electrode 14, the lower electrode 16, and the insulating film 50 will be described. For other processes, known manufacturing methods can be appropriately adopted.

[0028] First, a semiconductor substrate 12 is prepared as shown in Figure 4. An IGBT is formed inside the semiconductor substrate 12 shown in Figure 4. Next, an electrode layer 18 is formed on the upper surface 12a of the semiconductor substrate 12.

[0029] Next, as shown in Figure 5, a first nickel layer 20 is formed on the electrode layer 18 by plating. The first nickel layer 20 is composed of a material containing nickel and phosphorus. The phosphorus concentration of the first nickel layer 20 is less than 4 wt%.

[0030] Next, a second nickel layer 22 is formed on the first nickel layer 20 by plating. The second nickel layer 22 is composed of a material containing nickel and phosphorus. The second nickel layer 22 is formed such that its phosphorus concentration is higher than that of the first nickel layer 20. The phosphorus concentration of the second nickel layer 22 is 4 wt% or more and less than 8 wt%. Furthermore, the second nickel layer 22 is formed such that its thickness is thinner than that of the first nickel layer 20.

[0031] Next, a protective layer 24 is formed on the second nickel layer 22 by plating. The protective layer 24 is made of gold. This forms the upper electrode 14 on the semiconductor substrate 12.

[0032] Next, an insulating film 50 is formed to cover the outer edge of the upper electrode 14. Then, by forming the lower electrode 16 on the lower surface 12b of the semiconductor substrate 12, the semiconductor device 10 shown in Figure 1 is completed.

[0033] (Method for manufacturing semiconductor module 100) Next, the method for manufacturing the semiconductor module 100 will be described. First, the semiconductor device 10 shown in Figure 1 is prepared. Next, the protective layer 24 provided on the outermost surface of the upper electrode 14 and the conductive spacer 30 are joined by soldering. The protective layer 24 is joined to the conductive spacer 30 via a solder layer 40.

[0034] Next, the lower electrode 16 and the surface metal body 32 are joined by soldering. The lower electrode 16 is joined to the surface metal body 32 via a solder layer 42. The conductive spacer 30 and the surface metal body 34 are also joined by soldering. After that, a sealing member 52 is formed to seal the semiconductor device 10. This completes the semiconductor module 100 shown in Figure 3.

[0035] In the embodiment described above, an IGBT was formed on the semiconductor substrate 12. However, diodes, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and the like may also be formed on the semiconductor substrate 12.

[0036] In the embodiment described above, the phosphorus concentration of the first nickel layer 20 was lower than that of the second nickel layer 22. However, the phosphorus concentration of the nickel layers may be configured such that the phosphorus concentration increases from the lower surface of the first nickel layer 20 towards the upper surface of the second nickel layer 22.

[0037] The conductive spacer 30 is an example of a "first conductor member". The surface metal body 32 is an example of a "second conductor member". Also, the solder layer 40 is an example of a "first joining member". The solder layer 42 is an example of a "second joining member".

[0038] The semiconductor device and its manufacturing method, and the configuration of the semiconductor module and its manufacturing method disclosed herein are described below. (Configuration 1) A semiconductor device comprising: a semiconductor substrate; an upper electrode provided on the upper surface of the semiconductor substrate, wherein the upper electrode comprises: an electrode layer in contact with the semiconductor substrate; a first nickel layer provided on the electrode layer and composed of nickel containing phosphorus; a second nickel layer provided on the first nickel layer and composed of nickel containing phosphorus, having a higher phosphorus concentration than the first nickel layer and a higher internal stress than the first nickel layer; and a protective layer provided on the second nickel layer and composed of gold. (Configuration 2) The semiconductor device according to Configuration 1, wherein the thickness of the first nickel layer is greater than the thickness of the second nickel layer. (Configuration 3) A semiconductor device comprising: a semiconductor substrate; an upper electrode provided on the upper surface of the semiconductor substrate; wherein the upper electrode comprises: an electrode layer in contact with the semiconductor substrate; a first nickel layer provided on the electrode layer and composed of nickel containing phosphorus with a phosphorus concentration of less than 4 wt%; a second nickel layer provided on the first nickel layer and composed of nickel containing phosphorus with a phosphorus concentration of 4 wt% or more and less than 8 wt%; and a protective layer provided on the second nickel layer and composed of gold. (Configuration 4) A semiconductor module comprising: a semiconductor device according to any one of Configurations 1 to 3; a first conductor member; and a second conductor member; wherein the semiconductor device comprises: a lower electrode provided on the lower surface of the semiconductor substrate; the first conductor member is bonded to the upper electrode via a first bonding member; and the second conductor member is bonded to the lower electrode via a second bonding member.(Configuration 5) A method for manufacturing a semiconductor device, comprising: a step of forming an electrode layer on a semiconductor substrate; a step of forming a first nickel layer made of phosphorus-containing nickel on the electrode layer by plating; a step of forming a second nickel layer made of phosphorus-containing nickel on the first nickel layer by plating, having a higher phosphorus concentration than the first nickel layer and a higher internal stress than the first nickel layer; and a step of forming a protective layer made of gold on the second nickel layer by plating. (Configuration 6) The method for manufacturing a semiconductor device according to claim 5, wherein the thickness of the first nickel layer is greater than the thickness of the second nickel layer. (Configuration 7) A method for manufacturing a semiconductor device, comprising: a step of forming an electrode layer on a semiconductor substrate; a step of forming a first nickel layer made of phosphorus-containing nickel with a phosphorus concentration of less than 4 wt% on the electrode layer by plating; a step of forming a second nickel layer made of phosphorus-containing nickel with a phosphorus concentration of 4 wt% or more and less than 8 wt% on the first nickel layer by plating; and a step of forming a protective layer made of gold on the second nickel layer by plating. (Configuration 8) A manufacturing method according to any one of Configurations 5 to 7, further comprising the step of forming a lower electrode on the lower surface of the semiconductor substrate. (Configuration 9) A method for manufacturing a semiconductor module using a semiconductor device manufactured by the manufacturing method according to Configuration 8, comprising the steps of: joining a first conductor member to the protective layer via a first bonding member; and joining a second conductor member to the lower electrode via a second bonding member.

[0039] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness.

Claims

1. A semiconductor device comprising: a semiconductor substrate; an upper electrode provided on the upper surface of the semiconductor substrate, wherein the upper electrode comprises: an electrode layer in contact with the semiconductor substrate; a first nickel layer provided on the electrode layer and composed of nickel containing phosphorus; a second nickel layer provided on the first nickel layer and composed of nickel containing phosphorus, having a higher phosphorus concentration than the first nickel layer and a higher internal stress than the first nickel layer; and a protective layer provided on the second nickel layer and composed of gold.

2. The semiconductor device according to claim 1, wherein the thickness of the first nickel layer is greater than the thickness of the second nickel layer.

3. A semiconductor device comprising: a semiconductor substrate; an upper electrode provided on the upper surface of the semiconductor substrate, wherein the upper electrode comprises: an electrode layer in contact with the semiconductor substrate; a first nickel layer provided on the electrode layer and composed of nickel containing phosphorus with a phosphorus concentration of less than 4 wt%; a second nickel layer provided on the first nickel layer and composed of nickel containing phosphorus with a phosphorus concentration of 4 wt% or more and less than 8 wt%; and a protective layer provided on the second nickel layer and composed of gold.

4. A semiconductor module comprising: a semiconductor device according to any one of claims 1 to 3; a first conductor member; and a second conductor member, wherein the semiconductor device has a lower electrode provided on the lower surface of the semiconductor substrate; the first conductor member is bonded to the upper electrode via a first bonding member; and the second conductor member is bonded to the lower electrode via a second bonding member.

5. A method for manufacturing a semiconductor device, comprising: a step of forming an electrode layer on a semiconductor substrate; a step of forming a first nickel layer made of phosphorus-containing nickel on the electrode layer by plating; a step of forming a second nickel layer made of phosphorus-containing nickel, having a higher phosphorus concentration than the first nickel layer and a higher internal stress than the first nickel layer by plating; and a step of forming a protective layer made of gold on the second nickel layer by plating.

6. The method for manufacturing a semiconductor device according to claim 5, wherein the thickness of the first nickel layer is greater than the thickness of the second nickel layer.

7. A method for manufacturing a semiconductor device, comprising: a step of forming an electrode layer on a semiconductor substrate; a step of forming a first nickel layer on the electrode layer by plating, which is made of nickel containing phosphorus and has a phosphorus concentration of less than 4 wt%; a step of forming a second nickel layer on the first nickel layer by plating, which is made of nickel containing phosphorus and has a phosphorus concentration of 4 wt% or more and less than 8 wt%; and a step of forming a protective layer on the second nickel layer by plating, which is made of gold.

8. The manufacturing method according to any one of claims 5 to 7, further comprising the step of forming a lower electrode on the lower surface of the semiconductor substrate.

9. A method for manufacturing a semiconductor module using a semiconductor device manufactured by the manufacturing method described in claim 8, comprising the steps of: joining a first conductor member to the protective layer via a first bonding member; and joining a second conductor member to the lower electrode via a second bonding member.

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