Imaging device

Abstract

An imaging device includes a plurality of pixels. Each of the plurality of pixels includes a photoelectric conversion film, a first electrode, a second electrode, a third electrode, and a partition wall. The photoelectric conversion film includes a first surface and a second surface facing each other. The photoelectric conversion film converts light into an electric charge. The first electrode and the second electrode are disposed at a position closer to the first surface than to the second surface. The first electrode collects electric charges. The second electrode does not overlap with the first electrode in plan view. The third electrode is disposed at a position closer to the second surface than to the first surface. The third electrode is located between the photoelectric conversion film and the partition wall. The plurality of pixels include a first pixel. In the first pixel, the partition wall overlaps with the second electrode in plan view.

Description

Imaging device

[0001] The present disclosure relates to an imaging device.

[0002] Various studies have been conducted on imaging devices. In one embodiment of Patent Document 1, it is described that a shield electrode is provided. In another embodiment of Patent Document 1, it is described that a partition wall is provided as a light condensing element.

[0003] Japanese Patent No. 7359766

[0004] The present disclosure provides a technique suitable for improving image quality.

[0005] The present disclosure provides an imaging device including a plurality of pixels, each of the plurality of pixels including a photoelectric conversion film including a first surface and a second surface facing the first surface, the photoelectric conversion film configured to convert light into electric charges, a first electrode disposed at a position closer to the first surface than the second surface, the first electrode configured to collect the electric charges, a second electrode disposed at a position closer to the first surface than the second surface, the second electrode not overlapping the first electrode in plan view, a third electrode disposed at a position closer to the second surface than the first surface, and a partition wall, the third electrode being located between the photoelectric conversion film and the partition wall, the plurality of pixels including a first pixel, and in the first pixel, in the plan view, the partition wall overlapping the second electrode.

[0006] The technology according to the present disclosure is suitable for improving image quality.

[0007] Figure 1 is a cross-sectional view showing an imaging device according to Embodiment 1. Figure 2 is a cross-sectional view showing an example of the dimensions of the imaging device according to Embodiment 1. Figure 3A is a plan view showing an imaging device according to Embodiment 1. Figure 3B is a plan view showing an imaging device according to Embodiment 1. Figure 3C is a plan view showing an imaging device according to Embodiment 1. Figure 4 is a cross-sectional view showing an imaging device according to Embodiment 2. Figure 5 is an explanatory diagram schematically showing the paths of light and charge. Figure 6 is an explanatory diagram schematically showing the paths of light and charge. Figure 7A is a plan view showing an imaging device according to Embodiment 2. Figure 7B is a plan view showing an imaging device according to Embodiment 2. Figure 7C is a plan view showing an imaging device according to Embodiment 2. Figure 8 is a cross-sectional view showing the shape of an applicable partition wall. Figure 9 is a cross-sectional view showing the shape of an applicable partition wall. Figure 10 is a cross-sectional view showing the shape of an applicable partition wall. Figure 11 is a cross-sectional view for explaining the material of an applicable partition wall. Figure 12 is a cross-sectional view for explaining the material of an applicable partition wall. Figure 13 is a cross-sectional view for explaining the material of an applicable partition wall. Figure 14 is a cross-sectional view showing applicable pixel vias and shield vias. Figure 15 is a plan view showing the arrangement of applicable shield vias. Figure 16 is a plan view showing the arrangement of applicable shield vias. Figure 17 is a plan view showing the configuration of applicable electrodes and vias. Figure 18 is a plan view showing the configuration of applicable electrodes and vias. Figure 19 is a plan view showing the configuration of applicable electrodes and vias. Figure 20 is a plan view showing the configuration of applicable electrodes and vias. Figure 21 is a plan view showing the configuration of applicable electrodes and vias. Figure 22 is a plan view showing an example configuration of an applicable imaging device. Figure 23 is a schematic diagram showing an example configuration of a camera system according to Embodiment 3. Figure 24A is a cross-sectional view showing an imaging device according to the first reference embodiment. Figure 24B is a cross-sectional view showing an imaging device according to the second reference embodiment. Figure 24C is a cross-sectional view showing an imaging device according to the third reference embodiment.

[0008] (Background to this Disclosure) Figure 24A is a cross-sectional view showing an imaging device according to the first reference embodiment. Figure 24B is a cross-sectional view showing an imaging device according to the second reference embodiment. Figure 24C is a cross-sectional view showing an imaging device according to the third reference embodiment. Figures 24A, 24B, and 24C show imaging devices 1X, 1Y, and 1Z, respectively. In Figures 24A, 24B, and 24C, one pixel 81, 82, and 83 are shown in an enlarged view, respectively.

[0009] The imaging device 1X in Figure 24A includes a plurality of pixels 81. The plurality of pixels 81 constitute a pixel array. Each of the plurality of pixels 81 outputs an output signal. The imaging device 1X forms an image based on these output signals.

[0010] The imaging device 1Y in Figure 24B includes a plurality of pixels 82. The plurality of pixels 82 constitute a pixel array. Each of the plurality of pixels 82 outputs an output signal. The imaging device 1Y forms an image based on these output signals.

[0011] The imaging device 1Z in Figure 24C includes a plurality of pixels 83. The plurality of pixels 83 constitute a pixel array. Each of the plurality of pixels 83 outputs an output signal. The imaging device 1Z forms an image based on these output signals.

[0012] In each of the pixels 81, 82, and 83, the pixel electrode 91, photoelectric conversion film 94, counter electrode 93, and protective film 95 are stacked in this order. When a potential is applied to the counter electrode 93, a potential difference is created between the pixel electrode 91 and the counter electrode 93, and an electric field is applied to the photoelectric conversion film 94. With the electric field applied, the photoelectric conversion film 94 converts light that has passed through the counter electrode 93 and entered the photoelectric conversion film 94 into electric charge. The electric charge is collected by the pixel electrode 91.

[0013] In pixel 81 of Figure 24A, the packing layer 96 and the partition wall 97 are positioned at the same height above the protective film 95. The partition wall 97 exerts an optical effect that focuses the light incident on the imaging device 1X. This optical effect prevents light that would normally be incident on the photoelectric conversion film 94 of one pixel 81 from being incident on the photoelectric conversion film 94 of an adjacent pixel 81. In this way, interference of output signals between adjacent pixels 81, i.e., crosstalk, is suppressed.

[0014] In pixel 82 of Figure 24B, the shield electrode 92 is positioned below the photoelectric conversion film 94 and at the same height as the pixel electrode 91. The shield electrode 92 exerts an electrical effect when a potential is applied to it. Due to this electrical effect, the charge in the region of the photoelectric conversion film 94 directly above the shield electrode 92 is collected by the shield electrode 92. This prevents the situation where charge that would normally reach the pixel electrode 91 of one pixel 82 reaches the pixel electrode 91 of an adjacent pixel 82. In this way, crosstalk is suppressed.

[0015] Thus, both the partition wall 97 and the shield electrode 92 can suppress crosstalk. This can contribute to improving image quality. In a color imaging device where the packed layer 96 is a color filter, suppressing crosstalk can suppress color mixing.

[0016] The pixel 83 in Figure 24C includes a packed layer 96, a partition wall 97, and a shielding electrode 92. According to the inventors' research, crosstalk can be effectively suppressed by using the partition wall 97 and the shielding electrode 92 in combination. However, when using them in combination, both a sensitivity loss region 97L originating from the partition wall 97 and a sensitivity loss region 92L originating from the shielding electrode 92 may occur. The sensitivity loss region 97L is a region of the photoelectric conversion film 94 directly below the partition wall 97, where light is less likely to be incident and therefore does not contribute much to sensitivity. The sensitivity loss region 92L corresponds to the region of the photoelectric conversion film 94 directly above the shielding electrode 92, where charge is recovered by the shielding electrode 92. The presence of both the sensitivity loss region 97L and the sensitivity loss region 92L can lead to a decrease in pixel sensitivity and a decrease in image quality.

[0017] Figure 24C illustrates a phenomenon in which some of the charge generated by the light focused by the partition wall 97 is taken up by the shield electrode 92 instead of the pixel electrode 91, thereby reducing the sensitivity of the pixel 83. This phenomenon can become apparent when the pixel 83 is miniaturized, making it difficult to increase the aspect ratio and height of the partition wall 97, and resulting in insufficient light-gathering ability of the partition wall 97.

[0018] Therefore, the inventors investigated how to improve image quality by ensuring sensitivity while suppressing crosstalk. Through their investigations, the inventors came up with the idea of ​​suppressing the overall width of the partition wall and shield electrode by creating an overlap in a plan view.

[0019] Embodiments of this disclosure are described below. Note that the embodiments described below are either comprehensive or specific examples. The numerical values, shapes, materials, components, arrangement and connection configurations of components, processes, process sequences, etc., shown in the following embodiments are examples only and are not intended to limit this disclosure. Furthermore, components in the following embodiments that are not described in an independent claim are described as optional components.

[0020] In the embodiments shown below, terms such as "up," "down," "lateral," and "height" are used solely to specify the relative positions of the elements. These terms are not intended to limit the orientation of the imaging device during use. "Height" refers to the position in the vertical direction. The lateral direction is perpendicular to the vertical direction.

[0021] In some drawings, the illustration of certain components may be omitted. For example, in Figure 1, the illustration of the pixel via 18 and the shield via 19 is omitted. In Figure 2, the illustration of the packing layer 16 is omitted.

[0022] (Embodiment 1) Figure 1 is a cross-sectional view showing an imaging device 1A according to Embodiment 1.

[0023] The imaging device 1A includes n pixels 10, where n is a natural number greater than or equal to 2. The n pixels 10 constitute a pixel array 20 (see Figure 22). Each of the n pixels 10 outputs an output signal. The imaging device 1A forms an image based on these output signals. In Figure 1, one pixel 10 is shown in magnified view.

[0024] Each of the n pixels 10 includes a pixel electrode 11, a shield electrode 12, a photoelectric conversion film 14, a counter electrode 13, a protective film 15, a packing layer 16, and a partition wall 17. The combinations of the pixel electrode 11 and the shield electrode 12, and the combinations of the photoelectric conversion film 14, the counter electrode 13, the protective film 15, the packing layer 16, and the partition wall 17 are stacked in this order from bottom to top. In addition, each of the n pixels 10 includes a microlens (not shown) above the packing layer 16 and the partition wall 17. In the example of Figure 1, the heights of the packing layer 16 and the partition wall 17 are the same. However, the height of the packing layer 16 may be higher or lower than the height of the partition wall 17.

[0025] In Embodiment 1, the partition wall 17 separates the packed layers 16 of adjacent pixels 10. The packed layers 16 are color filters. The imaging device 1A is a color imaging device.

[0026] The photoelectric conversion film 14 has a first surface 14a and a second surface 14b. The first surface 14a and the second surface 14b face each other in the vertical direction. The second surface 14b is positioned above the first surface 14a. The photoelectric conversion film 14 converts light into electric charge. In Embodiment 1, the photoelectric conversion film 14 contains an organic material. Specifically, the organic material may be an organic semiconductor material.

[0027] The pixel electrode 11 is positioned below the first surface 14a of the photoelectric conversion film 14. The pixel electrode 11 collects electric charge. In Embodiment 1, the pixel electrode 11 includes a metal. The metal may be a single metal, a metal compound, or an alloy. The pixel electrode 11 includes, for example, at least one selected from the group consisting of titanium nitride, copper, tungsten, titanium, tantalum, and aluminum. The pixel electrode 11 may also include at least two alloys selected from the group consisting of these materials.

[0028] The shield electrode 12 is positioned below the first surface 14a of the photoelectric conversion film 14. In Embodiment 1, the second electrode 12 is electrically isolated from the first electrode 11. In the pixel 10 of Embodiment 1, in a plan view, the shield electrode 12 is positioned outside the pixel electrode 11 and does not overlap with the pixel electrode 11. In Embodiment 1, "plan view" refers to the view from the thickness direction Dt of the photoelectric conversion film 14. Specifically, in the pixel 10, in a plan view, the shield electrode 12 surrounds the pixel electrode 11. In a plan view, the shield electrode 12 is positioned between adjacent pixel electrodes 11. The shield electrode 12 is positioned at the same height as the pixel electrode 11. An example of the material included in the shield electrode 12 is the material exemplified as the material included in the pixel electrode 11. The shield electrode 12 and the pixel electrode 11 may include the same material. The same material means that the composition is the same.

[0029] The counter electrode 13 is positioned above the second surface 14b of the photoelectric conversion film 14. The counter electrode 13 is a transparent electrode and transmits light. In Embodiment 1, the counter electrode 13 contains indium tin oxide (ITO). The counter electrode 13 may also contain indium zinc oxide (IZO).

[0030] The protective film 15 is positioned above the counter electrode 13. The partition wall 17 and the packing layer 16 are positioned above the counter electrode 13, specifically above the protective film 15. In Embodiment 1, the partition wall 17 is positioned at the same height as the packing layer 16.

[0031] The partition wall 17 includes, for example, at least one selected from the group consisting of metals, metal compounds, carbon, and insulating materials. The metal includes, for example, at least one selected from the group consisting of aluminum, tungsten, titanium, titanium-aluminum (TiAl), copper, tantalum, cobalt, and ruthenium. The metal compound includes, for example, at least one selected from the group consisting of titanium nitride, tantalum oxide, and tantalum nitride. The insulating material includes, for example, at least one selected from the group consisting of inorganic materials and resins. The inorganic material includes, for example, at least one selected from the group consisting of silicon oxide and silicon nitride. The silicon oxide or silicon nitride may be silicon oxynitride. The silicon oxide is, for example, SiO2. The silicon nitride is, for example, SiN. The silicon oxynitride is, for example, SiON. The resin includes, for example, at least one selected from the group consisting of styrene resin, acrylic resin, styrene-acrylic copolymer resin, and siloxane resin. The partition wall 17 may contain the above materials in the form of pigments such as titanium black and carbon black.

[0032] The packed layer 16 includes, for example, a resin. The resin may be an organic material. For example, the resin is an acrylic resin.

[0033] When a potential is applied to the counter electrode 13, a potential difference is created between the pixel electrode 11 and the counter electrode 13, and an electric field is applied to the photoelectric conversion film 14. With the electric field applied, the photoelectric conversion film 14 converts light that has passed through the counter electrode 13 and entered the photoelectric conversion film 14 into electric charge. The electric charge is collected by the pixel electrode 11. The pixel 10 outputs an output signal corresponding to the amount of charge thus collected. Specifically, although not shown in the figures, the imaging device 1A includes a circuit provided on a semiconductor substrate. The circuit is electrically connected to the pixel electrode 11. The circuit includes a charge storage unit and an amplifying transistor. The charge storage unit is a diffusion region on the semiconductor substrate. The charge collected by the pixel electrode 11 is stored in the charge storage unit. The amplifying transistor outputs an output signal corresponding to the potential of the charge storage unit.

[0034] The shield electrode 12 exerts an electrical effect when a potential is applied to it. Due to this electrical effect, the charge in the region of the photoelectric conversion film 14 directly above the shield electrode 12 is collected by the shield electrode 12. This prevents the situation where a charge that would normally reach the pixel electrode 11 of one pixel 10 reaches the pixel electrode 11 of an adjacent pixel 10. In this way, interference, or crosstalk, of the output signals between adjacent pixels 10 is suppressed.

[0035] The partition wall 17 exerts an optical effect that focuses the light incident on the imaging device 1A. This optical effect prevents light that should be incident on the photoelectric conversion film 14 of one pixel 10 from incident on the photoelectric conversion film 14 of an adjacent pixel 10. In this way, crosstalk is suppressed.

[0036] n pixels 10 contain m pixels 10. m is a natural number between 1 and n, typically between 2 and n.

[0037] In m pixels 10, the partition wall 17 overlaps with the shield electrode 12 in a planar view. Here, "the partition wall 17 overlaps with the shield electrode 12" means that at least a part of the partition wall 17 overlaps with at least a part of the shield electrode 12. This configuration is suitable for improving image quality. Specifically, this configuration suppresses crosstalk while suppressing the decrease in sensitivity caused by using the partition wall 17 and the shield electrode 12 together. In a color imaging device 1A where the packed layer 16 is a color filter, color mixing can be suppressed by suppressing crosstalk.

[0038] Further explanation will be given regarding the suppression of crosstalk in Embodiment 1. In the imaging device 1A of Embodiment 1, the photoelectric conversion unit is provided above the semiconductor substrate (not shown). In the photoelectric conversion unit, a photoelectric conversion film 14 is arranged between the pixel electrode 11 and the counter electrode 13. Light is incident on the photoelectric conversion film 14 from above via the light incident surface of the imaging device 1A, and the charge generated by photoelectric conversion in the photoelectric conversion film 14 is recovered by the pixel electrode 11. An imaging device 1A having the photoelectric conversion unit above the semiconductor substrate is more effective at suppressing crosstalk than an imaging device having a photodiode as the photoelectric conversion unit within the semiconductor substrate. This is because the distance from the light incident surface to the photoelectric conversion unit in the imaging device 1A is shorter. In Embodiment 1, the configuration in which the photoelectric conversion unit is provided above the semiconductor substrate, combined with the use of the partition wall 17 and the shield electrode 12, can exhibit an excellent crosstalk suppression effect. Furthermore, as described above, since the partition wall 17 overlaps with the shield electrode 12 in a plan view, the decrease in sensitivity caused by using the partition wall 17 and the shield electrode 12 together can be suppressed.

[0039] In Figure 1, the array direction Da is the direction in which the pixels 10 are arranged in the pixel array 20. If the pixels 10 are arranged in multiple directions in the pixel array 20, the array direction Da can be one of these multiple directions. In the example shown in Figures 3A to 3C described later, the pixels 10 are arranged in the vertical direction Dv and the horizontal direction Dh in the pixel array 20, and the array direction Da can be either the vertical direction Dv or the horizontal direction Dh. Typically, the vertical direction Dv and the horizontal direction Dh are orthogonal to each other.

[0040] In Embodiment 1, "cross-sectional view" refers to a cross-section parallel to the thickness direction Dt and the arrangement direction Da, and showing the view through the pixel electrode 11, the shield electrode 12, and the partition wall 17. Unless otherwise contradictory, various explanations of the cross-sectional view may be explanations of the same cross-section.

[0041] In Embodiment 1, the thickness direction Dt is the vertical direction. The arrangement direction Da is one direction in the lateral direction.

[0042] In Embodiment 1, the width L1 is the width of the shield electrode 12 in sectional view. The maximum width L2 is the maximum width of the partition wall 17 in sectional view. In the m pixels 10 in Embodiment 1, the width L1 is smaller than the maximum width L2. This is advantageous from the viewpoint of suppressing the sensitivity decrease resulting from the combined use of the partition wall 17 and the shield electrode 12. Specifically, in the m pixels 10, in sectional view, the width L1 is completely within the maximum width L2.

[0043] FIG. 2 is a cross-sectional view showing a dimensional example of the imaging device 1A according to Embodiment 1.

[0044] In FIG. 2, the width L is the width of the pixel 10 in sectional view. In Embodiment 1, as will be described later with reference to FIG. 16, a repeating pattern with the shield electrode 12 of each pixel 10 as a unit pattern can be formed. The width L can be the same as the repeating pitch in sectional view of this repeating pattern.

[0045] The width Lg is the width of the pixel electrode 11 in sectional view.

[0046] As described above, the width L1 is the width of the shield electrode 12 in sectional view. The maximum width L2 is the maximum width of the partition wall 17 in sectional view. In this dimensional example, the maximum width L2 is larger than the width L1.

[0047] The voltage V1 is the potential difference between the potential applied to the shield electrode 12 and the potential applied to the counter electrode 13. In this dimensional example, fixed potentials are applied to the counter electrode 13 and the shield electrode 12.

[0048] The voltage Vg is the potential difference between the saturation potential of the pixel electrode 11 and the potential applied to the counter electrode 13. In the first example, the saturation potential of the pixel electrode 11 takes a value that depends on the upper limit of the amount of light that the photoelectric conversion film 14 can photoelectrically convert. As described above, a circuit provided on the semiconductor substrate is electrically connected to the pixel electrode 11. Although not shown, in the second example, the circuit includes a charge storage section and an overflow transistor. When the charge storage in the charge storage section progresses and the potential of the charge storage section exceeds a predetermined potential, the overflow transistor turns on, and excess charge in the charge storage section is discharged through the overflow transistor. In the second example, the saturation potential of the pixel electrode 11 is the above-mentioned predetermined potential.

[0049] The side end 11e is the side end of the pixel electrode 11 in a cross-sectional view. The side end 12e is the side end of the shield electrode 12 in a cross-sectional view. In the cross-sectional view, the side end 11e and the side end 12e face each other. The intervening position 12x is a position between the side end 11e and the side end 12e in the cross-sectional view and is a position based on the following formula 3.

[0050] The distance a is the distance between the intervening position 12x and the side end 12e in the cross-sectional view and is a distance given by the following formula 3. In this dimensional example, the distance a is zero or more. The distance b is the distance between the side end 11e and the side end 12e in the cross-sectional view.

[0051] In this dimensional example, the following formulas 1 to 7 are satisfied. Specifically, based on formulas 2 and 3, formula 4 is derived. Based on formulas 1 and 4, formula 5 is derived. Based on formulas 2 and 3, formula 6 is derived. Based on formulas 1 and 6, formula 7 is derived.

[0052]

[0053] Satisfying formula 5 and / or formula 7 is advantageous from the viewpoint of suppressing a decrease in sensitivity caused by using the partition wall 17 and the shield electrode 12 in combination.

[0054] Satisfying the following equations 8 and / or 9 may also be advantageous from the viewpoint of suppressing the decrease in sensitivity caused by using the partition wall 17 and shield electrode 12 in combination. Equations 8 and 9 are obtained by setting V1 = Vg in equations 5 and 7.

[0055] In the embodiment, the equations obtained by replacing "voltage Vg" with "voltage Vx" in equations 1 to 9 are also valid. The explanations related to equations 1 to 9 obtained by replacing "voltage Vg" with "voltage Vx" are also valid. Voltage Vx is the potential difference between the potential applied to the counter electrode 13 and a specific potential at the pixel electrode 11. The specific potential is any potential within the range from the initial potential to the saturation potential. The initial potential is the potential of the pixel electrode 11 immediately before reading out the output signal, and is the reset potential. As described above, in the embodiment, a circuit provided on a semiconductor substrate is electrically connected to the pixel electrode 11. The circuit includes a charge storage unit and a reset transistor. The reset transistor resets the potential of the charge storage unit and the pixel electrode 11 by resetting the charge in the charge storage unit. The charge storage unit may be the source or drain of the reset transistor.

[0056] Figures 3A, 3B, and 3C are plan views showing the imaging device 1A according to Embodiment 1.

[0057] Figure 3A shows the pixel electrode 11 and shield electrode 12 in a plan view. In the plan view, the shield electrode 12 has a grid shape. In the plan view, the grid shape of the shield electrode 12 divides a plurality of rectangular regions inside it. In Embodiment 1, a rectangle is a concept that encompasses a square. Specifically, the rectangular region is a square region. In the plan view, rectangular pixel electrodes 11 are arranged within each region. Specifically, the rectangular pixel electrodes 11 are square pixel electrodes 11.

[0058] Figure 3B shows the partition wall 17 in a plan view. In the plan view, the partition wall 17 has a grid shape.

[0059] Figure 3C is a combined view of Figures 3A and 3B, showing the pixel electrode 11, shield electrode 12, and partition wall 17 viewed from below. For m pixels 10, in a plan view, the entire shield electrode 12 is positioned inside the outer edge of the partition wall 17. This is advantageous from the viewpoint of suppressing the decrease in sensitivity caused by using the partition wall 17 and shield electrode 12 together.

[0060] As can be seen from Figures 1 and 3C, in Embodiment 1, in m pixels 10, the center C2 of the width of the partition wall 17 and the center C1 of the width of the shield electrode 12 coincide in a plan view. When m is a natural number of 2 or more and the m pixels 10 are adjacent to each other, this configuration is advantageous from the viewpoint of improving the uniformity of image quality.

[0061] Let's explain the expression, "In a plan view, the center C2 of the width of the partition wall 17 coincides with the center C1 of the width of the shield electrode 12." This expression means that, in a plan view, the difference between the center C2 of the width of the partition wall 17 and the center C1 of the width of the shield electrode 12 is 20% or less of the width of the shield electrode 12. In a plan view, the difference between the center C2 of the width of the partition wall 17 and the center C1 of the width of the shield electrode 12 may be 15% or less, 10% or less, or 5% or less of the width of the shield electrode 12.

[0062] Other embodiments will be described below. In the following, elements common to embodiments and their modifications already described and embodiments and their modifications described later will be denoted by the same reference numerals, and their descriptions may be omitted. The descriptions of each embodiment and its modifications may be mutually applicable, insofar as they do not conflict with technical standards. Insofar as they do not conflict with technical standards, each embodiment and its modifications may be combined with one another.

[0063] (Embodiment 2) Figure 4 is a cross-sectional view showing the imaging device 1B according to Embodiment 2.

[0064] In Embodiment 2, for m pixels 10, the width L1 is greater than the maximum width L2. This configuration suppresses the increase in manufacturing cost of the imaging device 1B caused by the miniaturization of the shield electrode 12. Specifically, for m pixels 10, in a cross-sectional view, the maximum width L2 is completely contained within the width L1.

[0065] Figures 5 and 6 are schematic diagrams illustrating the paths of light and charge in the imaging device 1B according to Embodiment 2.

[0066] As shown in Figures 5 and 6, crosstalk can be suppressed even if the maximum width L2 is smaller than the width L1. To achieve this, for example, a partition wall 17 with high light-gathering ability can be employed. For example, the light-gathering ability can be improved by increasing the height of the partition wall 17. Alternatively, the light-gathering ability can be improved by increasing the difference between the refractive index of the partition wall 17 and the refractive index of the packed layer 16.

[0067] Figures 7A, 7B, and 7C are plan views showing the imaging device 1B according to Embodiment 2.

[0068] Figure 7A shows the pixel electrode 11 and shield electrode 12 in a plan view. Figure 7B shows the partition wall 17 in a plan view. In a plan view, the partition wall 17 has a grid shape. Figure 7C is a combined view of Figures 7A and 7B, showing the pixel electrode 11, shield electrode 12, and partition wall 17 from above. For m pixels 10, in a plan view, the entire partition wall 17 is positioned inward from the outer edge of the shield electrode 12. This configuration makes it possible to suppress the increase in manufacturing cost of the imaging device 1B caused by the miniaturization of the shield electrode 12.

[0069] (Technologies applicable to Embodiments 1 and 2) The technologies applicable to Embodiments 1 and 2 will be described below.

[0070] Figures 8 to 10 are cross-sectional views showing the shape of the partition wall 17 that can be applied in Embodiment 1 and Embodiment 2.

[0071] In the example shown in Figure 8, for m pixels 10, in a cross-sectional view, the length of the lower surface of the partition wall 17 is longer than the length of the upper surface. In a cross-sectional view, the partition wall 17 is trapezoidal. The example in Figure 8 is advantageous in that it exhibits a light-gathering effect on the partition wall 17 by reflecting light off the partition wall 17 and directing it towards the pixel electrode 11. Furthermore, if the packed layer 16 is a color filter, the example in Figure 8 makes it easier to increase the length of light that passes through the color filter. This is advantageous in that it allows the color filter to absorb unwanted light components.

[0072] In the example shown in Figure 9, for m pixels 10, in a cross-sectional view, the length of the lower surface of the partition wall 17 is equal to the length of the upper surface. In a cross-sectional view, the partition wall 17 is rectangular.

[0073] In the example shown in Figure 10, for m pixels 10, in a cross-sectional view, the length of the lower surface of the partition wall 17 is shorter than the length of the upper surface. In a cross-sectional view, the partition wall 17 is trapezoidal.

[0074] The partition wall 17 may have other shapes. For example, the partition wall 17 may have a membrane shape. The partition wall 17 may be a light-shielding film.

[0075] In m pixels 10, the height H2 of the partition wall 17 is, in one example, between 50 nm and 1500 nm, and in one specific example, between 300 nm and 1000 nm. A higher height H2 is advantageous from the viewpoint of allowing the partition wall 17 to exhibit light-gathering ability.

[0076] The aspect ratio H2 / L2 is the ratio of the height H2 to the maximum width L2 of the partition wall 17. For m pixels 10, the aspect ratio H2 / L2 is between 1 and 10 in one example, and between 1.5 and 5 in one specific example. A high aspect ratio H2 / L2 is advantageous from the viewpoint of enabling the partition wall 17 to exhibit light-gathering ability.

[0077] In m pixels 10, the ratio of width L1 to maximum width L2, L1 / L2 (see Figure 1), is between 0.3 and 2 in one example, and between 0.5 and 1.5 in one specific example.

[0078] The overlap width Lo shown in Figure 1 is the length over which the maximum width L2 and width L1 overlap in a cross-sectional view. The overlap ratio Lo / max(L2+L1) is the ratio of the overlap width Lo to the larger of the maximum width L2 and width L1. For m pixels 10, the overlap ratio Lo / max(L2+L1) is between 0.1 and 1 in one example, and between 0.3 and 0.7 in one specific example.

[0079] In a plan view, the partition wall 17 may have a portion that protrudes from the shield electrode 12, and the shield electrode 12 may have a portion that protrudes from the partition wall 17. In this case, a large overlap width Lo is advantageous from the viewpoint of improving sensitivity.

[0080] Figures 11 to 13 are cross-sectional views illustrating the material of the partition wall 17 that may be applied in Embodiment 1 and Embodiment 2.

[0081] In the example shown in Figure 11, the partition wall 17 includes an insulating material. The refractive index of the partition wall 17 is lower than that of the packed layer 16. With this configuration, it is possible to create a light-focusing effect on the partition wall 17 by directing the light toward the pixel electrode 11 through the refraction of light as it travels from the partition wall 17 to the packed layer 16. In one example, the difference between the refractive index of the packed layer 16 and the refractive index of the partition wall 17 is between 0.05 and 1.0, and in another specific example, it is between 0.15 and 0.5.

[0082] In the example shown in Figure 12, the partition wall 17 contains a metal. With this configuration, it is possible to make the partition wall 17 exhibit a light-focusing effect by reflecting light and directing it toward the pixel electrode 11. Aluminum is an example of a metal suitable for such light reflection. Furthermore, with this configuration, by absorbing light at the partition wall 17, it is possible to suppress the situation in which light that should originally be incident on the photoelectric conversion film 14 of one pixel 10 is incident on the photoelectric conversion film 14 of an adjacent pixel 10. Titanium is an example of a metal suitable for such light absorption.

[0083] In the example shown in Figure 13, the partition wall 17 includes a first portion 17a and a second portion 17b. The first portion 17a is located above the second portion 17b. The first portion 17a contains an insulating material. The refractive index of the first portion 17a is lower than that of the packing layer 16. The second portion 17b contains a metal. This configuration allows for the performance of both the configuration shown in Figure 11 and the configuration shown in Figure 12. Furthermore, because the first portion 17a, which contains a non-metallic material, is located above the second portion 17b, which contains a metal, it is easier to avoid the situation where reflected light from the upper surface of the second portion 17b becomes stray light. An example of the material included in the first portion 17a is the material exemplified as the material included in the partition wall 17 in the example shown in Figure 11. An example of the material included in the second portion 17b is the material exemplified as the material included in the partition wall 17 in the example shown in Figure 12.

[0084] It is possible to combine any one shape of partition wall 17 as described above with any one material of partition wall 17 as described above. Partition wall 17 may contain multiple types of insulating materials. Partition wall 17 may contain multiple types of metals. Although not shown in the figures, if partition wall 17 contains metal, there may be an insulating layer covering partition wall 17. The insulating layer can suppress metal corrosion. The thickness of the insulating layer is, for example, about several tens of nanometers.

[0085] The partition wall 17 may have light-shielding properties. An example of a light-shielding partition wall 17 is a light-reflecting partition wall 17 illustrated with reference to Figure 12. Another example of a light-shielding partition wall 17 is a light-absorbing partition wall 17 illustrated with reference to Figure 12. The light-shielding partition wall 17 may contain metal. The partition wall 17 may be transparent. The partition wall 17 may contain a transparent material such as a transparent insulating material.

[0086] Figure 14 is a cross-sectional view showing a pixel via 18 and a shield via 19 that may be applied in Embodiment 1 and Embodiment 2. In this application example, a via refers to a configuration that bundles a via hole and the conductor inside it. The pixel via 18 is electrically connected to a circuit on a semiconductor substrate (not shown). The circuit may include a charge storage unit, an amplification transistor, a reset transistor, an overflow transistor, and the like.

[0087] In the example shown in Figure 14, the pixel via 18 is connected to the pixel electrode 11. The shield via 19 is connected to the shield electrode 12.

[0088] The pixel via 18 includes, for example, a metal. The metal includes, for example, at least one selected from the group consisting of copper, tungsten, and cobalt. An example of the material included in the shield via 19 is the material exemplified for the material included in the pixel via 18. The shield via 19 and the pixel via 18 may include the same material.

[0089] Figures 15 and 16 are plan views showing the arrangement of shield vias 19 that may be applied in Embodiment 1 and Embodiment 2. Note that Figures 15 and 16 are examples, and this disclosure is not limited to these embodiments.

[0090] In the examples shown in Figures 15 and 16, multiple shield vias 19 are connected to the shield electrode 12. The portion of the shield electrode 12 to which the shield vias 19 are connected is thicker in plan view compared to the surrounding area. This configuration can improve robustness against misalignment of the shield vias 19 to the shield electrode 12.

[0091] In the example shown in Figure 15, the shield electrode 12 has a grid shape in plan view. The grid shape of the shield electrode 12 has multiple intersections 12j. The grid shape of the shield electrode 12 also has intervening portions 12k between adjacent intersections 12j. Shield vias 19 are connected to each of the intersections 12j and intervening portions 12k. In the shield electrode 12, the intersections 12j are thicker in plan view than the surrounding area of ​​the intersections 12j. In the shield electrode 12, the intervening portions 12k are thicker in plan view than the surrounding area of ​​the intervening portions 12k.

[0092] In the example of Figure 16, similar to the example of Figure 15, the intersection 12j of the shield electrode 12 is thicker in plan view compared to the surrounding area. A shield via 19 is connected to the intersection 12j. On the other hand, in the example of Figure 16, unlike the example of Figure 15, the width of the intervening portion 12k of the shield electrode 12 is equal to the width of the surrounding area in plan view. A shield via 19 is not connected to the intervening portion 12k. In the example of Figure 16, there is less thickened portion in plan view of the shield electrode 12 compared to the example of Figure 15. This is advantageous from the viewpoint of suppressing the decrease in sensitivity caused by using the partition wall 17 and the shield electrode 12 in combination. Also, thickening the intersection 12j is less likely to cause a decrease in sensitivity compared to thickening the intervening portion 12k. This is because the distance La between the pixel electrode 11 and the intersection portion 12j can be made larger than the distance Lb between the pixel electrode 11 and the intervening portion 12k if the intervening portion 12k were made thicker. In the example in Figure 16, the distance La is √2 times the distance Lb.

[0093] The example in Figure 16 has the following configuration. That is, in the imaging device, a repeating pattern is configured with each of the n pixels 10's shield electrodes 12 as a unit pattern. In a plan view, the n unit patterns divide the imaging device into n polygonal regions 30. In a plan view, for m pixels 10, the shield vias 19 are located at the corners of the polygonal regions 30. "The shield vias 19 are located at the corners of the polygonal regions 30" means that in a plan view, at least a part of the shield vias 19 and at least a part of the corners of the polygonal regions 30 overlap. As can be understood from the above explanation comparing Figure 16 and Figure 15, this configuration is less likely to cause a decrease in sensitivity due to the part of the shield electrode 12 to which the shield vias 19 are connected becoming thicker. The corners of the polygonal regions 30 can correspond to the intersections 12j of the shield electrodes 12. In the example in Figure 16, the polygonal regions 30 are quadrilateral regions.

[0094] Here, the corners of the polygonal region 30 will be explained. The corners of the polygonal region 30 are not just a single point at the tip of the corner of the polygonal region 30, but a concept that includes the area surrounding that tip. The area surrounding the tip of the corner of the polygonal region 30 is, for example, the part within a predetermined distance from that tip. The predetermined distance can be explained as follows, for example. That is, as shown in Figure 16, in a plan view, in one polygonal region 30, the line segment connecting one tip 34 of the polygonal region 30 and the geometric center 37 of the polygonal region 30 is denoted as line segment 35. In a plan view, the part of line segment 35 that overlaps with the shield electrode 12 is denoted as a specific portion 36. With respect to the corner including the tip 34, the predetermined distance is 0.3 times the length of the specific portion 36. The predetermined distances for corners including other tips of the polygonal region 30 can be explained in a similar manner.

[0095] Figures 17 to 21 are plan views showing the configurations of the pixel electrode 11, shield electrode 12, and shield via 19 that may be applied in Embodiment 1 and Embodiment 2. In Figures 17 to 21, the fact that the portion of the shield electrode 12 to which the shield via 19 is connected is thicker in plan view than the surrounding portion is omitted from the illustration. Note that Figures 17 to 21 are examples, and this disclosure is not limited to these embodiments.

[0096] The example in Figure 17 corresponds to the example in Figure 16. In the example in Figure 17, the shield electrode 12 has a grid shape in a plan view. In a plan view, the grid shape of the shield electrode 12 divides the inside into angular rectangular regions. Specifically, these angular rectangular regions are angular square regions. In a plan view, angular rectangular pixel electrodes 11 are arranged within each region. Specifically, these angular rectangular pixel electrodes 11 are angular square pixel electrodes 11.

[0097] In the example shown in Figure 18, in a plan view, the grid shape of the shield electrode 12 divides the inside into rectangular regions with rounded corners. Specifically, these rectangular regions with rounded corners are square regions with rounded corners. In a plan view, octagonal pixel electrodes 11 are arranged within each region. Specifically, these octagonal pixel electrodes 11 are regular octagonal pixel electrodes 11.

[0098] In the example shown in Figure 19, a shield via 19 is connected to at least one of the multiple intersections 12j in the grid shape of the shield electrode 12. On the other hand, a shield via 19 is not connected to at least one other intersection 12j in the grid shape. Specifically, a shield via 19 is connected to a first pair of diagonal corners of the polygonal region 30. A shield via 19 is not connected to a second pair of diagonal corners of the polygonal region 30.

[0099] In the example shown in Figure 20, in a plan view, the shield electrode 12 has a shape in which a part of the grid is interrupted. Specifically, in a plan view, the shield electrode 12 has an interrupted portion between adjacent intersections 12j and intersections 12j.

[0100] In the example shown in Figure 21, one pixel 10 includes a first pixel electrode 11 and a second pixel electrode 11. Specifically, in a plan view, the shield electrode 12 has partitions 12p that divide the area within its grid shape into multiple regions. The first pixel electrode 11 is located in one of the partitioned regions. The second pixel electrode 11 is located in another of the partitioned regions.

[0101] The positional relationship between the partition wall 17 and the shield electrode 12 is not limited to the example described with reference to Figures 1 to 21.

[0102] In Embodiments 1 and 2, in m pixels 10, in a cross-sectional view, one of the width L1 and the maximum width L2 is completely contained within the other. However, in m pixels 10, in a cross-sectional view, the width L1 may have a portion that extends beyond the maximum width L2, and the maximum width L2 may have a portion that extends beyond the width L1.

[0103] In Embodiments 1 and 2, in m pixels 10, in a plan view, the entirety of one of the partition wall 17 and the shield electrode 12 is positioned inward from the outer edge of the other. However, in m pixels 10, in a plan view, the partition wall 17 may have a portion that protrudes from the shield electrode 12, and the shield electrode 12 may have a portion that protrudes from the partition wall 17.

[0104] In Embodiments 1 and 2, the partition wall 17 is in contact with the protective film 15. However, the partition wall 17 may also be in contact with the opposing electrode 13. The protective film 15 is optional.

[0105] In Embodiments 1 and 2, the shield electrode 12 is in contact with the photoelectric conversion film 14. The shield electrode 12 is positioned at the same height as the pixel electrode 11. However, the shield electrode 12 does not have to be in contact with the photoelectric conversion film 14. The shield electrode 12 may be positioned at a different height than the pixel electrode 11. For example, an intervening layer may be provided between the shield electrode 12 and the photoelectric conversion film 14. The intervening layer may be, for example, an insulating film.

[0106] The shapes of the partition wall 17, pixel electrode 11, and shield electrode 12 in a plan view are not limited to the examples described with reference to Figures 1 to 21. For example, the shape of the pixel electrode 11 in a plan view may be L-shaped or trapezoidal. The shapes of the partition wall 17 and shield electrode 12 in a plan view may also be L-shaped.

[0107] In Embodiments 1 and 2, the polygonal region 30 is a quadrilateral region in a plan view. However, the polygonal region 30 may be a region of other shapes. For example, the polygonal region 30 may be a hexagonal region or an octagonal region. In this way, a honeycomb structure can be formed by multiple polygonal regions 30.

[0108] In the configurations of Embodiment 1 and Embodiment 2, the direction in which light enters the imaging device may be downward or in an oblique direction deviating from downward. In either case, the effect of suppressing the decrease in sensitivity caused by using the partition wall 17 and the shield electrode 12 together can be obtained.

[0109] The packed layer 16 does not have to be a color filter. The imaging device may be a monochrome imaging device.

[0110] In Embodiments 1 and 2, positive charges, specifically holes, are used as carriers. However, negative charges, specifically electrons, may also be used as carriers.

[0111] Figure 22 is a plan view showing an example configuration of an imaging device applicable to Embodiment 1 and Embodiment 2.

[0112] In the configuration example shown in Figure 22, the pixel array 20 includes a first region 21 and a second region 22. In a plan view, the second region 22 is located outside the first region 21. Also in a plan view, the second region 22 is located between the edge of the pixel array 20 and the first region 21. Specifically, in a plan view, the second region 22 surrounds the first region 21.

[0113] In the configuration example shown in Figure 22, the natural number m is smaller than the natural number n. Each n-pixel array 10 contains q pixels 10. q is a natural number between 1 and n, typically between 2 and n. The pixel array 20 contains n pixels 10. The first region 21 contains m pixels 10. The second region 22 contains q pixels 10.

[0114] In the q pixels 10, the partition wall 17 is spaced apart from the shield electrode 12 so that, in a plan view, it is located closer to the outer edge of the pixel array 20 than the shield electrode 12. This configuration may be advantageous in terms of improving sensitivity in the second region 22. Specifically, compared to the first region 21, light is more likely to be incident in the second region 22 in an oblique direction, deviating from downward. With this configuration, it is easier to guide the light incident in an oblique direction to the photoelectric conversion film 14 of the pixel 10 to which it is to be received. Adjusting the configuration of the pixels 10 in the second region 22 compared to the pixels 10 in the first region 21 may be called pupil correction.

[0115] (Embodiment 3) The camera system 50 according to Embodiment 3 will be described with reference to Figure 23.

[0116] Figure 23 schematically shows an example of the configuration of a camera system 50 according to Embodiment 3. The camera system 50 comprises a lens optical system 51, an imaging device 52, a system controller 53, and a camera signal processing circuit 54. The camera system 50 may be, for example, a smartphone, a digital camera, a video camera, or an in-vehicle camera.

[0117] The lens optical system 51 may include, for example, a lens group including an autofocus lens and a zoom lens, and an aperture. The lens optical system 51 focuses light onto the imaging surface of the imaging device 52. The imaging device 52 can be broadly used as the imaging device 52, as can be any of the embodiments 1 and 2 described above, or any modifications thereof.

[0118] The system controller 53 controls the entire camera system 50. The system controller 53 is typically a semiconductor integrated circuit, such as a CPU (Central Processing Unit).

[0119] The camera signal processing circuit 54 has the function of processing the output signal from the imaging device 52. The camera signal processing circuit 54 receives output data from the imaging device 52 and performs processing such as gamma correction, color interpolation, spatial interpolation, and auto white balance. The imaging device 52 and the camera signal processing circuit 54 may be implemented as a single semiconductor device. The semiconductor device may be, for example, a so-called SoC (System on a Chip). With such a configuration, the electronic device that includes the imaging device 52 as part can be made smaller. The camera signal processing circuit 54 is, for example, a DSP (Digital Signal Processor).

[0120] (Note) The following technologies are disclosed in this disclosure. The first electrode, second electrode, and third electrode of the following technologies may correspond to the pixel electrode 11, shield electrode 12, and counter electrode 13, respectively. The via of the following technologies may correspond to the shield via 19.

[0121] (Technical 1) An imaging device comprising a plurality of pixels, each of the plurality of pixels comprising: a photoelectric conversion film including a first surface and a second surface facing the first surface, which converts light into electric charge; a first electrode positioned closer to the first surface than the second surface, which collects the electric charge; a second electrode positioned closer to the first surface than the second surface, which does not overlap with the first electrode in a plan view; a third electrode positioned closer to the second surface than the first surface; and a partition wall, wherein the third electrode is located between the photoelectric conversion film and the partition wall, and the plurality of pixels include a first pixel, and in the first pixel, the partition wall overlaps with the second electrode in a plan view.

[0122] (Technical 2) The imaging apparatus according to Technical 1, wherein in the first pixel, in a cross-sectional view, the width of the second electrode is smaller than the maximum width of the partition wall.

[0123] (Technical 3) The imaging apparatus according to Technical 1, wherein in the first pixel, in a cross-sectional view, the width of the second electrode is greater than the maximum width of the partition wall.

[0124] (Technical 4) The imaging apparatus according to Technical 1 or 3, wherein in the first pixel, in the plan view, the entire partition wall is positioned inward from the outer edge of the second electrode.

[0125] (Technical 5) The imaging apparatus according to Technical 1 or 2, wherein in the first pixel, in the plan view, the entire second electrode is positioned inward from the outer edge of the partition wall.

[0126] (Technical 6) The imaging apparatus according to any one of Technical 1 to 5, wherein in the first pixel, in the plan view, the center of the width of the partition wall and the center of the width of the second electrode coincide.

[0127] (Technical 7) In the first pixel, the relationship L1 ≤ {L2(V1 + Vg) - (L - Lg)V1} / Vg is satisfied, where L1 is the width of the second electrode in a cross-sectional view, L2 is the maximum width of the partition in a cross-sectional view, L is the width of the pixel in a cross-sectional view, Lg is the width of the first electrode in a cross-sectional view, Vg is the potential difference between the potential of the first electrode and the potential of the third electrode, and V1 is the potential difference between the potential of the second electrode and the potential of the third electrode, as described in any one of Technical 1 to 6.

[0128] (Technical 8) The imaging apparatus according to any one of Technical 1 to 7, wherein the partition wall has light-shielding properties.

[0129] (Technical 9) The imaging device according to any one of Technical 1 to 8, further comprising vias connected to the second electrode, wherein a repeating pattern is formed with each of the plurality of pixels having the second electrode as a unit pattern, and in a plan view, the unit pattern divides the imaging device into a plurality of polygonal regions, and in the first pixel, the via is located at one corner of the plurality of polygonal regions.

[0130] (Technical 10) The imaging apparatus according to any one of Technical 1 to 9, further comprising a pixel array including a plurality of pixels, wherein the pixel array includes a first region and a second region located between the first region and the outer edge of the pixel array, the plurality of pixels further include a second pixel, the first region includes the first pixel, the second region includes the second pixel, and in the second pixel, in the plan view, the partition wall is located closer to the outer edge than the second electrode and spaced apart from the second electrode.

[0131] (Technical 11) A camera system comprising: an imaging device described in any one of Technical 1 to 10; a lens optical system for focusing light onto the imaging surface of the imaging device; and a camera signal processing circuit for processing the output signal from the imaging device.

[0132] The imaging device of this disclosure can be used in imaging devices for various applications.

[0133] 1A, 1B, 1X, 1Y, 1Z, 52 Imaging device 10, 81, 82, 83 Pixel 11, 91 Pixel electrode 11e, 12e Side edge 12, 92 Shield electrode 12p Partition 13, 93 Opposing electrode 12j Intersection 12k Intervening part 12x Intervening position 14, 94 Photoelectric conversion film 14a First surface 14b Second surface 15, 95 Protective film 16, 96 Packing layer 17, 97 Partition 17a First part 17b Second part 18 Pixel via 19 Shield via 20 Pixel array 21 First region 22 Second region 30 Polygonal region 34 Corner tip 35 Line segment 36 Specific part 37 Geometric center 50 Camera system 51 Lens optical system 53 System controller 54 Camera signal processing circuit 92L, 97L Sensitivity loss region Dt Thickness direction Da Array direction Dv Vertical direction Dh Horizontal direction

Claims

1. An imaging device comprising a plurality of pixels, each of the plurality of pixels comprising: a photoelectric conversion film including a first surface and a second surface facing the first surface, which converts light into electric charge; a first electrode positioned closer to the first surface than the second surface, which collects the electric charge; a second electrode positioned closer to the first surface than the second surface, which does not overlap with the first electrode in a plan view; a third electrode positioned closer to the second surface than the first surface; and a partition wall, wherein the third electrode is located between the photoelectric conversion film and the partition wall, and the plurality of pixels include a first pixel, and in the first pixel, the partition wall overlaps with the second electrode in a plan view.

2. In the first pixel, in a cross-sectional view, the width of the second electrode is smaller than the maximum width of the partition wall, as described in claim 1.

3. In the first pixel, in a cross-sectional view, the width of the second electrode is greater than the maximum width of the partition wall, as described in claim 1.

4. In the first pixel, in the plan view, the entire partition wall is positioned inward from the outer edge of the second electrode, as described in claim 1.

5. In the first pixel, in the plan view, the entire second electrode is positioned inward from the outer edge of the partition wall, as described in claim 1.

6. In the first pixel, in the plan view, the center of the width of the partition wall and the center of the width of the second electrode coincide, the imaging apparatus according to claim 1.

7. In the first pixel, the relationship L1 ≤ {L2(V1 + Vg) - (L - Lg)V1} / Vg is satisfied, where L1 is the width of the second electrode in a cross-sectional view, L2 is the maximum width of the partition in a cross-sectional view, L is the width of the first pixel in a cross-sectional view, Lg is the width of the first electrode in a cross-sectional view, Vg is the potential difference between the potential of the first electrode and the potential of the third electrode, and V1 is the potential difference between the potential of the second electrode and the potential of the third electrode, as described in claim 1.

8. The imaging apparatus according to claim 1, wherein the partition wall has light-shielding properties.

9. The imaging device according to claim 1, further comprising vias connected to the second electrode, wherein a repeating pattern is formed with each of the plurality of pixels having the second electrode as a unit pattern, and in a plan view, the unit pattern divides the imaging device into a plurality of polygonal regions, and in the first pixel, the via is located at one corner of the plurality of polygonal regions.

Images