Semiconductor integrated circuit device

Abstract

An inverter cell (C1) is provided with: an active region (2P1) formed in a lower part of the cell; an active region (2N1) formed in an upper part of the cell; a first input terminal made of first wiring formed in a rear wiring layer; and a second input terminal made of second wiring formed in a metal wiring layer.

Description

Semiconductor integrated circuit device

[0001] The present disclosure relates to a semiconductor integrated circuit device including a standard cell (hereinafter, also simply referred to as a cell for convenience) including a CFET (Complementary FET).

[0002] As a method of forming a semiconductor integrated circuit on a semiconductor substrate, a standard cell method is known. The standard cell method is a method of designing an LSI chip by preparing basic units (for example, inverters, latches, flip - flops, full - adders, etc.) having specific logic functions in advance as standard cells, arranging a plurality of standard cells on a semiconductor substrate, and connecting these standard cells with wiring.

[0003] In addition, transistors, which are basic components of LSIs, have achieved improved integration density, reduced operating voltage, and improved operating speed by reducing the gate length (scaling). However, in recent years, the off - current due to excessive scaling and the resulting significant increase in power consumption have become problems. To solve this problem, three - dimensional structure transistors in which the transistor structure is changed from the conventional planar type to a three - dimensional type have been actively studied. Among them, nanosheet FETs have attracted attention as one type of three - dimensional structure transistors.

[0004] Patent Document 1 discloses a semiconductor integrated circuit device using a CFET (Complementary FET) in which a P - type nanosheet transistor and an N - type nanosheet transistor are stacked on a substrate for miniaturization of the semiconductor integrated circuit device. In Patent Document 1, a standard cell having input / output terminals provided on the surface wiring layer side of the transistor and a standard cell having input / output terminals provided on the back - side wiring layer side of the transistor are provided, and the input / output terminals are connected by wiring between these standard cells.

[0005] U.S. Patent Application Publication No. 2022 / 0344255

[0006] However, the technology described in Patent Document 1 requires the provision of standard cells with input / output terminals on the surface wiring layer side of the transistor and standard cells with input / output terminals on the back wiring layer side of the transistor, and then the replacement of these as needed before performing inter-cell wiring, which makes the design difficult. Furthermore, since it is not possible to connect the wiring on the back wiring layer side and the surface wiring layer side to standard cells with input / output terminals on the surface wiring layer side and the back wiring layer side, respectively, the degree of design freedom is reduced.

[0007] This disclosure aims to provide a semiconductor integrated circuit device layout that facilitates design while improving design flexibility for standard cells using CFETs.

[0008] A first aspect of the present disclosure provides a semiconductor integrated circuit apparatus comprising a plurality of standard cells, including a first standard cell, wherein the first standard cell constitutes the channel, source, and drain of a first transistor of a first conductivity type, and the channel comprises a first active region including a first nanosheet extending in a first direction, and a second active region comprising a second transistor of a second conductivity type having a different conductivity type from the first, formed above the first active region in the depth direction and overlapping with the first active region in a plan view, and the channel comprises a second active region including a second nanosheet extending in the first direction, and a first input terminal comprising a first wiring formed in a back wiring layer below the first transistor in the depth direction, to which a first input signal is input, and a second input terminal comprising a second wiring formed in a metal wiring layer above the first transistor in the depth direction, to which the first input signal is input.

[0009] According to this disclosure, the first standard cell has wiring that constitutes the input terminals formed in the back wiring layer and the metal wiring layer. As a result, the wiring formed in the back wiring layer and the wiring formed in the metal wiring layer can be connected to the input terminals of the first standard cell, thereby facilitating the design of semiconductor integrated circuit devices while improving design flexibility.

[0010] A second aspect of the present disclosure provides a semiconductor integrated circuit apparatus comprising a plurality of standard cells, including a first standard cell, wherein the first standard cell constitutes the channel, source, and drain of a first transistor of a first conductivity type, and the channel comprises a first active region including a first nanosheet extending in a first direction, and a second active region comprising the channel, source, and drain of a second transistor of a second conductivity type having a different conductivity type from the first, formed above the first active region in the depth direction and overlapping with the first active region in a plan view, and the channel comprises a second active region including a second nanosheet extending in the first direction, and a first output terminal comprising a first wiring formed in a back wiring layer below the first transistor in the depth direction, to which a first output signal is output, and a second output terminal comprising a second wiring formed in a metal wiring layer above the first transistor in the depth direction, to which the first output signal is output.

[0011] According to this disclosure, the first standard cell has wiring that constitutes the output terminals formed in the back wiring layer and the metal wiring layer. As a result, the wiring formed in the back wiring layer and the wiring formed in the metal wiring layer can be connected to the output terminals of the first standard cell, thereby simplifying the design of semiconductor integrated circuit devices and improving design flexibility.

[0012] According to this disclosure, a standard cell using a CFET can be designed to facilitate the design of semiconductor integrated circuit devices while improving design flexibility.

[0013] A plan view showing an example of the layout structure of an inverter cell according to the embodiment. A cross-sectional view of the inverter cell in Figure 1. A circuit diagram of the inverter cell. A plan view showing another example of the layout structure of an inverter cell according to the embodiment. A plan view showing another example of the layout structure of an inverter cell according to the embodiment. A plan view showing the layout structure of a two-input NAND cell according to the embodiment. Circuit diagrams of a two-input NAND cell and a two-input NOR cell. A plan view showing another example of the layout structure of a two-input NAND cell according to the embodiment. A plan view showing another example of the layout structure of a two-input NAND cell according to the embodiment. A plan view showing the layout structure of a two-input NOR cell according to the embodiment. A plan view showing an example of the layout of a circuit block included in a semiconductor integrated circuit device according to the embodiment. A plan view showing an example of the layout of a circuit block included in a semiconductor integrated circuit device according to the embodiment.

[0014] The embodiments will be described below with reference to the drawings. In the following embodiments, the semiconductor integrated circuit device comprises a plurality of standard cells. At least some of these standard cells are equipped with nanosheet FETs, and furthermore, they are equipped with a CFET structure in which transistors with different conductivity types (in this embodiment, the lower part of the cell is P-conducting and the upper part of the cell is N-conducting) are stacked.

[0015] Furthermore, in this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. Also, in this specification, expressions meaning that widths, etc., are the same, such as "same wiring width," include a range of manufacturing variations.

[0016] (Configuration of the inverter cell) Figure 1 is a plan view showing an example of the layout structure of the inverter cell according to the embodiment, Figure 2 is a cross-sectional view showing an example of the layout structure of the inverter cell according to the embodiment, and Figure 3 is a circuit diagram configured in the inverter cell according to the embodiment. Specifically, Figure 1(a) shows the lower part of the inverter cell C1, Figure 1(b) shows the upper part of the inverter cell C1, Figure 2(a) is a cross-section of X1-X1' in Figures 1(a) and (b), Figure 2(b) is a cross-section of Y1-Y1' in Figures 1(a) and (b), and Figure 2(c) is a cross-section of Y2-Y2' in Figures 1(a) and (b).

[0017] Furthermore, in the following explanation, the dashed lines running vertically and horizontally in plan views such as Figure 1, and the dashed lines running vertically in cross-sectional views such as Figure 2, indicate a grid used for arranging components during the design phase. The grid is arranged at equal intervals in the X direction and at equal intervals in the Y direction. Note that the grid spacing may be the same or different in the X and Y directions. Also, the grid spacing may differ from layer to layer. Moreover, each component does not necessarily have to be placed on the grid.

[0018] Furthermore, in plan views such as Figure 1, the solid lines surrounding the cells indicate the cell frame (outer edge of the standard cell) of the standard cell. Standard cells are arranged so that their cell frames touch the cell frames of adjacent cells in the X or Y direction.

[0019] As shown in Figure 3, the inverter cell C1 has transistors P1 and N1, and an inverter circuit with input A and output Y is configured.

[0020] As shown in Figure 1(a), a BM0 wiring layer, which is a wiring layer, is formed on the back of the semiconductor chip on which the transistor is formed. Power supply wiring 11 and wirings 12 and 13 extending in the X direction are formed on the BM0 wiring layer. Power supply wiring 11 supplies the power supply voltage VDD. Wiring 12 corresponds to input A, and wiring 13 corresponds to output Y.

[0021] The power supply wiring 11 is formed in the center of the cell in the Y direction. In a plan view, the power supply wiring 11 overlaps with the active region 2P1. The power supply wiring 11 is connected to the source portion of transistor P1 in the active region 2P1 via via 61 and local interconnect (LI) 41.

[0022] The wiring 12 is located on the lower side of the diagram in the Y direction. The wiring 12 is connected to the gate wiring 31 via via 62.

[0023] Wiring 13 is positioned on the upper side of the drawing in the Y direction. Wiring 13 is connected via vias 63, 64 and local wirings 42, 44 to the drain portion of transistor P1 in the active region 2P1 and to the drain portion of transistor N1 in the active region 2N1.

[0024] In the P-type transistor region at the bottom of the cell, active regions constituting the channel, source, and drain of the P-type transistor are formed. Specifically, an active region 2P1 is formed in the P-type transistor region. In a plan view, the active region 2P1 overlaps with the power supply wiring 11.

[0025] A P-type transistor P1 is formed in the P-type transistor region. Transistor P1, as a channel, consists of three overlapping sheet structures in a planar view and has a nanosheet 21 extending in the X direction.

[0026] As shown in Figure 1(b), the active regions constituting the channel, source, and drain of the N-type transistor are formed in the N-type transistor region at the top of the cell. Specifically, an active region 2N1 is formed in the N-type transistor region. Active region 2N1 is located above active region 2P1 in the Z direction. Active region 2N1 overlaps with active region 2P1 in a plan view.

[0027] An N-type transistor N1 is formed in the N-type transistor region. Transistor N1 has a channel consisting of three overlapping sheet structures in a planar view and a nanosheet 22 extending in the X direction.

[0028] Regarding the active region, the source and drain portions on both sides of the nanosheet are formed, for example, by epitaxial growth from the nanosheet.

[0029] In the X-direction of the cell, a gate wiring 31 is formed in the center of the diagram, extending in the Y-direction and extending in the Z-direction from the top to the bottom of the cell. The nanosheets 21 and 22 overlap with the gate wiring 31 in a plan view. The gate wiring 31 corresponds to the gates of transistors P1 and N1.

[0030] Dummy gate wiring 32 and 33 are formed on the cell frames on both sides in the X direction, extending in the Y and Z directions. Dummy gate wiring 32 is shared with other cells located on the left side of the drawing. Dummy gate wiring 33 is shared with other cells located on the right side of the drawing.

[0031] As shown in Figure 1(a), local wirings 41 and 42 extending in the Y direction are formed at the bottom of the cell. Local wiring 41 is connected to the source portion of transistor P1 in the active region 2P1. Local wiring 42 is connected to the drain portion of transistor P1 in the active region 2P1.

[0032] As shown in Figure 1(b), local wirings 43 and 44 extending in the Y direction are formed on the upper part of the cell. Local wiring 43 is connected to the source portion of transistor N1 in the active region 2N1. Local wiring 44 is connected to the drain portion of transistor N1 in the active region 2N1.

[0033] In the M0 wiring layer, which is a metal wiring layer located above the active region 2N1, power supply wiring 51 and wirings 52 and 53 extending in the X direction are formed. Power supply wiring 51 supplies the power supply voltage VSS. Wiring 52 corresponds to input A, and wiring 53 corresponds to output Y.

[0034] The power supply wiring 51 is formed in the center of the cell in the Y direction. In a plan view, the power supply wiring 51 overlaps with the power supply wiring 11 and the active region 2N1. The power supply wiring 51 is connected to the source portion of transistor N1 in the active region 2N1 via via 65 and local wiring 43.

[0035] Wiring 52 is located on the lower side of the drawing in the Y direction. In a plan view, wiring 52 overlaps with wiring 12. Wiring 52 is connected to gate wiring 31 via via 66.

[0036] Wiring 53 is located on the upper side of the drawing in the Y direction. In a plan view, wiring 53 overlaps with wiring 13. Wiring 53 is connected via vias 64, 67 and local wirings 42, 44 to the drain portion of transistor P1 in the active region 2P1 and to the drain portion of transistor N1 in the active region 2N1.

[0037] With the above configuration, the inverter cell C1 has wiring 12 corresponding to input A and wiring 13 corresponding to output Y formed in the BM0 wiring layer, and wiring 52 corresponding to input A and wiring 53 corresponding to output Y formed in the M0 wiring layer. In other words, the inverter cell C1 has wiring that constitutes the input terminal (input A) and wiring that constitutes the output terminal (output Y) formed in both the M0 wiring layer and the BM0 wiring layer. As a result, wiring formed in the back wiring layer such as the BM0 wiring layer and wiring formed in the metal wiring layer such as the M0 wiring layer can be connected to the input terminal and output terminal of the inverter cell C1, thereby simplifying the design of semiconductor integrated circuit devices and improving design flexibility.

[0038] Furthermore, wirings 12 and 52 overlap in a plan view. Wirings 13 and 53 overlap in a plan view. That is, the wiring that constitutes the input terminal (input A) formed in the BM0 wiring layer and the M0 wiring layer overlaps in a plan view. The wiring that constitutes the output terminal (output Y) formed in the BM0 wiring layer and the M0 wiring layer overlaps in a plan view. This reduces the difference in characteristics between when the input signal is input from the rear wiring layer side and when it is input from the metal wiring layer side, and also reduces the difference in characteristics between when the output signal is output from the rear wiring layer side and when it is output from the metal wiring layer side.

[0039] (Modification of Inverter Cell 1) Figure 4 is a plan view showing another example of the layout structure of the inverter cell according to the embodiment. Specifically, Figure 4(a) shows the lower part of the inverter cell C2, and Figure 4(b) shows the upper part of the inverter cell C2. In Figure 4, the positions of wiring 52 and 53 in the M0 wiring layer are swapped compared to Figure 1.

[0040] As shown in Figure 4(b), wiring 52 is located on the upper side of the drawing in the Y direction. Wiring 53 is located on the lower side of the drawing in the Y direction. Wiring 52 overlaps with wiring 13 in a plan view. Wiring 53 overlaps with wiring 12 in a plan view. That is, in the inverter cell C2 of Figure 4, wiring 12, which constitutes the input terminal (input A) formed in the BM0 wiring layer, and wiring 53, which constitutes the output terminal (output Y) formed in the M0 wiring layer, overlap in a plan view. Wiring 13, which constitutes the output terminal (output Y) formed in the BM0 wiring layer, and wiring 52, which constitutes the input terminal (input A) formed in the M0 wiring layer, overlap in a plan view.

[0041] The configuration shown in Figure 4 can achieve the same effect as shown in Figure 1.

[0042] (Modified Inverter Cell 2) Figures 5(a) and 5(b) are plan views showing other examples of the layout structure of the inverter cell according to the embodiment. Specifically, Figure 5(a) shows the lower part of the inverter cell C3, and Figure 5(b) shows the upper part of the inverter cell C3. Compared to Figure 1, the wiring 52 in the M0 wiring layer is omitted in Figures 5(a) and 5(b).

[0043] In the inverter cell C3 shown in Figure 5, wiring 13 and 53 corresponding to output Y are formed in the BM0 wiring layer and the M0 wiring layer, respectively. That is, in the inverter cell C3, wiring constituting the output terminal (output Y) is formed in both the M0 wiring layer and the BM0 wiring layer. As a result, wiring formed in back wiring layers such as the BM0 wiring layer, and wiring formed in metal wiring layers such as the M0 wiring layer, can be connected to the output terminal of the inverter cell C3, thereby simplifying the design of semiconductor integrated circuit devices while improving design flexibility.

[0044] Further, the wirings 13 and 53 overlap in a plan view. That is, the wirings forming the output terminal (output Y) formed in the BM0 wiring layer and the M0 wiring layer overlap in a plan view. Thereby, the difference in characteristics between the case where the output signal is output from the back wiring layer side and the case where it is output from the metal wiring layer side can be reduced.

[0045] Further, the wiring forming the input terminal (input A) is only the wiring 12 in the BM0 wiring layer. Thereby, since the load of the input terminal of the inverter cell C3 can be reduced, the semiconductor integrated circuit device can be made faster.

[0046] Note that in FIGS. 5(a) and 5(b), instead of the wiring 52, the wiring 12 in the BM0 wiring layer may be omitted.

[0047] (Modified Example 3 of Inverter Cell) FIGS. 5(c) and 5(d) are plan views showing another example of the layout structure of the inverter cell according to the embodiment. Specifically, FIG. 5(c) shows the lower part of the cell of the inverter cell C4, and FIG. 5(d) shows the upper part of the cell of the inverter cell C4. In FIGS. 5(c) and 5(d), compared with FIG. 1, the wiring 53 in the M0 wiring layer is omitted.

[0048] In the inverter cell C4 of FIG. 5, the wirings 12 and 52 corresponding to the input A are formed in the BM0 wiring layer and the M0 wiring layer, respectively. That is, in the inverter cell C4, the wiring forming the input terminal (input A) is formed in both the M0 wiring layer and the BM0 wiring layer. Thereby, since the wiring formed in the back wiring layer such as the BM0 wiring layer and the wiring formed in the metal wiring layer such as the M0 wiring layer can be connected to the input terminal of the inverter cell C4, the design freedom in the semiconductor integrated circuit device can be improved.

[0049] Further, the wirings 12 and 52 overlap in a plan view. That is, the wirings forming the input terminal (input A) formed in the BM0 wiring layer and the M0 wiring layer overlap in a plan view. Thereby, the difference in characteristics between the case where the input signal is input from the back wiring layer side and the case where it is input from the metal wiring layer side can be reduced.

[0050] Furthermore, the wiring constituting the output terminal (output Y) consists only of the wiring 13 of the BM0 wiring layer. This reduces the load on the output terminal of the inverter cell C4, thereby enabling higher speeds for the semiconductor integrated circuit device.

[0051] Note that in Figures 5(c) and 5(d), the wiring 13 in the BM0 wiring layer may be omitted instead of the wiring 53.

[0052] (Configuration of a 2-input NAND cell) Figure 6 is a plan view showing the layout structure of a 2-input NAND cell according to this embodiment, and Figure 7(a) is a circuit diagram of the 2-input NAND cell. Specifically, Figure 6(a) shows the lower part of the 2-input NAND cell C5, and Figure 6(b) shows the upper part of the 2-input NAND cell C5.

[0053] As shown in Figure 6(a), power supply wiring 111 and wirings 112-114 extending in the X direction are formed on the BM0 wiring layer. Power supply wiring 111 supplies the power supply voltage VDD. Wiring 112 corresponds to input A, wiring 113 corresponds to input B, and wiring 114 corresponds to output Y.

[0054] The power supply wiring 111 is formed in the center of the cell in the Y direction. In plan view, the power supply wiring 111 overlaps with the active region 2P2. The power supply wiring 111 is connected to the source portion of transistor P11 in the active region 2P2 via via 161 and local wiring 141. The power supply wiring 111 is connected to the source portion of transistor P12 in the active region 2P2 via via 162 and local wiring 143.

[0055] The wiring 112 is located in the lower left of the drawing in the Y direction. The wiring 112 is connected to the gate wiring 131 via via 163.

[0056] The wiring 113 is located in the lower right of the drawing in the Y direction. The wiring 113 is connected to the gate wiring 132 via via 164.

[0057] Wiring 114 is located on the upper side of the drawing in the Y direction. Wiring 114 is connected via vias 165, 166, 170, local wires 142, 146, and 154 to the drain portion of transistor P11 in the active region 2P2, the drain portion of transistor P12 in the active region 2P2, and the drain portion of transistor N12 in the active region 2N2.

[0058] An active region 2P2 is formed in the P-type transistor region. In a plan view, the active region 2P2 overlaps with the power supply wiring 111.

[0059] Transistors P11 and P12 are formed in the active region 2P2. Transistors P11 and P12 each have nanosheets 121 and 122 extending in the X direction.

[0060] As shown in Figure 6(b), an active region 2N2 is formed in the N-type transistor region. The active region 2N2 is located above the active region 2P2 in the Z direction. The active region 2N2 overlaps with the active region 2P2 in a plan view.

[0061] Transistors N11 and N12 are formed in the active region 2N2. Transistors N11 and N12 each have nanosheets 123 and 124 extending in the X direction.

[0062] Gate wirings 131 and 132 are formed, extending in the Y and Z directions. Nanosheets 121 and 123 overlap with gate wiring 131 in a plan view. Nanosheets 122 and 124 overlap with gate wiring 132 in a plan view. Gate wiring 131 corresponds to the gates of transistors P11 and N11. Gate wiring 132 corresponds to the gates of transistors P12 and N12.

[0063] As shown in Figure 6(a), local wirings 141 to 143 extending in the Y direction are formed at the bottom of the cell. Local wiring 141 is connected to the source portion of transistor P11 in the active region 2P2. Local wiring 142 is connected to the drain portions of transistor P11 and transistor P12 in the active region 2P2. Local wiring 143 is connected to the source portion of transistor P12 in the active region 2P2.

[0064] As shown in Figure 6(b), local wirings 144 to 146 extending in the Y direction are formed on the upper part of the cell. Local wiring 144 is connected to the source portion of transistor N11 in the active region 2N2. Local wiring 145 is connected to the drain portion of transistor N11 and the source portion of transistor N12 in the active region 2N2. Local wiring 146 is connected to the drain portion of transistor N12 in the active region 2N2.

[0065] The M0 wiring layer has power supply wiring 151 and wirings 152-154 extending in the X direction. Power supply wiring 151 supplies the power supply voltage VSS. Wiring 152 corresponds to input A, wiring 153 corresponds to input B, and wiring 154 corresponds to output Y.

[0066] The power supply wiring 151 is formed in the center of the cell in the Y direction. In a plan view, the power supply wiring 151 overlaps with the power supply wiring 111 and the active region 2N2. The power supply wiring 151 is connected to the source portion of transistor N11 in the active region 2N2 via via 167 and local wiring 144.

[0067] Wiring 152 is located in the lower left of the drawing in the Y direction. In a plan view, wiring 152 overlaps with wiring 112. Wiring 152 is connected to gate wiring 131 via via 168.

[0068] Wiring 153 is located in the lower right of the drawing in the Y direction. In a plan view, wiring 153 overlaps with wiring 113. Wiring 153 is connected to gate wiring 132 via via 169.

[0069] Wiring 154 is located on the upper side of the drawing in the Y direction. In a plan view, wiring 154 overlaps with wiring 114. Wiring 154 is connected via vias 166, 170 and local wirings 142, 146 to the drain portion of transistor P11 in active region 2P2, the drain portion of transistor P12 in active region 2P2, and the drain portion of transistor N12 in active region 2N2.

[0070] With the above configuration, the two-input NAND cell C5 has wiring 112 corresponding to input A, wiring 113 corresponding to input B, and wiring 114 corresponding to output Y formed on the BM0 wiring layer, and wiring 152 corresponding to input A, wiring 153 corresponding to input B, and wiring 154 corresponding to output Y formed on the M0 wiring layer. In other words, the two-input NAND cell C5 has wiring that constitutes the input terminals (inputs A and B) and wiring that constitutes the output terminal (output Y) formed on both the M0 wiring layer and the BM0 wiring layer. As a result, wiring formed on back wiring layers such as the BM0 wiring layer and wiring formed on metal wiring layers such as the M0 wiring layer can be connected to the input and output terminals of the two-input NAND cell C5, thereby simplifying the design of semiconductor integrated circuit devices while improving design flexibility.

[0071] Furthermore, wirings 112 and 152 overlap in a plan view. Wirings 113 and 153 overlap in a plan view. Wirings 114 and 154 overlap in a plan view. In other words, the wirings that constitute the input terminals (inputs A and B) formed in the BM0 wiring layer and the M0 wiring layer overlap in a plan view. The wirings that constitute the output terminal (output Y) formed in the BM0 wiring layer and the M0 wiring layer overlap in a plan view. This reduces the difference in characteristics between when the input signal is input from the rear wiring layer side and when it is output from the metal wiring layer side, and also reduces the difference in characteristics between when the output signal is output from the rear wiring layer side and when it is output from the metal wiring layer side.

[0072] (Modification 1 of the 2-input NAND cell) Figure 8 is a plan view showing another example of the layout structure of the 2-input NAND cell according to the embodiment. Specifically, Figure 8(a) shows the lower part of the 2-input NAND cell C6, and Figure 8(b) shows the upper part of the 2-input NAND cell C6. In Figure 8, the positions of wirings 112, 113 and wiring 114 in the BM0 wiring layer are swapped compared to Figure 6.

[0073] As shown in Figure 8(b), wirings 112 and 113 are located on the upper side of the drawing in the Y direction. Wiring 114 is located on the lower side of the drawing in the Y direction. Wirings 112 and 113 overlap with wiring 154 in a plan view. Wiring 114 overlaps with wirings 152 and 153 in a plan view. That is, in the 2-input NAND cell C6 of Figure 8, wirings 112 and 113, which constitute the input terminals (inputs A and B) formed in the BM0 wiring layer, and wiring 154, which constitutes the output terminal (output Y) formed in the M0 wiring layer, overlap in a plan view. Wiring 114, which constitutes the output terminal (output Y) formed in the BM0 wiring layer, and wirings 152 and 153, which constitute the input terminals (inputs A and B) formed in the M0 wiring layer, overlap in a plan view.

[0074] The configuration shown in Figure 8 can achieve the same effect as shown in Figure 6.

[0075] (Modification 2 of the 2-input NAND cell) Figures 9(a) and 9(b) are plan views showing other examples of the layout structure of the 2-input NAND cell according to the embodiment. Specifically, Figure 9(a) shows the lower part of the 2-input NAND cell C7, and Figure 9(b) shows the upper part of the 2-input NAND cell C7. Compared with Figure 6, in Figures 9(a) and 9(b), wiring 112 in the BM0 wiring layer and wiring 153 in the M0 wiring layer are omitted.

[0076] In the two-input NAND cell C7 shown in Figure 9, wirings 114 and 154 corresponding to output Y are formed in the BM0 wiring layer and the M0 wiring layer, respectively. That is, in the two-input NAND cell C7, wiring constituting the output terminal (output Y) is formed in both the M0 wiring layer and the BM0 wiring layer. As a result, wiring formed in back wiring layers such as the BM0 wiring layer, and wiring formed in metal wiring layers such as the M0 wiring layer, can be connected to the output terminal of the two-input NAND cell C7, thereby simplifying the design of semiconductor integrated circuit devices while improving design flexibility.

[0077] Furthermore, wirings 114 and 154 overlap in a plan view. That is, the wirings forming the output terminal (output Y) on the BM0 wiring layer and the M0 wiring layer overlap in a plan view. This reduces the difference in characteristics between when the output signal is output from the back wiring layer side and when it is output from the metal wiring layer side.

[0078] Furthermore, the wiring constituting the input terminal (input A) consists only of wiring 152 in the M0 wiring layer, and the wiring constituting the input terminal (input B) consists only of wiring 113 in the BM0 wiring layer. This reduces the load on the input terminals of the two-input NAND cell C7, thereby enabling higher speeds for the semiconductor integrated circuit device.

[0079] In Figure 6, it is also possible to omit only one of the wirings 112 and 113 of the BM0 wiring layer and the wirings 152 and 153 of the M0 wiring layer. Alternatively, in Figure 6, it is also possible to omit only wirings 112 and 113, or only wirings 152 and 153, or only wirings 113 and 152.

[0080] (Modification 3 of the 2-input NAND cell) Figures 9(c) and 9(d) are plan views showing other examples of the layout structure of the 2-input NAND cell according to the embodiment. Specifically, Figure 9(c) shows the lower part of the 2-input NAND cell C8, and Figure 9(d) shows the upper part of the 2-input NAND cell C8. Compared with Figure 6, the wiring 154 in the M0 wiring layer is omitted in Figures 9(c) and 9(d).

[0081] In the two-input NAND cell C8 shown in Figure 9, wirings 112 and 152 corresponding to input A are formed in the BM0 wiring layer and the M0 wiring layer, respectively, and wirings 113 and 153 corresponding to input B are formed in the BM0 wiring layer and the M0 wiring layer, respectively. In other words, in the two-input NAND cell C8, wiring constituting the input terminals (inputs A and B) is formed in both the M0 wiring layer and the BM0 wiring layer. This allows wiring formed in back wiring layers such as the BM0 wiring layer, and wiring formed in metal wiring layers such as the M0 wiring layer, to be connected to the input terminals of the two-input NAND cell C8, thereby improving the design flexibility of semiconductor integrated circuit devices.

[0082] Furthermore, wirings 112 and 152 overlap in a plan view. Wirings 113 and 153 also overlap in a plan view. In other words, the wirings forming the input terminals (inputs A and B) on the BM0 wiring layer and M0 wiring layer overlap in a plan view. This reduces the difference in characteristics between when the input signal is input from the rear wiring layer side and when it is input from the metal wiring layer side.

[0083] Furthermore, the wiring constituting the output terminal (output Y) consists only of the wiring 114 of the BM0 wiring layer. This reduces the load on the output terminal of the 2-input NAND cell C8, thereby enabling higher speeds for the semiconductor integrated circuit device.

[0084] In addition, in Figures 9(c) and 9(d), wiring 114 in the BM0 wiring layer may be omitted instead of wiring 154.

[0085] (Configuration of a 2-input NOR cell) Figure 10 is a plan view showing the layout structure of a 2-input NOR cell according to the embodiment, and Figure 7(b) is a circuit diagram of the 2-input NOR cell. Specifically, Figure 10(a) shows the lower part of the 2-input NOR cell C9, and Figure 10(b) shows the upper part of the 2-input NOR cell C9.

[0086] As shown in Figure 10(a), power supply wiring 211 and wirings 212-214 extending in the X direction are formed on the BM0 wiring layer. Power supply wiring 211 supplies the power supply voltage VDD. Wiring 212 corresponds to input A, wiring 213 corresponds to input B, and wiring 214 corresponds to output Y.

[0087] The power supply wiring 211 is formed in the center of the cell in the Y direction. In plan view, the power supply wiring 211 overlaps with the active region 2P3. The power supply wiring 211 is connected to the source portion of transistor P21 in the active region 2P3 via via 261 and local wiring 241.

[0088] The wiring 212 is located in the lower left of the drawing in the Y direction. The wiring 212 is connected to the gate wiring 231 via via 262.

[0089] The wiring 213 is located in the lower right of the drawing in the Y direction. The wiring 213 is connected to the gate wiring 232 via via 263.

[0090] Wiring 214 is positioned on the upper side of the drawing in the Y direction. Wiring 214 is connected via vias 264, 265, 270, local wires 243, 245, and 254 to the drain portion of transistor P22 in the active region 2P3, the drain portion of transistor N21 in the active region 2N3, and the drain portion of transistor N22 in the active region 2N3.

[0091] An active region 2P3 is formed in the P-type transistor region. In a plan view, the active region 2P3 overlaps with the power supply wiring 211.

[0092] In the active region 2P3, transistors P21 and P22 are formed. Transistors P21 and P22 each have nanosheets 221 and 222 that extend in the X direction.

[0093] As shown in Figure 10(b), an active region 2N3 is formed in the N-type transistor region. The active region 2N3 is located above the active region 2P3 in the Z direction. The active region 2N3 overlaps with the active region 2P3 in a plan view.

[0094] Transistors N21 and N22 are formed in the active region 2N3. Transistors N21 and N22 each have nanosheets 223 and 224 extending in the X direction.

[0095] Gate wirings 231 and 232 are formed extending in the Y and Z directions. Nanosheets 221 and 223 overlap with gate wiring 231 in a plan view. Nanosheets 222 and 224 overlap with gate wiring 232 in a plan view. Gate wiring 231 corresponds to the gates of transistors P21 and N21. Gate wiring 232 corresponds to the gates of transistors P22 and N22.

[0096] As shown in Figure 10(a), local wirings 241 to 243 extending in the Y direction are formed at the bottom of the cell. Local wiring 241 is connected to the source portion of transistor P21 in the active region 2P3. Local wiring 242 is connected to the drain portion of transistor P21 and the source portion of transistor P22 in the active region 2P3. Local wiring 243 is connected to the drain portion of transistor P22 in the active region 2P3.

[0097] As shown in Figure 10(b), local wirings 244 to 246 extending in the Y direction are formed on the upper part of the cell. Local wiring 244 is connected to the source portion of transistor N21 in the active region 2N3. Local wiring 245 is connected to the drain portions of transistor N21 and transistor N22 in the active region 2N3. Local wiring 246 is connected to the source portion of transistor N22 in the active region 2N3.

[0098] The M0 wiring layer has power supply wiring 251 and wirings 252-254 extending in the X direction. Power supply wiring 251 supplies the power supply voltage VSS. Wiring 252 corresponds to input A, wiring 253 corresponds to input B, and wiring 254 corresponds to output Y.

[0099] The power supply wiring 251 is formed in the center of the cell in the Y direction. In a plan view, the power supply wiring 251 overlaps with the power supply wiring 211 and the active region 2N3. The power supply wiring 251 is connected to the source portion of transistor N21 in the active region 2N3 via via 266 and local wiring 244. The power supply wiring 251 is connected to the source portion of transistor N22 in the active region 2N3 via via 267 and local wiring 246.

[0100] Wiring 252 is located in the lower left of the drawing in the Y direction. In a plan view, wiring 252 overlaps with wiring 212. Wiring 252 is connected to gate wiring 231 via via 268.

[0101] Wiring 253 is located in the lower right of the drawing in the Y direction. In a plan view, wiring 253 overlaps with wiring 213. Wiring 253 is connected to gate wiring 232 via via 269.

[0102] Wiring 254 is located on the upper side of the drawing in the Y direction. In a plan view, wiring 254 overlaps with wiring 214. Wiring 254 is connected via vias 264, 265, 270 and local wirings 243, 245 to the drain portion of transistor P22 in the active region 2P3, the drain portion of transistor N21 in the active region 2N3, and the drain portion of transistor N22 in the active region 2N3.

[0103] With the above configuration, the two-input NOR cell C9 has wiring 212 corresponding to input A, wiring 213 corresponding to input B, and wiring 214 corresponding to output Y formed on the BM0 wiring layer, and wiring 252 corresponding to input A, wiring 253 corresponding to input B, and wiring 254 corresponding to output Y formed on the M0 wiring layer. In other words, the two-input NOR cell C9 has wiring that constitutes the input terminals (inputs A and B) and wiring that constitutes the output terminal (output Y) formed on both the M0 wiring layer and the BM0 wiring layer. As a result, wiring formed on back wiring layers such as the BM0 wiring layer and wiring formed on metal wiring layers such as the M0 wiring layer can be connected to the input and output terminals of the two-input NOR cell C9, thereby simplifying the design of semiconductor integrated circuit devices while improving design flexibility.

[0104] Furthermore, wirings 212 and 252 overlap in a plan view. Wirings 213 and 253 overlap in a plan view. Wirings 214 and 254 overlap in a plan view. In other words, the wirings that constitute the input terminals (inputs A and B) formed in the BM0 wiring layer and the M0 wiring layer overlap in a plan view. The wirings that constitute the output terminal (output Y) formed in the BM0 wiring layer and the M0 wiring layer overlap in a plan view. This reduces the difference in characteristics between input signals input from the rear wiring layer side and input from the metal wiring layer side, and also reduces the difference in characteristics between output signals output from the rear wiring layer side and output from the metal wiring layer side.

[0105] Although a detailed explanation will be omitted, the two-input NOR cell C9 can be modified in the same way as in Figures 8 and 9 for Figure 6.

[0106] (Block Layout) Figures 11 and 12 are plan views showing an example of the layout of a circuit block in a semiconductor integrated circuit device according to the embodiment. Specifically, Figure 11 shows the upper part of a cell, and Figure 12 shows the lower part of a cell. In Figures 11 and 12, only the wiring formed on the back wiring layers (BM0 to BM2 wiring layers) and metal wiring layers (M0 to M2 wiring layers) is shown, and other parts are omitted from the illustration. In addition, the circuit block also includes cells other than the standard cells shown in Figures 11 and 12, but these are omitted from the illustration.

[0107] As shown in Figures 11 and 12, the lower cell row contains a 2-input NAND cell C8 and an inverter cell C1. The central cell row contains inverter cells C2 and C1. The upper cell row contains a 2-input NAND cell C5 and a 2-input NOR cell C9. Note that the inverter cell C1 located in the lower cell row may be referred to as inverter cell C1a, and the inverter cell C1 located in the central cell row may be referred to as inverter cell C1b.

[0108] As shown in Figure 12, the back wiring layer has BM1 and BM2 wiring layers formed below the BM0 wiring layer. Wires 311 to 318 extending in the Y direction are formed in the BM1 wiring layer. Wires 321 to 324 extending in the X direction are formed in the BM2 wiring layer.

[0109] The wiring 114 (output Y) formed in the BM0 wiring layer of the 2-input NAND cell C8 is connected to the wiring 12 (input A) formed in the BM0 wiring layer of the inverter cell C2 via wirings 311, 321, 312 and vias.

[0110] The wiring 13 (output Y) formed in the BM0 wiring layer of inverter cell C2 is connected to the wiring 113 (input B) formed in the BM0 wiring layer of 2-input NAND cell C5 via wirings 313, 322, 314 and vias.

[0111] The wiring 13 (output Y) formed in the BM0 wiring layer of inverter cell C1b is connected to the wiring 213 (input B) formed in the BM0 wiring layer of 2-input NOR cell C9 via wirings 315, 323, 316 and vias.

[0112] The wiring 114 (output Y) formed in the BM0 wiring layer of the 2-input NAND cell C5 is connected to the wiring 212 (input A) formed in the BM0 wiring layer of the 2-input NOR cell C9 via wirings 317, 324, 318 and vias.

[0113] As shown in Figure 11, the metal wiring layer has M1 and M2 wiring layers formed above the M0 wiring layer. Wires 351 to 354 extending in the Y direction are formed in the M1 wiring layer. Wires 361 and 362 extending in the X direction are formed in the M2 wiring layer.

[0114] The wiring 53 (output Y) formed in the M0 wiring layer of inverter cell C1a is connected to the wiring 52 (input A) formed in the M0 wiring layer of inverter cell C1b via wirings 351, 361, 352 and vias.

[0115] The wiring 53 (output Y) formed in the M0 wiring layer of inverter cell C1b is connected to the wiring 152 (input A) formed in the M0 wiring layer of 2-input NAND cell C5 via wirings 353, 362, 354 and vias.

[0116] In the block layouts of Figures 11 and 12, the inverter cell C2 has wirings 12 and 52 constituting its input terminal (input A) formed in the BM0 wiring layer and the M0 wiring layer, respectively. The wiring 114 (output Y) of the two-input NAND cell C8 is connected to the wiring 12 of the inverter cell C2, which is formed at the bottom of the diagram in the Y direction, that is, the wiring constituting the input terminal formed on the side closer to the two-input NAND cell C8 in the Y direction in a plan view. This allows for a shorter wiring length between cells, thereby enabling higher speeds for semiconductor integrated circuit devices.

[0117] Furthermore, the inverter cell C2 has wirings 13 and 53 that constitute the output terminal (output Y) formed in the BM0 wiring layer and the M0 wiring layer, respectively. The wiring 113 (input B) of the two-input NAND cell C5 is connected to the wiring 13 of the inverter cell C2 that constitutes the output terminal, which is formed at the top of the diagram in the Y direction, that is, the wiring that constitutes the input terminal formed on the side closer to the two-input NAND cell C5 in the Y direction in a plan view. This makes it possible to shorten the wiring length of the wiring connecting the cells, thereby increasing the speed of the semiconductor integrated circuit device.

[0118] Furthermore, in inverter cell C1b, the wirings 13 and 53 constituting the output terminal (output Y) are formed in the BM0 wiring layer and the M0 wiring layer, respectively. Wiring 13 of inverter cell C1b is connected to wiring 213 (input B) of 2-input NOR cell C9. Wiring 53 of inverter cell C1b is connected to wiring 152 (input A) of 2-input NAND cell C5. As a result, when the output terminal of a standard cell is connected to multiple input terminals, the output terminals formed on the back wiring layer side and the metal wiring layer side of the standard cell can be connected to separate input terminals, thereby improving the design flexibility of the semiconductor integrated circuit device.

[0119] In the embodiments and modifications described above, each transistor is provided with three nanosheets, but some or all of the transistors may be provided with one, two, or four or more nanosheets.

[0120] Furthermore, while the cross-sectional shape of the nanosheet is rectangular in each of the embodiments and modifications described above, it is not limited to this. For example, it may be square, circular, elliptical, or the like.

[0121] Furthermore, in the embodiments and modifications described above, a P-type transistor is formed at the bottom of the cell and an N-type transistor at the top of the cell, but the invention is not limited to this, and a P-type transistor may be formed at the top of the cell and an N-type transistor at the bottom of the cell.

[0122] Furthermore, in the above-described embodiment, the power supply wiring for VDD is formed on the BM0 layer and the power supply wiring for VSS is formed on the M0 layer, but the wiring layers on which the power supply wiring is formed are not limited to these. For example, both the power supply wiring for VDD and the power supply wiring for VSS may be formed on the back layer of the transistor. Also, the arrangement position of the power supply wiring in the Y direction is not limited to that shown in the above-described embodiment and drawings. In addition, the power supply wiring may be formed on multiple wiring layers.

[0123] Furthermore, the width and position of the active area in the Y direction at the top and bottom of the cell may be the same or different.

[0124] Furthermore, while the transistors in the embodiments described above are nanosheet FETs, the invention is not limited to them. For example, fin FETs or other types of transistors may also be used.

[0125] This disclosure provides a semiconductor integrated circuit device layout that facilitates design while improving design flexibility for standard cells using CFETs.

[0126] 11, 51, 111, 151, 211, 251 Power wiring 21, 22, 121-124, 211-214 Nanosheet 31, 131, 132, 231, 232 Gate wiring 12, 13, 52, 53, 112-114, 152-154, 212-214, 252-254, 311-318, 321-324, 351-354, 361, 362 Wiring 2P1-2P3, 2N1-2N3 Active region P1, P11, P12, P21, P22, N1, N11, N12, N21, N22 Transistor C1 (C1a, C1b), C2-C4 Inverter cell C5-C8 2-input NAND cell C9 2-input NOR cell

Claims

1. A semiconductor integrated circuit device comprising a plurality of standard cells, including a first standard cell, wherein the first standard cell comprises: a channel, source, and drain of a first transistor of a first conductivity type, the channel comprising a first active region including a first nanosheet extending in a first direction; a second active region formed above the first active region in the depth direction, overlapping with the first active region in a plan view, and comprising a channel, source, and drain of a second transistor of a second conductivity type having a different conductivity type from the first, the channel comprising a second nanosheet extending in the first direction; a first input terminal comprising a first wiring formed in a back wiring layer below the first transistor in the depth direction, to which a first input signal is input; and a second input terminal comprising a second wiring formed in a metal wiring layer above the first transistor in the depth direction, to which the first input signal is input.

2. A semiconductor integrated circuit apparatus according to claim 1, wherein the first and second wirings overlap in a plan view.

3. A semiconductor integrated circuit apparatus according to claim 1, wherein the first standard cell further comprises a first output terminal composed of a third wiring formed on the back wiring layer.

4. A semiconductor integrated circuit apparatus according to claim 3, wherein the second and third wirings overlap in a plan view.

5. A semiconductor integrated circuit apparatus according to claim 1, wherein the first standard cell further comprises a second output terminal composed of a fourth wiring formed in the metal wiring layer.

6. A semiconductor integrated circuit apparatus according to claim 5, wherein the first and fourth wirings overlap in a plan view.

7. A semiconductor integrated circuit apparatus according to claim 1, wherein the first standard cell is composed of a fifth wiring formed on the back wiring layer, and further comprises a third input terminal to which a second input signal different from the first input signal is input.

8. A semiconductor integrated circuit apparatus according to claim 1, wherein the first standard cell is composed of a sixth wiring formed in the metal wiring layer, and further comprises a fourth input terminal to which a second input signal different from the first input signal is input.

9. A semiconductor integrated circuit apparatus according to claim 1, wherein the first standard cell comprises a fifth wiring formed in the back wiring layer and a third input terminal to which a second input signal different from the first input signal is input, and the first standard cell comprises a sixth wiring formed in the metal wiring layer and a fourth input terminal to which the second input signal is input, and the fifth and sixth wirings overlap in a plan view.

10. A semiconductor integrated circuit apparatus according to claim 1, wherein the plurality of standard cells include a second standard cell disposed on the first side of the first standard cell, which is one side of the second direction perpendicular to the first direction and the depth direction, and of the first and second wirings, the wiring disposed on the first side in a plan view is connected to the output terminal of the second standard cell.

11. A semiconductor integrated circuit device comprising a plurality of standard cells, including a first standard cell, wherein the first standard cell comprises: a channel, source, and drain of a first transistor of a first conductivity type, the channel comprising a first active region including a first nanosheet extending in a first direction; a second active region formed above the first active region in the depth direction, overlapping with the first active region in a plan view, and comprising a channel, source, and drain of a second transistor of a second conductivity type having a different conductivity type from the first, the channel comprising a second nanosheet extending in the first direction; a first output terminal comprising a first wiring formed in a back wiring layer below the first transistor in the depth direction, to which a first output signal is output; and a second output terminal comprising a second wiring formed in a metal wiring layer above the first transistor in the depth direction, to which the first output signal is output.

12. A semiconductor integrated circuit apparatus according to claim 11, wherein the first and second wirings overlap in a plan view.

13. A semiconductor integrated circuit apparatus according to claim 11, wherein the first standard cell further comprises a first input terminal composed of a third wiring formed on the back wiring layer.

14. A semiconductor integrated circuit apparatus according to claim 13, wherein the second and third wirings overlap in a plan view.

15. A semiconductor integrated circuit apparatus according to claim 13, wherein the first standard cell further comprises a second input terminal composed of a fourth wiring formed on the back wiring layer, and the second wiring overlaps with the third and fourth wiring in a plan view.

16. A semiconductor integrated circuit apparatus according to claim 13, wherein the first standard cell further comprises a third input terminal composed of a fifth wiring formed in the metal wiring layer.

17. A semiconductor integrated circuit apparatus according to claim 16, wherein the first and fifth wirings overlap in a plan view.

18. A semiconductor integrated circuit apparatus according to claim 16, wherein the first standard cell further comprises a fourth input terminal composed of a sixth wiring formed on the back wiring layer, and the first wiring overlaps with the fifth and sixth wiring in a plan view.

19. A semiconductor integrated circuit apparatus according to claim 11, wherein the plurality of standard cells include a second standard cell disposed on the first side of the first standard cell, which is one side of the second direction perpendicular to the first direction and the depth direction, and of the first and second wirings, the wiring disposed on the first side in a plan view is connected to the input terminal of the second standard cell.

20. A semiconductor integrated circuit apparatus according to claim 11, wherein the plurality of standard cells include second and third standard cells, the first wiring is connected to the input terminal of the second standard cell, and the second wiring is connected to the input terminal of the third standard cell.

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