Substrate processing method and substrate processing device

Abstract

In one exemplary embodiment, a substrate processing method comprises: (a) a step for placing a silicon substrate on a substrate support part in a chamber, the silicon substrate having a substrate body and a mask on the substrate body, the mask providing an opening, and the silicon substrate having a bevel which is at least partly exposed; (b) a step for forming a protective film on the silicon substrate, the protective film having a first thickness on the substrate body at the bottom of the opening and a second thickness larger than the first thickness on the bevel; and (c) a step for dicing the silicon substrate through the opening by means of plasma generated from a processing gas containing a halogen-containing gas.

Description

Substrate Processing Method and Substrate Processing Apparatus

[0001] Exemplary embodiments of the present disclosure relate to a substrate processing method and a substrate processing apparatus.

[0002] Patent Document 1 discloses a protection method for protecting a semiconductor wafer. In this protection method, a wafer protection member is attached over at least half of the circumference of the semiconductor wafer. Thereafter, the protection member attached to the semiconductor wafer is thermally cured.

[0003] Japanese Patent Application Laid-Open No. 2010-171297

[0004] The present disclosure provides a substrate processing method and a substrate processing apparatus capable of improving the etching rate of a silicon substrate.

[0005] In one exemplary embodiment, the substrate processing method includes: (a) a step of placing a silicon substrate on a substrate support in a chamber, the silicon substrate having a substrate body and a mask on the substrate body, the mask providing an opening and at least a part of the bevel of the silicon substrate being exposed; (b) a step of forming a protective film on the silicon substrate, the protective film having a first thickness on the substrate body at the bottom of the opening and a second thickness greater than the first thickness on the bevel; and (c) a step of dicing the silicon substrate through the opening by plasma generated from a processing gas containing a halogen-containing gas.

[0006] According to one exemplary embodiment, the etching rate of the silicon substrate can be improved.

[0007] Figure 1 is a schematic diagram showing a plasma processing apparatus according to one exemplary embodiment. Figure 2 is a schematic diagram showing a plasma processing apparatus according to one exemplary embodiment. Figure 3 is a flowchart of a substrate processing method according to one exemplary embodiment. Figure 4 is a cross-sectional view of an example silicon substrate to which the method of Figure 3 may be applied. Figure 5 is a cross-sectional view showing one step of the substrate processing method according to one exemplary embodiment. Figure 6 is a cross-sectional view showing one step of the substrate processing method according to one exemplary embodiment. Figure 7 is a cross-sectional view showing one step of the substrate processing method according to one exemplary embodiment. Figure 8 is a cross-sectional view showing one step of the substrate processing method according to one exemplary embodiment. Figure 9 is a cross-sectional view showing one step of the substrate processing method according to one exemplary embodiment. Figure 10 is a cross-sectional view showing one step of the substrate processing method according to one exemplary embodiment. Figure 11 is a flowchart of a substrate processing method according to one exemplary embodiment. Figure 12 is a diagram showing a substrate processing system according to one exemplary embodiment.

[0008] Various exemplary embodiments will be described in detail below with reference to the drawings. In each drawing, the same or corresponding parts will be denoted by the same reference numerals.

[0009] Figure 1 is a diagram illustrating an example configuration of a plasma processing system. In one embodiment, the plasma processing system includes a plasma processing apparatus 1 and a control unit 2. The plasma processing system is an example of a substrate processing system, and the plasma processing apparatus 1 is an example of a substrate processing apparatus. The plasma processing apparatus 1 includes a plasma processing chamber 10, a substrate support unit 11, and a plasma generation unit 12. The plasma processing chamber 10 has a plasma processing space. The plasma processing chamber 10 also has at least one gas supply port for supplying at least one processing gas to the plasma processing space, and at least one gas outlet for discharging gas from the plasma processing space. The gas supply port is connected to a gas supply unit 20, which will be described later, and the gas outlet is connected to an exhaust system 40, which will be described later. The substrate support unit 11 is located in the plasma processing space and has a substrate support surface for supporting a substrate.

[0010] The plasma generation unit 12 is configured to generate plasma from at least one processing gas supplied into the plasma processing space. The plasma formed in the plasma processing space may be capacitively coupled plasma (CCP), inductively coupled plasma (ICP), ECR (Electron-Cyclotron-Resonance) plasma, helicon wave excited plasma (HWP), or surface wave plasma (SWP), etc. Furthermore, various types of plasma generation units may be used, including AC (Alternating Current) plasma generation units and DC (Direct Current) plasma generation units. In one embodiment, the AC signal (AC power) used in the AC plasma generation unit has a frequency in the range of 100 kHz to 10 GHz. Therefore, the AC signal includes an RF (Radio Frequency) signal and a microwave signal. In one embodiment, the RF signal has a frequency in the range of 100 kHz to 150 MHz.

[0011] The control unit 2 processes computer-executable instructions that cause the plasma processing apparatus 1 to perform the various processes described herein. The control unit 2 may be configured to control the elements of the plasma processing apparatus 1 to perform the various processes described herein. In one embodiment, part or all of the control unit 2 may be included in the plasma processing apparatus 1. The control unit 2 may include a processing unit 2a1, a storage unit 2a2, and a communication interface 2a3. The control unit 2 is implemented, for example, by a computer 2a. The control unit 2 may include a processing unit 2a1, a storage unit 2a2, and a communication interface 2a3. The functions realized by the processing unit 2a1 described herein may be implemented in a circuit or processing circuit, including a general-purpose processor, an application-specific processor, integrated circuits, ASICs (Application Specific Integrated Circuits), a CPU (Central Processing Unit), a conventional circuit, and / or a combination thereof, programmed to realize the described functions. The processor is considered to be a circuit or processing circuit, including transistors and other circuits. The processor may also be a programmed processor that executes a program stored in the memory unit 2a2. The processing unit 2a1 may be configured to perform various control operations by reading a program from the storage unit 2a2 and executing the read program. This program may be stored in the storage unit 2a2 in advance, or it may be obtained via a medium when needed. The obtained program is stored in the storage unit 2a2 and read from the storage unit 2a2 and executed by the processing unit 2a1. The medium may be various storage media readable by the computer 2a, or it may be a communication line connected to the communication interface 2a3. The processing unit 2a1 may be a CPU (Central Processing Unit).The storage unit 2a2 may include RAM (Random Access Memory), ROM (Read Only Memory), HDD (Hard Disk Drive), SSD (Solid State Drive), or a combination thereof. The communication interface 2a3 may communicate with the plasma processing apparatus 1 via a communication line such as a LAN (Local Area Network). In this disclosure, circuits, units, and means are hardware programmed to perform or execute the functions described. Such hardware may be any hardware described in this disclosure, or any hardware known to be programmed to perform or execute the functions described. If such hardware is a processor that is considered to be a type of circuit, such circuit, means, or unit is a combination of hardware and software used to constitute such hardware and / or processor.

[0012] The following describes an example configuration of an inductively coupled plasma processing apparatus as an example of a plasma processing apparatus 1. Figure 2 is a diagram illustrating an example configuration of an inductively coupled plasma processing apparatus.

[0013] The inductively coupled plasma processing apparatus 1 includes a plasma processing chamber 10, a gas supply unit 20, a power supply system 30, and an exhaust system 40. The plasma processing chamber 10 includes a dielectric window 101. The plasma processing apparatus 1 also includes a substrate support unit 11, a gas introduction unit, and an antenna 14. The substrate support unit 11 is located inside the plasma processing chamber 10. The antenna 14 is located on or above the plasma processing chamber 10 (i.e., on or above the dielectric window 101). The plasma processing chamber 10 has a plasma processing space 10s defined by the dielectric window 101, the side walls 102 of the plasma processing chamber 10, and the substrate support unit 11. The plasma processing chamber 10 is grounded.

[0014] The substrate support portion 11 includes a main body portion 111 and a ring assembly 112. The main body portion 111 has a central region 111a for supporting the substrate W and an annular region 111b for supporting the ring assembly 112. A wafer is an example of a substrate W. The annular region 111b of the main body portion 111 surrounds the central region 111a of the main body portion 111 in a plan view. The substrate W is placed on the central region 111a of the main body portion 111, and the ring assembly 112 is placed on the annular region 111b of the main body portion 111 so as to surround the substrate W on the central region 111a of the main body portion 111. Therefore, the central region 111a is also called the substrate support surface for supporting the substrate W, and the annular region 111b is also called the ring support surface for supporting the ring assembly 112.

[0015] In one embodiment, the main body 111 includes a base 1110 and an electrostatic chuck 1111. The base 1110 includes a conductive member. The conductive member of the base 1110 can function as a bias electrode. The electrostatic chuck 1111 is placed on the base 1110. The electrostatic chuck 1111 includes a ceramic member 1111a and an electrostatic chuck electrode 1111b placed within the ceramic member 1111a. The electrostatic chuck electrode 1111b is also called a clamping electrode. In one embodiment, the electrostatic chuck electrode 1111b is electrically connected or coupled to a chuck power supply. The chuck power supply may be a DC power supply or an AC power supply. The ceramic member 1111a has a central region 111a. In one embodiment, the ceramic member 1111a also has an annular region 111b. Furthermore, other members surrounding the electrostatic chuck 1111, such as an annular electrostatic chuck or an annular insulating member, may have an annular region 111b. In this case, the ring assembly 112 may be placed on the annular electrostatic chuck or the annular insulating member, or it may be placed on both the electrostatic chuck 1111 and the annular insulating member. In addition, at least one RF / DC bias electrode, which is electrically connected to or coupled to the RF power supply 31 and / or DC power supply 32 described later, may be placed inside the ceramic member 1111a. In this case, at least one RF / DC electrode functions as a bias electrode. Furthermore, the conductive member of the base 1110 and at least one bias electrode in the RF / DC ceramic member 1111a may function as multiple bias electrodes. Also, the electrostatic chuck electrode 1111b may function as a bias electrode. Therefore, the substrate support portion 11 includes at least one bias electrode.

[0016] The ring assembly 112 includes one or more annular members. In one embodiment, the one or more annular members include one or more edge rings and at least one covering ring. The edge rings are formed of a conductive or insulating material, and the covering rings are formed of an insulating material.

[0017] The substrate support section 11 may also include a temperature control module configured to adjust at least one of the electrostatic chuck 1111, the ring assembly 112, and the substrate to a target temperature. The temperature control module may include a heater, a heat transfer medium, a flow path 1110a, or a combination thereof. A heat transfer fluid such as brine or gas flows through the flow path 1110a. In one embodiment, the flow path 1110a is formed within the base 1110, and one or more heaters are arranged within the ceramic member 1111a of the electrostatic chuck 1111. The substrate support section 11 may also include a heat transfer gas supply section configured to supply heat transfer gas to the gap between the back surface of the substrate W and the central region 111a.

[0018] The gas introduction section is configured to introduce at least one processing gas from the gas supply section 20 into the plasma processing space 10s. In one embodiment, the gas introduction section includes a central gas injector (CGI) 13. The central gas injector 13 is located above the substrate support section 11 and is attached to a central opening formed in the dielectric window 101. The central gas injector 13 has at least one gas supply port 13a, at least one gas flow path 13b, and at least one gas inlet 13c. The processing gas supplied to the gas supply port 13a passes through the gas flow path 13b and is introduced into the plasma processing space 10s from the gas inlet 13c. In addition to or instead of the central gas injector 13, the gas introduction section may also include one or more side gas injectors (SGI) attached to one or more openings formed in the side wall 102.

[0019] The gas supply unit 20 may include at least one gas source 21 and at least one flow controller 22. In one embodiment, the gas supply unit 20 is configured to supply at least one processing gas to the gas inlet from a corresponding gas source 21 via a corresponding flow controller 22. Each flow controller 22 may include, for example, a mass flow controller or a pressure-controlled flow controller. Furthermore, the gas supply unit 20 may include at least one flow modulation device that modulates or pulses the flow rate of at least one processing gas.

[0020] The power supply system 30 includes an RF power supply 31 that is electrically connected to or coupled to the plasma processing chamber 10 via at least one impedance matching circuit. In one embodiment, the power supply 31 is electrically connected to or coupled to the plasma processing chamber 10 via at least one impedance matcher. The impedance matcher may be a mechanically controlled matcher or an electronically controlled matcher. The RF power supply 31 is configured to supply at least one RF signal (RF power) to at least one bias electrode and antenna 14. This causes plasma to be formed and generated from at least one processing gas supplied to the plasma processing space 10s. Therefore, the RF power supply 31 can function as at least part of the plasma generation unit 12. Furthermore, by supplying a bias RF signal to at least one bias electrode, a bias potential is generated on the substrate W, and ions in the formed plasma can be drawn into the substrate W.

[0021] In one embodiment, the RF power supply 31 includes a first RF generation unit 31a and a second RF generation unit 31b. The first RF generation unit 31a is electrically connected or coupled to the antenna 14 via at least one impedance matching circuit and is configured to generate a source RF signal (source RF power) to generate plasma in a plasma processing space 10s for plasma generation. In one embodiment, the first RF generation unit 31a is electrically connected or coupled to the antenna 14 via at least one impedance matcher. In one embodiment, the source RF signal has a frequency in the range of 10 MHz to 150 MHz. In one embodiment, the first RF generation unit 31a may be configured to generate a plurality of source RF signals having different frequencies. The generated one or more source RF signals are supplied to the antenna 14.

[0022] The second RF generation unit 31b is electrically connected or coupled to at least one bias electrode via at least one impedance matching circuit and is configured to generate a bias RF signal (bias RF power). In one embodiment, the second RF generation unit 31b is electrically connected or coupled to at least one bias electrode via at least one impedance matcher. The frequency of the bias RF signal may be the same as or different from the frequency of the source RF signal. In one embodiment, the bias RF signal has a lower frequency than the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency in the range of 100 kHz to 60 MHz. In one embodiment, the second RF generation unit 31b may be configured to generate a plurality of bias RF signals having different frequencies. The generated one or more bias RF signals are supplied to at least one bias electrode. In various embodiments, at least one of the source RF signal and the bias RF signal may be pulsed.

[0023] The power supply system 30 may also include a DC power supply 32 that is electrically connected to or coupled to the plasma processing chamber 10. The DC power supply 32 includes a bias DC voltage generation unit 32a. In one embodiment, the bias DC voltage generation unit 32a is electrically connected to or coupled to at least one bias electrode and is configured to generate a bias DC voltage signal. The generated bias DC voltage signal is applied to at least one bias electrode.

[0024] In various embodiments, the bias DC voltage signal may be pulsed. In this case, the voltage generation unit 32a functions as a voltage pulse generation unit configured to generate a sequence of voltage pulses. Thus, the sequence of voltage pulses is applied to at least one bias electrode. In one embodiment, the sequence of voltage pulses has a plurality of cycles, each cycle including a burst of voltage pulses in a first period and a constant reference voltage in a second period. That is, the burst of voltage pulses is repeated in the sequence of voltage pulses. The absolute value of the voltage level of the voltage pulse is greater than the absolute value of the voltage level of the reference voltage. The voltage pulse may have a pulse arbitrary waveform having a rectangular, trapezoidal, triangular, or a combination thereof, and the arbitrary waveform may change over time. In one embodiment, a waveform generation unit for generating a sequence of voltage pulses from a DC signal is connected between the bias DC generation unit 32a and at least one bias electrode. Thus, the bias DC generation unit 32a and the waveform generation unit constitute a voltage pulse generation unit. The voltage pulse may have positive polarity or negative polarity. Furthermore, the voltage pulse sequence may include one or more positive voltage pulses and one or more negative voltage pulses within one cycle. The bias DC voltage generation unit 32a may be provided in addition to the RF power supply 31, or it may be provided in place of the second RF generation unit 31b.

[0025] The antenna 14 includes one or more coils. In one embodiment, the antenna 14 may include an outer coil and an inner coil arranged coaxially. In this case, the RF power supply 31 may be connected to both the outer coil and the inner coil, or to either the outer coil or the inner coil. In the former case, the same RF generation unit may be connected to both the outer coil and the inner coil, or separate RF generation units may be connected to the outer coil and the inner coil separately.

[0026] The exhaust system 40 may be connected to, for example, a gas outlet 10e located at the bottom of the plasma processing chamber 10. The exhaust system 40 may include a pressure regulating valve and a vacuum pump. The pressure regulating valve regulates the pressure in the plasma processing space 10s. The vacuum pump may include a turbomolecular pump, a dry pump, or a combination thereof.

[0027] Figure 3 is a flowchart of a substrate processing method according to one exemplary embodiment. The substrate processing method MT1 shown in Figure 3 (hereinafter referred to as "method MT1") can be performed by the plasma processing apparatus 1 of the above embodiment. Method MT1 can be applied to the silicon substrate SW shown in Figure 4.

[0028] Figure 4 is a cross-sectional view of an example of a silicon substrate SW to which the method of Figure 3 may be applied. As shown in Figure 4, in one embodiment, the silicon substrate SW includes a substrate body SWa and a mask MK on the substrate body SWa. A native oxide film may be formed on the surface of the substrate body SWa. This native oxide film can be formed by oxidation of the surface of the substrate body SWa. That is, the native oxide film formed on the surface of the substrate body SWa may be part of the substrate body SWa. If a native oxide film is formed on the surface of the substrate body SWa, the mask MK may be formed on the native oxide film. The substrate body SWa may have a thickness of 700 μm or more.

[0029] At least a portion of the bevel BVL of the silicon substrate SW is exposed. A mask MK does not need to be provided on the bevel BVL of the silicon substrate SW. The entire bevel BVL may be exposed. Alternatively, a native oxide film may be formed on the surface of the bevel BVL. In this embodiment, the bevel BVL of the silicon substrate SW is the bevel of the substrate body SWa. As described above, the native oxide film that can be formed on the surface of the substrate body SWa is a part of the substrate body SWa, so the native oxide film formed by oxidation of the surface of the bevel of the substrate body SWa is included in the silicon substrate SW. Therefore, even if a native oxide film is formed on the surface of the bevel BVL, the native oxide film is a part of the bevel BVL, and it can be said that at least a portion of the bevel BVL is exposed.

[0030] The mask MK may be patterned. The mask MK may include an oxide film OX on the substrate body SWa and a resist film RF on the oxide film OX. The oxide film OX is a film that can be formed by exposing the substrate body SWa to an oxidizing gas, and is different from the native oxide film formed by the oxidation of the surface of the substrate body SWa. The oxide film OX may be a silicon oxide film or a metal oxide film. The oxide film OX may contain silicon oxide or a metal oxide. Wiring may be embedded in the oxide film OX. That is, the oxide film OX may be a wiring layer. The wiring may be, for example, copper wiring. The resist film RF may be a photoresist film. The resist film RF may have a thickness of 2 μm or more, or a thickness of 30 μm or less.

[0031] The mask MK provides an opening OP. In this embodiment, the oxide film OX and the resist film RF may provide the opening OP. The opening OP may have a width of 1 μm or more. The width of the opening OP is, for example, the dimension of the opening OP (CD: Critical Dimension). The opening OP may expose the substrate body SWa. That is, the bottom OPa of the opening OP may be the upper surface of the substrate body SWa. If the native oxide film is formed on the substrate body SWa, the opening OP may expose the native oxide film. That is, the bottom OPa of the opening OP may be the upper surface of the native oxide film.

[0032] In one example, an opening OP may be formed by partially removing the oxide film OX using the resist film RF as a mask. In this example, the oxide film OX can be etched by plasma generated from the processing gas. That is, an opening OP may be formed by etching the oxide film OX using the resist film RF as a mask. In this case, the silicon substrate SW located below the portion of the oxide film OX that is removed may be removed together with that portion. The processing gas used to form the opening OP may be a processing gas containing a halogen-containing gas (first processing gas) used in step ST141 described later.

[0033] The following describes method MT1, taking as an example the case where method MT1 is applied to a silicon substrate SW using the plasma processing apparatus 1 of the above embodiment, with reference to Figures 3 to 8. Figures 5 to 8 are cross-sectional views showing one step of an etching method according to one exemplary embodiment. When the plasma processing apparatus 1 is used, method MT1 can be executed in the plasma processing apparatus 1 by the control unit 2 controlling each part of the plasma processing apparatus 1. In method MT1, as shown in Figure 2, the silicon substrate SW on the substrate support part 11 arranged in the plasma processing chamber 10 is processed.

[0034] As shown in Figure 3, method MT1 comprises steps ST11, ST12, ST13, and ST14. Steps ST11, ST12, ST13, and ST14 may be performed in order.

[0035] (Step ST11) In step ST11, the silicon substrate SW shown in Figure 4 is placed on the substrate support portion 11 inside the plasma processing chamber 10. That is, the silicon substrate SW is provided inside the plasma processing chamber 10.

[0036] (Step ST12) In step ST12, a protective film is formed on the silicon substrate SW. In step ST12, as shown in Figure 5, the protective film PF is formed by plasma (second plasma) PL1 generated from a processing gas (second processing gas) containing silicon-containing gas or metal-containing gas. At the end of step ST12, the supply of the processing gas containing silicon-containing gas or metal-containing gas may be stopped.

[0037] The silicon-containing gas may contain at least one selected from the group consisting of monosilane gas, disilane gas, dichlorosilane gas, monochlorosilane gas, trichlorosilane gas, tetrachlorosilane gas, and hexachlorodisilane gas. The metal-containing gas may contain at least one selected from the group consisting of tungsten-containing gas, tin-containing gas, molybdenum-containing gas, zirconium-containing gas, ruthenium-containing gas, titanium-containing gas, hafnium-containing gas, and tantalum-containing gas. The second processing gas may further contain at least one selected from the group consisting of an oxygen-containing gas, a nitrogen-containing gas, and a gas containing carbon and hydrogen.

[0038] The tungsten-containing gas may contain at least one of a gas containing tungsten and fluorine and a gas containing tungsten and chlorine. The gas containing tungsten and fluorine may contain at least one selected from the group consisting of WF ２ gas, WF ４ gas, WF ５ gas, and WF ６ gas. The gas containing tungsten and chlorine may contain at least one selected from the group consisting of WCl ２ gas, WCl ４ gas, WCl ５ gas, and WCl ６ gas.

[0039] The tin-containing gas may contain at least one selected from the group consisting of an organotin compound gas, SnCl ４ gas, Sn(CH ３ ) ４ gas, and SnH ４ gas. The molybdenum-containing gas may contain MoF ６ gas. The zirconium-containing gas may contain Zr[N(CH ３ )C ２ H ５ ４ gas.

[0040] The ruthenium-containing gas may contain an organoruthenium gas. The organoruthenium gas may contain EtCp ２ Ru((C ２ ​H ５ C ５ H ５ ) ２ Ru) gas, Ru(C ５ H ４ C ２ H ５ ) ２ Gas, Ru(C １１ H １９ O ２ ) ３ gas, and Ru ３ (CO) １２ It may include at least one selected from the group consisting of gases. Titanium-containing gases include titanium compound-containing gases, C ２ H ７ NTi Gas, TiCp(NME ２ ) ３ Gas, TiMe ５ Cp(NMe ２ ) ３ Gas, and TiCl ４ It may include at least one selected from the group consisting of gases. Hafnium-containing gases include [(CH ３ ) (C ２ H ５ )N] ４ It may contain Hf gas. Tantalum-containing gas is TaCl ５ It may contain gas.

[0041] In step ST12, the pressure inside the plasma processing chamber 10 containing the silicon substrate SW may be 0.1 Pa (0.75 mTorr) or higher. The pressure inside the plasma processing chamber 10 containing the silicon substrate SW may be 5.3 Pa (40 mTorr) or higher, or 40.0 Pa (300 mTorr) or higher. The pressure inside the plasma processing chamber 10 containing the silicon substrate SW may be 100 Pa (750 mTorr) or lower. The pressure inside the plasma processing chamber 10 containing the silicon substrate SW may be 53.3 Pa (400 mTorr) or lower.

[0042] In step ST12, the protective film PF may be formed by CVD (Chemical Vapor Deposition) or PVD (Physical Vapor Deposition). In one example, the protective film PF may be formed by plasma CVD or plasma PVD. That is, plasma may be used in the CVD or PVD method. Alternatively, heat may be used in the CVD method. In step ST12, the protective film PF may be formed by PE (Plasma Enhanced)-CVD or thermal CVD.

[0043] The protective film PF may contain a silicon-containing film or a metal-containing film. The silicon-containing film may include a silicon oxide film, a silicon nitride film, a silicon carbide film, or a silicon-containing low dielectric constant film. The silicon oxide film is SiO ２ The film may contain a film. The silicon nitride film may contain a SiN film. The silicon carbide film may contain a SiC film. The silicon-containing low dielectric film is a silicon-containing low dielectric film (low-k film). The silicon-containing low dielectric film may have a relative dielectric constant of 3.9 or less. The silicon-containing low dielectric film may contain a SiOC film or a SiOCN film. The protective film PF may contain silicon oxide, silicon nitride, a mixture of silicon oxide and carbon, or a mixture of silicon oxynitride (SiON) and carbon.

[0044] The metal-containing film may include a tungsten film, a tin film, a molybdenum film, a zirconium film, a ruthenium film, a titanium-containing film, a hafnium-containing film, or a tantalum-containing film. The protective film PF may contain tungsten, tin, molybdenum, zirconium, ruthenium, titanium, hafnium, or tantalum.

[0045] In step ST12, the protective film PF is formed on the substrate body SWa at the bottom OPa of the opening OP, and on the bevel BVL of the silicon substrate SW. The protective film PF has a first thickness T1 on the substrate body SWa and a second thickness T2 on the bevel BVL. The second thickness T2 is greater than the first thickness T1. The first thickness T1 may be greater than 0 nm, 1 nm or more, or 50 nm or more. The first thickness T1 may be 500 nm or less. The second thickness T2 may be 10 nm or more, or 100 nm or more. The second thickness T2 may be 1 μm or less.

[0046] The protective film PF may be formed on the upper surface of the mask MK. The protective film PF may have a third thickness T3 on the upper surface of the mask MK. In this embodiment, the protective film PF may be formed on the upper surface of the resist film RF, or the protective film PF may have a third thickness T3 on the upper surface of the resist film RF. The third thickness T3 may be 10 nm or more, or 100 nm or more. The third thickness T3 may be 1 μm or less. The third thickness T3 may be greater than the first thickness T1, or the same as the second thickness T2. The ratio of the third thickness T3 to the first thickness T1 may be the same as the ratio of the second thickness T2 to the first thickness T1, or it may be different.

[0047] The protective film PF may also be formed on the sides of the mask MK. On the sides of the mask MK, the protective film PF may have the same thickness as the third thickness T3, or it may have a thickness smaller than the third thickness T3. In this embodiment, the protective film PF may be formed on the sides of the resist film RF and the oxide film OX. On the sides of the resist film RF and the oxide film OX, the protective film PF may have the same thickness as the third thickness T3, or it may have a thickness smaller than the third thickness T3.

[0048] In one example, in step ST12, the protective film PF may include a first region R1 located on the substrate body SWa, a second region R2 located on the bevel BVL, and a third region R3 located on the mask MK. That is, the protective film PF may include a first region R1 which is formed on the bottom OPa of the opening OP, a second region R2 which is formed on the bevel BVL, and a third region R3 which is formed on the mask MK. In this embodiment, the third region R3 may be located on the resist film RF. In this example, the first region R1 may have a first thickness T1, the second region R2 may have a second thickness T2, and the third region R3 may have a third thickness T3.

[0049] (Step ST13) In step ST13, as shown in Figure 6, the first region R1, which is the portion of the protective film PF formed on the bottom OPa of the opening OP, is removed. In step ST13, the first region R1 may be removed by supplying a processing gas into the plasma processing chamber 10. In one example, the first region R1 may be removed by plasma generated from the processing gas. That is, in one example, the first region R1 may be etched through the opening OP by plasma generated from the processing gas. Step ST13 can also be called a breakthrough step. The processing gas used in step ST13 may be a processing gas containing a halogen-containing gas (first processing gas) used in step ST141, which will be described later. In step ST13, the bottom OPa of the opening OP may be exposed by removing the first region R1. At this time, the protective film PF formed on the side surface of the mask MK (oxide film OX and resist film RF) inside the opening OP may be removed together with the first region R1. At the end of step ST13, the supply of the processing gas containing the halogen gas may be stopped.

[0050] (Step ST14) In step ST14, the silicon substrate SW is diced. In method MT1, steps ST12, ST13, and ST14 may be performed in the same chamber (plasma processing chamber 10). Step ST14 may include steps ST141, ST142, and ST143. As shown in Figure 3, steps ST141, ST142, and ST143 may be performed in order.

[0051] (Step ST141) In step ST141, as shown in Figure 7, the silicon substrate SW is etched through the aperture OP by plasma (first plasma) PL2 generated from a processing gas (first processing gas) containing a halogen-containing gas. In step ST141, anisotropic etching and isotropic etching may be performed. In anisotropic etching, etching may proceed in the direction from the top surface to the bottom surface of the substrate body SWa. In isotropic etching, etching may proceed in all directions. Anisotropic etching may be performed by supplying an electrical bias to the substrate support part 11. Isotropic etching may be performed without supplying an electrical bias to the substrate support part 11. At the end of step ST141, the supply of the processing gas containing the halogen-containing gas may be stopped. The halogen-containing gas may contain a fluorine-containing gas. The halogen-containing gas is SF ６ Gas, NF ３ Gas, CF ４ Gas, hydrofluorocarbon gas, HF gas, IF ７ Gas, C ４ F ８ Gas, C ３ F ８ Gas, C ５ F ８ Gas, F ２ Gas, Cl ２ Gas, HCl gas, HBr gas, Br ２ Gas, ClF ３ Gas, BBr ３ Gas, BCl ３ Gas, BF ３ Gas, CF ３ I gas, PF ３ It may include at least one selected from the group consisting of gases and HI gases.

[0052] In step ST141, the temperature of the substrate support portion 11 may be -100°C or higher, or -40°C or higher. The temperature of the substrate support portion 11 may be 60°C or lower, or 10°C or lower.

[0053] In step ST141, the protective film PF formed on the side surface of the mask MK (oxide film OX and resist film RF) within the opening OP may be removed by etching of the silicon substrate SW. In step ST141, the entire protective film PF formed on the side surface of the mask MK may be removed, or a portion of the protective film PF formed on the side surface of the mask MK may be removed. In step ST141, the protective film PF formed on the mask MK (photoresist film PR) and the bevel BVL may or may not be removed by etching of the silicon substrate SW.

[0054] (Step ST142) In step ST142, a protective film PF is formed again on the silicon substrate SW as shown in Figure 8. In step ST142, the protective film PF may be formed on the silicon substrate SW in the same manner as in step ST12. The process conditions for step ST142 may be the same as the process conditions for step ST12. The second thickness T2 at the end of step ST142 may be greater than or the same as the second thickness T2 at the end of step ST12. Similarly, the third thickness T3 at the end of step ST142 may be greater than or the same as the third thickness T3 at the end of step ST12.

[0055] (Step ST143) In step ST143, as shown in Figure 9, the first region R1, which is the portion of the newly formed protective film PF that is formed on the bottom OPa of the opening OP, is removed. In step ST143, the first region R1 may be removed in the same manner as in step ST13. The process conditions for step ST143 may be the same as the process conditions for step ST13.

[0056] (Step ST144) Step ST144 is repeated, following steps ST141, ST142, and ST143. Step ST144 may be repeated until the opening OP penetrates the substrate body SWa. That is, step ST141, ST142, and ST143 may be repeated until the silicon substrate SW is diced.

[0057] In method MT1, as described above, steps ST141, ST142, and ST143 are repeated until the aperture OP penetrates the substrate body SWa, thereby dicing the silicon substrate SW as shown in Figure 10. Thus, in step ST14 of method MT1, the silicon substrate SW may be diced through the aperture OP by plasma PL2.

[0058] In method MT1, step ST14 does not necessarily include steps ST142, ST143, and ST144. In this case, in step ST141, the silicon substrate SW may be etched by plasma PL2 through the aperture OP until the aperture OP penetrates the substrate body SWa.

[0059] According to the substrate processing apparatus and method MT1 described above, a protective film PF is formed on the silicon substrate SW in step ST12. Specifically, the protective film is formed on the upper surface of the mask MK. Therefore, when etching the silicon substrate SW, the etching rate of the silicon substrate SW can be improved. In one example, the etching rate of the silicon substrate SW in step ST141 can be improved.

[0060] The mechanism by which the etching rate of the silicon substrate SW is improved by the formation of a protective film PF on the silicon substrate SW is presumed to be as follows, but is not limited to this. When the mask MK is exposed to plasma PL2 generated from a processing gas containing a halogen-containing gas, the mask MK may react with halogen ions. Such a reaction with halogen ions is more likely to occur when the mask MK contains a resist film RF. That is, when the resist film RF is exposed to plasma PL2, the resist film RF may react with halogen ions. When the mask MK reacts with halogen ions, the flux of halogen ions supplied to the silicon substrate SW to be etched in step ST141 decreases. In contrast, in method MT1, a protective film PF is formed on the upper surface of the mask MK, so the reaction between the mask MK and halogen ions can be prevented. Therefore, compared to the method in which the protective film PF is not formed, in method MT1, the flux of halogen ions supplied to the silicon substrate SW does not decrease, and as a result, the etching rate of the silicon substrate SW is presumed to be improved.

[0061] The protective film PF has a first thickness T1 on the substrate body SWa at the bottom OPa of the opening OP, and a second thickness T2 greater than the first thickness T1 on the bevel BVL. Therefore, the bevel BVL of the silicon substrate SW can be protected. In one example, damage to the bevel BVL can be suppressed during etching of the silicon substrate SW in process ST141.

[0062] In method MT1, the protective film PF may have a third thickness T3 greater than the first thickness T1 on the upper surface of the mask MK. In this case, the decrease in the etching selectivity ratio of the silicon substrate SW in step ST141 can be suppressed. It is presumed that the mechanism by which the decrease in the etching selectivity ratio of the silicon substrate SW can be suppressed when the protective film PF has a third thickness T3 on the upper surface of the mask MK is the same as the mechanism described above.

[0063] In method MT1, in step ST12, the pressure inside the plasma processing chamber 10 may be 0.1 Pa or more and 100 Pa or less. In this case, a configuration in which the protective film PF has a second thickness T2 greater than the first thickness T1 on the bevel BVL can be easily realized.

[0064] In method MT1, in step ST12, the pressure inside the plasma processing chamber 10 may be 40.0 Pa or more and 53.3 Pa or less. In this case, a configuration in which the protective film PF has a second thickness T2 greater than the first thickness T1 on the bevel BVL can be easily and reliably realized.

[0065] Figure 11 is a flowchart of a substrate processing method according to another exemplary embodiment. The substrate processing method MT2 shown in Figure 11 (hereinafter referred to as "method MT2") comprises steps ST21, ST22, ST23, ST24, and ST25. Steps ST21, ST22, ST23, ST24, and ST25 may be performed in order.

[0066] Figure 12 shows a substrate processing system according to one exemplary embodiment. In one example, method MT2 can be performed using the substrate processing system PS shown in Figure 12. The substrate processing system PS comprises load ports 102a to 102d, containers 4a to 4d, loader module LM, aligner AN, load lock modules LL1 and LL2, process modules PM1 to PM6, transport module TM, and control unit 2. The number of load ports, containers, and load lock modules in the substrate processing system PS can be one or more arbitrary numbers. Also, the number of process modules in the substrate processing system PS can be one or more arbitrary numbers.

[0067] The load ports 102a to 102d are arranged along one edge of the loader module LM. The containers 4a to 4d are each mounted on the load ports 102a to 102d. Each of the containers 4a to 4d is, for example, a container called a FOUP (Front Opening Unified Pod). Each of the containers 4a to 4d is configured to house the substrate W inside.

[0068] The loader module LM has a chamber. The pressure inside the chamber of the loader module LM is set to atmospheric pressure. The loader module LM has a transport device TU1. The transport device TU1 is, for example, a transport robot and is controlled by the control unit 2. The transport device TU1 is configured to transport the substrate W through the chamber of the loader module LM. The transport device TU1 can transport the substrate W between each of the containers 4a to 4d and the aligner AN, between the aligner AN and each of the load lock modules LL1 and LL2, and between each of the load lock modules LL1 and LL2 and each of the containers 4a to 4d. The aligner AN is connected to the loader module LM. The aligner AN is configured to adjust (calibrate) the position of the substrate W.

[0069] Load lock module LL1 and load lock module LL2 are each located between loader module LM and transport module TM. Load lock module LL1 and load lock module LL2 each provide a pre-pressure chamber.

[0070] The transport module TM is connected to each of the load lock modules LL1 and LL2 via gate valves. The transport module TM has a transport chamber TC whose internal space is configured to be depressurized. The transport module TM has a transport device TU2. The transport device TU2 is, for example, a transport robot and is controlled by the control unit 2. The transport device TU2 is configured to transport the substrate W through the transport chamber TC. The transport device TU2 can transport the substrate W between each of the load lock modules LL1 and LL2 and each of the process modules PM1 to PM6, and between any two process modules among the process modules PM1 to PM6.

[0071] Each of the process modules PM1 to PM6 is a device configured to perform a dedicated substrate processing. One of the process modules PM1 to PM6 may be the plasma processing apparatus 1 used in method MT2.

[0072] (Step ST21) In step ST21, the silicon substrate SW is placed on the substrate support (first substrate support) located in the first chamber. That is, the silicon substrate SW is provided in the first chamber. The first chamber is a chamber provided in one of the process modules PM1 to PM6 (hereinafter referred to as the "first process module").

[0073] (Step ST22) In step ST22, a protective film PF is formed on the silicon substrate SW in the first chamber. The process conditions in step ST22 may be the same as the process conditions in step ST12 of method MT1. Therefore, in step ST22 as well, a protective film PF having a first thickness T1 on the substrate body SWa and a second thickness T2 on the bevel BVL is formed on the silicon substrate SW. Similarly, in step ST22, the protective film PF may have a third thickness T3 on the upper surface of the mask MK.

[0074] (Step ST23) In step ST23, the substrate W is transported from the first chamber to the second chamber. The second chamber is a chamber provided in a process module other than the first process module (hereinafter referred to as the "second process module") among the process modules PM1 to PM6. In one example, the transport device TU2 may transport the silicon substrate SW on which the protective film PF is formed from the first chamber of the first process module to the second chamber of the second process module.

[0075] (Step ST24) In step ST24, the silicon substrate SW is placed on the substrate support (second substrate support) located in the second chamber. That is, the silicon substrate SW is provided in the second chamber. The configuration of the substrate support located in the second chamber may be different from or the same as the configuration of the substrate support located in the first chamber.

[0076] (Step ST25) In step ST25, the silicon substrate SW is diced in the second chamber. That is, in method MT2, steps ST22 and ST25 may be carried out in different chambers. Step ST25 may include steps ST251, ST252, ST253, ST254, and ST255.

[0077] Steps ST251 to ST255 can be carried out in the same manner as steps ST13 and ST141 to ST144, except that the processing is carried out in the second chamber. That is, the process conditions for step ST251 may be the same as the process conditions for step ST13 of method MT1. The process conditions for step ST252 may be the same as the process conditions for step ST141 of method MT1. The process conditions for step ST253 may be the same as the process conditions for step ST142 of method MT1. The process conditions for step ST254 may be the same as the process conditions for step ST143 of method MT1. In step ST255, as in step ST144 of method MT1, steps ST252 to ST254 may be repeated until the aperture OP penetrates the substrate body SWa, thereby dicing the silicon substrate SW. In this way, in step ST25 of method MT2, the silicon substrate SW is also diced by the plasma PL2 through the aperture OP.

[0078] In method MT2, a protective film PF is formed on the silicon substrate SW in step ST22. This improves the etching rate of the silicon substrate SW. Furthermore, it protects the bevel BVL of the silicon substrate SW.

[0079] Although various exemplary embodiments have been described above, the invention is not limited to the exemplary embodiments described above, and various additions, omissions, substitutions, and modifications may be made. Furthermore, it is possible to combine elements from different embodiments to form other embodiments.

[0080] In the method MT1 described above, the silicon substrate SW is diced in step ST14 by repeatedly etching the silicon substrate SW and forming a protective film PF. However, the dicing of the silicon substrate SW is not limited to the above-described process. For example, in addition to etching the silicon substrate SW and forming the protective film PF, grinding of the silicon substrate SW may also be performed. The dicing in this disclosure differs from so-called "etching" (processing on the nm order) in that it involves processing on the order of at least μm. In the dicing in this disclosure, processing of 10 μm or more is performed, preferably 50 μm or more. In addition, in the dicing in this disclosure, laser dicing using laser light and plasma dicing using plasma, which will be described later, may be combined, or dicing may be performed using plasma dicing alone without laser dicing.

[0081] In one example, grinding of the silicon substrate SW may be performed after the repeated etching of the silicon substrate SW and the formation of the protective film PF is completed. That is, grinding of the silicon substrate SW may be performed after step ST144. Therefore, in this example, etching of the silicon substrate SW and grinding of the silicon substrate SW are performed in this order. In this example, first, in step ST144, the repetition of steps ST141, ST142, and ST143 is completed before the opening OP penetrates the substrate body SWa. That is, at the end of step ST144, the bottom OPa of the opening OP becomes the top surface of the substrate body SWa.

[0082] Next, the etched silicon substrate SW is ground into individual pieces. In grinding the silicon substrate SW, the substrate body SWa can be ground in the direction from its bottom surface toward its top surface. Here, the top surface of the substrate body SWa is the surface on which the mask MK is placed, and the bottom surface of the substrate body SWa is the surface opposite to the top surface. Polishing of the substrate body SWa can be performed, for example, by chemical mechanical polishing (CMP).

[0083] In another example, grinding of the silicon substrate SW may be performed before the formation of the protective film PF. That is, grinding of the silicon substrate SW may be performed before step ST12. Therefore, in this example, grinding of the silicon substrate SW and etching of the silicon substrate SW are performed in this order. Grinding of the silicon substrate SW performed before step ST12 can be performed in the same way as grinding of the silicon substrate SW performed after step ST144. In this example as well, the substrate body SWa may be ground in the direction from its bottom surface toward its top surface.

[0084] In method MT2, grinding of the silicon substrate SW may be performed in the same way as in method MT1. That is, in method MT2, grinding of the silicon substrate SW may be performed after the repeated etching of the silicon substrate SW and formation of the protective film PF in the second chamber is completed. In one example, grinding of the silicon substrate SW may be performed after the repeated etching of the silicon substrate SW and formation of the protective film PF in the second chamber is completed. In this example, grinding of the silicon substrate SW may be performed in the second chamber after step ST255. Grinding of the silicon substrate SW performed after step ST255 may be performed in the same way as grinding of the silicon substrate SW performed after step ST144. In another example, grinding of the silicon substrate SW may be performed before the formation of the protective film PF in the first chamber. In this example, grinding of the silicon substrate SW may be performed in the first chamber before step ST22. Grinding of the silicon substrate SW performed before step ST22 may be performed in the same way as grinding of the silicon substrate SW performed before step ST12.

[0085] Herein, various exemplary embodiments included in this disclosure are described in [E1] to [E22] below.

[0086] [E1] A substrate processing method comprising: (a) a step of placing a silicon substrate on a substrate support in a chamber, wherein the silicon substrate has a substrate body and a mask on the substrate body, the mask providing an opening so that at least a portion of the bevel of the silicon substrate is exposed; (b) a step of forming a protective film on the silicon substrate, wherein the protective film has a first thickness on the substrate body at the bottom of the opening and a second thickness greater than the first thickness on the bevel; and (c) a step of dicing the silicon substrate through the opening with plasma generated from a processing gas containing a halogen-containing gas.

[0087] According to the substrate processing method [E1], the bevel of the silicon substrate can be protected.

[0088] [E2] The substrate processing method according to [E1], wherein the protective film has a third thickness greater than the first thickness on the upper surface of the mask, in the case of (b) above.

[0089] According to the substrate processing method [E2], it is possible to suppress a decrease in the etching selectivity ratio of the silicon substrate.

[0090] [E3] (d) The substrate processing method according to [E1] or [E2], further comprising the step of removing the portion of the protective film that is formed on the bottom after (b) and before (c).

[0091] [E4] The substrate processing method according to [E1] or [E2], wherein in (b), the pressure in the chamber containing the silicon substrate is 0.1 Pa or more and 100 Pa or less.

[0092] According to the substrate processing method [E4], a configuration in which the protective film has a second thickness greater than the first thickness on the bevel can be easily realized.

[0093] [E5] The substrate processing method according to [E4], wherein in (b), the pressure in the chamber containing the silicon substrate is 40.0 Pa or more and 53.3 Pa or less.

[0094] According to the substrate processing method [E5], a configuration in which the protective film has a second thickness greater than the first thickness on the bevel can be easily and reliably realized.

[0095] [E6] The substrate processing method according to any one of [E1] to [E5], wherein the protective film comprises a silicon-containing film or a metal-containing film.

[0096] [E7] The substrate processing method according to any one of [E1] to [E6], wherein the processing gas is a first processing gas, the plasma generated from the first processing gas is a first plasma, and in (b), the protective film is formed by a second plasma generated from a second processing gas containing a silicon-containing gas or a metal-containing gas.

[0097] [E8] The substrate processing method according to [E7], wherein the second processing gas further comprises at least one selected from the group consisting of an oxygen-containing gas, a nitrogen-containing gas, and a gas containing carbon and hydrogen.

[0098] [E9] The substrate processing method according to [E7] or [E8], wherein the metal-containing gas comprises at least one selected from the group consisting of tungsten-containing gas, tin-containing gas, molybdenum-containing gas, zirconium-containing gas, ruthenium-containing gas, titanium-containing gas, hafnium-containing gas, and tantalum-containing gas.

[0099] [E10] The substrate processing method according to any one of [E1] to [E9], wherein the mask is not provided on the bevel of the silicon substrate.

[0100] [E11] The substrate processing method according to any one of [E1] to [E10], wherein the second thickness is 100 nm or more and 1 μm or less.

[0101] [E12] The substrate processing method according to any one of [E1] to [E11], wherein the protective film is formed by plasma CVD or plasma PVD in (b).

[0102] [E13] The halogen-containing gas is SF ６ Gas, NF ３ Gas, CF ４Gas, hydrofluorocarbon gas, HF gas, IF ７ Gas, C ４ F ８ Gas, C ３ F ８ Gas, C ５ F ８ Gas, F ２ Gas, Cl ２ Gas, HCl gas, HBr gas, Br ２ Gas, BBr ３ Gas, BCl ３ Gas, BF ３ Gas, CF ３ I gas, PF ３ A substrate processing method according to any one of [E1] to [E12], comprising at least one selected from the group consisting of gas and HI gas.

[0103] [E14] A substrate processing method comprising: (a) a step of placing a silicon substrate on a substrate support in a chamber, wherein the silicon substrate has a substrate body and a mask on the substrate body, and the mask provides an opening; (b) a step of forming a protective film on the silicon substrate; and (c) a step of dicing the silicon substrate through the opening with plasma generated from a processing gas containing a halogen gas.

[0104] According to the substrate processing method [E14], the etching speed of the silicon substrate can be improved.

[0105] [E15] (d) The substrate processing method according to [E14], further comprising the step of removing the portion of the protective film that is formed at the bottom of the opening after (b) and before (c).

[0106] [E16] The substrate processing method according to [E14] or [E15], wherein the protective film is formed by plasma CVD or plasma PVD in (b).

[0107] [E17] A chamber, a substrate support for supporting a silicon substrate within the chamber, a gas supply unit configured to supply a first processing gas and a second processing gas into the chamber, wherein the first processing gas includes a halogen-containing gas, a plasma generation unit configured to generate plasma from the first processing gas within the chamber, and a control unit, wherein the control unit is configured to control the gas supply unit and the plasma generation unit to execute a dicing sequence, the dicing sequence comprising: a step of placing the silicon substrate on the substrate support, wherein the silicon substrate has a substrate body and a mask on the substrate body, wherein the mask provides an opening and at least a portion of the bevel of the silicon substrate is exposed; a step of forming a protective film on the silicon substrate with the second processing gas, wherein the protective film has a first thickness on the substrate body at the bottom of the opening and a second thickness greater than the first thickness on the bevel; and a step of dicing the silicon substrate through the opening with the plasma generated from the first processing gas. A substrate processing apparatus, including

[0108] [E18] The substrate processing apparatus according to [E17], further comprising a pressure regulating valve for adjusting the pressure in the chamber, wherein the control unit is configured to control the pressure regulating valve so that the pressure in the chamber is 0.1 Pa or more and 100 Pa or less in the step of forming the protective film.

[0109] [E19] The substrate processing apparatus according to [E18], wherein the control unit is configured to control the pressure regulating valve so that the pressure in the chamber is 40.0 Pa or more and 53.3 Pa or less in the process of forming the protective film.

[0110] [E20] A first chamber, a second chamber, a first substrate support for supporting a silicon substrate within the first chamber, a second substrate support for supporting the silicon substrate within the second chamber, a first gas supply unit configured to supply a first processing gas containing a halogen-containing gas into the second chamber, a second gas supply unit configured to supply a second processing gas into the first chamber, a plasma generation unit configured to generate plasma from the first processing gas within the second chamber, and a control unit, wherein the control unit is configured to control the first gas supply unit, the second gas supply unit, and the plasma generation unit to execute a dicing sequence, the dicing sequence comprising the steps of: placing the silicon substrate on the first substrate support unit, wherein the silicon substrate has a substrate body and a mask on the substrate body, the mask providing an opening, and at least a portion of the bevel of the silicon substrate is exposed. A substrate processing apparatus comprising: a step of forming a protective film on a silicon substrate using a second processing gas in a first chamber, wherein the protective film has a first thickness on the substrate body at the bottom of the opening and a second thickness greater than the first thickness on the bevel; a step of transporting the silicon substrate from the first chamber to the second chamber; a step of placing the silicon substrate on a second substrate support; and a step of dicing the silicon substrate through the opening using the plasma generated from the first processing gas in the second chamber.

[0111] [E21] The substrate processing apparatus according to [E20], further comprising a pressure regulating valve for adjusting the pressure in the first chamber, wherein the control unit is configured to control the pressure regulating valve so that the pressure in the first chamber is 0.1 Pa or more and 100 Pa or less in the step of forming the protective film.

[0112] [E22] The substrate processing apparatus according to [E21], wherein the control unit is configured to control the pressure regulating valve so that the pressure in the first chamber is 40.0 Pa or more and 53.3 Pa or less in the process of forming the protective film.

[0113] 1...Plasma processing apparatus, 2...Control unit, 11...Substrate support unit, 20...Gas supply unit, MK...Mask, OP...Aperture, OPa...Bottom, PF...Protective film, PL1...Second plasma, PL2...First plasma, SW...Silicon substrate.

Claims

1. A substrate processing method comprising: (a) a step of placing a silicon substrate on a substrate support portion in a chamber, wherein the silicon substrate has a substrate body and a mask on the substrate body, the mask providing an opening so that at least a portion of the bevel of the silicon substrate is exposed; (b) a step of forming a protective film on the silicon substrate, wherein the protective film has a first thickness on the substrate body at the bottom of the opening and a second thickness greater than the first thickness on the bevel; and (c) a step of dicing the silicon substrate through the opening with plasma generated from a processing gas containing a halogen-containing gas.

2. The substrate processing method according to claim 1, wherein in (b) above, the protective film has a third thickness greater than the first thickness on the upper surface of the mask.

3. (d) The substrate processing method according to claim 1 or 2, further comprising the step of removing the portion of the protective film that is formed on the bottom after (b) and before (c).

4. The substrate processing method according to claim 1 or 2, wherein in (b) above, the pressure in the chamber containing the silicon substrate is 0.1 Pa or more and 100 Pa or less.

5. The substrate processing method according to claim 4, wherein in (b) above, the pressure in the chamber containing the silicon substrate is 40.0 Pa or more and 53.3 Pa or less.

6. The substrate processing method according to claim 1 or 2, wherein the protective film includes a silicon-containing film or a metal-containing film.

7. The substrate processing method according to claim 1 or 2, wherein the processing gas is a first processing gas, the plasma generated from the first processing gas is a first plasma, and in (b), the protective film is formed by a second plasma generated from a second processing gas containing a silicon-containing gas or a metal-containing gas.

8. The substrate processing method according to claim 7, wherein the second processing gas further comprises at least one selected from the group consisting of an oxygen-containing gas, a nitrogen-containing gas, and a gas containing carbon and hydrogen.

9. The substrate processing method according to claim 7, wherein the metal-containing gas includes at least one selected from the group consisting of tungsten-containing gas, tin-containing gas, molybdenum-containing gas, zirconium-containing gas, ruthenium-containing gas, titanium-containing gas, hafnium-containing gas, and tantalum-containing gas.

10. The substrate processing method according to claim 1 or 2, wherein the mask is not provided on the bevel of the silicon substrate.

11. The substrate processing method according to claim 1 or 2, wherein the second thickness is 100 nm or more and 1 μm or less.

12. The substrate processing method according to claim 1 or 2, wherein in (b) above, the protective film is formed by plasma CVD or plasma PVD.

13. The halogen-containing gas is SF ６ gas, NF ３ gas, CF ４ gas, hydrofluorocarbon gas, HF gas, IF ７ gas, C ４ F ８ gas, C ３ F ８ gas, C ５ F ８ gas, F ２ gas, Cl ２ gas, HCl gas, HBr gas, Br ２ gas, BBr ３ gas, BCl ３ gas, BF ３ gas, CF ３ I gas, PF ３ gas, and at least one selected from the group consisting of HI gas, the substrate processing method according to claim 1 or 2.

14. A substrate processing method comprising: (a) a step of placing a silicon substrate on a substrate support portion in a chamber, wherein the silicon substrate has a substrate body and a mask on the substrate body, and the mask provides an opening; (b) a step of forming a protective film on the silicon substrate; and (c) a step of dicing the silicon substrate through the opening with plasma generated from a processing gas containing a halogen gas.

15. (d) The substrate processing method according to claim 14, further comprising the step of removing the portion of the protective film that is formed at the bottom of the opening, after (b) and before (c).

16. The substrate processing method according to claim 14 or 15, wherein the protective film is formed by plasma CVD or plasma PVD in (b).

17. A chamber, a substrate support for supporting a silicon substrate within the chamber, a gas supply unit configured to supply a first processing gas and a second processing gas into the chamber, wherein the first processing gas includes a halogen-containing gas, a plasma generation unit configured to generate plasma from the first processing gas within the chamber, and a control unit, wherein the control unit is configured to control the gas supply unit and the plasma generation unit to execute a dicing sequence, the dicing sequence comprising: a step of placing the silicon substrate on the substrate support unit, wherein the silicon substrate has a substrate body and a mask on the substrate body, the mask providing an opening, and at least a portion of the bevel of the silicon substrate being exposed; a step of forming a protective film on the silicon substrate with the second processing gas, wherein the protective film has a first thickness on the substrate body at the bottom of the opening and a second thickness greater than the first thickness on the bevel; and a step of dicing the silicon substrate through the opening with the plasma generated from the first processing gas. A substrate processing apparatus, including 18. The substrate processing apparatus according to claim 17, further comprising a pressure regulating valve for adjusting the pressure in the chamber, wherein the control unit is configured to control the pressure regulating valve so that the pressure in the chamber is 0.1 Pa or more and 100 Pa or less in the step of forming the protective film.

19. The substrate processing apparatus according to claim 18, wherein the control unit is configured to control the pressure regulating valve so that the pressure in the chamber is 40.0 Pa or more and 53.3 Pa or less in the process of forming the protective film.

20. The apparatus comprises: a first chamber; a second chamber; a first substrate support portion for supporting a silicon substrate within the first chamber; a second substrate support portion for supporting the silicon substrate within the second chamber; a first gas supply unit configured to supply a first processing gas containing a halogen-containing gas into the second chamber; a second gas supply unit configured to supply a second processing gas into the first chamber; a plasma generation unit configured to generate plasma from the first processing gas within the second chamber; and a control unit, wherein the control unit is configured to control the first gas supply unit, the second gas supply unit, and the plasma generation unit to execute a dicing sequence, the dicing sequence comprising: a step of placing the silicon substrate on the first substrate support portion, wherein the silicon substrate comprises a substrate body and a mask on the substrate body, the mask providing an opening, and at least a portion of the bevel of the silicon substrate is exposed. A substrate processing apparatus comprising: a step of forming a protective film on a silicon substrate using a second processing gas in a first chamber, wherein the protective film has a first thickness on the substrate body at the bottom of the opening and a second thickness greater than the first thickness on the bevel; a step of transporting the silicon substrate from the first chamber to the second chamber; a step of placing the silicon substrate on a second substrate support; and a step of dicing the silicon substrate through the opening using the plasma generated from the first processing gas in the second chamber.

21. The substrate processing apparatus according to claim 20, further comprising a pressure regulating valve for adjusting the pressure in the first chamber, wherein the control unit is configured to control the pressure regulating valve so that the pressure in the first chamber is 0.1 Pa or more and 100 Pa or less in the step of forming the protective film.

22. The substrate processing apparatus according to claim 21, wherein the control unit is configured to control the pressure regulating valve so that the pressure in the first chamber is 40.0 Pa or more and 53.3 Pa or less in the process of forming the protective film.

Images