Semiconductor circuit device, display device, and electronic appliance

Abstract

Provided is a semiconductor circuit device provided with a transistor of a first conductivity type and a transistor of a second conductivity type adjacent to each other, in which the latch-up resistance can be improved.　A semiconductor circuit device according to the present invention is provided with: a semiconductor substrate of a first conductivity type; a well of a second conductivity type, provided with at least one transistor of the first conductivity type; a well of the first conductivity type, provided with at least one transistor of the second conductivity type; and a deep well of the second conductivity type, provided between the wells of the first conductivity type and the second conductivity type and the semiconductor substrate of the first conductivity type. The deep well of the second conductivity type is electrically separated at a position corresponding to a position between the transistor of the first conductivity type and the transistor of the second conductivity type by a part of the semiconductor substrate of the first conductivity type.

Description

Semiconductor circuit devices, display devices, and electronic devices

[0001] This disclosure relates to semiconductor circuit devices, display devices and electronic devices equipped therewith.

[0002] In recent years, there has been a demand for improved latch-up resistance in semiconductor circuit devices that use a triple-well structure as their layout structure. To meet this demand, for example, Patent Document 1 considers preventing the risk of latch-up by separating the deep N-type wells that constitute the I / O logic area from the deep N-type wells that constitute the I / O buffer area.

[0003] Japanese Patent Publication No. 2016-066823

[0004] In recent years, there has been a desire to improve latch-up resistance in semiconductor circuit devices comprising adjacent transistors of a first conductivity type and a second conductivity type. However, Patent Document 1 does not discuss any techniques for improving latch-up resistance in semiconductor circuit devices with such a configuration.

[0005] The object of this disclosure is to provide a semiconductor circuit device, a display device, and an electronic device that can improve latch-up resistance in a semiconductor circuit device comprising adjacent transistors of a first conductivity type and a second conductivity type.

[0006] To solve the above-mentioned problems, a semiconductor circuit device according to a first aspect of the present disclosure comprises: a semiconductor substrate of a first conductivity type; a well of a second conductivity type provided with at least one transistor of the first conductivity type; a well of the first conductivity type provided with at least one transistor of the second conductivity type; and a deep well of a second conductivity type provided between the wells of the first conductivity type and the well of the second conductivity type and the semiconductor substrate of the first conductivity type, wherein the deep well of the second conductivity type is electrically isolated by a part of the semiconductor substrate of the first conductivity type at a position corresponding to the space between the transistor of the first conductivity type and the transistor of the second conductivity type.

[0007] A semiconductor circuit device according to a second aspect of the present disclosure comprises a plurality of semiconductor circuit sections, at least one of the plurality of semiconductor circuit sections comprising: a semiconductor substrate of a first conductivity type; a well of a second conductivity type provided with at least one transistor of the first conductivity type; a well of the first conductivity type provided with at least one transistor of the second conductivity type; and a deep well of a second conductivity type provided between the well of the first conductivity type, the well of the second conductivity type, and the semiconductor substrate of the first conductivity type, wherein the deep well of the second conductivity type is electrically isolated by a portion of the semiconductor substrate of the first conductivity type at a position corresponding to the position between the transistor of the first conductivity type and the transistor of the second conductivity type.

[0008] Figure 1 is a block diagram of a display device according to the first embodiment. Figure 2 is a schematic diagram of the vertical analog section. Figure 3 is an enlarged view of the vertical analog section. Figure 4 is a diagram of a CMOS circuit. Figure 5 is an enlarged view of the vertical analog section of a semiconductor circuit device according to a comparative example. Figure 6 is a diagram of the equivalent circuit of a parasitic transistor circuit and a parasitic thyristor formed by the parasitic transistor circuit. Figure 7 is a block diagram of a display device according to the second embodiment. Figure 8 is a block diagram of a display device according to a modified example. Figure 9 is an enlarged view of the vertical analog section of the display device according to a modified example. Figure 10 is an enlarged view of the vertical analog section of the display device according to a modified example. Figure 11 is a schematic diagram of the vertical analog section and pixel circuit section of the display device according to a modified example. Figure 12 is an enlarged view of the portion between the vertical analog section and the pixel circuit section of the display device according to a modified example. Figure 13 is a schematic diagram of the horizontal analog section and pixel circuit section of the display device according to a modified example. Figure 14 is an enlarged view of the vertical analog section and pixel circuit section of the display device according to a modified example. Figure 15 is a schematic diagram of the power supply processing section of the display device according to a modified example. Figure 16 is an enlarged view of region 113R in Figure 15. Figure 17 is a schematic diagram of the gamma processing unit of a modified display device. Figure 18 is an enlarged view of region 112R in Figure 17. Figure 19 is an enlarged view of the output switch shown in Figure 17. Figure 20A is a front view of a digital still camera. Figure 20B is a rear view of a digital still camera. Figure 21 is a perspective view of a head-mounted display. Figure 22 is a perspective view of a see-through head-mounted display.

[0009] The embodiments of this disclosure will be described in the following order: 1. General description of semiconductor circuit devices according to the first and second embodiments of this disclosure 2. First embodiment (example of a display device) 3. Second embodiment (example of a display device) 4. Modifications 5. Application examples (example of an electronic device)

[0010] The embodiments described below are preferred examples of the present disclosure, and the content of the present disclosure is not limited to these embodiments. In all the figures of the following embodiments, the same or corresponding parts are denoted by the same reference numerals. In addition, in order to prevent the illustration from becoming complicated, only some components may be denoted by reference numerals, or the illustration may be simplified, enlarged, or reduced.

[0011] <1. General Description of Semiconductor Circuit Devices According to the First Aspect of the Disclosure and Semiconductor Circuit Devices According to the Second Aspect of the Disclosure> In the semiconductor circuit devices according to the first aspect of the Disclosure and the semiconductor circuit devices according to the second aspect of the Disclosure, the deep well of the second conductivity type is electrically isolated by a part of the semiconductor substrate of the first conductivity type at a position corresponding to the space between the transistor of the first conductivity type and the transistor of the second conductivity type. This structurally eliminates the path through which a parasitic thyristor turns on between adjacent transistors of the first conductivity type and the transistor of the second conductivity type. Therefore, in a semiconductor circuit device comprising adjacent transistors of the first conductivity type and the transistor of the second conductivity type, latch-up resistance can be improved.

[0012] In the first and second embodiments of this disclosure, the semiconductor circuit device further comprises an input / output section that can be connected to the outside, and one or both of the first conductivity type transistors and the second conductivity type transistors may be connected to the input / output section. In this case, the risk of noise flowing into one or both of the transistors from the outside via the input / output section increases. Therefore, when one or both of the transistors are connected to the outside of the semiconductor circuit device, it is particularly effective to employ the isolation structure of the second conductivity type deep well to structurally eliminate the path through which the parasitic thyristor turns on.

[0013] In the first and second embodiments of this disclosure, the device further comprises an input / output section that can be connected to a negative power supply, wherein the well of the first conductivity type is a P-type well, and the well of the first conductivity type may be connected to a negative power supply via the input / output section. When the well of the first conductivity type, which is a P-type well, is connected to a negative power supply via the input / output section, the risk of noise flowing into one or both of the transistors of the first conductivity type and the second conductivity type increases. Therefore, when the well of the first conductivity type, which is a P-type well, is connected to a negative power supply via the input / output section, it is particularly effective to adopt the isolation structure of the deep well of the second conductivity type described above and structurally eliminate the path through which the parasitic thyristor turns on.

[0014] In the first and second embodiments of this disclosure, the first and second conductivity types may be P-type and N-type, respectively, or the first and second conductivity types may be N-type and P-type, respectively. Regardless of whether the semiconductor substrate is P-type or N-type, by employing the above-described separation structure of the deep well of the second conductivity type, the path through which the parasitic thyristor turns on can be structurally eliminated.

[0015] In the first and second embodiments of the present disclosure, it is preferable that at least one transistor of a first conductivity type includes a plurality of transistors of the first conductivity type, the plurality of transistors of the first conductivity type sharing a well of a second conductivity type, and at least one transistor of a second conductivity type includes a plurality of transistors of the second conductivity type, the plurality of transistors of the second conductivity type sharing a well of the first conductivity type. Such a configuration is advantageous when there are limitations on the size of the region in which the plurality of transistors of the first conductivity type and the plurality of transistors of the second conductivity type are provided.

[0016] In the first and second embodiments of this disclosure, the wells of the first conductivity type and the wells of the second conductivity type may be contained within the same circuit block. In this case, the path through which the parasitic thyristor turns on can be structurally eliminated within the circuit block. When the wells of the first conductivity type and the wells of the second conductivity type are contained within the same circuit block, the transistors of the first conductivity type and the transistors of the second conductivity type may constitute a complementary metal-oxide-semiconductor.

[0017] In the first and second embodiments of this disclosure, the well of a first conductivity type may be contained in a first circuit block, and the well of a second conductivity type may be contained in a second circuit block adjacent to the first circuit block. In this case, the path through which the parasitic thyristor turns on between the first and second circuit blocks can be structurally eliminated.

[0018] In the first and second embodiments of this disclosure, the well of the first conductivity type may be included in the pixel circuit, and the well of the second conductivity type may be included in a driver adjacent to the pixel circuit. In this case, the path through which the parasitic thyristor turns on between the pixel circuit and the driver can be structurally eliminated.

[0019] In the first and second embodiments of this disclosure, the first-voltage transistor and the second-voltage transistor may be high-voltage transistors of 5.0V or higher. When the first-voltage transistor and the second-voltage transistor are high-voltage transistors of 5.0V or higher, if the deep well of the second-voltage transistor is connected between the well of the first-voltage transistor and the well of the second-voltage transistor, the well potential fluctuation that triggers latch-up is large, making it easy for the base-emitter voltage of the parasitic bipolar transistor to exceed Vf, and as a result, the parasitic bipolar transistor tends to be turned on more easily. For this reason, when the first-voltage transistor and the second-voltage transistor are high-voltage transistors, it is preferable to adopt the above-described separation structure of the deep well of the second-voltage transistor. The high-voltage transistor may be 6.0V or higher. In this case, it is even more preferable to adopt the above-described separation structure of the deep well of the second-voltage transistor.

[0020] The semiconductor circuit device according to the first aspect of this disclosure and the semiconductor circuit device according to the second aspect of this disclosure may be provided in a display device. The display device may be a display device that can be mounted on an electronic device.

[0021] The semiconductor circuit devices according to the first aspect of this disclosure and the semiconductor circuit devices according to the second aspect of this disclosure may be installed in electronic devices. Examples of such electronic devices include eyewear devices, digital cameras (e.g., digital video cameras, digital SLR cameras, etc.), smartphones (mobile phones), television equipment, audio equipment, game equipment, medical equipment, and measuring equipment. Specific examples of eyewear devices include VR (Virtual Reality) devices, MR (Mixed Reality) devices, and AR (Augmented Reality) devices. Headsets are also included in the definition of eyewear devices.

[0022] <2 First Embodiment> [Configuration of Display Device 10] Figure 1 is a block diagram of the display device 10 according to the first embodiment. The display device 10 comprises a semiconductor circuit device 11 and a display unit 12 provided on one side of the semiconductor circuit device 11. The display device 10 may be a microdisplay.

[0023] (Semiconductor Circuit Device 11) The semiconductor circuit device 11 is a so-called backplane and includes a semiconductor substrate 20. An input / output unit (IO) 111, a gamma processing unit 112, a power supply processing unit 113, an interface unit (IF) 114, a timing controller (TCON) 115, a horizontal logic unit (HLOGIC) 116H, a horizontal analog unit (HANALOG) 117H, a vertical logic unit (VLOGIC) 116V, a vertical analog unit (VANALOG) 117V, and a pixel circuit unit (not shown) are mounted on one side of the semiconductor substrate 20. In this disclosure, the semiconductor circuit device 11 refers to the semiconductor substrate 20 on which each circuit block is mounted.

[0024] (Semiconductor Substrate 20) In the first embodiment, the semiconductor substrate 20 is a P-type semiconductor substrate. A P-type semiconductor substrate is an example of a first conductivity type semiconductor substrate. The semiconductor substrate 20 is preferably a silicon substrate. The silicon substrate includes, for example, amorphous silicon, polycrystalline silicon, or single-crystal silicon.

[0025] (Input / Output Unit 111) The input / output unit 111 can be connected to the outside of the display device 10 (i.e., outside of the semiconductor circuit device 11) and performs input / output of various data, etc., and is composed of, for example, pads. The input / output unit 111 may be configured to be connectable to an FPC (Flexible Printed Circuits). In this case, the input / output unit 111 may be connected to the main board of an electronic device, etc. via the FPC. The input / output unit 111 is connected to the gamma processing unit 112, the power processing unit 113 and the interface unit 114.

[0026] (Gamma Processing Unit 112) The gamma processing unit 112 performs gamma correction processing. The gamma processing unit 112 is connected to the input / output unit 111 and the horizontal analog unit 117H. The gamma processing unit 112 sets the gamma correction based on the gamma correction setting value input via the input / output unit 111. As a result, the pixel signal output from the horizontal analog unit 117H to the display unit 12 is gamma corrected.

[0027] (Power Processing Unit 113) The power processing unit 113 is a circuit that outputs power for driving the display unit 12, and includes, for example, an LDO (Low Drop Out) regulator. The power processing unit 113 is connected to the input / output unit 111 and the pixel circuit unit. The power processing unit 113 converts the power supply input via the input / output unit 111 into a power supply voltage for driving the display unit 12 and supplies it to the pixel circuit unit.

[0028] (Interface Unit 114) The interface unit 114 is connected to the input / output unit 111 and the timing controller 115. The interface unit 114 is an interface for inputting and outputting image data and the like to the outside world via the input / output unit 111. For this interface, a high-speed interface standard such as MIPI (Mobile Industry Processor Interface) can be adopted, for example.

[0029] (Timing Controller 115) The timing controller 115 controls the operating timing of each circuit block. The timing controller 115 is connected to the interface unit 114, the horizontal logic unit 116H, the horizontal analog unit 117H, the vertical logic unit 116V, and the vertical analog unit 117V. Based on a clock signal supplied from an oscillator unit (not shown), the timing controller 115 outputs image data and the like, which are input via the input / output unit 111 and the interface unit 114, to the horizontal logic unit 116H, and also outputs signals as needed to the horizontal logic unit 116H and the horizontal analog unit 117H. In addition, based on the above clock signal, the timing controller 115 outputs signals as needed to the vertical logic unit 116V and the vertical analog unit 117V.

[0030] (Horizontal logic unit 116H, horizontal analog unit 117H) The horizontal logic unit 116H and the horizontal analog unit 117H constitute a horizontal driver. The horizontal driver may be configured as a RAMPDAC type circuit that uses a ramp waveform analog signal to generate the pixel signal to be output to the signal line. The horizontal driver is not limited to this, and may be configured as a voltage follower type circuit that has a voltage follower circuit at the output section to the signal line, for example. The horizontal logic unit 116H distributes the image data input from the timing controller 115 to each signal line. The horizontal analog unit 117H converts the distributed image data into a gamma-corrected pixel signal and outputs it to the corresponding signal line of the pixel circuit unit.

[0031] The horizontal logic unit 116H and the horizontal analog unit 117H are arranged on one of the vertical sides of the display unit 12 in a plan view. The horizontal analog unit 117H is positioned in front of the horizontal logic unit 116H when viewed from the display unit 12. The vertical direction of the display unit 12 is an example of the first of two orthogonal directions within the plane of the display unit 12.

[0032] (Vertical logic section 116V, vertical analog section 117V) The vertical logic section 116V and the vertical analog section 117V constitute a vertical driver. The vertical driver can be configured as, for example, a shift register type circuit having a shift register circuit in the signal input section. The vertical driver is not limited to this, and may be configured as, for example, an address decoder type circuit having an address decoder in the signal input section. The vertical logic section 116V generates a shift signal for each row of subpixels from the signal input from the timing controller 115. The vertical analog section 117V generates a control signal to drive the scan lines (control lines) using the shift signal and outputs it to the display section 12.

[0033] The vertical logic section 116V and the vertical analog section 117V are arranged on one side in the horizontal direction of the display section 12 in a plan view. The vertical analog section 117V is arranged closer to the front side than the vertical logic section 116V when viewed from the display section 12. The horizontal direction of the display section 12 is an example of the second direction among the first direction and the second direction orthogonal to each other in the plane of the display section 12.

[0034] (Pixel circuit section) The pixel circuit section controls the driving of the pixels included in the display section 12 in response to signals from the horizontal driver and the vertical driver. The semiconductor circuit device 11 has a display section mounting region where the display section 12 is provided, and includes a pixel circuit section in this display section mounting region. The pixel circuit section includes, for example, a plurality of driving transistors, a plurality of capacitive elements, a plurality of signal lines, a plurality of scanning lines, and the like.

[0035] The plurality of signal lines extend in the vertical direction of the display section 12. The signal lines are provided for each column of sub-pixels. The signal lines connect the output terminals of the horizontal analog section 117H and each sub-pixel constituting the column of sub-pixels corresponding to the output terminals. The plurality of scanning lines extend in the horizontal direction of the display section 12. The scanning lines are provided for each row of sub-pixels. The scanning lines connect the output terminals of the vertical analog section 117V and each sub-pixel constituting the row of sub-pixels corresponding to the output terminals. Here, the column of sub-pixels represents a group of pixels arranged in the vertical direction of the display section 12, and the row of sub-pixels represents a group of pixels arranged in the vertical direction of the display section 12.

[0036] (Display section 12) The display section 12 is configured to be able to display a color image. However, the color representation of the image is not limited to this, and the display section 12 may be configured to be able to display, for example, a monochrome (black and white) image. In the first embodiment, the display section 12 has a rectangular shape in a plan view. However, the shape of the display section 12 is not limited to a rectangular shape and can be arbitrarily selected. The display section 12 includes a plurality of sub-pixels. The plurality of sub-pixels are two-dimensionally arranged in a predetermined arrangement pattern. The predetermined arrangement pattern may be, for example, a stripe arrangement, a delta arrangement, a mosaic arrangement, a square arrangement, or other arrangements.

[0037] The plurality of sub-pixels includes a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels. The first sub-pixel is, for example, a red sub-pixel that can emit red light. The second sub-pixel is a green sub-pixel that can emit green light. The third sub-pixel is a blue sub-pixel that can emit blue light. One pixel (one pixel) is composed of, for example, three sub-pixels of adjacent first sub-pixel, second sub-pixel, and third sub-pixel. However, the configuration of one pixel is not limited to this example, and one pixel may be composed of four sub-pixels or more sub-pixels.

[0038] The sub-pixel includes a light-emitting element. More specifically, for example, the first sub-pixel includes a red light-emitting element that can emit red light, the second sub-pixel includes a green light-emitting element that can emit green light, and the third sub-pixel may include a blue light-emitting element that can emit blue light. The plurality of light-emitting elements includes, for example, at least one type of light-emitting element selected from the group consisting of an organic light-emitting diode (OLED) element, a light-emitting diode (LED) element, a quantum dot light-emitting diode (QLED) element, a liquid crystal display element, and a semiconductor laser element. The plurality of light-emitting elements may include a plurality of invisible light-emitting elements that can emit invisible light (for example, ultraviolet light, near-infrared light, or infrared light, etc.).

[0039] At least a part of the plurality of sub-pixels may further include a color filter provided above or on the light-emitting element. More specifically, for example, the first sub-pixel further includes a red filter provided above or on a white light-emitting element, the second sub-pixel further includes a green filter provided above or on a white light-emitting element, and the third sub-pixel may further include a blue filter provided above or on a white light-emitting element. Here, the white light-emitting element represents a light-emitting element that can emit white light. At least a part of the plurality of sub-pixels may include a color conversion layer provided above or on the light-emitting element.

[0040] [Configuration of the Vertical Analog Section 117V] Figure 2 is a schematic diagram of the vertical analog section 117V. The vertical analog section 117V has a first region 117VA and a second region 117VB. The first region 117VA is a region containing a plurality of high-voltage transistors. Specifically, the first region 117VA is an output circuit region including an output buffer (BUF), etc. The second region 117VB is a region containing a plurality of low-voltage transistors with a lower voltage rating than the plurality of high-voltage transistors in the first region 117VA. The voltage rating of the high-voltage transistors is, for example, 5.0V or higher. The voltage rating of the low-voltage transistors is, for example, less than 5.0V.

[0041] The first region 117VA and the second region 117VB each have an elongated shape (specifically, for example, a long, narrow rectangle) that extends along one of the two horizontal sides of the display unit 12 in a plan view. The first region 117VA is positioned in front of the second region 117VB when viewed from the display unit 12.

[0042] The vertical analog section 117V includes in a first region 117VA one N-type well 31 provided with a plurality of P-channel MOSFETs 30Tr, one P-type well 41 provided with a plurality of N-channel MOSFETs 40Tr, and one N-type well 45 surrounding the side of the P-type well 41. The vertical analog section 117V includes, for example, one N-type well 61 in a second region 117VB. In the first embodiment, an example is described in which the N-type well 31 and the P-type well 41 are included in the same circuit block, the vertical analog section 117V.

[0043] Multiple P-channel MOSFETs 30Tr are arranged in a line along the longitudinal direction (extension direction) of the first region 117VA, and multiple N-channel MOSFETs 40Tr are arranged in a line along the longitudinal direction (extension direction) of the first region 117VA. A pair of P-channel MOSFETs 30Tr and N-channel MOSFETs 40Tr are aligned in the width direction of the first region 117VA. A CMOS (Complementary Metal Oxide Semiconductor) 20Tr is formed by a pair of P-channel MOSFETs 30Tr and N-channel MOSFETs 40Tr aligned in the width direction of the first region 117VA. A diagram of the CMOS circuit is shown in Figure 4. In the first embodiment, the P-channel MOSFETs 30Tr and N-channel MOSFETs 40Tr are connected to a noise inflow source outside the display device 10 (i.e., outside the semiconductor circuit device 11) via an input / output unit 111, etc.

[0044] Figure 2 shows an example in which the row of N-channel MOSFETs 40Tr is arranged on the display unit 12 side, and the row of P-channel MOSFETs 30Tr is arranged on the second region 117VB side, opposite to the display unit 12 side. However, the positional relationship between the row of P-channel MOSFETs 30Tr and the row of N-channel MOSFETs 40Tr is not limited to this example, and the positional relationship may be the opposite of the example shown in Figure 2.

[0045] Figure 3(a) is an enlarged plan view of a part of the first region 117VA. Figure 3(b) is a cross-sectional view along line A-A in Figure 3(a). The vertical analog section 117V further includes two N-type deep wells 51 in the first region 117VA. The semiconductor substrate 20, the N-type deep wells 51, the N-type well 31, and the P-type well 41 constitute a triple-well structure. That is, the vertical analog section 117V has a triple-well structure in the first region 117VA.

[0046] Figure 2 shows an example where multiple P-channel MOSFETs 30Tr share one N-type well 31, but as shown in Figure 3, each of the multiple P-channel MOSFETs 30Tr may have its own individual N-type well 31. Also, Figure 2 shows an example where multiple N-channel MOSFETs 40Tr share one P-type well 41, but as shown in Figure 3, each of the multiple N-channel MOSFETs 40Tr may have its own individual P-type well 41.

[0047] (P-channel MOSFET 30Tr) The P-channel MOSFET 30Tr is an example of a first-conductivity type transistor. The P-channel MOSFET 30Tr includes a gate electrode 32, a source region 33S which is a P-type diffusion layer, and a drain region 33D which is a P-type diffusion layer.

[0048] The gate electrode 32 is connected to the gate input terminal. The source region 33S is connected to the power supply VDD. The drain region 33D is connected to a noise inflow source outside the display device 10 (i.e., outside the semiconductor circuit device 11) via the input / output unit 111, etc.

[0049] The gate electrode 32 is located above the channel region between the source region 33S and the drain region 33D of the N-type well 31, and a gate insulating layer (not shown) is sandwiched between the gate electrode 32 and the channel region.

[0050] The gate electrode 32 includes, for example, at least one metal selected from the group consisting of titanium (Ti), tungsten (W), tantalum (Ta), aluminum (Al), molybdenum (Mo), silver (Ag), neodymium (Nd), and copper (Cu). The gate electrode 32 may include the above at least one metal as a constituent element of an alloy, or it may include the above at least one metal as a constituent element of a compound such as a nitride. A specific example of a nitride is titanium nitride (TiN ｘ Examples include: The gate electrode 32 may have a single-layer structure or a multilayer structure. A specific example of a multilayer gate electrode 32 is a multilayer film of a titanium film and a titanium nitride film. In this case, the titanium film may be provided on the gate insulating layer side.

[0051] The gate insulating layer is, for example, silicon oxide (SiO ｘ ), silicon nitride (SiN ｘ ) and silicon oxynitride (SiO ｘ N ｙ It includes at least one selected from the group consisting of ) etc. The gate insulating layer may have a single layer structure or a multilayer structure.

[0052] The source region 33S and the drain region 33D are P-type semiconductor regions provided within the N-type well 31. The P-type semiconductor region is an impurity region doped with P-type impurities. The source region 33S and the drain region 33D are provided spaced apart on one side of the semiconductor circuit device 11.

[0053] (N-channel MOSFET 40Tr) The N-channel MOSFET 40Tr is an example of a second-conductivity type transistor. The N-channel MOSFET 40Tr includes a gate electrode 42, a source region 43S which is an N-type diffusion layer, and a drain region 43D which is an N-type diffusion layer.

[0054] The gate electrode 42 is connected to the gate input terminal. The source region 43S is connected to the power supply VSS2. The drain region 43D is connected to a noise inflow source outside the display device 10 (i.e., outside the semiconductor circuit device 11) via the input / output unit 111, etc.

[0055] The gate electrode 42 is located above the channel region between the source region 43S and the drain region 43D of the P-type well 41, and a gate insulating layer (not shown) is sandwiched between the gate electrode 42 and the channel region.

[0056] The materials and structure of the gate electrode 42 can be similar to those of the gate electrode 32. The materials and structure of the gate insulating layer can be similar to those of the gate insulating layer provided below the gate electrode 32.

[0057] The source region 43S and the drain region 43D are N-type semiconductor regions provided within the P-type well 41. The N-type semiconductor region is an impurity region doped with N-type impurities. The source region 43S and the drain region 43D are provided spaced apart on one side of the semiconductor circuit device 11.

[0058] (N-type well 31) The N-type well 31 is an N-type semiconductor region provided on one side of the semiconductor circuit device 11. The N-type well 31 is an example of a second-conductivity well. As shown in Figure 2, the N-type well 31 has an elongated shape (specifically, for example, a long, narrow rectangular shape) in a plan view, extending in the longitudinal direction (extension direction) of the first region 117VA. Multiple P-channel MOSFETs 30Tr arranged in a row are provided in one N-type well 31. That is, multiple P-channel MOSFETs 30Tr arranged in a row share one N-type well 31.

[0059] However, the N-type well 31 is not limited to the example shown in Figure 2. For example, as shown in Figure 3, the N-type well 31 may have a dot-like shape in plan view, and a plurality of N-type wells 31 may be arranged in a line in the longitudinal direction (extension direction) of the first region 117VA. In this case, a plurality of P-channel MOSFETs 30Tr arranged in a line may each be provided in an individual N-type well 31.

[0060] A contact region 34 is provided within an N-type well 31. The contact region 34 is an N-type diffusion layer. For example, in a plan view, the contact region 34 has a closed-loop shape surrounding the P-channel MOSFET 30Tr. However, the shape of the contact region 34 is not limited to this example. The contact region 34 is connected to the power supply VDD.

[0061] (P-type well 41) The P-type well 41 is a P-type semiconductor region provided on one side of the semiconductor circuit device 11. The P-type well 41 is an example of a well of the first conductivity type. As shown in Figure 2, the P-type well 41 has an elongated shape (specifically, for example, a long, narrow rectangular shape) in a plan view, extending in the longitudinal direction (extension direction) of the first region 117VA. Multiple N-channel MOSFETs 40Tr arranged in a row are provided in one P-type well 41. That is, multiple N-channel MOSFETs 40Tr arranged in a row share one P-type well 41.

[0062] However, the P-type well 41 is not limited to the example shown in Figure 2. For example, as shown in Figure 3, the P-type well 41 may have a dot shape in plan view, and a plurality of P-type wells 41 may be arranged in a line in the longitudinal direction (extension direction) of the first region 117VA. In this case, a plurality of N-channel MOSFETs 40Tr arranged in a line may each be provided in an individual P-type well 41.

[0063] A contact region 44 is provided within a P-type well 41. The contact region 44 is a P-type diffusion layer. For example, in a plan view, the contact region 44 has a closed-loop shape surrounding the N-channel MOSFET 40Tr. However, the shape of the contact region 44 is not limited to this example. The contact region 44 is connected to a power supply VSS 2.

[0064] (N-type well 45) The N-type well 45 is an N-type semiconductor region provided on one side of the semiconductor circuit device 11. The N-type well 45 covers the outer side surface of the P-type well 41. In a plan view, the N-type well 45 has a closed loop shape surrounding the P-type well 41.

[0065] A contact region 46 is provided within an N-type well 45. The contact region 46 is an N-type semiconductor region. For example, in a plan view, the contact region 46 has a closed-loop shape surrounding a P-type well 41. However, the shape of the contact region 34 is not limited to this example. The contact region 46 is connected to a power supply VDD.

[0066] (Wall portion 21) The P-type semiconductor substrate 20 has a wall portion 21 on one side. The wall portion 21 is positioned perpendicular to one side of the semiconductor substrate 20. The wall portion 21 is integrally formed with the main body of the P-type semiconductor substrate 20 and is made of P-type semiconductor material, just like the main body of the P-type semiconductor substrate 20. The wall portion 21 separates the rows of P-channel MOSFETs 30Tr and the rows of N-channel MOSFETs 40Tr. That is, the wall portion 21 separates the N-type well 31 and the N-type well 45, and electrically isolates the N-type deep well 51 at a position corresponding to the space between the P-channel MOSFETs 30Tr and the N-channel MOSFETs 40Tr.

[0067] As shown in Figure 2, if multiple P-channel MOSFETs 30Tr share one N-type well 31, and multiple N-channel MOSFETs 40Tr arranged in a row share one P-type well 41 and one N-type well 45, the wall portion 21 may cover the side surface of one N-type well 31 and the outer side surface of one N-type well 45. However, as shown in Figure 3, if each of the multiple P-channel MOSFETs 30Tr has its own individual N-type well 31, and each of the multiple N-channel MOSFETs 40Tr has its own individual P-type well 41 and N-type well 45, the wall portion 21 may cover the side surfaces of each of the multiple N-type wells 31 and the outer side surfaces of each of the multiple N-type wells 45.

[0068] The wall portion 21 has a contact region 22, which is a P-type diffusion layer, at its tip. The contact region 22 is provided, for example, to surround an N-type well 31 and an N-type well 45 in a plan view. However, the contact region 34 is not limited to this example. The contact region 22 is connected to the power supply VSS.

[0069] (N-type deep well 51) The N-type deep well 51 is an example of a first-conductivity deep well. The N-type deep well 51 is an N-type semiconductor region. The N-type deep well 51 is located below the N-type well 31, the P-type well 41, and the N-type well 45. That is, the N-type deep well 51 is located between the N-type well 31, the P-type well 41, the N-type well 45 and the semiconductor substrate 20.

[0070] An interface may or may not be provided between the N-type well 31 and the N-type deep well 51. Similarly, an interface may or may not be provided between the N-type well 45 and the N-type deep well 51. In Figure 3(b), the location of the above interface is shown by a dashed line.

[0071] The N-type deep well 51 is electrically isolated by the wall portion 21 of the semiconductor substrate 20 (i.e., a part of the semiconductor substrate 20) at a position corresponding to the space between the P-channel MOSFET 30Tr and the N-channel MOSFET 40Tr. The P-type well 41 is surrounded by the N-type well 45 and the N-type deep well 51. As a result, the P-type well 41 has a structure independent of the semiconductor substrate 20.

[0072] [Effects] To facilitate understanding of the effects obtained by the semiconductor circuit device 11 provided in the display device 10 according to the first embodiment, the effects obtained by the semiconductor circuit device 11 will be explained by comparing the configuration of the semiconductor circuit device 11M according to Comparative Example 1 with the configuration of the semiconductor circuit device 11.

[0073] Figure 5(a) is an enlarged plan view of the vertical analog section of the semiconductor circuit device 11M according to Comparative Example 1. Figure 5(b) is a cross-sectional view along the line A-A in Figure 5(a). The semiconductor circuit device 11M according to Comparative Example 1 differs from the semiconductor circuit device 11 according to the first embodiment in the following respects: The N-type well 31 and the P-type well 41 are provided adjacent to each other. In addition, the N-type deep well 151 is not separated at a position corresponding to the space between the P-channel MOSFET 30Tr and the N-channel MOSFET 40Tr, but is connected.

[0074] In the semiconductor circuit device 11M according to Comparative Example 1, a parasitic transistor circuit is formed as shown in Figure 5(b). Figure 6(a) is the equivalent circuit of the parasitic transistor circuit shown in Figure 5(b). The parasitic transistor circuit includes a PNP-type parasitic transistor 35, a PNP-type parasitic transistor 36, a parasitic resistor 37, an NPN-type parasitic transistor 47, and a parasitic resistor 48.

[0075] The PNP parasitic transistor 35 is formed by a path from the source region 33S connected to the power supply VDD, through the N-type well 31 and the N-type deep well 151, to the P-type well 41. The PNP parasitic transistor 36 is formed by a path from the drain region 33D connected to the noise inflow source (output terminal), through the N-type well 31 and the N-type deep well 151, to the P-type well 41. The parasitic resistor 37 is located between the contact region 34 and the base of the PNP parasitic transistor 35.

[0076] The NPN parasitic transistor 47 is formed by a path from the source region 43S connected to the power supply VSS2, through the P-type well 41 and the N-type deep well 151, to the N-type well 31. The parasitic resistor 48 is located between the contact region 44 and the base of the NPN parasitic transistor 47.

[0077] In the semiconductor circuit device 11M according to Comparative Example 1, as described above, the N-type deep well 151 is connected at a position corresponding to the P-channel MOSFET 30Tr and the N-channel MOSFET 40Tr. Therefore, as shown in (b) of Figure 6, the PNP-type parasitic transistor 35 and the NPN-type parasitic transistor 47 are electrically connected, and as a result, a parasitic thyristor is formed. Consequently, for example, if noise flows in from the outside or if the negative power supply rises sharply, there is a risk that the parasitic thyristor will turn on. In particular, if the P-channel MOSFET 30Tr and the N-channel MOSFET 40Tr are high-voltage transistors (for example, with a voltage rating of 5.0V or higher), the parasitic thyristor tends to turn on more easily.

[0078] In the semiconductor circuit device 11 provided in the display device 10 according to the first embodiment, the N-type well 31 and the N-type well 45 are separated by the wall portion 21 (part of the semiconductor substrate 20) of the semiconductor substrate 20, and the N-type deep well 51 is separated by the wall portion 21 (part of the semiconductor substrate 20) of the semiconductor substrate 20 at a position corresponding to the space between the P-channel MOSFET 30Tr and the N-channel MOSFET 40Tr. As a result, as shown in Figure 3(b), the PNP-type parasitic transistor 35 and the NPN-type parasitic transistor 47 are electrically disconnected, and as a result, the path through which the parasitic thyristor turns on can be structurally eliminated. Therefore, it is possible to provide a semiconductor circuit device 11 that is resistant to noise flowing in from the outside, surge currents flowing in from the outside during power supply startup, and surge voltages applied from the outside. In other words, it is possible to provide a highly reliable semiconductor circuit device 11 with improved latch-up resistance.

[0079] The CMOS 20Tr may be electrically connected to the outside of the display device 10, that is, to the outside of the semiconductor circuit device 11. When the CMOS 20Tr is electrically connected to the outside of the display device 10 in this way, the risk of noise inflow from the outside to the vertical analog section 117V increases. Therefore, when the CMOS 20Tr is electrically connected to the outside of the display device 10, it is particularly effective to employ the N-type deep well 51 having the above-mentioned isolation structure and structurally eliminate the path through which the parasitic thyristor turns on.

[0080] P-channel MOSFET 30Tr and N-channel MOSFET 40Tr may be high-voltage transistors. In high-voltage transistors, the following techniques are often employed to increase the voltage withstand capability: (1) Diluting the implant concentration in the well. (2) Increasing the STI (Shallow Trench Isolation) depth and the distance between substrate contacts to ensure voltage withstand capability. (3) Increasing the voltage amplitude of the circuit.

[0081] However, when the above technology is adopted, the resistance value in the well depth direction increases, resulting in a large well potential fluctuation that triggers latch-up. This makes the parasitic bipolar transistor (BIP) more likely to turn on, and as a result, the latch-up risk tends to increase. Therefore, when the P-channel MOSFET 30Tr and the N-channel MOSFET 40Tr are high-voltage transistors, it is particularly effective to adopt the N-type deep well 51 having the above separation structure to structurally eliminate the path through which the parasitic thyristor turns on.

[0082] In the semiconductor circuit device 11, the N-type deep well 51 is separated by a part of the semiconductor substrate 20 (the wall portion 21 of the semiconductor substrate 20). Therefore, the manufacturing process of the semiconductor circuit device 11 can be simplified compared to the case where the N-type deep well 51 is separated by an insulating layer or the like separate from the semiconductor substrate 20.

[0083] <3 Second Embodiment> [Configuration of Display Device 10A] Fig. 7 is a block diagram of a display device 10A according to the second embodiment. The display device 10A includes a semiconductor circuit device 11A and a display unit 12. The semiconductor circuit device 11A includes a first semiconductor circuit portion 11A １ and a second semiconductor circuit portion 11A ２ The display unit 12 is provided on one surface side of the first semiconductor circuit portion 11A １ The first semiconductor circuit portion 11A １ and the second semiconductor circuit portion 11A ２ are an example of a plurality of semiconductor circuit portions.

[0084] (First Semiconductor Circuit Portion 11A １ ) The first semiconductor circuit portion 11A １ is, for example, a pixel chip. The first semiconductor circuit portion 11A １ includes a first semiconductor substrate 20A. A vertical logic portion 116V and a vertical analog portion 117V are mounted on one surface side of the first semiconductor substrate 20A. The vertical analog portion 117V has the configuration described in the first embodiment.

[0085] (Second Semiconductor Circuit Portion 11A ２) Second semiconductor circuit section 11A ２ For example, this is a DDIC (Display Driver Integrated Circuit). Second semiconductor circuit section 11A ２ This includes a second semiconductor substrate 20B. An input / output unit 111, a gamma processing unit 112, a power supply processing unit 113, an interface unit 114, a timing controller 115, a horizontal logic unit 116H, and a horizontal analog unit 117H are mounted on one side of the second semiconductor substrate 20B.

[0086] [Effect] The first semiconductor circuit section 11A provided in the display device 10A according to the second embodiment １ In this configuration, the N-type deep well 51 is separated by a wall portion 21 (part of the semiconductor substrate 20) at a position corresponding to the space between the P-channel MOSFET 30Tr and the N-channel MOSFET 40Tr. Therefore, the same effects as in the first embodiment can be obtained.

[0087] <4 Modifications> The following describes modifications of the display device 10 according to the first embodiment, but the following modifications can also be applied to the display device 10A according to the first embodiment.

[0088] [Modification 1] The input / output unit 111 may be connected to a negative power supply (negative power supply voltage) VSS2, as shown in Figure 8. The source region 43S of the N-channel MOSFET 40Tr and the contact region 44 provided in the P-type well 41 may be connected to the negative power supply (negative power supply voltage) VSS2 via the input / output unit 111 (see Figure 3). When the source region 43S of the N-channel MOSFET 40Tr and the contact region 44 provided in the P-type well 41 are connected to a negative power supply in this way, the risk of noise inflow from the outside increases. Therefore, when the source region 43S and the contact region 44 provided in the P-type well 41 are connected to a negative power supply as described above, it is particularly effective to use the N-type deep well 51 in the first embodiment (the N-type deep well 51 is separated by a wall portion 21 at a position corresponding to the space between the P-channel MOSFET 30Tr and the N-channel MOSFET 40Tr) and structurally eliminate the path through which the parasitic thyristor turns on.

[0089] [Modification 2] In the first embodiment, an example was described in which the semiconductor circuit device 11 includes a P-type semiconductor substrate 20. However, the semiconductor substrate is not limited to this example, and as shown in Figure 9, the semiconductor circuit device 11 may also include an N-type semiconductor substrate 20C.

[0090] The N-type semiconductor substrate 20C has a wall portion 21C on one side. The wall portion 21C is integrally formed with the main body of the N-type semiconductor substrate 20C and is made of N-type semiconductor material, just like the main body of the N-type semiconductor substrate 20C. The wall portion 21C has a contact region 22C, which is an N-type diffusion layer, at its tip. The contact region 22C is connected to the power supply VSS.

[0091] When the semiconductor circuit device 11 includes an N-type semiconductor substrate 20C, the vertical analog section 117V includes a P-type well 38 surrounding the side of an N-type well 31 in the first region 117VA instead of an N-type well 45 surrounding the side of a P-type well 41, and includes a P-type deep well 51C in the first region 117VA instead of an N-type deep well 51.

[0092] The P-type well 38 has a closed-loop shape surrounding the N-type well 31 in a plan view. A contact region 39 is provided within the P-type well 38. The contact region 39 is a P-type semiconductor region. The contact region 39 has a closed-loop shape surrounding the N-type well 31 in a plan view, for example. However, the shape of the contact region 39 is not limited to this example. The contact region 39 is connected to the power supply VSS 2.

[0093] The P-type deep well 51C is an example of a first-conductivity deep well. The P-type deep well 51C is a P-type semiconductor region. The P-type deep well 51 is located below the N-type well 31, the P-type well 38, and the P-type well 41. That is, the P-type deep well 51C is located between the N-type well 31, the P-type well 38, the P-type well 41 and the semiconductor substrate 20.

[0094] An interface may or may not be provided between the P-type well 41 and the P-type deep well 51C. Similarly, an interface may or may not be provided between the P-type well 38 and the P-type deep well 51C. In Figure 9(b), the location of the above interface is shown by a dashed line.

[0095] The P-type deep well 51C is electrically isolated by the wall portion 21C of the semiconductor substrate 20C (i.e., a part of the semiconductor substrate 20C) at a position corresponding to the space between the P-channel MOSFET 30Tr and the N-channel MOSFET 40Tr. The N-type well 31 is surrounded by the P-type well 38 and the P-type deep well 51C. As a result, the N-type well 31 has a structure independent of the semiconductor substrate 20C.

[0096] [Modification 3] In the example shown in Figure 3, one P-channel MOSFET 30Tr is provided in one N-type well 31. However, the number of P-channel MOSFETs 30Tr provided in one N-type well 31 is not limited to this example, and as shown in Figure 10, multiple P-channel MOSFETs 30Tr may be provided in one N-type well 31.

[0097] Furthermore, the example in Figure 3 shows an example in which one N-channel MOSFET 40Tr is provided in the P-type well 41. However, the number of N-channel MOSFETs 40Tr provided in one P-type well 41 is not limited to this example, and as shown in Figure 10, multiple N-channel MOSFETs 40Tr may be provided in one P-type well 41.

[0098] The above configuration is advantageous when there are limitations on the width and / or length of the first region 117VA, which is provided with multiple P-channel MOSFETs 30Tr and multiple N-channel MOSFETs 40Tr.

[0099] [Modification 4] In the first embodiment, an example was described in which the N-type deep well 51 of the vertical analog section 117V is separated by the wall portion 21 of the semiconductor substrate 20 at a position corresponding to the space between the P-channel MOSFET 30Tr and the N-channel MOSFET 40Tr (see Figure 3). However, the separation structure in which the N-type deep well 51 is separated in this way is not limited to the vertical analog section 117V, but can also be applied to circuit blocks other than the vertical analog section 117V. Applying the above separation structure to a circuit block that includes high-voltage transistors is particularly effective. Furthermore, the above separation structure can be applied not only to circuit blocks but also to the boundary between two adjacent circuit blocks. Applying the above separation structure to the boundary between two adjacent circuit blocks that each include high-voltage transistors is particularly effective.

[0100] Examples of circuit blocks to which the above separation structure can be applied include at least one of the following: the gamma processing unit 112, the power supply processing unit 113, the vertical analog unit 117V, the horizontal analog unit 117H, and the pixel circuit unit. Examples of boundaries between circuit blocks to which the above separation structure can be applied include at least one of the following: the boundary between the vertical analog unit 117V and the pixel circuit unit, and the boundary between the horizontal analog unit 117H and the pixel circuit unit. Below, specific examples of applications to which the separation structure is applied, namely Application Examples 1 to 4, will be described in order.

[0101] (Application Example 1: An example in which a separation structure is applied to the boundary between adjacent vertical analog units 117V and pixel circuit units) Figure 11 is a schematic diagram of the vertical analog unit 117V and the pixel circuit unit. Figure 12(a) is an enlarged plan view of the boundary between adjacent vertical analog units 117V and pixel circuit units. Figure 12(b) is a cross-sectional view along line A-A in Figure 12(a). In Application Example 1, the pixel circuit unit is an example of the first circuit block, and the vertical analog unit 117V or vertical driver is an example of the second circuit block.

[0102] The vertical analog section 117V is as described in the first embodiment.

[0103] The pixel circuit section includes one N-type well 71 provided with multiple P-channel MOSFETs 70Tr and one N-type deep well 51. The multiple P-channel MOSFETs 70Tr share one N-type well 71. The multiple P-channel MOSFETs 70Tr are arranged two-dimensionally in a predetermined arrangement pattern such as a matrix. The CMOS 20Tr of the vertical analog section 117V and the P-channel MOSFETs 70Tr of the pixel circuit section may be arranged so as to be aligned horizontally (in the width direction of the first region 117VA) of the display section 12. In Application Example 1, an example is described in which both the number of N-type wells 71 and the number of N-type deep wells 51 are one, but these numbers are not particularly limited and may be multiple. In Application Example 1, an example is described in which the N-type well 71 as the first conductivity type well is included in the pixel circuit section as the first circuit block, and the P-type well 41 as the second conductivity type well is included in the driver as the second circuit block adjacent to the pixel circuit section.

[0104] The N-type well 71 is an N-type semiconductor region provided on one side of the semiconductor circuit device 11. The N-type well 71 is an example of a first conductivity type well. The N-type well 71 is provided over substantially the entire display unit mounting area. The N-type well 71 has a rectangular shape in plan view, for example.

[0105] One or more contact regions 74 are provided within the N-type well 71. The contact region 34 is an N-type semiconductor region. One or more contact regions 74 have a predetermined shape or pattern in a plan view. The contact region 74 is connected to the power supply VCCP.

[0106] The P-channel MOSFET 70Tr includes a gate electrode 72, a source region 73S, and a drain region 73D. The gate electrode 72, source region 73S, and drain region 73D are the same as those of the gate electrode 32, source region 33S, and drain region 33D in the P-channel MOSFET 30Tr. The gate electrode 72 is connected to the gate input terminal. The source region 73S is connected to the power supply VCCP. The drain region 73D is connected to a drive transistor (not shown) for driving the light-emitting element.

[0107] The PNP-type parasitic transistors 75, 76, and 77 formed in the semiconductor circuit device 11 of Application Example 1 are the same as the PNP-type parasitic transistors 35, 36, and 37 in the first embodiment.

[0108] The N-type well 45 of the vertical analog section 117V and the N-type well 71 of the pixel circuit section are separated by the wall portion 21 of the semiconductor substrate 20. In addition, the N-type deep well 51 is electrically isolated by the wall portion 21 of the semiconductor substrate 20 at a position corresponding to the space between the N-channel MOSFET 40Tr of the vertical analog section 117V and the P-channel MOSFET 70Tr of the pixel circuit section.

[0109] In the semiconductor circuit device 11 having the above configuration, the N-type deep well 51 is electrically isolated by the wall portion 21 (part of the semiconductor substrate 20) of the semiconductor substrate 20 at a position corresponding to the space between the N-channel MOSFET 40Tr of the vertical analog section 117V and the P-channel MOSFET 30Tr of the pixel circuit section. This makes it possible to suppress the formation of noise paths and thyristors between the pixel circuit section, which has a large number of elements, and the vertical analog section 117V. Therefore, it is possible to suppress the occurrence of latch-up caused by peripheral circuits.

[0110] (Application Example 2: An example in which a separation structure is applied to the boundary between adjacent horizontal analog units 117H and pixel circuit units) Figure 13 is a schematic diagram of the horizontal analog unit 117H and the pixel circuit unit. Figure 14(a) is an enlarged plan view of the boundary between adjacent horizontal analog units 117H and pixel circuit units. Figure 14(b) is a cross-sectional view along the line A-A in Figure 14(a). In Application Example 2, the pixel circuit unit is an example of the first circuit block, and the horizontal analog unit 117H or horizontal driver is an example of the second circuit block.

[0111] The horizontal analog section 117H has a region 117HA that includes a plurality of high-voltage transistors. This region 117HA is an output circuit region that includes, for example, an output buffer (BUF). In a plan view, region 117HA has an elongated shape (specifically, for example, a long, narrow rectangle) that extends along one of the two vertical sides of the display section 12.

[0112] The horizontal analog section 117H includes in region 117HA one N-type well 31 provided with multiple P-channel MOSFETs 30Tr, one P-type well 41 provided with multiple N-channel MOSFETs 40Tr, and one N-type well 45 surrounding the side of the P-type well 41. In each part constituting the horizontal analog section 117H, the same reference numerals are used for parts that are the same as or correspond to parts constituting the vertical analog section 117V. In Application Example 2, an example is described in which the N-type well 71 as the first conductivity type well is included in the pixel circuit section as the first circuit block, and the P-type well 41 as the second conductivity type well is included in the driver as the second circuit block adjacent to the pixel circuit section.

[0113] Figure 13 shows an example where multiple P-channel MOSFETs 30Tr share one N-type well 31, but as shown in Figure 14, each of the multiple P-channel MOSFETs 30Tr may have its own individual N-type well 31. Also, Figure 13 shows an example where multiple N-channel MOSFETs 40Tr share one P-type well 41, but as shown in Figure 14, each of the multiple N-channel MOSFETs 40Tr may have its own individual P-type well 41.

[0114] The pixel circuit section is as described in Application Example 1.

[0115] The N-type well 45 of the horizontal analog section 117H and the N-type well 71 of the pixel circuit section are separated by the wall portion 21 of the semiconductor substrate 20. In addition, the N-type deep well 51 is electrically isolated by the wall portion 21 of the semiconductor substrate 20 at a position corresponding to the space between the N-channel MOSFET 40Tr of the horizontal analog section 117H and the P-channel MOSFET 70Tr of the pixel circuit section.

[0116] In the semiconductor circuit device 11 having the above configuration, the N-type deep well 51 is electrically isolated by the wall portion 21 (part of the semiconductor substrate 20) of the semiconductor substrate 20 at a position corresponding to the space between the N-channel MOSFET 40TrH of the horizontal analog section 117H and the P-channel MOSFET 70Tr of the pixel circuit section. This makes it possible to obtain the same effects as in Application Example 1.

[0117] (Application Example 3: Example in which a separation structure is provided in the power supply processing unit 113) Figure 15 is a schematic diagram of the power supply processing unit 113. Figure 16(a) is an enlarged view of region 113R in Figure 15. Figure 16(b) is a cross-sectional view along line A-A in Figure 16(a). The power supply processing unit 113 has a triple-well structure. The power supply processing unit 113 includes a control circuit 113A and an output stage 113B. The control circuit 113A and the output stage 113B are arranged adjacent to each other.

[0118] The control circuit 131A controls the power supply to the pixel circuit section and the like. The control circuit 131A includes one N-type well 31 provided with multiple P-channel MOSFETs 30Tr, one P-type well 41 provided with multiple N-channel MOSFETs 40Tr, and one N-type deep well 51. In Application Example 3, the N-type well 31 is provided within the P-type well 41. In Application Example 3, an example is described in which the number of N-type wells 31, P-type wells 41, and N-type deep wells 51 in the control circuit 131A is one each, but these numbers are not particularly limited and may be multiple.

[0119] The output stage 113B is connected to the input / output unit 111 and the pixel circuit unit, and outputs power supplied via the input / output unit 111 to the pixel circuit unit and the like. The output stage 113B includes one N-type well 31 provided with multiple P-channel MOSFETs 30Tr and one N-type deep well 51. In Application Example 3, an example is described in which both the number of N-type wells 31 and the number of N-type deep wells 51 in the output stage 113B are one, but these numbers are not particularly limited and may be multiple.

[0120] The N-type well 45 of the control circuit 131A and the N-type well 31 of the output stage 113B are separated by the wall portion 21 of the semiconductor substrate 20. The N-type deep well 51 is electrically isolated by the wall portion 21 of the semiconductor substrate 20 at a position corresponding to the space between the N-channel MOSFET 40Tr of the control circuit 131A and the P-channel MOSFET 30Tr of the output stage 113B. This suppresses the formation of a thyristor due to the combination of the output stage 113B and the control circuit 131A.

[0121] The N-type deep well 51 may be electrically isolated by the wall portion 21 of the semiconductor substrate 20 at a position corresponding to the space between the P-channel MOSFET 30Tr and the N-channel MOSFET 40Tr included in the control circuit 131A.

[0122] (Application Example 4: Example in which a separation structure is provided in the gamma processing unit 112) Figure 17 is a schematic diagram of the gamma processing unit 112. The gamma processing unit 112 has a triple-well structure. The gamma processing unit 112 includes a drive circuit 112A, an output stage 112B, and an output switch 112C.

[0123] The drive circuit 112A drives the output stage 112B. The drive circuit 112A includes one N-type well 31 provided with a plurality of P-channel MOSFETs 30Tr and one P-type well 41 provided with a plurality of N-channel MOSFETs 40Tr. The drive circuit 112A may further include one N-type deep well 51. In application example 4, the N-type well 31 is provided within the P-type well 41.

[0124] Figure 18(a) is an enlarged view of a part of the output stage 112B, specifically region 112R in Figure 17. Figure 18(b) is a cross-sectional view along line A-A in Figure 18(a). The output stage 112B is connected to the outside via the input / output unit 111. The output stage 112B includes one N-type well 31 provided with a plurality of P-channel MOSFETs 30Tr, one P-type well 41 provided with a plurality of N-channel MOSFETs 40Tr, one N-type well 45 surrounding the side of the P-type well 41, and two N-type deep wells 51. The N-type well 31 and P-type well 41 of the output stage 112B are arranged adjacent to each other. The P-channel MOSFETs 30Tr and N-channel MOSFETs 40Tr of the output stage 112B may be high-voltage transistors. Note that the number of N-type wells 31, P-type wells 41, N-type wells 45, and deep wells 51 in the output stage 112B is not limited to the example above.

[0125] The N-type wells 31 and 45 of the output stage 112B are separated by the wall portion 21 of the semiconductor substrate 20. The N-type deep well 51 of the output stage 112B is electrically isolated by the wall portion 21 of the semiconductor substrate 20 at a position corresponding to the space between adjacent P-channel MOSFETs 30Tr and N-channel MOSFETs 40Tr in the output stage 112B. This suppresses the formation of thyristors in the output stage 112B connected by the input / output unit 111.

[0126] Figure 19(a) is an enlarged view of the output switch 112C. Figure 19(b) is a cross-sectional view along line A-A in Figure 19(a). The output switch 112C is connected to the outside via the input / output unit 111. The output switch 112C includes one N-type well 31 provided with one P-channel MOSFET 30Tr, one P-type well 41 provided with one N-channel MOSFET 40Tr, one N-type well 45 surrounding the side of the P-type well 41, and two N-type deep wells 51. The N-type well 31 and P-type well 41 of the output switch 112C are arranged adjacent to each other. The P-channel MOSFET 30Tr and N-channel MOSFET 40Tr of the output switch 112C may be high-voltage transistors. Note that the number of N-type wells 31, P-type wells 41, N-type wells 45 and N-type deep wells 51 of the output switch 112C is not limited to the above example.

[0127] The N-type wells 31 and 45 of the output switch 112C are separated by the wall portion 21 of the semiconductor substrate 20. The N-type deep well 51 is electrically isolated by the wall portion 21 of the semiconductor substrate 20 at a position corresponding to the space between the N-type well 31 and the P-type well 41 of the output switch 112C. This suppresses the formation of thyristors in the output switch 112C.

[0128] In the above example, an example was described in which an isolated structure with an N-type deep well 51 is applied to the output stage 112B and output switch 112C, which are connected to the outside via the input / output unit 111. However, the isolated structure of the N-type deep well 51 is not limited to the output stage 112B and output switch 112C, but may also be applied to the drive circuit 112A, or to at least one of the boundaries between the drive circuit 112A and the output stage 112B, the drive circuit 112A and the output switch 112C, and the output stage 112B and the output switch 112C.

[0129] [Other Modifications] Although one embodiment of the present disclosure and its modifications (hereinafter referred to as "Embodiment, etc.") have been described in detail above, the present disclosure is not limited to Embodiment, etc., and various modifications based on the technical idea of ​​the present disclosure are possible.

[0130] For example, the configurations, methods, processes, shapes, materials, and numerical values ​​listed in one embodiment are merely examples, and different configurations, methods, processes, shapes, materials, and numerical values ​​may be used as needed.

[0131] The configuration, methods, processes, shapes, materials, and numerical values ​​of one embodiment, etc., can be combined with each other without departing from the spirit of this disclosure.

[0132] Unless otherwise specified, the materials exemplified in one embodiment, etc., can be used individually or in combination of two or more types.

[0133] Furthermore, the present disclosure may also adopt the following configurations: (1) A semiconductor circuit device comprising: a semiconductor substrate of a first conductivity type; a well of a second conductivity type provided with at least one transistor of the first conductivity type; a well of a first conductivity type provided with at least one transistor of the second conductivity type; and a deep well of a second conductivity type provided between the well of the first conductivity type, the well of the second conductivity type and the semiconductor substrate of the first conductivity type, wherein the deep well of the second conductivity type is electrically isolated by a part of the semiconductor substrate of the first conductivity type at a position corresponding to the position between the transistor of the first conductivity type and the transistor of the second conductivity type. (2) The semiconductor circuit device according to (1), further comprising an input / output unit that can be connected to an external source, wherein one or both of the transistors of the first conductivity type and the transistors of the second conductivity type are connected to the input / output unit. (3) The semiconductor circuit device according to (1), further comprising an input / output unit that can be connected to a negative power supply, wherein the well of the first conductivity type is a P-type well, and the well of the first conductivity type can be connected to the negative power supply via the input / output unit. (4) The semiconductor circuit device according to any one of (1) to (3), wherein the first conductivity type and the second conductivity type are P-type and N-type, respectively, or the first conductivity type and the second conductivity type are N-type and P-type, respectively. (5) The semiconductor circuit device according to any one of (1) to (4), wherein the at least one transistor of the first conductivity type includes a plurality of transistors of the first conductivity type, the plurality of transistors of the first conductivity type share a well of the second conductivity type, and the at least one transistor of the second conductivity type includes a plurality of transistors of the second conductivity type, the plurality of transistors of the second conductivity type share a well of the first conductivity type. (6) The semiconductor circuit device according to any one of (1) to (5), wherein the well of the first conductivity type and the well of the second conductivity type are contained in the same circuit block. (7) The semiconductor circuit device according to (6), wherein the transistor of the first conductivity type and the transistor of the second conductivity type constitute a complementary metal oxide semiconductor.(8) The semiconductor circuit device according to any one of (1) to (5), wherein the well of the first conductivity type is included in a first circuit block, and the well of the second conductivity type is included in a second circuit block adjacent to the first circuit block. (9) The semiconductor circuit device according to any one of (1) to (5), wherein the well of the first conductivity type is included in a pixel circuit section, and the well of the second conductivity type is included in a driver adjacent to the pixel circuit section. (10) A semiconductor circuit device comprising a plurality of semiconductor circuit sections, wherein at least one of the plurality of semiconductor circuit sections comprises: a semiconductor substrate of a first conductivity type; a well of a second conductivity type provided with at least one transistor of the first conductivity type; a well of a first conductivity type provided with at least one transistor of the second conductivity type; and a deep well of a second conductivity type provided between the well of the first conductivity type, the well of the second conductivity type, and the semiconductor substrate of the first conductivity type, wherein the deep well of the second conductivity type is electrically isolated by a part of the semiconductor substrate of the first conductivity type at a position corresponding to the position between the transistor of the first conductivity type and the transistor of the second conductivity type. (11) A display device comprising the semiconductor circuit device according to any one of (1) to (10). (12) An electronic device comprising the semiconductor circuit device according to any one of (1) to (10).

[0134] <5. Application Examples> (Electronic Devices) The display device 10 according to the first embodiment, the display device 10A according to the second embodiment, and the display devices 10, 10A according to their modified forms (hereinafter referred to as "display device 10 etc. according to the first embodiment") may be provided in various electronic devices. The display device 10 etc. according to the first embodiment is particularly suitable for eyewear devices such as head-mounted displays, or for devices that require high resolution and are used magnified close to the eyes, such as electronic viewfinders of video cameras or single-lens reflex cameras.

[0135] (Specific Example 1) Figures 20A and 20B show an example of the external appearance of a digital still camera 310. This digital still camera 310 is a single-lens reflex type with interchangeable lenses, and has an interchangeable shooting lens unit (interchangeable lens) 312 located approximately in the center of the front of the camera body 311, and a grip portion 313 for the photographer to hold on the left side of the front.

[0136] A monitor 314 is provided on the back of the camera body 311, slightly to the left of the center. An electronic viewfinder (eyepiece) 315 is provided above the monitor 314. The photographer can determine the composition by looking through the electronic viewfinder 315 and visually confirming the light image of the subject guided by the shooting lens unit 312. The electronic viewfinder 315 includes one of the display devices 10, etc., according to the first embodiment.

[0137] (Specific Example 2) Figure 21 shows an example of the appearance of a head-mounted display 320. The head-mounted display 320 is an example of an eyewear device. The head-mounted display 320 has, for example, a glasses-shaped display unit 321 and ear hooks 322 on both sides for attachment to the user's head. The display unit 321 comprises one of the display devices 10, etc., according to the first embodiment.

[0138] (Specific Example 3) Figure 22 shows an example of the appearance of a see-through head-mounted display 340. The see-through head-mounted display 340 is an example of an eyewear device. The see-through head-mounted display 340 comprises a main body 341, an arm 342, and a lens barrel 343.

[0139] The main body 341 is connected to the arm 342 and the eyeglasses 350. Specifically, the long end of the main body 341 is connected to the arm 342, and one side of the main body 341 is connected to the eyeglasses 350 via a connecting member. The main body 341 may also be directly attached to the head of a person.

[0140] The main body 341 houses a control board for controlling the operation of the see-through head-mounted display 340, as well as a display unit. The arm 342 connects the main body 341 to the lens barrel 343 and supports the lens barrel 343. Specifically, the arm 342 is connected to the end of the main body 341 and the end of the lens barrel 343, respectively, to fix the lens barrel 343 in place. The arm 342 also houses signal lines for communicating image-related data provided from the main body 341 to the lens barrel 343.

[0141] The microscope tube 343 projects image light, provided from the main body 341 via the arm 342, through the eyepiece 351 towards the eyes of the user wearing the see-through head-mounted display 340. In this see-through head-mounted display 340, the display unit of the main body 341 includes one of the display devices 10, etc., according to the first embodiment.

[0142] 10, 10A Display device 11, 11A, 11M Semiconductor circuit device 11A １ First semiconductor circuit section 11A ２116V 117 N-type well (an example of a second-type conductivity well) 32 Gate electrode 33S Source region 33D Drain region 34 Contact region 35, 36 PNP parasitic transistor 37 Parasitic resistor 38 P-type well 39 Contact region 40Tr N-channel MOSFET (an example of a second-type conductivity transistor) 41 P-type well (an example of a first-type conductivity well) 42 Gate electrode 43S Source region 43D Drain region 44 Contact region 45 N-type well 46 Contact region 47 NPN parasitic transistor 48 Parasitic resistor 51 N-type deep well (an example of a second-type conductivity deep well) 51C P-type deep well (an example of a second-type conductivity deep well) 61 N-type well 70Tr P-channel MOSFET (an example of a first-type conductivity transistor) 71 N-type well (an example of a second-type conductivity well) 72 Gate electrode 73S Source region 73D Drain area 74 Contact area 310 Digital still camera 320 Head-mounted display 340 See-through head-mounted display

Claims

1. A semiconductor circuit device comprising: a semiconductor substrate of a first conductivity type; a well of a second conductivity type provided with at least one transistor of the first conductivity type; a well of the first conductivity type provided with at least one transistor of the second conductivity type; and a deep well of a second conductivity type provided between the first conductivity type well, the second conductivity type well, and the semiconductor substrate of the first conductivity type, wherein the deep well of the second conductivity type is electrically isolated by a portion of the semiconductor substrate of the first conductivity type at a position corresponding to the position between the transistor of the first conductivity type and the transistor of the second conductivity type.

2. The semiconductor circuit device according to claim 1, further comprising an input / output section that can be connected to an external source, wherein one or both of the first conductivity type transistor and the second conductivity type transistor are connected to the input / output section.

3. The semiconductor circuit device according to claim 1, further comprising an input / output section that can be connected to a negative power supply, wherein the well of the first conductivity type is a P-type well, and the well of the first conductivity type can be connected to the negative power supply via the input / output section.

4. The semiconductor circuit device according to claim 1, wherein the first conductivity type and the second conductivity type are P-type and N-type, respectively, or the first conductivity type and the second conductivity type are N-type and P-type, respectively.

5. The semiconductor circuit device according to claim 1, wherein the at least one transistor of a first conductivity type comprises a plurality of transistors of a first conductivity type, the plurality of transistors of a first conductivity type sharing a well of a second conductivity type, and the at least one transistor of a second conductivity type comprises a plurality of transistors of a second conductivity type, the plurality of transistors of a second conductivity type sharing a well of a first conductivity type.

6. The semiconductor circuit apparatus according to claim 1, wherein the well of the first conductivity type and the well of the second conductivity type are included in the same circuit block.

7. The semiconductor circuit device according to claim 6, wherein the first conductivity type transistor and the second conductivity type transistor constitute a complementary metal oxide film semiconductor.

8. The semiconductor circuit apparatus according to claim 1, wherein the well of the first conductivity type is included in a first circuit block, and the well of the second conductivity type is included in a second circuit block adjacent to the first circuit block.

9. The semiconductor circuit device according to claim 1, wherein the well of the first conductivity type is included in the pixel circuit section, and the well of the second conductivity type is included in a driver adjacent to the pixel circuit section.

10. A semiconductor circuit device comprising a plurality of semiconductor circuit sections, wherein at least one of the plurality of semiconductor circuit sections comprises: a semiconductor substrate of a first conductivity type; a well of a second conductivity type provided with at least one transistor of the first conductivity type; a well of a first conductivity type provided with at least one transistor of the second conductivity type; and a deep well of a second conductivity type provided between the first conductivity type well, the second conductivity type well, and the semiconductor substrate of the first conductivity type, wherein the deep well of the second conductivity type is electrically isolated by a portion of the semiconductor substrate of the first conductivity type at a position corresponding to the position between the transistor of the first conductivity type and the transistor of the second conductivity type.

11. A display device comprising the semiconductor circuit device described in claim 1.

12. An electronic device comprising the semiconductor circuit device described in claim 1.

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