Semiconductor device

Abstract

This semiconductor device comprises: a chip having a main surface containing an active region; a semiconductor region of a first conductivity type formed in a surface layer portion of the main surface; a stripe-shaped base impurity region of a second conductivity type formed in a surface layer portion of the semiconductor region and extending in a first direction; a first impurity region formed in a surface layer portion of the base impurity region in the active region; a gate structure that includes a plurality of stripe-shaped main body portions extending in the first direction in the active region and a plurality of bridging portions connecting the plurality of adjacent main body portions, wherein the gate structure faces a channel region formed by a part of the base impurity region; and a second impurity region of the second conductivity type that is selectively formed in a covered region of the main surface covered by the bridging portions and that is connected to the base impurity region.

Description

Semiconductor equipment Related applications

[0001] This application corresponds to Japanese Patent Application No. 2025-013866, filed with the Japan Patent Office on 30 January 2025, and the full disclosure of this application is incorporated herein by reference.

[0002] This disclosure relates to semiconductor devices.

[0003] Patent Document 1 discloses a semiconductor device comprising: a semiconductor layer having a first main surface; a unit cell including an n-type (first conductivity type) diode region formed on the surface of the first main surface; a p-type (second conductivity type) well region formed around the diode region on the surface of the first main surface; and an n-type impurity region formed on the surface of the well region; a gate electrode layer facing the well region and the impurity region with a gate insulating layer in between; and a first main surface electrode covering the diode region and the impurity region on the first main surface and forming a Schottky junction with the diode region.

[0004] Japanese Patent Publication No. 2022-168307

[0005] [Summary] One embodiment of the present disclosure provides a semiconductor device that can suppress variations in switching speed.

[0006] Figure 1 is a plan view of a semiconductor device according to one embodiment of the present disclosure. Figure 2 is a plan view showing the layout of the main surface electrode film. Figure 3 is a cross-sectional view taken along the line III-III shown in Figure 2. Figure 4 is a plan view showing the layout of the underlayment wiring layer. Figure 5 is a perspective view showing the layout of the well region. Figure 6 is a plan view showing the layout of the well region. Figure 7 is an enlarged view showing the main part of Figure 4. Figure 8 is an enlarged view showing the main part of Figure 4. Figure 9 is a perspective view showing the main part of the semiconductor device. Figure 10 is a plan view showing the main part of the semiconductor device. Figure 11 is an enlarged perspective view showing the portion enclosed by the dashed line XI in Figure 10. Figure 12 is a cross-sectional view taken along the line XII-XII shown in Figure 11. Figure 13 is a cross-sectional view taken along the line XIII-XIII shown in Figure 11. Figure 14 is a cross-sectional view taken along the line XIV-XIV shown in Figure 11. Figure 15 is a cross-sectional view taken along the line XV-XV shown in Figure 11. Figure 16 is a cross-sectional view along the line XVI-XVI shown in Figure 11. Figure 17 is a cross-sectional view along the line XVII-XVII shown in Figure 6. Figure 18 is a cross-sectional view along the line XVIII-XVIII shown in Figure 8. Figure 19 is a plan view showing a first modified example of the layout of the impurity region and gate structure of the first main surface. Figure 20 is a plan view showing a second modified example of the layout of the impurity region and gate structure of the first main surface. Figure 21 is a plan view showing a third modified example of the layout of the impurity region and gate structure of the first main surface. Figure 22 is a diagram showing a first modified example of the layout of the gate electrode film. Figure 23 is a diagram showing a second modified example of the layout of the gate electrode film. Figure 24 is a diagram showing a third modified example of the layout of the gate electrode film. Figure 25 is a diagram showing a fourth modified example of the layout of the gate electrode film. Figure 26 is a diagram showing a fifth modified example of the layout of the gate electrode film. Figure 27 is a diagram showing a first modified example of the layout of the substrate opening. Figure 28 is a diagram showing a second modified example of the layout of the substrate opening. Figure 29 is a diagram showing a third modified example of the layout of the substrate opening. Figure 30 shows a fourth modified example of the layout of the base opening. Figure 31 is a cross-sectional view of a semiconductor device having a trench gate structure.

[0007] [Detailed Description] Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0008] The attached drawings are all schematic diagrams and not strictly accurate; the scale, proportions, angles, etc., do not necessarily match. Corresponding structures in the attached drawings are given the same reference numerals, and redundant explanations are omitted or simplified. For structures whose explanations are omitted or simplified, the explanation given before the omission or simplification applies.

[0009] Where the word "substantially" is used in this specification, it includes not only numerical values ​​(forms) that are approximately equal to the numerical value (form) being compared, but also numerical errors (form errors) within a range of ±10% from the numerical value (form) being compared. In the following descriptions, words such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of explanation and are not intended to limit the names of each structure.

[0010] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "n-type" may be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." Of course, "p-type" may be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." "n-type" is the conductivity type due to pentavalent elements, and "p-type" is the conductivity type due to trivalent elements. Unless otherwise specified, trivalent elements are at least one of boron, aluminum, gallium, and indium. Unless otherwise specified, pentavalent elements are at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0011] (1) Basic structure diagram 1 of the semiconductor device 1 is a plan view of a semiconductor device 1 according to one embodiment of the present disclosure. Figure 2 is a plan view showing the layout of the main surface electrode film 33. Figure 3 is a cross-sectional view taken along the line III-III shown in Figure 2. Figure 4 is a plan view showing the layout of the underlayment wiring layer 22. Figure 5 is a perspective view showing the layout of the well region 16. Figure 6 is a plan view showing the layout of the well region 16. In Figures 5 and 6, the thick dashed line indicates the outline of the well region 16. The multiple rings shown in hatching are multiple field regions 18. Furthermore, in Figure 5, the outline of the active region 6 is shown by a dashed line, and in Figure 6, the outlines of the main surface electrode film 33 and the gate electrode film 34 are shown by dashed lines.

[0012] Semiconductor device 1 is a semiconductor switching device having an insulated gate type planar structure Tr as an example of a device structure. The planar structure Tr has a planar gate type vertical structure.

[0013] Referring to Figures 1 to 6, the semiconductor device 1 includes a chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In this embodiment, the chip 2 includes a single crystal of a wide-bandgap semiconductor. The semiconductor device 1 is a "wide-bandgap semiconductor device." The chip 2 may also be referred to as a "semiconductor chip," "wide-bandgap semiconductor chip," etc.

[0014] Wide-bandgap semiconductors are semiconductors that have a bandgap greater than that of silicon (Si). Examples of wide-bandgap semiconductors include gallium nitride (GaN), silicon carbide (SiC), and diamond (C). In this configuration, chip 2 is a "SiC chip" containing a hexagonal SiC single crystal as an example of a wide-bandgap semiconductor. Semiconductor device 1 is a "SiC semiconductor device".

[0015] Hexagonal SiC single crystals have multiple polytypes, including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, and 6H-SiC single crystals. In this embodiment, an example is shown in which chip 2 contains a 4H-SiC single crystal, but chip 2 may also contain other polytypes.

[0016] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a rectangular shape in a plan view from the vertical direction Z (hereinafter simply referred to as "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction of the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view.

[0017] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, the first main surface 3 is preferably formed by the silicon plane ((0001) plane) of the SiC single crystal, and the second main surface 4 is preferably formed by the carbon plane ((000-1) plane) of the SiC single crystal. The first main surface 3 and the second main surface 4 may have an off-angle that is inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane. The off-direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off-angle may be greater than 0° and less than or equal to 10°. The off-angle is preferably 5° or less.

[0018] The first side surface 5A and the second side surface 5B each extend in the first direction X along the first main surface 3 and face opposite directions in the second direction Y which intersects the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D each extend in the second direction Y and face opposite directions in the first direction X.

[0019] In this configuration, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0020] The XY plane, which includes the first direction X and the second direction Y, forms a horizontal plane perpendicular to the vertical direction Z. Hereafter, the axis extending along the vertical direction Z may be referred to as the "vertical axis." Also below, the first direction X and the second direction Y may be referred to as the "horizontal direction." The horizontal direction is also the direction extending along the first principal plane 3.

[0021] The first to fourth sides 5A to 5D may have a length of 0.5 mm or more and 20 mm or less in a plan view. The length of the first to fourth sides 5A to 5D may be a value that falls within any one of the following ranges: 0.5 mm or more and 1 mm or less, 1 mm or more and 2 mm or less, 2 mm or more and 5 mm or less, 5 mm or more and 10 mm or less, 10 mm or more and 15 mm or less, and 15 mm or more and 20 mm or less. The length of the first to fourth sides 5A to 5D may be 5 mm or more.

[0022] The semiconductor device 1 includes an active region 6 and an outer peripheral region 7 set on the first main surface 3 of the chip 2.

[0023] The active region 6 is a region (element region) that includes the device structure and generates output current (drain current). In a plan view, the active region 6 is set in the inner part of the chip 2, spaced apart from the periphery of the chip 2 (first to fourth side surfaces 5A to 5D). In a plan view, the active region 6 is formed in a polygonal shape with sides parallel to the periphery of the chip 2. In this embodiment, in a plan view, the active region 6 is formed in a polygonal shape with recesses that are indented along the gate pad electrode 37, which will be described later. The active region 6 may also be formed in a quadrilateral shape in a plan view. Preferably, the planar area of ​​the active region 6 is 50% to 90% of the planar area of ​​the first main surface 3.

[0024] The active region 6 may include a plurality of active regions 6 separated from each other. In this form, the active region 6 includes a first active region 61 and a second active region 62 separated from each other. The first active region 61 and the second active region 62 may be arranged on one side and the other side, respectively, with respect to the central portion of the chip 2 in the first direction X. The first active region 61 and the second active region 62 may have a plane shape that is line-symmetric with respect to the finger wiring 40 extending in the second direction Y.

[0025] The outer peripheral region 7 is a region that does not include a device structure. The outer peripheral region 7 is provided in a region between the peripheral edge of the chip 2 and the active region 6 in a plan view. The outer peripheral region 7 extends in a strip shape along the active region 6 in a plan view and is set to a polygonal annular shape (a square annular shape in this form) surrounding the active region 6.

[0026] The semiconductor device 1 includes an n-type first semiconductor layer 8 formed on the surface layer portion of the second main surface 4. A drain potential as a first potential (high potential) is applied to the first semiconductor layer 8. The first semiconductor layer 8 may be referred to as a "semiconductor region (layer)", a "base region (layer)", a "drain region (layer)", etc.

[0027] The first semiconductor layer 8 extends in a layer shape along the second main surface 4 and forms the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this form, the first semiconductor layer 8 is made of an n-type semiconductor layer. Specifically, the first semiconductor layer 8 is made of a substrate (SiC substrate) including a SiC single crystal (semiconductor single crystal) and has the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this form, the first semiconductor layer 8 is made of a substrate (SiC substrate) made of a SiC single crystal. The first semiconductor layer 8 has the off direction and off angle described above.

[0028] The first semiconductor layer 8 is 1×10 １８ cm －３ or more and 1×10 ２１ cm －３It may have the following n-type impurity concentration as a peak value. The first semiconductor layer 8 preferably has a substantially constant n-type impurity concentration in the thickness direction. The n-type impurity concentration of the first semiconductor layer 8 is preferably adjusted by a single type of pentavalent element. Particularly preferably, the n-type impurity concentration of the first semiconductor layer 8 is adjusted by a pentavalent element other than phosphorus. In this form, the n-type impurity concentration of the first semiconductor layer 8 is adjusted by nitrogen.

[0029] The first semiconductor layer 8 may have a first thickness T1 of 10 μm or more and 500 μm or less. The first thickness T1 may have a value belonging to at least one of the ranges of 10 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, and 400 μm or more and 500 μm or less.

[0030] The semiconductor device 1 includes an n-type second semiconductor layer 9 formed in the surface layer portion of the first main surface 3. The second semiconductor layer 9 may be referred to as a "semiconductor region (layer)", a "drift region (layer)", or the like. The second semiconductor layer 9 extends in a layer shape along the first main surface 3 and forms the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0031] In this form, the second semiconductor layer 9 is composed of an n-type semiconductor layer. Specifically, the second semiconductor layer 9 is composed of an epitaxial layer (SiC epitaxial layer) containing a SiC single crystal (semiconductor single crystal). The second semiconductor layer 9 (epitaxial layer) has the above-described off direction and off angle. The second semiconductor layer 9 is composed of an epitaxial layer (SiC epitaxial layer) grown epitaxially starting from the first semiconductor layer 8.

[0032] The second semiconductor layer 9 has a lower end and an upper end. The lower end of the second semiconductor layer 9 is the crystal growth starting point, and the upper end of the second semiconductor layer 9 is the crystal growth end point. The lower end of the second semiconductor layer 9 is also the bottom of the second semiconductor layer 9. Since the second semiconductor layer 9 is continuously grown epitaxially from the first semiconductor layer 8, the lower end of the second semiconductor layer 9 coincides with the upper end of the first semiconductor layer 8.

[0033] The second semiconductor layer 9 includes an n-type drift region 10. In this embodiment, the drift region 10 is formed by a part (n-type portion) of the second semiconductor layer 9.

[0034] The boundary between the first semiconductor layer 8 and the second semiconductor layer 9 is not necessarily visible and can be indirectly evaluated and / or determined from other components and elements. The second semiconductor layer 9 has an off-direction and off-angle that substantially coincides with the off-direction and off-angle of the first semiconductor layer 8.

[0035] The second semiconductor layer 9 may have a lower n-type impurity concentration than the first semiconductor layer 8. １５ cm －３ The above 1 x 10 １７ cm －３ The following n-type impurity concentrations may be present as peak values. Preferably, the second semiconductor layer 9 has a nearly constant n-type impurity concentration in the thickness direction.

[0036] The second semiconductor layer 9 has a second thickness T2 that is less than the first thickness T1. The second thickness T2 may be 5 μm or more and 15 μm or less. The second thickness T2 may have a value that falls within at least one of the following ranges: 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, and 12.5 μm or more and 15 μm or less.

[0037] Referring to Figure 3, the semiconductor device 1 includes a plurality of p-type body regions 11 as an example of base impurity regions formed on the surface layer of the first main surface 3 in the active region 6. The plurality of body regions 11 are assigned a source potential as a low potential (second potential) different from a high potential (first potential). The plurality of body regions 11 are arranged with spacing in the second direction Y and are each formed in a strip shape extending in the first direction X. In other words, the plurality of body regions 11 are arranged in a stripe shape extending in the first direction X.

[0038] Multiple body regions 11 are formed at intervals from the bottom of the second semiconductor layer 9 (drift region 10) toward the first main surface 3, and face the first semiconductor layer 8 with a portion of the second semiconductor layer 9 in between. Preferably, the multiple body regions 11 are formed at intervals from the middle of the second semiconductor layer 9 toward the first main surface 3. Multiple body regions 11 are exposed from the first main surface 3.

[0039] The semiconductor device 1 includes a plurality of planar electrode type gate structures 12 formed on the first main surface 3 in the active region 6. The gate structures 12 may also be referred to as "planar structures," "planar gate structures," etc. A gate potential is applied to the plurality of gate structures 12 as a control potential.

[0040] The gate structure 12 includes a main body portion 13 and a bridging portion 14. In this configuration, the main body portion 13 and the bridging portion 14 are integrally formed.

[0041] The main body portion 13 is formed in a strip shape extending in the first direction X. In other words, the direction of extension of the main body portion 13 coincides with the off-direction of the SiC single crystal. In this configuration, multiple main body portions 13 are arranged in a stripe shape extending in the first direction X.

[0042] The bridging section 14 crosses the area between multiple adjacent main body sections 13 in the second direction Y, connecting the multiple adjacent main body sections 13. The multiple adjacent main body sections 13 are connected by the bridging section 14, and in other parts they are spaced apart in the second direction Y. In this configuration, the gate structure 12 is formed in a grid pattern by the multiple main body sections 13 and the bridging section 14. The parts corresponding to windows in the grid-like gate structure 12 are gate openings 15 where the gate structure 12 is not formed. In this configuration, the multiple gate openings 15 are arranged in a matrix.

[0043] Referring to Figures 3, 5, and 6, the semiconductor device 1 includes a p-type well region 16 within the second semiconductor layer 9. The well region 16 is formed on the surface of the second semiconductor layer 9. The well region 16 is spaced inward from the outer edge of the chip 2. In Figures 5 and 6, the well region 16 is a planar region enclosed by a thick dashed line and has an outer edge that is set inward from the first to fourth sides 5A to 5D. In this configuration, the well region 16 has a rectangular shape in plan view. The well region 16 has first to fourth well edges 17A to 17D, each parallel to the first to fourth sides 5A to 5D. The first well edge 17A is parallel to the first side 5A, the second well edge 17B is parallel to the second side 5B, the third well edge 17C is parallel to the third side 5C, and the fourth well edge 17D is parallel to the fourth side 5D.

[0044] Multiple field regions 18 are arranged in the region between the periphery 17A to 17D of the first to fourth wells and the first to fourth side surfaces 5A to 5D. The p-shaped field region 18 is formed on the surface layer of the first main surface 3 in the outer peripheral region 7 (periphery of the first main surface 3).

[0045] The well region 16 includes an active well region 19 and an outer well region 20. The active well region 19 is the region inside the active region 6. The outer well region 20 is the region outside the active region 6. The outer well region 20 extends from the active well region 19 to the outer peripheral region 7 outside the gate electrode film 34. The active well region 19 and the outer well region 20 are integral, and the boundary between them does not need to be visible.

[0046] The semiconductor device 1 includes a surface insulating film 21 that selectively covers the first main surface 3. The surface insulating film 21 may also be referred to as the "main surface insulating film". The surface insulating film 21 coats the first main surface 3 in a film-like manner in the active region 6 and the peripheral region 7.

[0047] The surface insulating film 21 covers the outer well region 20 and the multiple field regions 18 in the outer peripheral region 7. The surface insulating film 21 is continuous with the first to fourth side surfaces 5A to 5D. The surface insulating film 21 may be formed with a gap inward from the first to fourth side surfaces 5A to 5D, exposing the peripheral edge of the first main surface 3.

[0048] Referring to Figure 4, the semiconductor device 1 includes a base wiring layer 22 as an example of a wiring layer formed on the first main surface 3 in the outer peripheral region 7. The base wiring layer 22 supplies current from the gate pad electrodes 37 (described later) to a plurality of gate structures 12. The base wiring layer 22 is the base for the metallic main surface electrode film 33 (described later) on the interlayer insulating film 29 (described later), and is laid out directly beneath the main surface electrode film 33. In Figure 4, for clarity, the formation regions of the base wiring layer 22 and the gate structures 12 are shown with hatching, and the outline of the main surface electrode film 33 above the base wiring layer 22 is shown with a dashed line.

[0049] In this embodiment, the base wiring layer 22 is formed integrally with the gate structure 12 using the same material as the gate structure 12. The base wiring layer 22 and the gate structure 12 may contain either or both of p-type conductive polysilicon and n-type conductive polysilicon.

[0050] The underlying wiring layer 22 includes a base portion 23 and an extension portion 24. The base portion 23 is located directly beneath the gate pad electrode 37 (described later). In a plan view, the base portion 23 is formed in an annular shape that surrounds the gate pad electrode 37. The base portion 23 is located near one of the first to fourth sides 5A to 5D of the chip 2. In this configuration, the base portion 23 is located in the central part of the first side 5A in the first direction X, and is located close to the first side 5A.

[0051] The extension portion 24 extends outward in a strip shape from the outer edge of the annular base portion 23. The semiconductor device 1 includes a plurality of extension portions 25 to 27 that extend outward in a strip shape from the outer edge of the base portion 23 in different directions. The plurality of extension portions 25 to 27 are arranged in a non-parallel positional relationship with respect to each other. The plurality of extension portions 25 to 27 may include a first extension portion 25, a second extension portion 26, and a third extension portion 27.

[0052] The first extension 25 and the second extension 26 extend from the base 23 in opposite directions along the periphery of the tip 2, and together surround the active region 6. In this configuration, the first extension 25 extends from the base 23 in the first direction X along the first side surface 5A, the third side surface 5C, and the second side surface 5B in that order. The second extension 26 extends from the base 23 in the first direction X along the first side surface 5A, the fourth side surface 5D, and the second side surface 5B in that order. The third extension 27 extends from the base 23 toward the center of the tip 2 and crosses the active region 6. The third extension 27 extends from the base 23 toward the second side surface 5B and may divide the active region 6 into left and right sides (both sides of the third side surface 5C and the fourth side surface 5D).

[0053] The first extension 25, the second extension 26, and the third extension 27 may be connected to each other on the opposite side of the base 23. As a result, the first active region 61 is surrounded by the first extension 25 and the third extension 27, and the second active region 62 is surrounded by the second extension 26 and the third extension 27.

[0054] The first extension portion 25 may be referred to as, for example, "first outer perimeter base wiring," "first outer perimeter base electrode," "first outer perimeter base finger wiring," or "first outer perimeter base finger electrode." The second extension portion 26 may be referred to as, for example, "second outer perimeter base wiring," "second outer perimeter base electrode," "second outer perimeter base finger wiring," or "second outer perimeter base finger electrode." The first extension portion 25 and the second extension portion 26 may be collectively referred to as "outer perimeter base wiring," "outer perimeter base electrode," "outer perimeter base finger wiring," or "outer perimeter base finger electrode" surrounding the active region 6. The third extension portion 27 may be referred to as, for example, "central base wiring," "central base electrode," "central base finger wiring," or "central base finger electrode."

[0055] Multiple gate structures 12 may be arranged across two different locations in the underlying wiring layer 22. One end and the other end of the main body 13 of each strip-shaped gate structure 12 are connected to two different locations in the underlying wiring layer 22. In this configuration, the main body 13 of the multiple gate structures 12 connect the base portion 23 to the first extension portion 25, the base portion 23 to the second extension portion 26, the first extension portion 25 to the third extension portion 27, and the second extension portion 26 to the third extension portion 27.

[0056] Multiple base openings 28 are formed in the base wiring layer 22. Multiple base openings 28 are formed in the first extension 25 and the second extension 26. The multiple base openings 28 are positioned opposite each other with the gate structure 12 in between. In this configuration, multiple base openings 28 are arranged on the first side surface 5A and the second side surface 5B of the first extension 25, and these face each other with the gate structure 12 in between in the second direction Y. Similarly, multiple base openings 28 are arranged on the first side surface 5A and the second side surface 5B of the second extension 26, and these face each other with the gate structure 12 in between in the second direction Y.

[0057] The semiconductor device 1 includes an insulating interlayer insulating film 29 that covers the surface insulating film 21. The interlayer insulating film 29 may also be called an "insulating film," "intermediate insulating film," etc. The interlayer insulating film 29 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0058] Referring to Figure 3, the interlayer insulating film 29 has a first contact opening 30 and a second contact opening 31 that expose the active region 6. The body region 11 is exposed through the first contact opening 30. The main surface contact region 32 formed in the well region 16 is exposed through the second contact opening 31.

[0059] The semiconductor device 1 includes a main surface electrode film 33 and a gate electrode film 34 disposed on an interlayer insulating film 29. In Figure 2, the interlayer insulating film 29 is shown as a white area, and the main surface electrode film 33 and gate electrode film 34 are shown as hatched areas.

[0060] The main surface electrode film 33 may also be called the source electrode film. The main surface electrode film 33 is a film that is physically and electrically separated from the gate electrode film 34. The main surface electrode film 33 is arranged on the interlayer insulating film 29 at a distance from the gate electrode film 34. The main surface electrode film 33 is an electrode to which a source potential is applied from the outside. The main surface electrode film 33 may also be called the "first main surface electrode," "source electrode film," "source pad electrode," "source metal," "first pad electrode," etc.

[0061] The main surface electrode film 33 is formed from a metallic material containing Al (aluminum). The main surface electrode film 33 includes an Al-based metal film. The main surface electrode film 33 may include at least one of the following: a pure Al film (an Al film with a purity of 99% or higher), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. The main surface electrode film 33 may also be a metal film other than an Al-based metal film. The main surface electrode film 33 may include at least one of the following: a Ti film, a TiN film, a W film, a Cu film, a Cu alloy film, and a conductive polysilicon film.

[0062] In this embodiment, the main surface electrode film 33 is positioned on the active region 6 in a plan view. The main surface electrode film 33 is formed in a polygonal shape in a plan view. The main surface electrode film 33 includes a first electrode region 35 and a second electrode region 36 that are separated from each other. In this embodiment, the main surface electrode film 33 includes a first electrode region 35 positioned on the third side surface 5C side of the center position in the first direction X of the active region 6 (first main surface 3), and a second electrode region 36 positioned on the fourth side surface 5D side of the said center position.

[0063] The gate electrode film 34 is an electrode to which a gate potential is applied from the outside. The gate electrode film 34 may also be referred to as the "second main surface electrode," "gate metal," "second pad electrode," etc.

[0064] The gate electrode film 34 is formed from a metallic material containing Al (aluminum). The gate electrode film 34 includes an Al-based metal film. The gate electrode film 34 may include at least one of the following: a pure Al film (an Al film with a purity of 99% or higher), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. The gate electrode film 34 may also be a metal film other than an Al-based metal film. The gate electrode film 34 may include at least one of the following: a Ti film, a TiN film, a W film, a Cu film, a Cu alloy film, and a conductive polysilicon film.

[0065] The gate electrode film 34 includes a gate pad electrode 37 as an example of a pad portion and a gate wiring 38 as an example of a finger portion. In this embodiment, the gate pad electrode 37 is located on the outer peripheral region 7. Specifically, the gate pad electrode 37 is located in a region adjacent to the center of one side (first side surface 5A in this embodiment) of the first main surface 3 in a plan view. The gate pad electrode 37 is located in a recess formed in the main surface electrode film 33. The gate pad electrode 37 may be located in a region along the center of any of the first to fourth side surfaces 5A to 5D. The gate pad electrode 37 may be located at any corner of the chip 2 on the first main surface 3 in a plan view. The gate pad electrode 37 may be located in the center of the first main surface 3 in a plan view. The gate pad electrode 37 may be located on the active region 6. In this embodiment, the gate pad electrode 37 is formed in a square shape in a plan view.

[0066] The gate wiring 38 is routed from the gate pad electrode 37 around the active region 6, encircling the active region 6. The gate wiring 38 transmits the gate potential applied to the gate pad electrode 37 to the multiple gate structures 12.

[0067] The gate wiring 38 includes base wiring 39 and finger wiring 40. The base wiring 39 is positioned directly above the base portion 23 of the underlying wiring layer 22. The base wiring 39 is formed in an annular shape that overlaps the base portion 23 and surrounds the gate pad electrode 37 in a plan view.

[0068] The finger wiring 40 extends outward in a strip shape from the outer edge of the annular base wiring 39. The semiconductor device 1 includes a plurality of finger wirings 41 to 43 that extend outward in strip shapes in different directions from the outer edge of the base wiring 39. The plurality of finger wirings 41 to 43 are arranged in a non-parallel positional relationship with respect to each other. The plurality of finger wirings 41 to 43 may include a first finger wiring 41, a second finger wiring 42, and a third finger wiring 43.

[0069] The first finger wiring 41 and the second finger wiring 42 extend from the base wiring 39 in opposite directions along the periphery of the chip 2, and together surround the main surface electrode film 33. As a result, the entire region drawn by the outer edge of the main surface electrode film 33 is located within the region enclosed by the first finger wiring 41 and the second finger wiring 42. In this embodiment, the entire main surface electrode film 33 is located within the region sandwiched between the first finger wiring 41 and the second finger wiring 42. The first finger wiring 41 extends from the base wiring 39 in the first direction X along the first side surface 5A, the third side surface 5C, and the second side surface 5B in that order. The second finger wiring 42 extends from the base wiring 39 in the first direction X along the first side surface 5A, the fourth side surface 5D, and the second side surface 5B in that order. The third finger wiring 43 extends from the base wiring 39 toward the center of the chip 2 and crosses the main surface electrode film 33. The third finger wiring 43 extends from the base wiring 39 toward the second side surface 5B, and may divide the main surface electrode film 33 into a first electrode region 35 and a second electrode region 36.

[0070] The first finger wiring 41, the second finger wiring 42, and the third finger wiring 43 may be connected to each other on the opposite side of the gate pad electrode 37. This causes the first electrode region 35 to be surrounded by the first finger wiring 41 and the third finger wiring 43, and the second electrode region 36 to be surrounded by the second finger wiring 42 and the third finger wiring 43.

[0071] The first finger wiring 41 may be referred to as, for example, "first outer peripheral wiring," "first outer peripheral electrode," "first outer peripheral finger wiring," or "first outer peripheral finger electrode." The second finger wiring 42 may be referred to as, for example, "second outer peripheral wiring," "second outer peripheral electrode," "second outer peripheral finger wiring," or "second outer peripheral finger electrode." The first finger wiring 41 and the second finger wiring 42 may be collectively referred to as "outer peripheral wiring," "outer peripheral electrode," "outer peripheral finger wiring," or "outer peripheral finger electrode" surrounding the active region 6. The third finger wiring 43 may be referred to as, for example, "central wiring," "central electrode," "central finger wiring," or "central finger electrode."

[0072] Referring to Figure 1, the semiconductor device 1 includes a protective film 44 that selectively covers the main surface electrode film 33 and the interlayer insulating film 29 on the first main surface 3. The protective film 44 includes a gate pad opening 46 that exposes a portion of the gate pad electrode 37 as a gate pad 45. The protective film 44 covers the peripheral edge of the gate pad electrode 37 and the entire area of ​​the gate wiring 38. The gate pad opening 46 is formed in a rectangular shape in plan view.

[0073] Referring to Figure 1, the protective film 44 includes a first source pad opening 49 that exposes a portion of the first electrode region 35 as a first source pad 47, and a second source pad opening 50 that exposes a portion of the second electrode region 36 as a second source pad 48. The protective film 44 covers the peripheral edges of the first electrode region 35 and the peripheral edges of the second electrode region 36.

[0074] The first source pad opening 49 is formed in a polygonal shape along the periphery of the first electrode region 35 in a plan view. The second source pad opening 50 is formed in a polygonal shape along the periphery of the second electrode region 36 in a plan view. Preferably, the planar area of ​​the first source pad opening 49 and the second source pad opening 50 is larger than the planar area of ​​the gate pad opening 46.

[0075] The protective film 44 may have a laminated structure including an inorganic insulating film and an organic insulating film stacked in this order from the chip 2 side. The protective film 44 only needs to include at least one of the inorganic insulating film and the organic insulating film, and does not necessarily need to include both at the same time. The inorganic insulating film may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is preferable that the inorganic insulating film includes an insulating material different from the interlayer insulating film 29. The organic insulating film is preferably a polyimide film, a polyamide film, or a polybenzoxazole film. In this embodiment, the organic insulating film includes a polybenzoxazole film.

[0076] The semiconductor device 1 includes a drain pad electrode 51 that covers the second main surface 4. The drain pad electrode 51 may also be referred to as the "third main surface electrode," "third terminal (electrode)," "third pad (electrode)," or "drain electrode." The drain pad electrode 51 is mechanically and electrically connected to the first semiconductor layer 8. The drain pad electrode 51 forms ohmic contact with the first semiconductor layer 8.

[0077] The drain pad electrode 51 may cover the entire area of ​​the second main surface 4 so as to be continuous with the periphery of the second main surface 4 (first to fourth side surfaces 5A to 5D). Alternatively, the drain pad electrode 51 may partially cover the second main surface 4 so as to expose the periphery of the second main surface 4.

[0078] The breakdown voltage that can be applied between the main surface electrode film 33 and the drain pad electrode 51 (between the first main surface 3 and the second main surface 4) may be 500V or more and 3000V or less. The breakdown voltage may have a value that falls within at least one of the following ranges: 500V or more and 750V or less, 750V or more and 1000V or less, 1000V or more and 1250V or less, 1250V or more and 1500V or less, 1500V or more and 1750V or less, 1750V or more and 2000V or less, 2000V or more and 2250V or more and 2250V or more and 2500V or more and 3000V or less.

[0079] (2) Detailed Structural Diagram of the Main Part of the Semiconductor Device 1 FIG. 7 is an enlarged view showing the main part of FIG. 4, mainly showing the formation range and formation pattern of the underlying wiring layer 22 directly under the main surface electrode film 33. FIG. 8 is an enlarged view showing the main part of FIG. 4, mainly showing the formation range and formation pattern of the underlying wiring layer 22 directly under the gate electrode film 34.

[0080] FIG. 9 is a perspective view showing the main part of the semiconductor device 1, mainly showing the cell structure within the active region 6 and the detailed structure of the gate structure 12. FIG. 10 is a plan view showing the main part of the semiconductor device 1, mainly showing the planar pattern of the cell structure and the gate structure 12. In FIG. 10, the gate opening 15 is shown as the hatched area, and the first contact opening 30 is shown by a dashed line.

[0081] FIG. 11 is a perspective view showing an enlarged view of the portion surrounded by the two-dot chain line XI in FIG. 10. FIG. 12 is a cross-sectional view taken along the XII-XII line shown in FIG. 11. FIG. 13 is a cross-sectional view taken along the XIII-XIII line shown in FIG. 11. FIG. 14 is a cross-sectional view taken along the XIV-XIV line shown in FIG. 11. FIG. 15 is a cross-sectional view taken along the XV-XV line shown in FIG. 11. FIG. 16 is a cross-sectional view taken along the XVI-XVI line shown in FIG. 11. FIG. 17 is a cross-sectional view taken along the XVII-XVII line shown in FIG. 6. FIG. 18 is a cross-sectional view taken along the XVIII-XVIII line shown in FIG. 8.

[0082] Mainly referring to FIGS. 9 and 10, the plurality of body regions 11 are arranged in a stripe shape extending in the first direction X. Each body region 11 provides each unit cell 52 of the semiconductor device 1. Referring to FIG. 10, the pitch P of the plurality of body regions 11 (for example, the distance between the centers of adjacent body regions 11 in the second direction Y) is, for example, 2.5 μm or more and 5 μm or less, preferably 3.0 μm or more and 3.6 μm or less.

[0083] The body region 11 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 9. The body region 11 has 1×10 １７ cm －３ or more and 1×10 １９ cm －３The following p-type impurity concentrations may be present as peak values.

[0084] The regions between the striped body regions 11 are surface drift regions 53, which are part of the drift region 10. Each of the multiple surface drift regions 53 is part of the drift region 10. The multiple surface drift regions 53 may have an n-type impurity concentration higher than that of the drift region 10, or they may have an n-type impurity concentration lower than that of the drift region 10.

[0085] Multiple surface drift regions 53 are each demarcated in the region between multiple adjacent body regions 11 in the second direction Y. Multiple surface drift regions 53 are each demarcated by multiple body regions 11 in the surface portion of the first main surface 3. Multiple surface drift regions 53 are arranged with intervals in the second direction Y and are each formed in a strip shape extending in the first direction X. Multiple surface drift regions 53 are formed in a stripe shape extending in the first direction X.

[0086] The semiconductor device 1 includes an n-type source region 54 as an example of a first impurity region formed on the surface of each of the multiple body regions 11. The source region 54 has an n-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 9. The source region 54 has a density of 1 × 10⁻⁶ １９ cm －３ The above 1 x 10 ２１ cm －３ The following n-type impurity concentrations may be present as peak values.

[0087] A source potential is applied to the source region 54. In Figure 10, the source region 54 is omitted from the illustration for clarity. Referring to Figure 9, the source region 54 is formed in a strip shape along the extending direction of each body region 11 (each unit cell 52). Multiple source regions 54 are arranged in a stripe shape extending in the first direction X as a whole.

[0088] The semiconductor device 1 includes a plurality of p-type channel regions 55 formed on the surface layer of the first main surface 3. The plurality of channel regions 55 are partitioned in the surface layer of the plurality of body regions 11, in the regions between the ends of the plurality of body regions 11 (a plurality of surface drift regions 53) and the periphery of the source region 54. In this embodiment, the plurality of channel regions 55 are arranged with spacing in the second direction Y and are each formed in a stripe shape extending in the first direction X. The plurality of channel regions 55 are arranged in a stripe shape extending in the first direction X.

[0089] Referring to Figures 9 and 10, the semiconductor device 1 includes a plurality of p-type contact regions 56 formed on the surface of a plurality of body regions 11 in the active region 6. The contact regions 56 may also be called "body contact regions" or "back gate regions". A source potential is applied to the plurality of contact regions 56. The contact regions 56 have a higher p-type impurity concentration than the p-type impurity concentration of the body regions 11. The contact regions 56 have a p-type impurity concentration of 1 × 10⁻¹⁶ １９ cm －３ The above 1 x 10 ２１ cm －３ The following p-type impurity concentrations may be present as peak values.

[0090] Referring to Figure 10, each unit cell 52 has a first section 57 and a second section 58 in the first direction X. A clear boundary does not need to be formed between the first section 57 and the second section 58. For example, in the first direction X, the first section 57 may be longer than the second section 58, or the first section 57 may be shorter than the second section 58.

[0091] The contact region 56 is selectively formed in the first section 57 such that it skips each second section 58 in the first direction X. In the body region 11, the contact region 56 and the regions on both sides of the contact region 56 in the second direction Y may be the first section 57. The second section 58 may be the region from the contact region 56 to both ends of the unit cell 52 in the first direction X.

[0092] Each contact region 56 extends in a strip shape along the extension direction (first direction X) of the unit cell 52. Each contact region 56 is formed at a distance from the bottom of the body region 11 toward the first main surface 3 and faces the drift region 10 across a portion of the body region 11. In the second direction Y, each contact region 56 is formed at a distance from both the periphery on one side and the other side of the body region 11. In this configuration, the contact region 56 is formed in the central part of the body region 11 in the second direction Y. Due to the formation of the contact regions 56, the source region 54 is separated into multiple source regions 54 in the first section 57.

[0093] From other perspectives, the multiple contact regions 56 are each selectively formed inside the source region 54. The multiple contact regions 56 are positioned to form a linear pattern along the second direction Y.

[0094] The semiconductor device 1 includes a plurality of planar electrode type gate structures 12 arranged on the first main surface 3 in the active region 6. The gate structures 12 are arranged on at least one channel region 55. In this embodiment, each gate structure 12 is arranged to span two adjacent body regions 11 across one surface drift region 53 and cover the plurality of channel regions 55. Each gate structure 12 is arranged to span a source region 54 on one body region 11 and a source region 54 on the other body region 11 and cover the surface drift region 53, the source region 54 and the channel region 55.

[0095] The gate structure 12 has a layered structure including a gate insulating film 59 and a gate electrode 60. The gate insulating film 59 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the gate insulating film 59 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the gate insulating film 59 includes a silicon oxide film made of the oxide of the chip 2. The gate insulating film 59 may be a film integrated with the surface insulating film 21.

[0096] Referring to Figure 9, the gate insulating film 59 covers the first main surface 3 in a film-like manner and is positioned on at least one channel region 55. In this embodiment, the gate insulating film 59 is positioned to span two adjacent body regions 11 across one surface drift region 53 and covers multiple channel regions 55. The gate insulating film 59 is positioned to span a source region 54 on one body region 11 and a source region 54 on the other body region 11 and covers the surface drift region 53, the source region 54 and the channel region 55.

[0097] The thickness of the gate insulating film 59 may be 10 nm or more and 150 nm or less. The thickness of the gate insulating film 59 may be a value that falls within at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less. Preferably, the thickness of the gate insulating film 59 is 25 nm or more and 75 nm or less.

[0098] The gate electrode 60 is positioned on the gate insulating film 59 and faces at least one channel region 55 across the gate insulating film 59. A gate potential is applied to the gate electrode 60 as a control potential. The gate electrode 60 controls the inversion and non-inversion of at least one channel region 55 in response to the gate potential.

[0099] The gate electrode 60 comprises a conductive semiconductor polycrystal. The gate electrode 60 may contain either or both of p-type conductive polysilicon and n-type conductive polysilicon. The conductivity type of the gate electrode 60 is adjusted according to the gate threshold voltage to be achieved. The gate electrode 60 may be referred to as a "polysilicon gate," "polygate," etc. The gate electrode 60 may be a film integrated with the underlying wiring layer 22.

[0100] The gate electrode 60 includes a main body portion 13 and a bridging portion 14. In this embodiment, the main body portion 13 and the bridging portion 14 are integrally formed. The main body portion 13 and the bridging portion 14 of the gate electrode 60 may also be referred to as the main body portion 13 and the bridging portion 14 of the gate structure 12.

[0101] The main body portion 13 is formed in a strip shape extending in a first direction X. The direction of extension of the main body portion 13 coincides with the off-direction of the SiC single crystal. In this configuration, multiple main body portions 13 are arranged in a stripe shape extending in the first direction X. Each main body portion 13 is positioned on the gate insulating film 59 so as to span two adjacent body regions 11, crossing one surface drift region 53 in a second direction Y, and facing multiple channel regions 55 across the gate insulating film 59.

[0102] The bridging portion 14 crosses the body region 11 between adjacent body portions 13 in the second direction Y, connecting the adjacent body portions 13. The bridging portion 14 is selectively positioned in the region covering the contact region 56. Multiple bridging portions 14 are arranged in a line along the direction that crosses the multiple body portions 13. In this configuration, the adjacent body portions 13 are connected by the bridging portion 14 at the location of each contact region 56, and are spaced apart in the other parts in the second direction Y.

[0103] The ratio (W1 / W2) of the width W1 of the bridging portion 14 in the first direction X to the width W2 between adjacent bridging portions 14 in the first direction X may be, for example, 0.01 or more and 1 or less. The width W1 may be, for example, 0.1 μm or more and 10 μm, preferably 0.3 μm or more and 5 μm or less. The width W2 may be, for example, 0.1 μm or more and 1000 μm, preferably 0.3 μm or more and 500 μm or less.

[0104] The thickness of the gate electrode 60 may be 0.1 μm or more and 2.0 μm or less. Preferably, the thickness of the gate electrode 60 is 0.2 μm or more and 1.0 μm or less. The width of the main body portion 13 may be, for example, 1.0 μm or more and 4.5 μm or less. The width of the main body portion 13 is the width in the direction perpendicular to the extension direction (i.e., the second direction Y). The width of the bridging portion 14 may be, for example, 1.0 μm or more and 4.5 μm or less. The width of the bridging portion 14 is the width in the direction perpendicular to the extension direction (i.e., the first direction X).

[0105] Next, with reference to Figures 11 to 16, a detailed explanation will be given of the impurity pattern in the region covered by the bridging portion 14 of the gate electrode 60 (hereinafter referred to as the covered region 63) and the structure of its surrounding area. The covered region 63 may also be referred to as the opposing region facing the bridging portion 14 of the gate electrode 60. The covered region 63 may also be referred to as the "gate covered region," "bridging portion covered region," "region directly below the bridging portion," "gate opposing region," or "bridging portion opposing region."

[0106] Referring to Figure 11, the body region 11 and the source region 54 each include a body covering portion 64 and a source covering portion 65. The body covering portion 64 and the source covering portion 65 are areas that are hatched in Figure 11. The body covering portion 64 and the source covering portion 65 are portions of the body region 11 and the source region 54 located in the covering region 63, respectively.

[0107] The contact area 56 is located in the covering area 63. In the covering area 63, the source covering portion 65 is spaced inward from both ends of the body covering portion 64 (unit cell 52) in the second direction Y. The contact area 56 is spaced further inward from both ends of the source covering portion 65 in the second direction Y. The contact area 56 is connected to the body covering portion 64 by penetrating the source covering portion 65.

[0108] The contact region 56 includes a covering portion 66 and a contact portion 67. The covering portion 66 is located in the covering region 63 and is formed in the center of the contact region 56 in the first direction X. The covering portion 66 may also be referred to as the central portion of the contact region 56. Referring to Figures 15 and 16, the covering portion 66 is the portion in the contact region 56 that covers the gate electrode 60 (bridging portion 14).

[0109] The contact portion 67 is a portion that extends from the covering portion 66 to both sides in the first direction X, and may be referred to as an extension of the contact region 56. The contact portion 67 extends in a band shape having a narrower width than the covering portion 66. In other words, the covering portion 66 is a wide portion in the contact region 56, and may have protrusions that project from the band-shaped contact portion 67 extending in the first direction X to both sides in the second direction Y. Referring to Figures 12 to 16, the contact portion 67 is a portion that protrudes outward from the gate electrode 60 (bridging portion 14) in the first direction X.

[0110] Referring to Figures 7 and 17, the well region 16 is formed spanning the active region 6 and the peripheral region 7. The well region 16 may be formed over substantially the entire area of ​​the first main surface 3. Preferably, the well region 16 has a p-type impurity concentration that is substantially equal to that of the body region 11. The well region 16 is 1 × 10 １７ cm －３ The above 1 x 10 １９ cm －３ The following p-type impurity concentrations may be present as peak values. The p-type impurity concentration in the well region 16 may be less than the p-type impurity concentration in the body region 11, or it may be higher than the p-type impurity concentration in the body region 11.

[0111] Referring to Figure 17, the well region 16 is formed with a gap from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3 toward the active region 6, and extends over almost the entire area of ​​the active region 6. In plan view, the well region 16 surrounds a plurality of stripe-shaped body regions 11 and may be integrally connected to both ends of the plurality of body regions 11. As a result, the well region 16 is fixed at the same potential as the plurality of body regions 11.

[0112] Referring to Figure 17, the well region 16 is formed with a gap from the bottom of the second semiconductor layer 9 toward the first main surface 3, and faces the first semiconductor layer 8 with a portion of the second semiconductor layer 9 in between. Preferably, the well region 16 is formed with a gap from the middle of the second semiconductor layer 9 toward the first main surface 3. The well region 16 is exposed from the first main surface 3.

[0113] Preferably, the well region 16 has a thickness (depth) approximately equal to the thickness (depth) of the body region 11. Of course, the thickness of the well region 16 may be less than the thickness of the body region 11, or it may be greater than the thickness of the body region 11.

[0114] The well region 16 includes an active well region 19 and an outer well region 20. The active well region 19 and the outer well region 20 extend continuously in the horizontal direction along the first main surface 3. The boundary between the active well region 19 and the outer well region 20 may be, for example, directly below an electrode removal region 68 that physically and electrically separates the main surface electrode film 33 and the gate electrode film 34.

[0115] The active well region 19 is formed over almost the entire area of ​​the active region 6 (excluding the area where the body region 11 is formed) and is integrally connected to both ends of the multiple stripe-shaped body regions 11. The active well region 19 faces the underlying wiring layer 22 via the surface insulating film 21. A main surface contact region 32 is formed on the surface of the active well region 19.

[0116] The main surface contact region 32 is selectively formed in the active well region 19 of the active well region 19 and the outer well region 20. The main surface contact region 32 has a higher p-type impurity concentration than the p-type impurity concentration of the body region 11. The main surface contact region 32 is 1 × 10 １９ cm －３ The above 1 x 10 ２１ cm －３ The following p-type impurity concentrations may be present as peak values.

[0117] Referring to Figure 7, the main surface contact region 32 is formed in a strip shape that extends along the multiple main body portions 13 of the gate structure 12. The main surface contact region 32 is positioned adjacent to the outermost main body portion 13 of the multiple main body portions 13.

[0118] Multiple base openings 28 are arranged along the extending direction of the main surface contact area 32. Multiple base openings 28 are located adjacent to the outermost main body portion 13 of the multiple main body portions 13. Multiple base openings 28 are arranged in a line with spacing in the direction along the outermost main body portion 13. The main surface contact area 32 is exposed from the multiple base openings 28.

[0119] Preferably, at least one of the multiple base openings 28 is positioned so as not to overlap with the bridging portion 14 in a direction that crosses the multiple main body portions 13. In other words, at least one of the multiple base openings 28 is positioned adjacent to the gate opening 15 (first contact opening 30) in the second direction Y. In this configuration, the multiple base openings 28 are positioned so as not to overlap with the bridging portion 14 in the second direction Y.

[0120] Multiple substrate openings 28 are selectively formed in the extension portion 24, which is an example of the extension portion 24, which is an example of the extension portion 24, which is an example of the first substrate portion of the substrate wiring layer 22. In particular, they are selectively formed in the first extension portion 25 and the second extension portion 26, which are among the extension portions 25 to 27 (see Figure 4).

[0121] The outer well region 20 extends integrally outward from the active well region 19 and is positioned with a gap between it and the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3 towards the active region 6. The outer well region 20 faces the underlying wiring layer 22 via the surface insulating film 21.

[0122] Referring to Figure 17, the semiconductor device 1 includes at least one (preferably two to twenty) p-type field regions 18 formed on the surface layer of the first main surface 3 in the outer peripheral region 7. The number of field regions 18 is typically three to eight. In this embodiment, the semiconductor device 1 includes three field regions 18. The multiple field regions 18 are formed in an electrically floating state and mitigate the electric field within the chip 2 at the periphery of the first main surface 3. The number, spacing, width, depth, and p-type impurity concentration of the field regions 18 are arbitrary and can take various values ​​depending on the electric field to be mitigated.

[0123] The field region 18 may have a p-type impurity concentration approximately equal to that of the body region 11. The field region 18 has a concentration of 1 × 10⁻⁶ impurities. １７ cm －３ The above 1 x 10 １９ cm －３ The following p-type impurity concentrations may be present as peak values. The p-type impurity concentration in the field region 18 may be higher than or lower than the p-type impurity concentration in the body region 11.

[0124] The multiple field regions 18 are formed in the region between the periphery of the first main surface 3 and the active region 6, spaced inward from the periphery of the first main surface 3. Specifically, the multiple field regions 18 are formed in the region between the periphery of the first main surface 3 and the outer well region 20. The multiple field regions 18 are arranged in the region between the periphery of the first main surface 3 and the outer well region 20, spaced apart from the outer well region 20 toward the periphery of the first main surface 3.

[0125] Referring to Figures 5 and 6, the multiple field regions 18 are formed in a strip shape extending along the active region 6 in a plan view. Each of the multiple field regions 18 has a portion extending in a strip shape in a first direction X and a portion extending in a strip shape in a second direction Y. In this embodiment, the multiple field regions 18 are formed in a polygonal ring (a quadrilateral ring in this embodiment) surrounding the active region 6 in a plan view. The multiple field regions 18 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0126] The multiple field regions 18 are formed at intervals from the bottom of the second semiconductor layer 9 toward the first main surface 3, and face the first semiconductor layer 8 with a portion of the second semiconductor layer 9 in between. Preferably, the multiple field regions 18 are formed at intervals from the middle of the second semiconductor layer 9 toward the first main surface 3.

[0127] Referring to Figures 8 and 18, the base portion 23 of the underlying wiring layer 22 faces the well region 16 across the surface insulating film 21. The base portion 23 is formed in an annular shape surrounding the gate pad electrode 37 in plan view. In this configuration, it is formed in a quadrilateral annular shape parallel to the four sides of the quadrilateral gate pad electrode 37 in plan view. The base portion 23 has a first portion 69, a second portion 70, a third portion 71, and a fourth portion 72 corresponding to each side of the quadrilateral annular shape.

[0128] The first portion 69 is positioned within the base portion 23, close to the side surface of the tip 2 (in this embodiment, the first side surface 5A). The first portion 69 is the base end of the first extension portion 25 and the second extension portion 26, and may integrally form a strip-shaped finger base portion with the first extension portion 25 and the second extension portion 26.

[0129] The first portion 69 has a gate projection 73 that protrudes inward toward the gate pad electrode 37 in a plan view. The gate projection 73 is spaced apart from the third portion 71 and the fourth portion 72. As a result, the internal opening 74 of the annular base portion 23 has a space 75 that selectively protrudes between the gate projection 73 and the third portion 71 and the fourth portion 72.

[0130] The second portion 70 is positioned on the opposite side of the first portion 69 from the gate pad electrode 37. The second portion 70 is the base end of the third extension 27 and is formed in a strip shape perpendicular to the third extension 27. The first portion 69 and the second portion 70 provide a pair of sides that face each other in the base portion 23.

[0131] The third portion 71 and the fourth portion 72 face each other in the first direction X, with the gate pad electrode 37 in between, and connect the first portion 69 and the second portion 70. The third portion 71 and the fourth portion 72 provide a pair of sides that face each other in the base portion 23.

[0132] The semiconductor device 1 includes an insulating interlayer insulating film 29 that covers the first main surface 3. The interlayer insulating film 29 covers the active region 6 and the outer peripheral region 7 on the first main surface 3 together.

[0133] Referring to Figures 3 and 12 to 16, the interlayer insulating film 29 covers multiple gate structures 12 in the active region 6. With respect to each gate structure 12, the interlayer insulating film 29 directly covers both the gate insulating film 59 and the gate electrode 60.

[0134] Referring to Figures 17 and 18, the interlayer insulating film 29 comprehensively covers the underlying wiring layer 22, the well region 16, the main surface contact region 32, and the multiple field regions 18. In this configuration, the interlayer insulating film 29 is continuous with the first to fourth side surfaces 5A to 5D. The interlayer insulating film 29 may be formed with an inward gap from the first to fourth side surfaces 5A to 5D, exposing the peripheral edge of the first main surface 3.

[0135] The semiconductor device 1 includes a plurality of first contact openings 30 and second contact openings 31 formed in the interlayer insulating film 29 in the active region 6. The first contact openings 30 may be referred to as "source openings" or "source contact openings." The second contact openings 31 may be referred to as "main surface contact openings" or "well contact openings."

[0136] Multiple first contact openings 30 are formed in the regions lateral to the gate electrode 60, spaced apart from the gate electrode 60, and exposing the first main surface 3 (chip 2). Specifically, referring to Figures 12 to 16, the multiple first contact openings 30 are formed in the regions between the gate electrode 60 and penetrate the gate insulating film 59 and the interlayer insulating film 29.

[0137] Referring to Figure 10, each first contact opening 30 is formed in a strip shape extending in the first direction X. At the ends of each first contact opening 30 (both ends in this configuration), the contact portion 67 of the contact region 56 is exposed. In addition, the source region 54 is exposed in most of each first contact opening 30.

[0138] Referring to Figures 7 and 17, the multiple second contact openings 31 are arranged along the extending direction of the main surface contact region 32. More specifically, the multiple second contact openings 31 are located adjacent to the outermost body portion 13 of the multiple body portions 13. The multiple second contact openings 31 are arranged in a line with spacing along the outermost body portion 13.

[0139] Each of the multiple second contact openings 31 is formed corresponding to one of the multiple base openings 28. In this configuration, the multiple second contact openings 31 are formed in a one-to-one relationship with the multiple base openings 28. The multiple second contact openings 31 penetrate the gate insulating film 59 and the interlayer insulating film 29, exposing the main surface contact region 32.

[0140] Referring to Figures 8 and 18, the semiconductor device 1 includes one or more (in this embodiment, more) gate contact openings 76 formed in the interlayer insulating film 29. The multiple gate contact openings 76 penetrate the interlayer insulating film 29 and expose the underlying wiring layer 22. The multiple gate contact openings 76 include base contact openings 77, pad contact openings 78, and finger contact openings 79.

[0141] The base contact opening 77 is located directly above the second portion 70, third portion 71, and fourth portion 72 of the base portion 23 of the underlying wiring layer 22. The pad contact opening 78 is located directly above the gate projection 73 of the base portion 23 of the underlying wiring layer 22. The finger contact opening 79 is located directly above the first portion 69, first extension portion 25, second extension portion 26, and third extension portion 27 of the base portion 23 of the underlying wiring layer 22.

[0142] The semiconductor device 1 includes a main surface electrode film 33 and a gate electrode film 34 disposed on an interlayer insulating film 29.

[0143] The main surface electrode film 33 is electrically connected to multiple body regions 11, multiple source regions 54, contact regions 56, and the main surface contact region 32, etc., via multiple first contact openings 30 and second contact openings 31. As a result, a body diode 80 is formed with the body region 11 as the anode and the second semiconductor layer 9 as the cathode (see Figure 12).

[0144] For example, when semiconductor device 1 is used in an inverter circuit, a freewheeling diode may be required to dissipate the current remaining in the inductance component when the MISFET is turned off. By passing current through the freewheeling diode, the energy stored in the inductance can be output, reducing surge voltages applied to the MISFET. A body diode 80 can be used as the freewheeling diode.

[0145] The gate electrode film 34 is electrically connected to the underlying wiring layer 22 via the gate contact opening 76. This connects the gate electrode film 34 to the gate electrode 60 via the underlying wiring layer 22. The gate potential applied to the gate pad electrode 37 is transmitted to the multiple gate electrode 60 via the gate wiring 38. This causes the multiple gate electrode 60 to turn on, controlling the on / off state of the multiple channel regions 55.

[0146] (3) Effects of the semiconductor device 1 The gate current from the gate pad electrode 37 is transmitted to a plurality of gate structures 12 (gate electrodes 60) via the gate wiring 38 (gate fingers) and the underlying wiring layer 22. When the gate structure 12 is striped, the gate current is generally supplied from both ends in the direction of extension of the gate structure 12. For example, the dashed arrow I in Figure 7 ２ The gate current flows and is supplied in the direction indicated.

[0147] However, for MISFETs made of wide-bandgap semiconductors such as SiC, it is desirable to reduce the on-resistance (Ron) from the viewpoint of reducing power consumption. In order to achieve a reduction in on-resistance, the chip size may be increased and the number of unit cells may be increased. As the chip size increases, the gate structure 12 becomes longer, and the distance from both ends becomes longer near the center in the direction of extension of the gate structure 12. As a result, due to signal propagation delay, variations in the switching speed occur in the gate structure 12.

[0148] Therefore, according to this semiconductor device 1, the gate structure 12 (gate electrode 60) has a striped main body portion 13, as well as a plurality of bridging portions (14) that connect a plurality of adjacent main body portions 13. As a result, the main body portion 13 of each gate structure 12 receives the gate current from the direction of extension of the gate structure 12 (dashed arrow I in Figure 7). ２ In addition, gate current is supplied from a direction intersecting the extending direction via the bridging section 14 (solid arrow I in Figure 7). １ As a result, the signal propagation delay near the center in the extending direction of the gate structure 12 can be eliminated.

[0149] Furthermore, by positioning the contact region 56 within the covering region 63 (see Figure 11) formed by the bridging portion 14, the area directly beneath the bridging portion 14 can be effectively utilized. In addition, the contact portion 67 of the contact region 56 protrudes outward from the gate electrode 60 (bridging portion 14) in the first direction X. This allows for proper connection between the contact region 56 and the main surface electrode film 33 on both sides of the bridging portion 14 in the first direction X.

[0150] Furthermore, well regions 16 and main surface contact regions 32 are formed to appropriately discharge holes from around the striped gate structure 12 and prevent defects inside the SiC. The main surface electrode film 33 and the main surface contact regions 32 are connected by contacts via a plurality of base openings 28. In this configuration, the plurality of base openings 28 are positioned so as not to overlap with the bridging portion 14 in the second direction Y. As a result, the base openings 28 do not obstruct the gate current in the path from the gate wiring 38 to the gate structure 12 (bridging portion 14), thereby further reducing the signal propagation delay.

[0151] (4) Variations in the layout of the bridging section 14 Next, variations in the layout of the bridging section 14 and the impurity region of the gate structure 12 will be described with reference to Figures 19 to 21. Figures 19 to 21 show the first to third modified examples of the layout of the bridging section 14 and the impurity region of the gate structure 12, respectively.

[0152] Referring to Figure 19, the arrangement period of the bridging sections 14 may be shorter than that shown in Figure 10. For example, the ratio (W1 / W2) of the width W1 of the bridging section 14 in the first direction X to the width W2 between adjacent bridging sections 14 in the first direction X may be, for example, 0.01 or more and 1 or less. The width W1 may be, for example, 0.1 μm or more and 10 μm, preferably 0.3 μm or more and 5 μm or less. The width W2 may be, for example, 0.1 μm or more and 1000 μm, preferably 0.3 μm or more and 500 μm or less.

[0153] Referring to Figure 20, the multiple bridging portions 14 may be arranged in a staggered pattern. Referring to Figure 21, the multiple striped body regions 11 may be separated in the contact region 56 formation region (covering region 63 in Figure 11). As a result, the multiple body regions 11 may provide multiple unit cells 52 arranged at intervals in the first direction X.

[0154] (5) Variations in the layout of the gate electrode film 34 Next, variations in the layout of the gate electrode film 34 will be described with reference to Figures 22 to 26. Figures 22 to 26 show the first to fifth modified examples of the layout of the gate electrode film 34, respectively.

[0155] Referring to Figure 22, the first finger wiring 41 extends from the base wiring 39 in a first direction X along the first side surface 5A and the third side surface 5C in that order, and may have a first tip portion 81 at the corner of the chip 2 where the third side surface 5C and the second side surface 5B intersect. The second finger wiring 42 extends from the base wiring 39 in a first direction X along the first side surface 5A and the fourth side surface 5D in that order, and may have a second tip portion 82 at the corner C of the chip 2 where the fourth side surface 5D and the second side surface 5B intersect. The third finger wiring 43 extends from the base wiring 39 toward the second side surface 5B and may have a third tip portion 83 in the vicinity of the second side surface 5B.

[0156] Referring to Figure 23, the first finger wiring 41 and the second finger wiring 42 may be connected to each other to provide a closed annular finger wiring 40 as a whole. In this case, the third tip 83 of the third finger wiring 43 may be spaced apart from the closed annular finger wiring 40.

[0157] Referring to Figure 24, the first finger wiring 41 extends from the base wiring 39 in the first direction X along the first side surface 5A, the third side surface 5C, and the second side surface 5B in that order, and may have a first tip portion 81 in the center of the second side surface 5B in the first direction X. The second finger wiring 42 extends from the base wiring 39 in the first direction X along the first side surface 5A, the fourth side surface 5D, and the second side surface 5B in that order, and may have a second tip portion 82 in the center of the second side surface 5B in the first direction X. The first tip portion 81 and the second tip portion 82 may face each other in the first direction X with a space S between them.

[0158] Referring to Figure 25, the gate electrode film 34 does not necessarily have to include the third finger wiring 43.

[0159] Referring to Figure 26, the first finger wiring 41 and the second finger wiring 42 may be connected to each other to provide a closed annular finger wiring 40 as a whole. In this case, the gate electrode film 34 does not need to include a third finger wiring 43.

[0160] (6) Variations in the layout of the base opening 28 (second contact opening 31) Next, variations in the layout of the base opening 28 (second contact opening 31) will be explained with reference to Figures 27 to 30. Figures 27 to 30 show the first to fourth modified examples of the layout of the base opening 28 (second contact opening 31), respectively.

[0161] Referring to Figure 27, at least one of the multiple base openings 28 (second contact openings 31) may be positioned to overlap the bridging portion 14 in a direction that spans the multiple main body portions 13. In other words, at least one of the multiple base openings 28 may be positioned adjacent to the bridging portion 14 in the second direction Y. In this configuration, base openings 28 that overlap the bridging portion 14 in the second direction Y and base openings 28 that do not overlap the bridging portion 14 are arranged alternately in the first direction X.

[0162] Referring to Figure 28, the number of lines of multiple substrate openings 28 (second contact openings 31) arranged linearly in the first direction X may be multiple. In this embodiment, three linearly arranged substrate openings 28 are formed. In this case, the multiple substrate openings 28 may be arranged in a matrix as a whole.

[0163] Referring to Figure 29, the number of lines of multiple substrate openings 28 (second contact openings 31) arranged linearly in the first direction X may be multiple. In this embodiment, three linearly arranged substrate openings 28 are formed. In this case, the multiple substrate openings 28 may be arranged in a staggered pattern as a whole.

[0164] Referring to Figure 30, the base opening 28 (second contact opening 31) does not need to be formed in multiple locations, but may be formed as a single strip in the first direction X.

[0165] (7) Variations in device structure Figure 31 is a cross-sectional view of a semiconductor device 1 having a trench gate structure. Referring to Figure 31, the semiconductor device 1 may be a semiconductor switching device having an insulated gate type trench structure Tr as an example of a device structure. The trench structure Tr has a trench gate type vertical structure.

[0166] The gate structure 12 includes a gate trench 91, a gate insulating film 92, and a gate electrode 93.

[0167] The gate trenches 91 are formed on the first main surface 3 and demarcate the inner surface of the gate structure 12. Between adjacent gate trenches 91, mesa portions 94 are formed by a part of the second semiconductor layer 9. The mesa portions 94 provide a unit cell 52 of the trench gate transistor. The unit cell 52 comprises at least a source region 54 and a body region 11 along the depth direction of the gate trench 91, starting from the first main surface 3 side.

[0168] The gate trench 91 integrally includes a trench body portion 95 and a trench bridging portion 96. The trench body portion 95 and the trench bridging portion 96 provide the main body portion 13 and the bridging portion 14 of the gate structure 12, respectively.

[0169] The trench body portion 95 is formed in a strip shape extending in a first direction X. In this configuration, multiple trench body portions 95 are arranged in a stripe shape extending in the first direction X. The trench bridging portion 96 crosses the area between multiple adjacent trench body portions 95 in a second direction Y, connecting the multiple adjacent trench body portions 95. Multiple adjacent trench body portions 95 are connected by the trench bridging portion 96, and in other parts they are spaced apart in the second direction Y. In this configuration, the gate trench 91 is formed in a grid shape by multiple trench body portions 95 and trench bridging portions 96.

[0170] The gate insulating film 92 covers the inner surface of the gate trench 91. The gate insulating film 92 may be made of the same material as the gate insulating film 59. The gate electrode 93 is embedded in the gate trench 91 and faces the body region 11 (channel region 55) across the gate insulating film 92. The gate electrode 93 may be made of the same material as the gate electrode 60 and the underlying wiring layer 22.

[0171] The contact area 56 may be formed at least at the bottom of the trench bridging portion 96. The contact area 56 may extend along the side surface of the gate trench 91 to the first main surface 3 and be exposed from the first main surface 3.

[0172] A semiconductor device 1 having a trench gate structure can exhibit the same effects and advantages as a semiconductor device 1 having a planar gate structure.

[0173] While embodiments of this disclosure have been described, this disclosure can also be implemented in other forms.

[0174] For example, in each of the embodiments described above, a chip 2 containing a SiC single crystal was used. However, chip 2 (first semiconductor layer 8 and second semiconductor layer 9) may also contain a single crystal of a wide-bandgap semiconductor other than a SiC single crystal. A wide-bandgap semiconductor is a semiconductor having a bandgap larger than that of silicon. Examples of wide-bandgap semiconductor single crystals include gallium nitride, diamond, and gallium oxide. Of course, chip 2 (first semiconductor layer 8 and second semiconductor layer 9) may also contain a silicon single crystal.

[0175] In each of the above-described embodiments, a structure may be adopted in which the conductivity type of the "n-type" semiconductor region is inverted to "p-type," and the conductivity type of the "p-type" semiconductor region is inverted to "n-type." The specific configuration in this case can be obtained by replacing "n-type" with "p-type" and simultaneously replacing "p-type" with "n-type" in the above description and attached drawings.

[0176] In each of the above-described embodiments, a p-type collector region may be formed on the surface layer of the second main surface 4 of the chip 2. In this case, the transistor structure Tr includes an IGBT (Insulated Gate Bipolar Transistor) structure instead of a MISFET structure. The specific configuration in this case is obtained by replacing the "source" of the MISFET structure with the "emitter" of the IGBT structure and the "drain" of the MISFET structure with the "collector" of the IGBT structure, as described above. In this case, the chip 2 may have a single-layer structure made of an n-type semiconductor substrate.

[0177] The following are examples of features extracted from this specification and drawings. The alphanumeric characters in parentheses below represent the corresponding components in the embodiments described above, but this is not intended to limit the scope of each Clause to the embodiments. The term "semiconductor device" in the following items may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier," "MISFET device," "IGBT device," "diode device," etc., as needed.

[0178] [Note 1-1] A chip (2) having a main surface (3) including an active region (6), a first conductivity type semiconductor region (9, 10) formed on the surface of the main surface (3), a stripe-shaped second conductivity type base impurity region (11, 16) formed on the surface of the semiconductor region (9, 10) and extending in a first direction (X), a first impurity region (54) formed on the surface of the base impurity region (11, 16) in the active region (6), a plurality of stripe-shaped main body portions (13) extending in the first direction (X) in the active region (6), and a plurality of bridging portions (14) connecting adjacent main body portions (13), and a gate structure (12) facing a channel region (55) formed by a part of the base impurity region (11, 16), A semiconductor device (1) comprising a second impurity region (56) of a second conductivity type, which is selectively formed in the covering region (63) of the main surface (3) covered by the bridging portion (14) and connected to the base impurity region (11, 16).

[0179] [Note 1-2] The semiconductor device (1) according to Note 1-1, wherein the base impurity region (11, 16) includes a base coating portion (64) formed on the coating region (63), and the second impurity region (56) is connected to the base coating portion (64).

[0180] [Note 1-3] The semiconductor device (1) according to Note 1-2, wherein the first impurity region (54) includes a first coating portion (65) formed on the surface of the base coating portion (64), and the second impurity region (56) is connected to the base coating portion (64) by penetrating the first coating portion (65).

[0181] [Appendix 1-4] The semiconductor device (1) according to any one of Appendix 1-1 to 1-3, wherein the base impurity regions (11, 16) have unit cells (52) extending in a strip shape in the first direction (X), the first impurity region (54) is spaced inward from both ends of the unit cells (52) in a second direction (Y) intersecting the first direction (X), and the second impurity region (56) is spaced further inward from both ends of the first impurity region (54) in the second direction (Y).

[0182] [Appendix 1-5] A semiconductor device (1) according to any one of Appendix 1-1 to 1-4, comprising: an insulating layer (29) formed on the main surface (3); a gate electrode film (34) formed on the insulating layer (29) and electrically connected to the gate structure (12), the gate electrode film (34) including a pad portion (37) and a finger portion (38) extending in a strip shape from the pad portion (37) and surrounding the active region (6); and a main surface electrode film (33) formed on the insulating layer (29) in the active region (6) and electrically connected to the first impurity region (54).

[0183] [Note 1-6] The semiconductor device (1) according to Note 1-5, wherein the finger portion (38) includes a first finger portion (43) extending from the pad portion (37) in a direction across the plurality of main body portions (13) and second finger portions (41, 42) extending from the pad portion (37) in a direction along the plurality of main body portions (13).

[0184] [Appendix 1-7] The semiconductor device (1) according to Appendix 1-5 or Appendix 1-6, further comprising a base wiring layer (22) disposed between the main surface (3) and the insulating layer (29), connected to the gate structure (12) in the active region (6), and supplying current from the gate electrode film (34) to the gate structure (12), wherein the base wiring layer (22) has a base opening (28) outside the gate structure (12) that provides contact between the base impurity region (11, 16) and the main surface electrode film (33).

[0185] [Note 1-8] The semiconductor device (1) described in Note 1-7, wherein the base opening (28) is located adjacent to the outermost body portion (13) of the plurality of body portions (13).

[0186] [Appendix 1-9] The semiconductor device (1) according to Appendix 1-8, comprising a plurality of base openings (28) arranged at intervals in a direction along the outermost main body portion (13), wherein at least one of the plurality of base openings (28) is positioned so as not to overlap with the bridging portion (14) in a direction traversing the plurality of main body portions (13).

[0187] [Appendix 1-10] The semiconductor device (1) according to Appendix 1-8 or Appendix 1-9, wherein the base wiring layer (22) integrally includes a first base portion (23, 27) extending in a direction transverse to the plurality of main body portions (13) and a second base portion (25, 26) extending in a direction along the plurality of main body portions (13), and the plurality of base openings (28) are selectively formed in the second base portion (25, 26) of the first base portion (23, 27) and the second base portion (25, 26).

[0188] [Appendix 1-11] The semiconductor device (1) according to any one of Appendix 1-7 to 1-10, further comprising a second conductivity type base contact region (32) formed in the active region (6) along the plurality of main body portions (13) in a part of the surface portion of the base impurity region (11, 16) and exposed from the base opening (28).

[0189] [Appendix 1-12] The semiconductor device (1) according to Appendix 1-11, wherein the base impurity region (11, 16) includes an active well region (19) within the active region (6) and an outer well region (20) extending from the active well region (19) to an outer peripheral region outside the gate electrode film (34), and the base contact region (32) is selectively formed in the active well region (19) from among the active well region (19) and the outer well region (20).

[0190] [Appendix 1-13] The semiconductor device (1) according to any one of Appendix 1-5 to 1-10, wherein the second impurity region (56) includes a contact portion (67) that protrudes outward from the bridging portion (14) in the first direction (X), the insulating layer (29) has a contact opening (30) that extends in a strip shape in the first direction (X) and exposes the first impurity region (54) and the contact portion (67) together, and the main surface electrode film (33) is connected to the first impurity region (54) and the contact portion (67) within the contact opening (30).

[0191] [Appendix 1-14] The semiconductor device (1) according to any one of the appendices 1-1 to 1-13, wherein the plurality of bridging portions (14) are arranged in a line along the direction that crosses the plurality of main body portions (13).

[0192] [Appendix 1-15] The plurality of bridging portions (14) are arranged in a staggered pattern, the semiconductor device (1) according to any one of the appendices 1-1 to 1-13.

[0193] [Appendix 1-16] The semiconductor device (1) according to any one of Appendix 1-1 to 1-15, wherein the ratio (W1 / W2) of the width W1 of the bridging portion (14) in the first direction (X) to the width W2 between adjacent bridging portions (14) in the first direction (X) is 0.01 or more and 1 or less.

[0194] [Appendix 1-17] The gate structure (12) is a semiconductor device (1) according to any one of the appendices 1-1 to 1-16, including a planar gate structure (12).

[0195] [Appendix 1-18] The gate structure (12) is a trench gate structure (12) as described in any one of Appendix 1-1 to 1-16.

[0196] [Appendix 1-19] The semiconductor device (1) according to any one of the appendices 1-1 to 1-18, wherein the base impurity region (11, 16) is a body region (11), the first impurity region (54) is a source region (54), and the second impurity region (56) is a body contact region (56) with a higher concentration than the body region (11).

[0197] [Appendix 1-20] The semiconductor device (1) described in any one of the appendices 1-1 to 1-19, wherein the chip (2) is a semiconductor chip (2) formed of a wide bandgap semiconductor.

[0198] 1: Semiconductor device, 2: Chip, 3: First main surface, 4: Second main surface, 5A: First side surface, 5B: Second side surface, 5C: Third side surface, 5D: Fourth side surface, 6: Active region, 7: Outer peripheral region, 8: First semiconductor layer, 9: Second semiconductor layer, 10: Drift region, 11: Body region, 12: Gate structure, 13: Main body, 14: Bridging portion, 15: Gate opening, 16: Well region, 17A: First well edge, 17B: Second well edge, 17C: Third well edge, 17D: Fourth well edge, 18: Field region, 19: Active well region, 20: Outer well region 21: Surface insulating film, 22: Underlayment wiring layer, 23: Base portion, 24: Extension portion, 25: First extension portion, 26: Second extension portion, 27: Third extension portion, 28: Underlayment opening, 29: Interlayer insulating film, 30: First contact opening, 31: Second contact opening, 32: Main surface contact region, 33: Main surface electrode film, 34: Gate electrode film, 35: First electrode region, 36: Second electrode region, 37: Gate pad electrode, 38: Gate wiring, 39: Base wiring, 40: Finger wiring, 41: First finger wiring, 42: Second finger wiring, 43: Third finger wiring 44: Protective film, 45: Gate pad, 46: Gate pad opening, 47: First source pad, 48: Second source pad, 49: First source pad opening, 50: Second source pad opening, 51: Drain pad electrode, 52: Unit cell, 53: Surface drift region, 54: Source region, 55: Channel region, 56: Contact region, 57: First section, 58: Second section, 59: Gate insulating film, 60: Gate electrode, 61: First active region, 62: Second active region, 63: Covering region, 64: Body covering portion, 65: Source covering portion, 66: Covering portion 67: Contact portion, 68: Electrode removal region, 69: First portion, 70: Second portion, 71: Third portion, 72: Fourth portion, 73: Gate projection, 74: Internal opening, 75: Space, 76: Gate contact opening, 77: Base contact opening, 78: Pad contact opening, 79: Finger contact opening, 80: Body diode, 81: First tip, 82: Second tip, 83: Third tip, 91: Gate trench, 92: Gate insulating film, 93: Gate electrode, 94: Mesa portion, 95: Trench body portion, 96: Trench bridging portion

Claims

1. A semiconductor device comprising: a chip having a main surface including an active region; a semiconductor region of a first conductivity type formed on the surface layer of the main surface; a stripe-shaped base impurity region of a second conductivity type formed on the surface layer of the semiconductor region and extending in a first direction; a first impurity region formed on the surface layer of the base impurity region in the active region; a gate structure facing a channel region formed by a part of the base impurity region, including a plurality of stripe-shaped main body portions extending in the first direction in the active region and a plurality of bridging portions connecting adjacent main body portions; and a second impurity region of a second conductivity type selectively formed in a covering region of the main surface covered by the bridging portions and connected to the base impurity region.

2. The semiconductor device according to claim 1, wherein the base impurity region includes a base coating portion formed in the coating region, and the second impurity region is connected to the base coating portion.

3. The semiconductor device according to claim 2, wherein the first impurity region includes a first coating formed on the surface layer of the base coating, and the second impurity region penetrates the first coating and is connected to the base coating.

4. The semiconductor device according to any one of claims 1 to 3, wherein the base impurity region has a unit cell extending in a strip shape in the first direction, the first impurity region is spaced inward from both ends of the unit cell in a second direction intersecting the first direction, and the second impurity region is spaced further inward from both ends of the first impurity region in the second direction.

5. A semiconductor device according to any one of claims 1 to 4, comprising: an insulating layer formed on the main surface; a gate electrode film formed on the insulating layer and electrically connected to the gate structure, the gate electrode film including a pad portion and a finger portion extending in a strip shape from the pad portion and surrounding the active region; and a main surface electrode film formed on the insulating layer in the active region and electrically connected to the first impurity region.

6. The semiconductor device according to claim 5, wherein the finger portion includes a first finger portion extending from the pad portion in a direction traversing the plurality of main body portions, and a second finger portion extending from the pad portion in a direction along the plurality of main body portions.

7. The semiconductor device according to claim 5 or 6, further comprising a base wiring layer disposed between the main surface and the insulating layer, connected to the gate structure in the active region, and supplying current from the gate electrode film to the gate structure, wherein the base wiring layer has a base opening that provides contact between the base impurity region and the main surface electrode film outside the gate structure.

8. The semiconductor device according to claim 7, wherein the base opening is located adjacent to the outermost body portion of the plurality of body portions.

9. The semiconductor device according to claim 8, comprising a plurality of base openings arranged at intervals in a direction along the outermost main body portion, wherein at least one of the plurality of base openings is positioned so as not to overlap the bridging portion in a direction traversing the plurality of main body portions.

10. The semiconductor device according to claim 8 or 9, wherein the base wiring layer integrally includes a first base portion extending in a direction transverse to the plurality of main body portions and a second base portion extending in a direction along the plurality of main body portions, and the plurality of base openings are selectively formed in the second base portion among the first base portion and the second base portion.

11. The semiconductor device according to any one of claims 7 to 10, further comprising a second conductive base contact region formed in a part of the surface layer of the base impurity region along the plurality of main body portions in the active region and exposed from the substrate opening.

12. The semiconductor device according to claim 11, wherein the base impurity region includes an active well region within the active region and an outer well region extending from the active well region to an outer peripheral region outside the gate electrode film, and the base contact region is selectively formed in the active well region from among the active well region and the outer well region.

13. The semiconductor device according to any one of claims 5 to 10, wherein the second impurity region includes a contact portion that protrudes outward from the bridging portion in the first direction, the insulating layer has a contact opening that extends in a strip shape in the first direction and exposes the first impurity region and the contact portion together, and the main surface electrode film is connected to the first impurity region and the contact portion within the contact opening.

14. The semiconductor device according to any one of claims 1 to 13, wherein the plurality of bridging portions are arranged in a line along a direction that crosses the plurality of main body portions.

15. The semiconductor device according to any one of claims 1 to 13, wherein the plurality of bridging portions are arranged in a staggered pattern.

16. The semiconductor device according to any one of claims 1 to 15, wherein the ratio (W1 / W2) of the width W1 of the bridging portion in the first direction to the width W2 between adjacent bridging portions in the first direction is 0.01 or more and 1 or less.

17. The semiconductor device according to any one of claims 1 to 16, wherein the gate structure includes a planar gate structure.

18. The semiconductor device according to any one of claims 1 to 16, wherein the gate structure includes a trench gate structure.

19. The semiconductor device according to any one of claims 1 to 18, wherein the base impurity region is a body region, the first impurity region is a source region, and the second impurity region is a body contact region with a higher concentration than the body region.

20. The semiconductor device according to any one of claims 1 to 19, wherein the chip is a semiconductor chip formed of a wide-bandgap semiconductor.

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