Wiring board, electronic device, and electronic module

Abstract

This wiring board comprises: an insulating substrate that has a plurality of insulating layers and includes a first surface, a second surface positioned on the opposite side from the first surface, and a third surface having a step between the third surface and the first surface or the second surface; and a first conductor that is positioned in the insulating substrate and extends in a direction intersecting the first surface or the second surface. When, among interlayers of the plurality of insulating layers, an interlayer continuous with the third surface is referred to as a first interlayer, the first conductor has a first via conductor connected to the first interlayer, a second via conductor connected to the first via conductor and positioned in an insulating layer spaced apart from the first interlayer, and a first pad conductor positioned in the first interlayer. The width of the first via conductor is smaller than the width of the second via conductor, and the width of the first pad conductor is larger than the width of the second via conductor.

Description

Wiring Substrate, Electronic Device, and Electronic Module

[0001] The present disclosure relates to a wiring substrate, an electronic device, and an electronic module.

[0002] Japanese Unexamined Patent Application Publication No. 2008 - 311682 discloses a wiring substrate in which a signal transmission path is located on an insulating substrate in which a plurality of insulating layers are laminated.

[0003] The wiring substrate according to the present disclosure includes: an insulating substrate having a plurality of insulating layers, a first surface, a second surface located on the opposite side of the first surface, and a third surface having a step between the first surface or the second surface; a first conductor located on the insulating substrate and extending in a direction intersecting the first surface or the second surface. When an interlayer connected to the third surface among the interlayers of the plurality of insulating layers is called a first interlayer, the first conductor has a first via conductor connected to the first interlayer, a second via conductor located in an insulating layer away from the first interlayer and connected to the first via conductor, and a first pad conductor located in the first interlayer. The width of the first via conductor is smaller than the width of the second via conductor, and the width of the first pad conductor is larger than the width of the second via conductor.

[0004] The electronic device according to the present disclosure includes the above wiring substrate and an electronic element mounted on the wiring substrate.

[0005] The electronic module according to the present disclosure includes the above electronic device and a module substrate on which the electronic device is mounted.

[0006] This is a cross-sectional view showing a wiring board according to Embodiment 1 of this disclosure. This is an enlarged view showing the main part of the wiring board according to Embodiment 1 of this disclosure. This is a graph showing the characteristic impedance of the transmission line in Embodiment 1. This is a graph showing the characteristic impedance of the transmission line in a comparative example. This is a graph showing the reflection loss of the transmission line in Embodiment 1. This is a graph showing the reflection loss of the transmission line in a comparative example. This is a cross-sectional view showing a wiring board according to Embodiment 2 of this disclosure. This is a cross-sectional view showing a wiring board according to Embodiment 3 of this disclosure. This is a cross-sectional view showing a wiring board according to Embodiment 4 of this disclosure. This is a cross-sectional view showing a wiring board according to Embodiment 5 of this disclosure. This is a cross-sectional view showing a wiring board according to Embodiment 6 of this disclosure. This is a cross-sectional view showing a wiring board according to Embodiment 7 of this disclosure. This is a cross-sectional view showing a wiring board according to Embodiment 8 of this disclosure. This is a cross-sectional view showing a wiring board according to Embodiment 9 of this disclosure. This is a cross-sectional view showing a wiring board according to Embodiment 10 of this disclosure. This is an enlarged view showing the main part of the wiring board according to Embodiment 10 of this disclosure. This is a cross-sectional view showing a wiring board according to Embodiment 11 of this disclosure. This is an enlarged view showing the main part of the wiring board according to Embodiment 11 of this disclosure. This is a cross-sectional view showing a wiring board according to Embodiment 12 of this disclosure. This is a cross-sectional view showing a wiring board according to Embodiment 13 of this disclosure. This is a cross-sectional view showing a wiring board according to Embodiment 14 of this disclosure. This is an enlarged view showing the main part of a wiring board according to Embodiment 14 of this disclosure. This is a cross-sectional view showing a wiring board according to Embodiment 15 of this disclosure. This is an enlarged view showing the main part of a wiring board according to Embodiment 15 of this disclosure. This is a diagram showing an electronic device and an electronic module according to an embodiment of this disclosure.

[0007] Each embodiment of this disclosure will be described in detail below with reference to the drawings. For the sake of clarity, the drawings shown below are simplified to show only the components necessary for describing the embodiments. Therefore, the wiring board, electronic device, and electronic module according to the embodiments may include any components not shown in the drawings. The dimensions of the components in each drawing do not faithfully represent the dimensions of the actual components or the dimensional ratios of each component. Regarding the orientation of the wiring board, electronic device, and electronic module, the direction perpendicular to the first surface S1 is called the vertical direction, and the direction along the first surface S1 is called the horizontal direction. In the following description, "plan view" means a view in the vertical direction, or a view through the vertical direction.

[0008] (Embodiment 1) Figures 1A and 1B are a cross-sectional view and an enlarged view showing the main part of a wiring board 1 according to Embodiment 1 of the present disclosure. The wiring board 1 of Embodiment 1 may have an insulating substrate 10 and a conductor 20 located within the insulating substrate 10. The insulating substrate 10 may have a configuration in which a plurality of insulating layers 11 are laminated. The conductor 20 may include via conductors 21 extending to penetrate each insulating layer 11, pad conductors 24 connecting the upper via conductor 21 and the lower via conductor 21, and film-like conductors 28 spreading linearly or planarly in the interlayer 12. The via conductors 21 may be columnar conductors extending in the vertical direction. The pad conductors 24 may be film-like conductors with various pad shapes in plan view, such as circular, elliptical, regular polygonal, polygonal, or shapes with rounded corners. Furthermore, the wiring board 1 may have electrode pads 29 exposed on its surface.

[0009] The insulating substrate 10 may include an upper first surface S1, a lower second surface S2, and a third surface S3 having a step between it and the first surface S1 or the second surface S2. "Having a step" can be rephrased as "having different heights in the vertical direction." The third surface S3 may be the bottom surface of a cavity (i.e., recess) 3, or the stepped surface of a stepped portion 3G (see Figure 7A). Alternatively, the third surface S3 may be the upper surface of a cavity 3B (see Figure 6B) that opens downwards, or the stepped surface facing downwards. In the following description, among the interlayers 12 of the plurality of insulating layers 11, the interlayer 12 connected to the third surface S3 will be referred to as the first interlayer 12A.

[0010] The insulating substrate 10 may be composed of, for example, an aluminum oxide sintered body, an aluminum nitride sintered body, a silicon carbide sintered body, a silicon nitride sintered body, a mullite sintered body, or a ceramic material such as glass ceramics. The insulating substrate 10 may also be composed of, for example, an organic insulating material such as polyimide, epoxy resin, fluororesin, polynorbornene, or benzocyclobutene.

[0011] <First Conductor 201> The wiring board 1 may include a first conductor 201 located on the insulating substrate 10 and extending in a direction intersecting the first surface S1 or the second surface S2. The first conductor 201 may be a signal conductor of a transmission line 200 that transmits high-frequency signals. The transmission line 200 may include the first conductor 201, which is a signal conductor, and a ground conductor 231 located around the first conductor 201. The ground conductor 231 may include a plurality of via conductors 21 located around the first conductor 201, and the via conductors 21 may be spaced apart from the first conductor 201 and positioned to surround the first conductor 201.

[0012] The transmission line 200 may include, in addition to the first conductor 201, a second conductor 202 extending in the horizontal direction such as front, back, left, and right, and a third conductor 203 extending in a direction that intersects the first plane S1 at a horizontally different position from the first conductor 201. Furthermore, multiple grounding conductors 232 may be positioned around the second conductor 202 so as to surround it. Similarly, multiple grounding conductors 233 may be positioned around the third conductor 203 so as to surround it. The first conductor 201, the second conductor 202, and the third conductor 203 may be connected in order. One end and the other end of the transmission line 200 may be located on the first plane S1 and the second plane S2. Note that the transmission line 200 is not limited to the path shown in Figure 1A, and various paths extending in the up, down, left, and right directions, or various paths including return trips in the up, down, left, and right directions in addition to the said path, may be adopted. Alternatively, the transmission line 200 may be a path that extends only in the vertical direction from the first surface S1 to the second surface S2. Furthermore, one end of the transmission line 200 is not limited to the example in Figure 1A, but may be located on the third surface S3, the side of the insulating substrate 10, or the side of a stepped portion. Furthermore, the second conductor 202 extending in the horizontal direction may have at least a portion of its length located on the third surface S3, and the open side of the third surface S3 of that portion may not be covered by the ground conductor.

[0013] In addition, although not shown in Figure 1A, the transmission line 200 may have two conductors (for example, signal conductors) extending parallel to each other, and a differential signal may be transmitted between these two conductors. Furthermore, the first conductor 201 may be included in at least one of these two conductors.

[0014] The first conductor 201 may have a first via conductor 211 connected to the first interlayer 12A, a second via conductor 212 located in the insulating layer 11 away from the first interlayer 12A, and a first pad conductor 241 located in the first interlayer 12A. Furthermore, as shown in equation (1) below, the width W211 of the first via conductor 211 may be smaller than the width W212 of the second via conductor 212, and the width W241 of the first pad conductor 241 may be larger than the width W212 of the second via conductor 212. W211 < W212 < W241 ... (1)

[0015] The second via conductor 212 may be a via conductor 21 located apart from the first layer 12A, separated by two or more insulating layers 11. The second via conductor 212 may also be a via conductor 21 that extends to the third surface S3 or the first surface S1.

[0016] The "width" mentioned above is defined as the maximum width in the horizontal direction. If the first via conductor 211 and the second via conductor 212 are cylindrical, "width" may be replaced with "diameter". If the first pad conductor 241 and the second pad conductor 242 (described later) are circular in plan view, the "width" of the first pad conductor 241 and the second pad conductor 242 (described later) may be replaced with "diameter".

[0017] The first conductor 201 having the relationship shown in equation (1) provides the following effect. That is, the step difference on the third surface S3 causes a difference in volume between the lower insulating layer 11 and the upper insulating layer 11 of the first interlayer 12A. Therefore, in the manufacturing process of the wiring board 1 (e.g., the firing process), a difference in the amount of thermal shrinkage occurs between the two insulating layers 11. Consequently, even if predetermined points on the lower and upper sides of the first interlayer 12A are designed to overlap, errors may be present in the arrangement that prevents these predetermined points from overlapping precisely. However, the presence of the first pad conductor 241 with a large width W241 absorbs these errors, reducing the likelihood of the connection of the first via conductor 211 being interrupted in the first interlayer 12A. More specifically, if the first via conductor 211 extends so as to cross the first interlayer 12A, the likelihood of the connection between the upper first via conductor 211 and the lower first via conductor 211 in the first interlayer 12A being severed is reduced. Also, although different from Figure 1A, if the first via conductor 211 is connected to a second conductor 202 that extends horizontally in the first interlayer 12A (see Figure 5A), the likelihood of the connection between the first via conductor 211 and the second conductor 202 being severed is reduced.

[0018] Furthermore, the presence of the wide first pad conductor 241 makes it easy for an impedance mismatch to occur at that point in the transmission line 200. However, by having the first via conductor 211 having the relationship shown in equation (1) above, the above impedance mismatch can be reduced, and the degradation of transmission characteristics caused by this mismatch can be reduced.

[0019] When the multiple interlayer spaces 12 between the multiple insulating layers 11 where the second via conductor 212 intersects are called the second interlayer space 12B, the first conductor 201 may further include a second pad conductor 242 located in the second interlayer space 12B. The second pad conductor 242 may be located in all of the second interlayer spaces 12B, or it may be located in only some of the interlayer spaces of the multiple second interlayer spaces 12B.

[0020] Furthermore, as shown in equation (2) below, the widths W211 of the first via conductor 211, W212 of the second via conductor 212, W241 of the first pad conductor 241, and W242 of the second pad conductor 242 may satisfy the following inequality: W211 < W212 < W242 < W241 ... (2)

[0021] In this configuration as well, the wide first pad conductor 241 can absorb the error in the overlapping position between the upper and lower sides of the first interlayer 12A, and can reduce the mismatch in characteristic impedance near the first interlayer 12A in the transmission line 200.

[0022] <Characteristic Impedance and Transmission Characteristics> Figures 2A and 2B are graphs showing the characteristic impedance of the transmission lines in Embodiment 1 and the Comparative Example, respectively. These graphs show the results of simulating the characteristic impedance using the TDR (Time Domain Reflectometry) method. Figures 3A and 3B are graphs showing the reflection losses of the transmission lines in Embodiment 1 and the Comparative Example, respectively. The Comparative Example in Figures 2B and 3B has a configuration in which the width of the first via conductor 211 in Figure 1B is the same as the width of the second via conductor 212.

[0023] As shown at location C2 in Figure 2B, in the comparative example, there is a region near the first pad conductor 241 where the characteristic impedance decreases due to the parasitic capacitance of the first pad conductor 241. Furthermore, as shown in Figure 3B, a return loss exceeding -15 dB occurs in the 48 GHz to 56 GHz band. On the other hand, as shown at location C1 in Figure 2A, in the wiring board 1 of Embodiment 1, the decrease in characteristic impedance near the first interlayer 12A is eliminated. Furthermore, as shown in Figure 3B, even in the 48 GHz to 60 GHz band, the return loss is -15 dB or less, demonstrating excellent transmission characteristics.

[0024] (Embodiments 2-9) Figures 4A to 7B are cross-sectional views showing wiring boards 1A to 1H of Embodiments 2 to 9 of the present disclosure. In the wiring board 1A of Embodiment 2 in Figure 4A, one end of the first conductor 201 is located on the first surface S1. In the wiring board 1B of Embodiment 3 in Figure 4B, a second via conductor 212, which is wider than the first via conductor 211, is connected to both the lower and upper sides of the first via conductor 211. In addition, in the wiring boards 1A and 1B, the first via conductor 211 is located in two layers: the upper insulating layer 11 and the lower insulating layer 11 of the first interlayer 12A.

[0025] In the wiring boards 1C and 1D of embodiments 4 and 5 shown in Figures 5A and 5B, the first via conductor 211 is connected to the second conductor 202 in the first interlayer 12A. Furthermore, in the wiring board 1C of embodiment 4, one end of the first conductor 201 is located on the second surface S2, while in the wiring board 1D of embodiment 5, one end of the first conductor 201 is located on the first surface S1.

[0026] In the wiring board 1E of Embodiment 6 in Figure 6A, the cavity 3 is located on the second surface S2 side, and in the wiring board 1F of Embodiment 7 in Figure 6B, the two cavities 3A and 3B are located on the first surface S1 side and the second surface S2 side. Since the wiring board 1F of Embodiment 7 has two cavities 3A and 3B, it may also have two third surfaces S3A and S3B as a third surface S3 having a step between it and the first surface S1 or the second surface S2. Furthermore, the wiring board 1F may have two first interlayers 12Aa and 12Ab connected to the third surfaces S3A and S3B, respectively. And in each of the two first interlayers 12Aa and 12Ab, the wiring board 1F may have two sets of first via conductors 211a and 211b as first via conductors 211 with a narrow width. Furthermore, in each of the two first layers 12Aa and 12Ab, the wiring board 1F may have two first pad conductors 241a and 241b, which are wider first pad conductors 241.

[0027] As shown in the wiring board 1G of Embodiment 8 in Figure 7A, the third surface S3 may not be the bottom surface of the cavity, but rather constitute the stepped surface of the stepped portion 3G.

[0028] In the wiring boards 1A to 1G of embodiments 2 to 8 shown above, the first conductor 201 has a structure that satisfies the relationship of formula (1) or formula (2) above. With this structure, the same effects and advantages as in embodiment 1 are achieved.

[0029] Figure 7B is a cross-sectional view showing a wiring board 1H of Embodiment 9 of the present disclosure. In the wiring board 1H of Embodiment 9, the first conductor 201 does not have a second pad conductor 242 that is wider than the second via conductor 212, and the multiple second via conductors 212 are connected without a wide pad conductor 24. In this configuration as well, the first conductor 201 has a structure that satisfies the relationship of formula (1) above. And with this structure, the same effects as in Embodiment 1 are achieved.

[0030] In embodiments 1 to 9, the narrow-width first via conductor 211 was shown to be located across one insulating layer 11 adjacent to the first interlayer 12A, or across two insulating layers 11 adjacent above and below the first interlayer 12A. However, the narrow-width first via conductor 211 may also be located across multiple insulating layers 11, such as two or three layers, that are continuous with the first interlayer 12A. If one insulating layer 11 is thin, the first via conductor 211 may be located across more insulating layers 11.

[0031] (Embodiments 10-13) Figures 8A, 9A, 10A, and 10B are cross-sectional views showing wiring boards 1I-1L of embodiments 10-13 of the present disclosure. Figures 8B and 9B are enlarged views showing the main parts of wiring boards 1I and 1J of embodiments 10 and 11. Embodiments 10-13 may be the same as the configurations of embodiments 1-9, except that the configuration of the pad conductors 24 connected to the first via conductor 211 is different.

[0032] In embodiments 10 to 13, among the multiple interlayers 12, the interlayer 12 to which the first via conductor 211 and the second via conductor 212 are connected is referred to as the connecting interlayer 12C. As shown in the wiring boards 1I to 1L, the first conductor 201 may have a connecting layer pad conductor 248 located in the connecting interlayer 12C. The connecting layer pad conductor 248 is one of the multiple pad conductors 24, and the width W248 of the connecting layer pad conductor 248 may be greater than the width W242 of the second pad conductor 242, as shown in the following equation (3) (see Figures 8B and 9B). W242 < W248 ... (3)

[0033] This configuration reduces abrupt changes in impedance of the transmission line 200 in the interlayer 12C. Therefore, the signal transmission characteristics in the high-frequency band can be further improved in the transmission line 200.

[0034] Furthermore, as in the wiring boards 1I to 1L of embodiments 10 to 13, the width W248 of the connecting layer pad conductor 248 may be given by the following equation (4). That is, the width W248 of the connecting layer pad conductor 248 may be greater than the width W212 of the second via conductor 212 and different from the width W241 of the first pad conductor 241 (see Figures 8B and 9B). W212 < W248 ≠ W241 ... (4) In this configuration as well, the abrupt change in impedance of the transmission line 200 in the inter-connecting layer 12C can be reduced. Therefore, the signal transmission characteristics in the high-frequency band, such as reflection loss, can be further improved.

[0035] In the wiring boards 1J and 1L of embodiments 11 and 13, one or more interlayers 12 are located between the first interlayer 12A and the connecting interlayer 12C, and these one or more interlayers 12 are referred to as the third interlayer 12D. As shown in the wiring boards 1J and 1L, the first conductor 201 may have a third pad conductor 243 located in the third interlayer 12D. The third pad conductor 243 may be one of the multiple pad conductors 24, and the width W243 of the third pad conductor 243 may be greater than the width W242 of the second pad conductor 242, as shown in the following equation (5) (see Figure 9B). W242 < W243 ... (5) With this configuration, by appropriately selecting the width W243 of the third pad conductor 243 at the design stage, adjustments can be made to reduce abrupt impedance changes in the transmission line 200 from the first interlayer 12A to the connecting interlayer 12C. Therefore, signal transmission characteristics in the high-frequency band, such as reflection loss, can be further improved.

[0036] As shown in the wiring board 1L of Embodiment 13, the width W243 of the third pad conductor 243 may be greater than the width W212 of the second via conductor 212 and different from the width W241 of the first pad conductor 241, as shown in the following equation (6): W212 < W243 ≠ W241 ... (6) In this configuration as well, by appropriately selecting the width W243 of the third pad conductor 243 at the design stage, adjustments can be made to reduce abrupt impedance changes in the transmission line 200 from the first interlayer 12A to the connecting interlayer 12C. Therefore, signal transmission characteristics in the high-frequency band, such as reflection loss, can be further improved.

[0037] (Embodiments 14, 15) Figures 11A and 12A are cross-sectional views showing wiring boards 1M and 1N of embodiments 14 and 15 of the present disclosure. Figures 11B and 12B are enlarged views showing the main parts of wiring boards 1M and 1N of embodiments 14 and 15. Embodiments 14 and 15 may be configured with the components of embodiments 1 to 13, except that the width of the first via conductor 211 is thinner than the second via conductor 212.

[0038] As in the wiring boards 1M and 1N of embodiments 14 and 15, the first via conductor 211 may have multiple sections with different widths. In other words, as shown in Figure 11A, the first via conductor 211 may be located across multiple consecutive insulating layers 11. The width W211a of the first via conductor 211a located in one insulating layer 11 may be different from the width W211b of the first via conductor 211b located in another insulating layer 11. Similarly, as shown in Figure 12A, the first via conductor 211 may be located across three consecutive insulating layers 11. The width W211c of the first via conductor 211c located in one insulating layer 11 may be different from the width W211d of the first via conductor 211d located in another insulating layer 11, and the width W211e of the first via conductor 211e located in yet another insulating layer 11.

[0039] As shown in Figures 11A and 12A, the widths of the multiple first via conductors 211 may increase in stages, approaching the width of the second via conductor 212 as they get closer. Specifically, as shown in Figure 11B, when the first via conductors 211a and 211b are arranged toward the second via conductor 212, the relationship shown in the following equation (7) may be: W211a < W211b < W212 ... (7)

[0040] Furthermore, as shown in the configuration of Figure 12B, when the first via conductors 211 are arranged as 211c, 211d, and 211e toward the second via conductor 212, the relationships shown in equation (8) or equation (9) below may also be applicable. W211c < W211d < W211e < W212 ... (8) W211c = W211d < W211e < W212 ... (9)

[0041] According to the configurations of embodiments 14 and 15, the width of the via conductor 21 gradually changes from the first via conductor 211 to the second via conductor 212, thereby reducing abrupt changes in impedance at that point. As a result, signal transmission characteristics in the high-frequency band, such as reflection loss, can be further improved.

[0042] In addition, in Embodiments 14 and 15, the first via conductor 211 has been shown to have a configuration in which the width gradually increases toward the second via conductor 212. However, various patterns of the order of the widths, such as a configuration in which the width decreases and then increases toward the second via conductor 212, can be applied. According to this configuration, adjustment can be made to reduce a sudden impedance change of the transmission line 200 in the section across the first via conductor 211 in the design stage. Therefore, the signal transmission characteristics in the high-frequency band, such as reflection loss, can be further improved.

[0043] <Manufacturing Method> The wiring boards 1, 1A to 1N of the above embodiments can be manufactured as follows. Note that the manufacturing method shown below is merely an example, and the wiring boards 1, 1A to 1N can also be manufactured by a method different from the following example.

[0044] When the insulating substrate 10 is made of, for example, an aluminum oxide (Al ２ O ３ ) sintered body, powders such as silica (SiO ２ O ３ ), magnesia (MgO), and calcia (CaO) are added to the powder of Al ２ as a sintering aid, and further an appropriate binder, solvent, and plasticizer are added. Next, these mixtures are kneaded to form a slurry. Thereafter, a ceramic green sheet is obtained by a forming method such as a conventionally well-known doctor blade method. The ceramic green sheet is an element that becomes each insulating layer 11 of the insulating substrate 10 after firing.

[0045] In the ceramic green sheet, through holes are formed at locations where the via conductors 21 are to be formed by a punching process or the like, and conductor paste is filled. The conductor paste is prepared by adding an appropriate solvent and binder to metal powders such as tungsten, molybdenum, manganese, silver, or copper and kneading them to adjust the viscosity to an appropriate level. Note that the conductor paste may contain glass or ceramics in order to increase the bonding strength with the insulating layer 11.

[0046] Furthermore, in the ceramic green sheet, conductor paste is printed in a predetermined shape by a screen printing method or the like at locations where the pad conductors 24 or the film-like conductors 28 of the interlayer 12 of the insulating layer 11 are located.

[0047] Then, a laminate is created by stacking the ceramic green sheets produced as described above, and a molded body is produced by processing the laminate to remove the open side of the third surface S3 while applying pressure to the laminate. Note that the void corresponding to the open side of the third surface S3 may be formed in advance by a punching process or the like at the stage of the ceramic green sheet before stacking.

[0048] Then, by firing the above molded body at a temperature of approximately 1500 to 1800°C, the ceramic green sheets are sintered in a laminated state, and the conductive paste is also sintered in a partially laminated state in the interlayer 12. This sintering yields a multi-cavity substrate in which multiple wiring boards 1, 1A to 1N are arranged. In the firing process, the volume of the ceramic green sheets differs between the open side and the opposite side of the third surface S3, which may result in differences in shrinkage. However, by positioning the wide first pad conductor 241 in the first interlayer 12A, stable connection of the conductors to be connected above and below the first interlayer 12A can be achieved.

[0049] In a multi-cavity substrate, dividing grooves are formed along the outer edges of the wiring boards 1, 1A to 1N, and the wiring boards 1, 1A to 1N are manufactured by dividing or cutting along these dividing grooves.

[0050] (Electronic Device and Electronic Module) Figure 13 shows an electronic device 300 and an electronic module 400 according to an embodiment of the present disclosure. The electronic device 300 according to this embodiment includes a wiring board 1 and an electronic component 310 mounted on the wiring board 1. The electronic component 310 has at least one terminal 311 connected to a transmission line 200, and transmits a high-frequency signal through the transmission line 200. The transmission line 200 may extend to connect the electronic component 310 and an electrode pad 411 of a module board 410. The electrode pad 411 may be a terminal that inputs or outputs a high-frequency signal. The wiring board 1 may be replaced with wiring boards 1A to 1N of other embodiments.

[0051] An electronic module 400 according to the embodiment of this disclosure comprises a module substrate 410 and an electronic device 300 mounted on the module substrate 410. In addition to the electronic device 300, other electronic devices, electronic elements, and electrical elements may be mounted on the module substrate 410. The module substrate 410 has electrode pads 411, while electrode pads 29 are located at corresponding locations on the wiring board 1, and the electrode pads 29 and 411 may be joined via a bonding material 331 such as solder.

[0052] According to the electronic device 300 and electronic module 400 of this embodiment, high-frequency signals can be transmitted smoothly between the electronic component 310 and the outside via the wiring board 1.

[0053] Embodiments of the present disclosure have been described above. However, the wiring boards, electronic devices, and electronic modules relating to the present disclosure are not limited to the embodiments described above. For example, the details shown in the embodiments can be modified as appropriate without departing from the spirit of the invention.

[0054] An embodiment of the present disclosure is described below. In one embodiment, (1) the wiring board comprises an insulating substrate having a plurality of insulating layers and including a first surface, a second surface located on the opposite side of the first surface, and a third surface having a step between it and the first surface or the second surface; and a first conductor located on the insulating substrate and extending in a direction intersecting the first surface or the second surface, wherein when the space between each of the plurality of insulating layers that is connected to the third surface is called the first space between layers, the first conductor comprises a first via conductor connected to the first space between layers, a second via conductor located in an insulating layer away from the first space between layers and connected to the first via conductor, and a first pad conductor located in the first space between layers, wherein the width of the first via conductor is smaller than the width of the second via conductor, and the width of the first pad conductor is larger than the width of the second via conductor.

[0055] (2) In the wiring board described in (1) above, when the multiple layers between which the second via conductors intersect are referred to as second layers, the first conductor includes a second pad conductor located in at least one of the multiple second layers, and the width of the first pad conductor is greater than the width of the second pad conductor.

[0056] (3) In the wiring board described in (2) above, when the interval between the layers of the plurality of insulating layers to which the first via conductor and the second via conductor are connected is called the connecting layer interval, the first conductor includes a connecting layer pad conductor located in the connecting layer interval, and the width of the connecting layer pad conductor is greater than the width of the second pad conductor.

[0057] (4) The wiring board described in (3) above has a width of the connecting layer pad conductor that is greater than the width of the second via conductor and different from the width of the first pad conductor.

[0058] (5) In the wiring board described in (3) above, one or more interlayers are located between the first interlayer and the connecting interlayer, and when such one or more interlayers are referred to as third interlayers, the first conductor includes one or more third pad conductors located in the one or more third interlayers, and the width of the one or more third pad conductors is greater than the width of the second pad conductor.

[0059] (6) The wiring board described in (5) above has a width that is greater than the width of the first pad conductor and different from the width of the first pad conductor.

[0060] (7) In any one of the wiring boards described in (1) to (6) above, the first via conductor has multiple sections with different widths from each other.

[0061] In one embodiment, (8) the electronic device comprises one of the wiring boards described in (1) to (7) above, and an electronic element mounted on the wiring board.

[0062] In one embodiment, (9) the electronic module comprises the electronic device described in (8) above, and a module substrate on which the electronic device is mounted.

[0063] This disclosure can be used in wiring boards, electronic devices, and electronic modules.

[0064] 1, 1A to 1N Wiring board 3, 3A, 3B Cavity 3G Step section 10 Insulating substrate 11 Insulating layer 12 Interlayer 12A, 12Aa, 12Ab First interlayer 12B Second interlayer 12C Interconnecting interlayer 12D Third interlayer 200 Transmission line 201 First conductor 211, 211a to 211e First via conductor 212 Second via conductor 241, 241a, 241b First pad conductor 242 Second pad conductor 243 Third pad conductor 248 Connecting layer pad conductor 300 Electronic device 310 Electronic component 400 Electronic module 410 Module substrate S1 First surface S2 Second surface S3, S3A, S3B Third surface W211, W211a-W211e, W212, W241-W243, W248 width

Claims

1. A wiring board comprising: an insulating substrate having a plurality of insulating layers, and including a first surface, a second surface located opposite to the first surface, and a third surface having a step between it and the first surface or the second surface; and a first conductor located on the insulating substrate and extending in a direction intersecting the first surface or the second surface, wherein when the interlayers of the plurality of insulating layers that are connected to the third surface are called the first interlayers, the first conductor comprises: a first via conductor connected to the first interlayers, a second via conductor located in an insulating layer away from the first interlayers and connected to the first via conductor, and a first pad conductor located in the first interlayers, wherein the width of the first via conductor is smaller than the width of the second via conductor, and the width of the first pad conductor is larger than the width of the second via conductor.

2. When the plurality of layers between which the second via conductor intersects is referred to as the second layer interval, the first conductor includes a second pad conductor located in at least one of the plurality of second layer intervals, and the width of the first pad conductor is greater than the width of the second pad conductor, the wiring board according to claim 1.

3. When the interval between the layers of the plurality of insulating layers in which the first via conductor and the second via conductor are connected is called a connecting layer interval, the first conductor includes a connecting layer pad conductor located in the connecting layer interval, and the width of the connecting layer pad conductor is greater than the width of the second pad conductor, the wiring board according to claim 2.

4. The wiring board according to claim 3, wherein the width of the connecting layer pad conductor is greater than the width of the second via conductor and different from the width of the first pad conductor.

5. When one or more interlayers are located between the first interlayer and the connecting interlayer, and the one or more interlayers are referred to as the third interlayer, the first conductor includes one or more third pad conductors located in the one or more third interlayers, and the width of the one or more third pad conductors is greater than the width of the second pad conductor, the wiring board according to claim 3.

6. The wiring board according to claim 5, wherein the width of one or more third pad conductors is greater than the width of the second via conductor and different from the width of the first pad conductor.

7. The wiring board according to any one of claims 1 to 6, wherein the first via conductor has a plurality of sections with different widths from each other.

8. An electronic device comprising: a wiring board according to any one of claims 1 to 7; and an electronic element mounted on the wiring board.

9. An electronic module comprising: an electronic device according to claim 8; and a module substrate on which the electronic device is mounted.

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